1/* 2 * Copyright (C) 2013 Emilio L��pez <emilio@elopez.com.ar> 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 * Adjustable factor-based clock implementation 9 */ 10 11#include <linux/clk-provider.h> 12#include <linux/delay.h> 13#include <linux/err.h> 14#include <linux/io.h> 15#include <linux/module.h> 16#include <linux/of_address.h> 17#include <linux/slab.h> 18#include <linux/string.h> 19 20#include "clk-factors.h" 21 22/* 23 * DOC: basic adjustable factor-based clock 24 * 25 * Traits of this clock: 26 * prepare - clk_prepare only ensures that parents are prepared 27 * enable - clk_enable only ensures that parents are enabled 28 * rate - rate is adjustable. 29 * clk->rate = (parent->rate * N * (K + 1) >> P) / (M + 1) 30 * parent - fixed parent. No clk_set_parent support 31 */ 32 33#define to_clk_factors(_hw) container_of(_hw, struct clk_factors, hw) 34 35#define FACTORS_MAX_PARENTS 5 36 37#define SETMASK(len, pos) (((1U << (len)) - 1) << (pos)) 38#define CLRMASK(len, pos) (~(SETMASK(len, pos))) 39#define FACTOR_GET(bit, len, reg) (((reg) & SETMASK(len, bit)) >> (bit)) 40 41#define FACTOR_SET(bit, len, reg, val) \ 42 (((reg) & CLRMASK(len, bit)) | (val << (bit))) 43 44static unsigned long clk_factors_recalc_rate(struct clk_hw *hw, 45 unsigned long parent_rate) 46{ 47 u8 n = 1, k = 0, p = 0, m = 0; 48 u32 reg; 49 unsigned long rate; 50 struct clk_factors *factors = to_clk_factors(hw); 51 struct clk_factors_config *config = factors->config; 52 53 /* Fetch the register value */ 54 reg = readl(factors->reg); 55 56 /* Get each individual factor if applicable */ 57 if (config->nwidth != SUNXI_FACTORS_NOT_APPLICABLE) 58 n = FACTOR_GET(config->nshift, config->nwidth, reg); 59 if (config->kwidth != SUNXI_FACTORS_NOT_APPLICABLE) 60 k = FACTOR_GET(config->kshift, config->kwidth, reg); 61 if (config->mwidth != SUNXI_FACTORS_NOT_APPLICABLE) 62 m = FACTOR_GET(config->mshift, config->mwidth, reg); 63 if (config->pwidth != SUNXI_FACTORS_NOT_APPLICABLE) 64 p = FACTOR_GET(config->pshift, config->pwidth, reg); 65 66 /* Calculate the rate */ 67 rate = (parent_rate * (n + config->n_start) * (k + 1) >> p) / (m + 1); 68 69 return rate; 70} 71 72static long clk_factors_round_rate(struct clk_hw *hw, unsigned long rate, 73 unsigned long *parent_rate) 74{ 75 struct clk_factors *factors = to_clk_factors(hw); 76 factors->get_factors((u32 *)&rate, (u32)*parent_rate, 77 NULL, NULL, NULL, NULL); 78 79 return rate; 80} 81 82static int clk_factors_determine_rate(struct clk_hw *hw, 83 struct clk_rate_request *req) 84{ 85 struct clk_hw *parent, *best_parent = NULL; 86 int i, num_parents; 87 unsigned long parent_rate, best = 0, child_rate, best_child_rate = 0; 88 89 /* find the parent that can help provide the fastest rate <= rate */ 90 num_parents = clk_hw_get_num_parents(hw); 91 for (i = 0; i < num_parents; i++) { 92 parent = clk_hw_get_parent_by_index(hw, i); 93 if (!parent) 94 continue; 95 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) 96 parent_rate = clk_hw_round_rate(parent, req->rate); 97 else 98 parent_rate = clk_hw_get_rate(parent); 99 100 child_rate = clk_factors_round_rate(hw, req->rate, 101 &parent_rate); 102 103 if (child_rate <= req->rate && child_rate > best_child_rate) { 104 best_parent = parent; 105 best = parent_rate; 106 best_child_rate = child_rate; 107 } 108 } 109 110 if (!best_parent) 111 return -EINVAL; 112 113 req->best_parent_hw = best_parent; 114 req->best_parent_rate = best; 115 req->rate = best_child_rate; 116 117 return 0; 118} 119 120static int clk_factors_set_rate(struct clk_hw *hw, unsigned long rate, 121 unsigned long parent_rate) 122{ 123 u8 n = 0, k = 0, m = 0, p = 0; 124 u32 reg; 125 struct clk_factors *factors = to_clk_factors(hw); 126 struct clk_factors_config *config = factors->config; 127 unsigned long flags = 0; 128 129 factors->get_factors((u32 *)&rate, (u32)parent_rate, &n, &k, &m, &p); 130 131 if (factors->lock) 132 spin_lock_irqsave(factors->lock, flags); 133 134 /* Fetch the register value */ 135 reg = readl(factors->reg); 136 137 /* Set up the new factors - macros do not do anything if width is 0 */ 138 reg = FACTOR_SET(config->nshift, config->nwidth, reg, n); 139 reg = FACTOR_SET(config->kshift, config->kwidth, reg, k); 140 reg = FACTOR_SET(config->mshift, config->mwidth, reg, m); 141 reg = FACTOR_SET(config->pshift, config->pwidth, reg, p); 142 143 /* Apply them now */ 144 writel(reg, factors->reg); 145 146 /* delay 500us so pll stabilizes */ 147 __delay((rate >> 20) * 500 / 2); 148 149 if (factors->lock) 150 spin_unlock_irqrestore(factors->lock, flags); 151 152 return 0; 153} 154 155static const struct clk_ops clk_factors_ops = { 156 .determine_rate = clk_factors_determine_rate, 157 .recalc_rate = clk_factors_recalc_rate, 158 .round_rate = clk_factors_round_rate, 159 .set_rate = clk_factors_set_rate, 160}; 161 162struct clk *sunxi_factors_register(struct device_node *node, 163 const struct factors_data *data, 164 spinlock_t *lock, 165 void __iomem *reg) 166{ 167 struct clk *clk; 168 struct clk_factors *factors; 169 struct clk_gate *gate = NULL; 170 struct clk_mux *mux = NULL; 171 struct clk_hw *gate_hw = NULL; 172 struct clk_hw *mux_hw = NULL; 173 const char *clk_name = node->name; 174 const char *parents[FACTORS_MAX_PARENTS]; 175 int i = 0; 176 177 /* if we have a mux, we will have >1 parents */ 178 i = of_clk_parent_fill(node, parents, FACTORS_MAX_PARENTS); 179 180 /* 181 * some factor clocks, such as pll5 and pll6, may have multiple 182 * outputs, and have their name designated in factors_data 183 */ 184 if (data->name) 185 clk_name = data->name; 186 else 187 of_property_read_string(node, "clock-output-names", &clk_name); 188 189 factors = kzalloc(sizeof(struct clk_factors), GFP_KERNEL); 190 if (!factors) 191 return NULL; 192 193 /* set up factors properties */ 194 factors->reg = reg; 195 factors->config = data->table; 196 factors->get_factors = data->getter; 197 factors->lock = lock; 198 199 /* Add a gate if this factor clock can be gated */ 200 if (data->enable) { 201 gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL); 202 if (!gate) { 203 kfree(factors); 204 return NULL; 205 } 206 207 /* set up gate properties */ 208 gate->reg = reg; 209 gate->bit_idx = data->enable; 210 gate->lock = factors->lock; 211 gate_hw = &gate->hw; 212 } 213 214 /* Add a mux if this factor clock can be muxed */ 215 if (data->mux) { 216 mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL); 217 if (!mux) { 218 kfree(factors); 219 kfree(gate); 220 return NULL; 221 } 222 223 /* set up gate properties */ 224 mux->reg = reg; 225 mux->shift = data->mux; 226 mux->mask = data->muxmask; 227 mux->lock = factors->lock; 228 mux_hw = &mux->hw; 229 } 230 231 clk = clk_register_composite(NULL, clk_name, 232 parents, i, 233 mux_hw, &clk_mux_ops, 234 &factors->hw, &clk_factors_ops, 235 gate_hw, &clk_gate_ops, 0); 236 237 if (!IS_ERR(clk)) { 238 of_clk_add_provider(node, of_clk_src_simple_get, clk); 239 clk_register_clkdev(clk, clk_name, NULL); 240 } 241 242 return clk; 243} 244