1/* 2 * pinmux driver for CSR SiRFprimaII 3 * 4 * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group 5 * company. 6 * 7 * Licensed under GPLv2 or later. 8 */ 9 10#include <linux/init.h> 11#include <linux/module.h> 12#include <linux/irq.h> 13#include <linux/platform_device.h> 14#include <linux/io.h> 15#include <linux/slab.h> 16#include <linux/err.h> 17#include <linux/pinctrl/pinctrl.h> 18#include <linux/pinctrl/pinmux.h> 19#include <linux/pinctrl/consumer.h> 20#include <linux/pinctrl/machine.h> 21#include <linux/of.h> 22#include <linux/of_address.h> 23#include <linux/of_device.h> 24#include <linux/of_platform.h> 25#include <linux/bitops.h> 26#include <linux/gpio.h> 27#include <linux/of_gpio.h> 28 29#include "pinctrl-sirf.h" 30 31#define DRIVER_NAME "pinmux-sirf" 32 33struct sirfsoc_gpio_bank { 34 int id; 35 int parent_irq; 36 spinlock_t lock; 37}; 38 39struct sirfsoc_gpio_chip { 40 struct of_mm_gpio_chip chip; 41 struct sirfsoc_gpio_bank sgpio_bank[SIRFSOC_GPIO_NO_OF_BANKS]; 42 spinlock_t lock; 43}; 44 45static struct sirfsoc_pin_group *sirfsoc_pin_groups; 46static int sirfsoc_pingrp_cnt; 47 48static int sirfsoc_get_groups_count(struct pinctrl_dev *pctldev) 49{ 50 return sirfsoc_pingrp_cnt; 51} 52 53static const char *sirfsoc_get_group_name(struct pinctrl_dev *pctldev, 54 unsigned selector) 55{ 56 return sirfsoc_pin_groups[selector].name; 57} 58 59static int sirfsoc_get_group_pins(struct pinctrl_dev *pctldev, 60 unsigned selector, 61 const unsigned **pins, 62 unsigned *num_pins) 63{ 64 *pins = sirfsoc_pin_groups[selector].pins; 65 *num_pins = sirfsoc_pin_groups[selector].num_pins; 66 return 0; 67} 68 69static void sirfsoc_pin_dbg_show(struct pinctrl_dev *pctldev, 70 struct seq_file *s, unsigned offset) 71{ 72 seq_printf(s, " " DRIVER_NAME); 73} 74 75static int sirfsoc_dt_node_to_map(struct pinctrl_dev *pctldev, 76 struct device_node *np_config, 77 struct pinctrl_map **map, unsigned *num_maps) 78{ 79 struct sirfsoc_pmx *spmx = pinctrl_dev_get_drvdata(pctldev); 80 struct device_node *np; 81 struct property *prop; 82 const char *function, *group; 83 int ret, index = 0, count = 0; 84 85 /* calculate number of maps required */ 86 for_each_child_of_node(np_config, np) { 87 ret = of_property_read_string(np, "sirf,function", &function); 88 if (ret < 0) 89 return ret; 90 91 ret = of_property_count_strings(np, "sirf,pins"); 92 if (ret < 0) 93 return ret; 94 95 count += ret; 96 } 97 98 if (!count) { 99 dev_err(spmx->dev, "No child nodes passed via DT\n"); 100 return -ENODEV; 101 } 102 103 *map = kzalloc(sizeof(**map) * count, GFP_KERNEL); 104 if (!*map) 105 return -ENOMEM; 106 107 for_each_child_of_node(np_config, np) { 108 of_property_read_string(np, "sirf,function", &function); 109 of_property_for_each_string(np, "sirf,pins", prop, group) { 110 (*map)[index].type = PIN_MAP_TYPE_MUX_GROUP; 111 (*map)[index].data.mux.group = group; 112 (*map)[index].data.mux.function = function; 113 index++; 114 } 115 } 116 117 *num_maps = count; 118 119 return 0; 120} 121 122static void sirfsoc_dt_free_map(struct pinctrl_dev *pctldev, 123 struct pinctrl_map *map, unsigned num_maps) 124{ 125 kfree(map); 126} 127 128static struct pinctrl_ops sirfsoc_pctrl_ops = { 129 .get_groups_count = sirfsoc_get_groups_count, 130 .get_group_name = sirfsoc_get_group_name, 131 .get_group_pins = sirfsoc_get_group_pins, 132 .pin_dbg_show = sirfsoc_pin_dbg_show, 133 .dt_node_to_map = sirfsoc_dt_node_to_map, 134 .dt_free_map = sirfsoc_dt_free_map, 135}; 136 137static struct sirfsoc_pmx_func *sirfsoc_pmx_functions; 138static int sirfsoc_pmxfunc_cnt; 139 140static void sirfsoc_pinmux_endisable(struct sirfsoc_pmx *spmx, 141 unsigned selector, bool enable) 142{ 143 int i; 144 const struct sirfsoc_padmux *mux = 145 sirfsoc_pmx_functions[selector].padmux; 146 const struct sirfsoc_muxmask *mask = mux->muxmask; 147 148 for (i = 0; i < mux->muxmask_counts; i++) { 149 u32 muxval; 150 muxval = readl(spmx->gpio_virtbase + 151 SIRFSOC_GPIO_PAD_EN(mask[i].group)); 152 if (enable) 153 muxval = muxval & ~mask[i].mask; 154 else 155 muxval = muxval | mask[i].mask; 156 writel(muxval, spmx->gpio_virtbase + 157 SIRFSOC_GPIO_PAD_EN(mask[i].group)); 158 } 159 160 if (mux->funcmask && enable) { 161 u32 func_en_val; 162 163 func_en_val = 164 readl(spmx->rsc_virtbase + mux->ctrlreg); 165 func_en_val = 166 (func_en_val & ~mux->funcmask) | (mux->funcval); 167 writel(func_en_val, spmx->rsc_virtbase + mux->ctrlreg); 168 } 169} 170 171static int sirfsoc_pinmux_set_mux(struct pinctrl_dev *pmxdev, 172 unsigned selector, 173 unsigned group) 174{ 175 struct sirfsoc_pmx *spmx; 176 177 spmx = pinctrl_dev_get_drvdata(pmxdev); 178 sirfsoc_pinmux_endisable(spmx, selector, true); 179 180 return 0; 181} 182 183static int sirfsoc_pinmux_get_funcs_count(struct pinctrl_dev *pmxdev) 184{ 185 return sirfsoc_pmxfunc_cnt; 186} 187 188static const char *sirfsoc_pinmux_get_func_name(struct pinctrl_dev *pctldev, 189 unsigned selector) 190{ 191 return sirfsoc_pmx_functions[selector].name; 192} 193 194static int sirfsoc_pinmux_get_groups(struct pinctrl_dev *pctldev, 195 unsigned selector, 196 const char * const **groups, 197 unsigned * const num_groups) 198{ 199 *groups = sirfsoc_pmx_functions[selector].groups; 200 *num_groups = sirfsoc_pmx_functions[selector].num_groups; 201 return 0; 202} 203 204static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev, 205 struct pinctrl_gpio_range *range, unsigned offset) 206{ 207 struct sirfsoc_pmx *spmx; 208 209 int group = range->id; 210 211 u32 muxval; 212 213 spmx = pinctrl_dev_get_drvdata(pmxdev); 214 215 muxval = readl(spmx->gpio_virtbase + 216 SIRFSOC_GPIO_PAD_EN(group)); 217 muxval = muxval | (1 << (offset - range->pin_base)); 218 writel(muxval, spmx->gpio_virtbase + 219 SIRFSOC_GPIO_PAD_EN(group)); 220 221 return 0; 222} 223 224static struct pinmux_ops sirfsoc_pinmux_ops = { 225 .set_mux = sirfsoc_pinmux_set_mux, 226 .get_functions_count = sirfsoc_pinmux_get_funcs_count, 227 .get_function_name = sirfsoc_pinmux_get_func_name, 228 .get_function_groups = sirfsoc_pinmux_get_groups, 229 .gpio_request_enable = sirfsoc_pinmux_request_gpio, 230}; 231 232static struct pinctrl_desc sirfsoc_pinmux_desc = { 233 .name = DRIVER_NAME, 234 .pctlops = &sirfsoc_pctrl_ops, 235 .pmxops = &sirfsoc_pinmux_ops, 236 .owner = THIS_MODULE, 237}; 238 239static void __iomem *sirfsoc_rsc_of_iomap(void) 240{ 241 const struct of_device_id rsc_ids[] = { 242 { .compatible = "sirf,prima2-rsc" }, 243 {} 244 }; 245 struct device_node *np; 246 247 np = of_find_matching_node(NULL, rsc_ids); 248 if (!np) 249 panic("unable to find compatible rsc node in dtb\n"); 250 251 return of_iomap(np, 0); 252} 253 254static int sirfsoc_gpio_of_xlate(struct gpio_chip *gc, 255 const struct of_phandle_args *gpiospec, 256 u32 *flags) 257{ 258 if (gpiospec->args[0] > SIRFSOC_GPIO_NO_OF_BANKS * SIRFSOC_GPIO_BANK_SIZE) 259 return -EINVAL; 260 261 if (flags) 262 *flags = gpiospec->args[1]; 263 264 return gpiospec->args[0]; 265} 266 267static const struct of_device_id pinmux_ids[] = { 268 { .compatible = "sirf,prima2-pinctrl", .data = &prima2_pinctrl_data, }, 269 { .compatible = "sirf,atlas6-pinctrl", .data = &atlas6_pinctrl_data, }, 270 {} 271}; 272 273static int sirfsoc_pinmux_probe(struct platform_device *pdev) 274{ 275 int ret; 276 struct sirfsoc_pmx *spmx; 277 struct device_node *np = pdev->dev.of_node; 278 const struct sirfsoc_pinctrl_data *pdata; 279 280 /* Create state holders etc for this driver */ 281 spmx = devm_kzalloc(&pdev->dev, sizeof(*spmx), GFP_KERNEL); 282 if (!spmx) 283 return -ENOMEM; 284 285 spmx->dev = &pdev->dev; 286 287 platform_set_drvdata(pdev, spmx); 288 289 spmx->gpio_virtbase = of_iomap(np, 0); 290 if (!spmx->gpio_virtbase) { 291 dev_err(&pdev->dev, "can't map gpio registers\n"); 292 return -ENOMEM; 293 } 294 295 spmx->rsc_virtbase = sirfsoc_rsc_of_iomap(); 296 if (!spmx->rsc_virtbase) { 297 ret = -ENOMEM; 298 dev_err(&pdev->dev, "can't map rsc registers\n"); 299 goto out_no_rsc_remap; 300 } 301 302 pdata = of_match_node(pinmux_ids, np)->data; 303 sirfsoc_pin_groups = pdata->grps; 304 sirfsoc_pingrp_cnt = pdata->grps_cnt; 305 sirfsoc_pmx_functions = pdata->funcs; 306 sirfsoc_pmxfunc_cnt = pdata->funcs_cnt; 307 sirfsoc_pinmux_desc.pins = pdata->pads; 308 sirfsoc_pinmux_desc.npins = pdata->pads_cnt; 309 310 311 /* Now register the pin controller and all pins it handles */ 312 spmx->pmx = pinctrl_register(&sirfsoc_pinmux_desc, &pdev->dev, spmx); 313 if (IS_ERR(spmx->pmx)) { 314 dev_err(&pdev->dev, "could not register SIRFSOC pinmux driver\n"); 315 ret = PTR_ERR(spmx->pmx); 316 goto out_no_pmx; 317 } 318 319 dev_info(&pdev->dev, "initialized SIRFSOC pinmux driver\n"); 320 321 return 0; 322 323out_no_pmx: 324 iounmap(spmx->rsc_virtbase); 325out_no_rsc_remap: 326 iounmap(spmx->gpio_virtbase); 327 return ret; 328} 329 330#ifdef CONFIG_PM_SLEEP 331static int sirfsoc_pinmux_suspend_noirq(struct device *dev) 332{ 333 int i, j; 334 struct sirfsoc_pmx *spmx = dev_get_drvdata(dev); 335 336 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { 337 for (j = 0; j < SIRFSOC_GPIO_BANK_SIZE; j++) { 338 spmx->gpio_regs[i][j] = readl(spmx->gpio_virtbase + 339 SIRFSOC_GPIO_CTRL(i, j)); 340 } 341 spmx->ints_regs[i] = readl(spmx->gpio_virtbase + 342 SIRFSOC_GPIO_INT_STATUS(i)); 343 spmx->paden_regs[i] = readl(spmx->gpio_virtbase + 344 SIRFSOC_GPIO_PAD_EN(i)); 345 } 346 spmx->dspen_regs = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_DSP_EN0); 347 348 for (i = 0; i < 3; i++) 349 spmx->rsc_regs[i] = readl(spmx->rsc_virtbase + 4 * i); 350 351 return 0; 352} 353 354static int sirfsoc_pinmux_resume_noirq(struct device *dev) 355{ 356 int i, j; 357 struct sirfsoc_pmx *spmx = dev_get_drvdata(dev); 358 359 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { 360 for (j = 0; j < SIRFSOC_GPIO_BANK_SIZE; j++) { 361 writel(spmx->gpio_regs[i][j], spmx->gpio_virtbase + 362 SIRFSOC_GPIO_CTRL(i, j)); 363 } 364 writel(spmx->ints_regs[i], spmx->gpio_virtbase + 365 SIRFSOC_GPIO_INT_STATUS(i)); 366 writel(spmx->paden_regs[i], spmx->gpio_virtbase + 367 SIRFSOC_GPIO_PAD_EN(i)); 368 } 369 writel(spmx->dspen_regs, spmx->gpio_virtbase + SIRFSOC_GPIO_DSP_EN0); 370 371 for (i = 0; i < 3; i++) 372 writel(spmx->rsc_regs[i], spmx->rsc_virtbase + 4 * i); 373 374 return 0; 375} 376 377static const struct dev_pm_ops sirfsoc_pinmux_pm_ops = { 378 .suspend_noirq = sirfsoc_pinmux_suspend_noirq, 379 .resume_noirq = sirfsoc_pinmux_resume_noirq, 380 .freeze_noirq = sirfsoc_pinmux_suspend_noirq, 381 .restore_noirq = sirfsoc_pinmux_resume_noirq, 382}; 383#endif 384 385static struct platform_driver sirfsoc_pinmux_driver = { 386 .driver = { 387 .name = DRIVER_NAME, 388 .of_match_table = pinmux_ids, 389#ifdef CONFIG_PM_SLEEP 390 .pm = &sirfsoc_pinmux_pm_ops, 391#endif 392 }, 393 .probe = sirfsoc_pinmux_probe, 394}; 395 396static int __init sirfsoc_pinmux_init(void) 397{ 398 return platform_driver_register(&sirfsoc_pinmux_driver); 399} 400arch_initcall(sirfsoc_pinmux_init); 401 402static inline struct sirfsoc_gpio_chip *to_sirfsoc_gpio(struct gpio_chip *gc) 403{ 404 return container_of(gc, struct sirfsoc_gpio_chip, chip.gc); 405} 406 407static inline struct sirfsoc_gpio_bank * 408sirfsoc_gpio_to_bank(struct sirfsoc_gpio_chip *sgpio, unsigned int offset) 409{ 410 return &sgpio->sgpio_bank[offset / SIRFSOC_GPIO_BANK_SIZE]; 411} 412 413static inline int sirfsoc_gpio_to_bankoff(unsigned int offset) 414{ 415 return offset % SIRFSOC_GPIO_BANK_SIZE; 416} 417 418static void sirfsoc_gpio_irq_ack(struct irq_data *d) 419{ 420 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 421 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(gc); 422 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq); 423 int idx = sirfsoc_gpio_to_bankoff(d->hwirq); 424 u32 val, offset; 425 unsigned long flags; 426 427 offset = SIRFSOC_GPIO_CTRL(bank->id, idx); 428 429 spin_lock_irqsave(&sgpio->lock, flags); 430 431 val = readl(sgpio->chip.regs + offset); 432 433 writel(val, sgpio->chip.regs + offset); 434 435 spin_unlock_irqrestore(&sgpio->lock, flags); 436} 437 438static void __sirfsoc_gpio_irq_mask(struct sirfsoc_gpio_chip *sgpio, 439 struct sirfsoc_gpio_bank *bank, 440 int idx) 441{ 442 u32 val, offset; 443 unsigned long flags; 444 445 offset = SIRFSOC_GPIO_CTRL(bank->id, idx); 446 447 spin_lock_irqsave(&sgpio->lock, flags); 448 449 val = readl(sgpio->chip.regs + offset); 450 val &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK; 451 val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK; 452 writel(val, sgpio->chip.regs + offset); 453 454 spin_unlock_irqrestore(&sgpio->lock, flags); 455} 456 457static void sirfsoc_gpio_irq_mask(struct irq_data *d) 458{ 459 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 460 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(gc); 461 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq); 462 463 __sirfsoc_gpio_irq_mask(sgpio, bank, d->hwirq % SIRFSOC_GPIO_BANK_SIZE); 464} 465 466static void sirfsoc_gpio_irq_unmask(struct irq_data *d) 467{ 468 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 469 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(gc); 470 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq); 471 int idx = sirfsoc_gpio_to_bankoff(d->hwirq); 472 u32 val, offset; 473 unsigned long flags; 474 475 offset = SIRFSOC_GPIO_CTRL(bank->id, idx); 476 477 spin_lock_irqsave(&sgpio->lock, flags); 478 479 val = readl(sgpio->chip.regs + offset); 480 val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK; 481 val |= SIRFSOC_GPIO_CTL_INTR_EN_MASK; 482 writel(val, sgpio->chip.regs + offset); 483 484 spin_unlock_irqrestore(&sgpio->lock, flags); 485} 486 487static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type) 488{ 489 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 490 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(gc); 491 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq); 492 int idx = sirfsoc_gpio_to_bankoff(d->hwirq); 493 u32 val, offset; 494 unsigned long flags; 495 496 offset = SIRFSOC_GPIO_CTRL(bank->id, idx); 497 498 spin_lock_irqsave(&sgpio->lock, flags); 499 500 val = readl(sgpio->chip.regs + offset); 501 val &= ~(SIRFSOC_GPIO_CTL_INTR_STS_MASK | SIRFSOC_GPIO_CTL_OUT_EN_MASK); 502 503 switch (type) { 504 case IRQ_TYPE_NONE: 505 break; 506 case IRQ_TYPE_EDGE_RISING: 507 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | 508 SIRFSOC_GPIO_CTL_INTR_TYPE_MASK; 509 val &= ~SIRFSOC_GPIO_CTL_INTR_LOW_MASK; 510 break; 511 case IRQ_TYPE_EDGE_FALLING: 512 val &= ~SIRFSOC_GPIO_CTL_INTR_HIGH_MASK; 513 val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK | 514 SIRFSOC_GPIO_CTL_INTR_TYPE_MASK; 515 break; 516 case IRQ_TYPE_EDGE_BOTH: 517 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | 518 SIRFSOC_GPIO_CTL_INTR_LOW_MASK | 519 SIRFSOC_GPIO_CTL_INTR_TYPE_MASK; 520 break; 521 case IRQ_TYPE_LEVEL_LOW: 522 val &= ~(SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | 523 SIRFSOC_GPIO_CTL_INTR_TYPE_MASK); 524 val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK; 525 break; 526 case IRQ_TYPE_LEVEL_HIGH: 527 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK; 528 val &= ~(SIRFSOC_GPIO_CTL_INTR_LOW_MASK | 529 SIRFSOC_GPIO_CTL_INTR_TYPE_MASK); 530 break; 531 } 532 533 writel(val, sgpio->chip.regs + offset); 534 535 spin_unlock_irqrestore(&sgpio->lock, flags); 536 537 return 0; 538} 539 540static struct irq_chip sirfsoc_irq_chip = { 541 .name = "sirf-gpio-irq", 542 .irq_ack = sirfsoc_gpio_irq_ack, 543 .irq_mask = sirfsoc_gpio_irq_mask, 544 .irq_unmask = sirfsoc_gpio_irq_unmask, 545 .irq_set_type = sirfsoc_gpio_irq_type, 546}; 547 548static void sirfsoc_gpio_handle_irq(struct irq_desc *desc) 549{ 550 unsigned int irq = irq_desc_get_irq(desc); 551 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 552 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(gc); 553 struct sirfsoc_gpio_bank *bank; 554 u32 status, ctrl; 555 int idx = 0; 556 struct irq_chip *chip = irq_desc_get_chip(desc); 557 int i; 558 559 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { 560 bank = &sgpio->sgpio_bank[i]; 561 if (bank->parent_irq == irq) 562 break; 563 } 564 BUG_ON(i == SIRFSOC_GPIO_NO_OF_BANKS); 565 566 chained_irq_enter(chip, desc); 567 568 status = readl(sgpio->chip.regs + SIRFSOC_GPIO_INT_STATUS(bank->id)); 569 if (!status) { 570 printk(KERN_WARNING 571 "%s: gpio id %d status %#x no interrupt is flagged\n", 572 __func__, bank->id, status); 573 handle_bad_irq(desc); 574 return; 575 } 576 577 while (status) { 578 ctrl = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, idx)); 579 580 /* 581 * Here we must check whether the corresponding GPIO's interrupt 582 * has been enabled, otherwise just skip it 583 */ 584 if ((status & 0x1) && (ctrl & SIRFSOC_GPIO_CTL_INTR_EN_MASK)) { 585 pr_debug("%s: gpio id %d idx %d happens\n", 586 __func__, bank->id, idx); 587 generic_handle_irq(irq_find_mapping(gc->irqdomain, idx + 588 bank->id * SIRFSOC_GPIO_BANK_SIZE)); 589 } 590 591 idx++; 592 status = status >> 1; 593 } 594 595 chained_irq_exit(chip, desc); 596} 597 598static inline void sirfsoc_gpio_set_input(struct sirfsoc_gpio_chip *sgpio, 599 unsigned ctrl_offset) 600{ 601 u32 val; 602 603 val = readl(sgpio->chip.regs + ctrl_offset); 604 val &= ~SIRFSOC_GPIO_CTL_OUT_EN_MASK; 605 writel(val, sgpio->chip.regs + ctrl_offset); 606} 607 608static int sirfsoc_gpio_request(struct gpio_chip *chip, unsigned offset) 609{ 610 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip); 611 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset); 612 unsigned long flags; 613 614 if (pinctrl_request_gpio(chip->base + offset)) 615 return -ENODEV; 616 617 spin_lock_irqsave(&bank->lock, flags); 618 619 /* 620 * default status: 621 * set direction as input and mask irq 622 */ 623 sirfsoc_gpio_set_input(sgpio, SIRFSOC_GPIO_CTRL(bank->id, offset)); 624 __sirfsoc_gpio_irq_mask(sgpio, bank, offset); 625 626 spin_unlock_irqrestore(&bank->lock, flags); 627 628 return 0; 629} 630 631static void sirfsoc_gpio_free(struct gpio_chip *chip, unsigned offset) 632{ 633 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip); 634 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset); 635 unsigned long flags; 636 637 spin_lock_irqsave(&bank->lock, flags); 638 639 __sirfsoc_gpio_irq_mask(sgpio, bank, offset); 640 sirfsoc_gpio_set_input(sgpio, SIRFSOC_GPIO_CTRL(bank->id, offset)); 641 642 spin_unlock_irqrestore(&bank->lock, flags); 643 644 pinctrl_free_gpio(chip->base + offset); 645} 646 647static int sirfsoc_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) 648{ 649 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip); 650 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, gpio); 651 int idx = sirfsoc_gpio_to_bankoff(gpio); 652 unsigned long flags; 653 unsigned offset; 654 655 offset = SIRFSOC_GPIO_CTRL(bank->id, idx); 656 657 spin_lock_irqsave(&bank->lock, flags); 658 659 sirfsoc_gpio_set_input(sgpio, offset); 660 661 spin_unlock_irqrestore(&bank->lock, flags); 662 663 return 0; 664} 665 666static inline void sirfsoc_gpio_set_output(struct sirfsoc_gpio_chip *sgpio, 667 struct sirfsoc_gpio_bank *bank, 668 unsigned offset, 669 int value) 670{ 671 u32 out_ctrl; 672 unsigned long flags; 673 674 spin_lock_irqsave(&bank->lock, flags); 675 676 out_ctrl = readl(sgpio->chip.regs + offset); 677 if (value) 678 out_ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK; 679 else 680 out_ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK; 681 682 out_ctrl &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK; 683 out_ctrl |= SIRFSOC_GPIO_CTL_OUT_EN_MASK; 684 writel(out_ctrl, sgpio->chip.regs + offset); 685 686 spin_unlock_irqrestore(&bank->lock, flags); 687} 688 689static int sirfsoc_gpio_direction_output(struct gpio_chip *chip, 690 unsigned gpio, int value) 691{ 692 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip); 693 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, gpio); 694 int idx = sirfsoc_gpio_to_bankoff(gpio); 695 u32 offset; 696 unsigned long flags; 697 698 offset = SIRFSOC_GPIO_CTRL(bank->id, idx); 699 700 spin_lock_irqsave(&sgpio->lock, flags); 701 702 sirfsoc_gpio_set_output(sgpio, bank, offset, value); 703 704 spin_unlock_irqrestore(&sgpio->lock, flags); 705 706 return 0; 707} 708 709static int sirfsoc_gpio_get_value(struct gpio_chip *chip, unsigned offset) 710{ 711 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip); 712 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset); 713 u32 val; 714 unsigned long flags; 715 716 spin_lock_irqsave(&bank->lock, flags); 717 718 val = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset)); 719 720 spin_unlock_irqrestore(&bank->lock, flags); 721 722 return !!(val & SIRFSOC_GPIO_CTL_DATAIN_MASK); 723} 724 725static void sirfsoc_gpio_set_value(struct gpio_chip *chip, unsigned offset, 726 int value) 727{ 728 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip); 729 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset); 730 u32 ctrl; 731 unsigned long flags; 732 733 spin_lock_irqsave(&bank->lock, flags); 734 735 ctrl = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset)); 736 if (value) 737 ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK; 738 else 739 ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK; 740 writel(ctrl, sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset)); 741 742 spin_unlock_irqrestore(&bank->lock, flags); 743} 744 745static void sirfsoc_gpio_set_pullup(struct sirfsoc_gpio_chip *sgpio, 746 const u32 *pullups) 747{ 748 int i, n; 749 const unsigned long *p = (const unsigned long *)pullups; 750 751 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { 752 for_each_set_bit(n, p + i, BITS_PER_LONG) { 753 u32 offset = SIRFSOC_GPIO_CTRL(i, n); 754 u32 val = readl(sgpio->chip.regs + offset); 755 val |= SIRFSOC_GPIO_CTL_PULL_MASK; 756 val |= SIRFSOC_GPIO_CTL_PULL_HIGH; 757 writel(val, sgpio->chip.regs + offset); 758 } 759 } 760} 761 762static void sirfsoc_gpio_set_pulldown(struct sirfsoc_gpio_chip *sgpio, 763 const u32 *pulldowns) 764{ 765 int i, n; 766 const unsigned long *p = (const unsigned long *)pulldowns; 767 768 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { 769 for_each_set_bit(n, p + i, BITS_PER_LONG) { 770 u32 offset = SIRFSOC_GPIO_CTRL(i, n); 771 u32 val = readl(sgpio->chip.regs + offset); 772 val |= SIRFSOC_GPIO_CTL_PULL_MASK; 773 val &= ~SIRFSOC_GPIO_CTL_PULL_HIGH; 774 writel(val, sgpio->chip.regs + offset); 775 } 776 } 777} 778 779static int sirfsoc_gpio_probe(struct device_node *np) 780{ 781 int i, err = 0; 782 static struct sirfsoc_gpio_chip *sgpio; 783 struct sirfsoc_gpio_bank *bank; 784 void __iomem *regs; 785 struct platform_device *pdev; 786 787 u32 pullups[SIRFSOC_GPIO_NO_OF_BANKS], pulldowns[SIRFSOC_GPIO_NO_OF_BANKS]; 788 789 pdev = of_find_device_by_node(np); 790 if (!pdev) 791 return -ENODEV; 792 793 sgpio = devm_kzalloc(&pdev->dev, sizeof(*sgpio), GFP_KERNEL); 794 if (!sgpio) 795 return -ENOMEM; 796 spin_lock_init(&sgpio->lock); 797 798 regs = of_iomap(np, 0); 799 if (!regs) 800 return -ENOMEM; 801 802 sgpio->chip.gc.request = sirfsoc_gpio_request; 803 sgpio->chip.gc.free = sirfsoc_gpio_free; 804 sgpio->chip.gc.direction_input = sirfsoc_gpio_direction_input; 805 sgpio->chip.gc.get = sirfsoc_gpio_get_value; 806 sgpio->chip.gc.direction_output = sirfsoc_gpio_direction_output; 807 sgpio->chip.gc.set = sirfsoc_gpio_set_value; 808 sgpio->chip.gc.base = 0; 809 sgpio->chip.gc.ngpio = SIRFSOC_GPIO_BANK_SIZE * SIRFSOC_GPIO_NO_OF_BANKS; 810 sgpio->chip.gc.label = kstrdup(np->full_name, GFP_KERNEL); 811 sgpio->chip.gc.of_node = np; 812 sgpio->chip.gc.of_xlate = sirfsoc_gpio_of_xlate; 813 sgpio->chip.gc.of_gpio_n_cells = 2; 814 sgpio->chip.gc.dev = &pdev->dev; 815 sgpio->chip.regs = regs; 816 817 err = gpiochip_add(&sgpio->chip.gc); 818 if (err) { 819 dev_err(&pdev->dev, "%s: error in probe function with status %d\n", 820 np->full_name, err); 821 goto out; 822 } 823 824 err = gpiochip_irqchip_add(&sgpio->chip.gc, 825 &sirfsoc_irq_chip, 826 0, handle_level_irq, 827 IRQ_TYPE_NONE); 828 if (err) { 829 dev_err(&pdev->dev, 830 "could not connect irqchip to gpiochip\n"); 831 goto out_banks; 832 } 833 834 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { 835 bank = &sgpio->sgpio_bank[i]; 836 spin_lock_init(&bank->lock); 837 bank->parent_irq = platform_get_irq(pdev, i); 838 if (bank->parent_irq < 0) { 839 err = bank->parent_irq; 840 goto out_banks; 841 } 842 843 gpiochip_set_chained_irqchip(&sgpio->chip.gc, 844 &sirfsoc_irq_chip, 845 bank->parent_irq, 846 sirfsoc_gpio_handle_irq); 847 } 848 849 err = gpiochip_add_pin_range(&sgpio->chip.gc, dev_name(&pdev->dev), 850 0, 0, SIRFSOC_GPIO_BANK_SIZE * SIRFSOC_GPIO_NO_OF_BANKS); 851 if (err) { 852 dev_err(&pdev->dev, 853 "could not add gpiochip pin range\n"); 854 goto out_no_range; 855 } 856 857 if (!of_property_read_u32_array(np, "sirf,pullups", pullups, 858 SIRFSOC_GPIO_NO_OF_BANKS)) 859 sirfsoc_gpio_set_pullup(sgpio, pullups); 860 861 if (!of_property_read_u32_array(np, "sirf,pulldowns", pulldowns, 862 SIRFSOC_GPIO_NO_OF_BANKS)) 863 sirfsoc_gpio_set_pulldown(sgpio, pulldowns); 864 865 return 0; 866 867out_no_range: 868out_banks: 869 gpiochip_remove(&sgpio->chip.gc); 870out: 871 iounmap(regs); 872 return err; 873} 874 875static int __init sirfsoc_gpio_init(void) 876{ 877 878 struct device_node *np; 879 880 np = of_find_matching_node(NULL, pinmux_ids); 881 882 if (!np) 883 return -ENODEV; 884 885 return sirfsoc_gpio_probe(np); 886} 887subsys_initcall(sirfsoc_gpio_init); 888 889MODULE_AUTHOR("Rongjun Ying <rongjun.ying@csr.com>"); 890MODULE_AUTHOR("Yuping Luo <yuping.luo@csr.com>"); 891MODULE_AUTHOR("Barry Song <baohua.song@csr.com>"); 892MODULE_DESCRIPTION("SIRFSOC pin control driver"); 893MODULE_LICENSE("GPL"); 894