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Searched refs:clk_base (Results 1 – 20 of 20) sorted by relevance

/linux-4.4.14/drivers/clk/tegra/
Dclk-tegra-super-gen4.c54 static void __init tegra_sclk_init(void __iomem *clk_base, in tegra_sclk_init() argument
66 clk_base + SCLK_BURST_POLICY, in tegra_sclk_init()
75 clk_base + SYSTEM_CLK_RATE, 4, 2, 0, in tegra_sclk_init()
79 clk_base + SYSTEM_CLK_RATE, in tegra_sclk_init()
90 clk_base + SYSTEM_CLK_RATE, 0, 2, 0, in tegra_sclk_init()
93 CLK_IGNORE_UNUSED, clk_base + SYSTEM_CLK_RATE, in tegra_sclk_init()
98 void __init tegra_super_clk_gen4_init(void __iomem *clk_base, in tegra_super_clk_gen4_init() argument
112 clk_base + CCLKG_BURST_POLICY, in tegra_super_clk_gen4_init()
123 clk_base + CCLKLP_BURST_POLICY, in tegra_super_clk_gen4_init()
128 tegra_sclk_init(clk_base, tegra_clks); in tegra_super_clk_gen4_init()
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Dclk-tegra20.c139 static void __iomem *clk_base; variable
584 u32 osc_ctrl = readl_relaxed(clk_base + OSC_CTRL); in tegra20_clk_measure_input_freq()
618 u32 pll_ref_div = readl_relaxed(clk_base + OSC_CTRL) & in tegra20_get_pll_ref_div()
640 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, NULL, 0, in tegra20_pll_init()
646 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra20_pll_init()
649 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT, in tegra20_pll_init()
654 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, NULL, in tegra20_pll_init()
661 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra20_pll_init()
664 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED | in tegra20_pll_init()
669 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, NULL, 0, in tegra20_pll_init()
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Dclk-tegra114.c167 static void __iomem *clk_base; variable
945 static void __init tegra114_fixed_clk_init(void __iomem *clk_base) in tegra114_fixed_clk_init() argument
966 static __init void tegra114_utmi_param_configure(void __iomem *clk_base) in tegra114_utmi_param_configure() argument
982 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2); in tegra114_utmi_param_configure()
999 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2); in tegra114_utmi_param_configure()
1002 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); in tegra114_utmi_param_configure()
1017 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); in tegra114_utmi_param_configure()
1020 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra114_utmi_param_configure()
1024 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra114_utmi_param_configure()
1026 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); in tegra114_utmi_param_configure()
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Dclk-tegra30.c173 static void __iomem *clk_base; variable
882 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2); in tegra30_utmi_param_configure()
899 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2); in tegra30_utmi_param_configure()
902 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); in tegra30_utmi_param_configure()
917 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); in tegra30_utmi_param_configure()
927 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, pmc_base, 0, in tegra30_pll_init()
933 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra30_pll_init()
936 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT, in tegra30_pll_init()
941 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, pmc_base, in tegra30_pll_init()
948 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra30_pll_init()
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Dclk-periph-gate.c31 readl_relaxed(gate->clk_base + (gate->regs->enb_reg))
33 writel_relaxed(val, gate->clk_base + (gate->regs->enb_set_reg))
35 writel_relaxed(val, gate->clk_base + (gate->regs->enb_clr_reg))
38 readl_relaxed(gate->clk_base + (gate->regs->rst_reg))
40 writel_relaxed(val, gate->clk_base + (gate->regs->rst_clr_reg))
87 writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE); in clk_periph_enable()
88 writel_relaxed(BIT(22), gate->clk_base + LVL2_CLK_GATE_OVRE); in clk_periph_enable()
90 writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE); in clk_periph_enable()
131 const char *parent_name, u8 gate_flags, void __iomem *clk_base, in tegra_clk_register_periph_gate() argument
156 gate->clk_base = clk_base; in tegra_clk_register_periph_gate()
Dclk-tegra124.c139 static void __iomem *clk_base; variable
1025 static void tegra124_utmi_param_configure(void __iomem *clk_base) in tegra124_utmi_param_configure() argument
1041 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2); in tegra124_utmi_param_configure()
1058 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2); in tegra124_utmi_param_configure()
1061 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); in tegra124_utmi_param_configure()
1076 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); in tegra124_utmi_param_configure()
1079 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra124_utmi_param_configure()
1083 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra124_utmi_param_configure()
1085 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); in tegra124_utmi_param_configure()
1088 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); in tegra124_utmi_param_configure()
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Dclk.h265 void __iomem *clk_base; member
291 void __iomem *clk_base, void __iomem *pmc,
296 void __iomem *clk_base, void __iomem *pmc,
301 void __iomem *clk_base, void __iomem *pmc,
307 void __iomem *clk_base, void __iomem *pmc,
313 void __iomem *clk_base, void __iomem *pmc,
319 void __iomem *clk_base, void __iomem *pmc,
326 void __iomem *clk_base, unsigned long flags,
331 void __iomem *clk_base, unsigned long flags,
406 void __iomem *clk_base; member
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Dclk-tegra-audio.c126 void __init tegra_audio_clk_init(void __iomem *clk_base, in tegra_audio_clk_init() argument
147 clk_base, pmc_base, 0, info->pll_params, in tegra_audio_clk_init()
157 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra_audio_clk_init()
160 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED | in tegra_audio_clk_init()
190 clk_base + data->offset, 0, 3, 0, in tegra_audio_clk_init()
199 0, clk_base + data->offset, 4, in tegra_audio_clk_init()
215 data->name_2x, clk_base + AUDIO_SYNC_DOUBLER, in tegra_audio_clk_init()
220 clk_base, CLK_SET_RATE_PARENT, data->clk_num, in tegra_audio_clk_init()
Dclk-periph.c143 void __iomem *clk_base, u32 offset, in _tegra_clk_register_periph() argument
171 periph->mux.reg = clk_base + offset; in _tegra_clk_register_periph()
172 periph->divider.reg = div ? (clk_base + offset) : NULL; in _tegra_clk_register_periph()
173 periph->gate.clk_base = clk_base; in _tegra_clk_register_periph()
190 struct tegra_clk_periph *periph, void __iomem *clk_base, in tegra_clk_register_periph() argument
194 periph, clk_base, offset, flags); in tegra_clk_register_periph()
199 struct tegra_clk_periph *periph, void __iomem *clk_base, in tegra_clk_register_periph_nodiv() argument
204 periph, clk_base, offset, CLK_SET_RATE_PARENT); in tegra_clk_register_periph_nodiv()
Dclk-pll.c186 #define pll_readl(offset, p) readl_relaxed(p->clk_base + offset)
191 #define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset)
249 lock_addr = pll->clk_base; in clk_pll_wait_for_lock()
771 val = readl(pll->clk_base + PLLE_SS_CTRL); in clk_plle_enable()
774 writel(val, pll->clk_base + PLLE_SS_CTRL); in clk_plle_enable()
839 void __iomem *clk_base, in _setup_dynamic_ramp() argument
869 writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg); in _setup_dynamic_ramp()
1414 static struct tegra_clk_pll *_tegra_init_pll(void __iomem *clk_base, in _tegra_init_pll() argument
1424 pll->clk_base = clk_base; in _tegra_init_pll()
1455 void __iomem *clk_base, void __iomem *pmc, in tegra_clk_register_pll() argument
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Dclk-tegra-periph.c581 static void __init periph_clk_init(void __iomem *clk_base, in periph_clk_init() argument
605 &data->periph, clk_base, data->offset, in periph_clk_init()
611 static void __init gate_clk_init(void __iomem *clk_base, in gate_clk_init() argument
629 clk_base, data->flags, in gate_clk_init()
636 static void __init init_pllp(void __iomem *clk_base, void __iomem *pmc_base, in init_pllp() argument
647 clk = tegra_clk_register_pll("pll_p", "pll_ref", clk_base, in init_pllp()
663 clk_base + data->offset, 0, data->div_flags, in init_pllp()
666 data->div_name, clk_base + data->offset, in init_pllp()
674 void __init tegra_periph_clk_init(void __iomem *clk_base, in tegra_periph_clk_init() argument
678 init_pllp(clk_base, pmc_base, tegra_clks, pll_params); in tegra_periph_clk_init()
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Dclk.c146 static void __iomem *clk_base; variable
162 clk_base + periph_regs[id / 32].rst_set_reg); in tegra_clk_rst_assert()
176 clk_base + periph_regs[id / 32].rst_clr_reg); in tegra_clk_rst_deassert()
199 clk_base = regs; in tegra_clk_init()
Dclk-tegra-fixed.c32 int __init tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks, in tegra_osc_clk_init() argument
42 val = readl_relaxed(clk_base + OSC_CTRL); in tegra_osc_clk_init()
/linux-4.4.14/drivers/clk/meson/
Dclkc.c51 void __iomem *clk_base) in meson_clk_register_composite() argument
67 mux->reg = clk_base + clk_conf->reg_off in meson_clk_register_composite()
85 div->reg = clk_base + clk_conf->reg_off in meson_clk_register_composite()
101 gate->reg = clk_base + clk_conf->reg_off in meson_clk_register_composite()
130 void __iomem *clk_base) in meson_clk_register_fixed_factor() argument
147 reg = readl(clk_base + clk_conf->reg_off + p->reg_off); in meson_clk_register_fixed_factor()
156 reg = readl(clk_base + clk_conf->reg_off + p->reg_off); in meson_clk_register_fixed_factor()
172 void __iomem *clk_base) in meson_clk_register_fixed_rate() argument
185 reg = readl(clk_base + clk_conf->reg_off + r->reg_off); in meson_clk_register_fixed_rate()
202 void __iomem *clk_base) in meson_clk_register_clks() argument
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Dmeson8b-clkc.c170 void __iomem *clk_base; in meson8b_clkc_init() local
176 clk_base = of_iomap(np, 0); in meson8b_clkc_init()
177 if (!clk_base) { in meson8b_clkc_init()
182 meson_clk_register_clks(&meson8b_xtal_conf, 1, clk_base); in meson8b_clkc_init()
183 iounmap(clk_base); in meson8b_clkc_init()
186 clk_base = of_iomap(np, 1); in meson8b_clkc_init()
187 if (!clk_base) { in meson8b_clkc_init()
194 clk_base); in meson8b_clkc_init()
Dclkc.h181 unsigned int nr_confs, void __iomem *clk_base);
/linux-4.4.14/arch/arm/mach-prima2/
Dplatsmp.c23 static void __iomem *clk_base; variable
57 clk_base = of_iomap(np, 0); in sirfsoc_boot_secondary()
58 if (!clk_base) in sirfsoc_boot_secondary()
69 clk_base + SIRFSOC_CPU1_JUMPADDR_OFFSET); in sirfsoc_boot_secondary()
73 clk_base + SIRFSOC_CPU1_WAKEMAGIC_OFFSET); in sirfsoc_boot_secondary()
/linux-4.4.14/drivers/mmc/host/
Dsdhci-of-at91.c62 unsigned int clk_base, clk_mul; in sdhci_at91_probe() local
107 clk_base = (caps0 & SDHCI_CLOCK_V3_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT; in sdhci_at91_probe()
109 gck_rate = clk_base * 1000000 * (clk_mul + 1); in sdhci_at91_probe()
123 clk_mul = real_gck_rate / (clk_base * 1000000) - 1; in sdhci_at91_probe()
/linux-4.4.14/drivers/cpufreq/
Ds5pv210-cpufreq.c25 static void __iomem *clk_base; variable
28 #define S5P_CLKREG(x) (clk_base + (x))
609 clk_base = of_iomap(np, 0); in s5pv210_cpufreq_probe()
610 if (!clk_base) { in s5pv210_cpufreq_probe()
/linux-4.4.14/drivers/clk/nxp/
Dclk-lpc18xx-cgu.c637 static struct clk *clk_base[BASE_CLK_MAX]; variable
639 .clks = clk_base,
648 clk_base[i] = lpc18xx_register_base_clk(&lpc18xx_cgu_base_clks[i], in lpc18xx_cgu_register_base_clks()
650 if (IS_ERR(clk_base[i]) && PTR_ERR(clk_base[i]) != -ENOENT) in lpc18xx_cgu_register_base_clks()