167 static void __iomem *clk_base;  variable
945 static void __init tegra114_fixed_clk_init(void __iomem *clk_base)  in tegra114_fixed_clk_init()  argument
966 static __init void tegra114_utmi_param_configure(void __iomem *clk_base)  in tegra114_utmi_param_configure()  argument
982 	reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);  in tegra114_utmi_param_configure()
999 	writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);  in tegra114_utmi_param_configure()
1002 	reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);  in tegra114_utmi_param_configure()
1017 	writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);  in tegra114_utmi_param_configure()
1020 	reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);  in tegra114_utmi_param_configure()
1024 	writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);  in tegra114_utmi_param_configure()
1026 	reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);  in tegra114_utmi_param_configure()
1029 	writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);  in tegra114_utmi_param_configure()
1035 	reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);  in tegra114_utmi_param_configure()
1038 	writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);  in tegra114_utmi_param_configure()
1043 	reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);  in tegra114_utmi_param_configure()
1045 	writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);  in tegra114_utmi_param_configure()
1048 static void __init tegra114_pll_init(void __iomem *clk_base,  in tegra114_pll_init()  argument
1055 	clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base,  in tegra114_pll_init()
1061 			clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,  in tegra114_pll_init()
1064 				clk_base + PLLC_OUT, 1, 0,  in tegra114_pll_init()
1069 	clk = tegra_clk_register_pllc("pll_c2", "pll_ref", clk_base, pmc, 0,  in tegra114_pll_init()
1074 	clk = tegra_clk_register_pllc("pll_c3", "pll_ref", clk_base, pmc, 0,  in tegra114_pll_init()
1079 	clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc,  in tegra114_pll_init()
1086 				clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,  in tegra114_pll_init()
1089 				clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |  in tegra114_pll_init()
1098 	val = readl(clk_base + pll_u_params.base_reg);  in tegra114_pll_init()
1100 	writel(val, clk_base + pll_u_params.base_reg);  in tegra114_pll_init()
1102 	clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc, 0,  in tegra114_pll_init()
1106 	tegra114_utmi_param_configure(clk_base);  in tegra114_pll_init()
1110 				CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,  in tegra114_pll_init()
1130 	clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0,  in tegra114_pll_init()
1140 	clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc, 0,  in tegra114_pll_init()
1150 	clk = tegra_clk_register_pllre("pll_re_vco", "pll_ref", clk_base, pmc,  in tegra114_pll_init()
1155 					 clk_base + PLLRE_BASE, 16, 4, 0,  in tegra114_pll_init()
1161 				      clk_base, 0, &pll_e_params, NULL);  in tegra114_pll_init()
1171 static __init void tegra114_periph_clk_init(void __iomem *clk_base,  in tegra114_periph_clk_init()  argument
1187 			       clk_base + PLLD_BASE, 25, 1, 0, &pll_d_lock);  in tegra114_periph_clk_init()
1194 			       clk_base + PLLD2_BASE, 25, 1, 0, &pll_d2_lock);  in tegra114_periph_clk_init()
1197 	clk = tegra_clk_register_periph_gate("dsia", "dsia_mux", 0, clk_base,  in tegra114_periph_clk_init()
1201 	clk = tegra_clk_register_periph_gate("dsib", "dsib_mux", 0, clk_base,  in tegra114_periph_clk_init()
1209 			       clk_base + CLK_SOURCE_EMC,  in tegra114_periph_clk_init()
1212 	clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,  in tegra114_periph_clk_init()
1220 			&data->periph, clk_base, data->offset, data->flags);  in tegra114_periph_clk_init()
1224 	tegra_periph_clk_init(clk_base, pmc_base, tegra114_clks,  in tegra114_periph_clk_init()
1234 		reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);  in tegra114_wait_cpu_in_reset()
1249 				readl(clk_base + CLK_SOURCE_CSITE);  in tegra114_cpu_clock_suspend()
1250 	writel(3 << 30, clk_base + CLK_SOURCE_CSITE);  in tegra114_cpu_clock_suspend()
1253 				readl(clk_base + CCLKG_BURST_POLICY);  in tegra114_cpu_clock_suspend()
1255 				readl(clk_base + CCLKG_BURST_POLICY + 4);  in tegra114_cpu_clock_suspend()
1261 					clk_base + CLK_SOURCE_CSITE);  in tegra114_cpu_clock_resume()
1264 					clk_base + CCLKG_BURST_POLICY);  in tegra114_cpu_clock_resume()
1266 					clk_base + CCLKG_BURST_POLICY + 4);  in tegra114_cpu_clock_resume()
1336 	readl_relaxed(clk_base + CPU_FINETRIM_SELECT);  in tegra114_car_barrier()
1354 	writel_relaxed(select, clk_base + CPU_FINETRIM_SELECT);  in tegra114_clock_tune_cpu_trimmers_high()
1381 	writel_relaxed(select, clk_base + CPU_FINETRIM_SELECT);  in tegra114_clock_tune_cpu_trimmers_low()
1403 	writel_relaxed(r, clk_base + CPU_FINETRIM_R);  in tegra114_clock_tune_cpu_trimmers_init()
1412 	writel_relaxed(dr, clk_base + CPU_FINETRIM_DR);  in tegra114_clock_tune_cpu_trimmers_init()
1427 	v = readl_relaxed(clk_base + RST_DFLL_DVCO);  in tegra114_clock_assert_dfll_dvco_reset()
1429 	writel_relaxed(v, clk_base + RST_DFLL_DVCO);  in tegra114_clock_assert_dfll_dvco_reset()
1444 	v = readl_relaxed(clk_base + RST_DFLL_DVCO);  in tegra114_clock_deassert_dfll_dvco_reset()
1446 	writel_relaxed(v, clk_base + RST_DFLL_DVCO);  in tegra114_clock_deassert_dfll_dvco_reset()
1455 	clk_base = of_iomap(np, 0);  in tegra114_clock_init()
1456 	if (!clk_base) {  in tegra114_clock_init()
1475 	clks = tegra_clk_init(clk_base, TEGRA114_CLK_CLK_MAX,  in tegra114_clock_init()
1480 	if (tegra_osc_clk_init(clk_base, tegra114_clks, tegra114_input_freq,  in tegra114_clock_init()
1485 	tegra114_fixed_clk_init(clk_base);  in tegra114_clock_init()
1486 	tegra114_pll_init(clk_base, pmc_base);  in tegra114_clock_init()
1487 	tegra114_periph_clk_init(clk_base, pmc_base);  in tegra114_clock_init()
1488 	tegra_audio_clk_init(clk_base, pmc_base, tegra114_clks,  in tegra114_clock_init()
1492 	tegra_super_clk_gen4_init(clk_base, pmc_base, tegra114_clks,  in tegra114_clock_init()