Lines Matching refs:clk_base
139 static void __iomem *clk_base; variable
584 u32 osc_ctrl = readl_relaxed(clk_base + OSC_CTRL); in tegra20_clk_measure_input_freq()
618 u32 pll_ref_div = readl_relaxed(clk_base + OSC_CTRL) & in tegra20_get_pll_ref_div()
640 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, NULL, 0, in tegra20_pll_init()
646 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra20_pll_init()
649 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT, in tegra20_pll_init()
654 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, NULL, in tegra20_pll_init()
661 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra20_pll_init()
664 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED | in tegra20_pll_init()
669 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, NULL, 0, in tegra20_pll_init()
674 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, NULL, 0, in tegra20_pll_init()
679 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, NULL, 0, in tegra20_pll_init()
689 clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, NULL, 0, in tegra20_pll_init()
695 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra20_pll_init()
698 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED | in tegra20_pll_init()
703 clk = tegra_clk_register_plle("pll_e", "pll_ref", clk_base, pmc_base, in tegra20_pll_init()
722 clk_base + CCLK_BURST_POLICY, 0, 4, 0, 0, NULL); in tegra20_super_clk_init()
728 clk_base + SCLK_BURST_POLICY, 0, 4, 0, 0, NULL); in tegra20_super_clk_init()
748 clk_base + AUDIO_SYNC_CLK, 0, 3, 0, NULL); in tegra20_audio_clk_init()
750 clk_base + AUDIO_SYNC_CLK, 4, in tegra20_audio_clk_init()
758 TEGRA_PERIPH_NO_RESET, clk_base, in tegra20_audio_clk_init()
810 clk_base, 0, 3, periph_clk_enb_refcnt); in tegra20_periph_clk_init()
814 clk = tegra_clk_register_periph_gate("apbdma", "pclk", 0, clk_base, in tegra20_periph_clk_init()
822 clk_base + CLK_SOURCE_EMC, in tegra20_periph_clk_init()
824 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0, in tegra20_periph_clk_init()
828 clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC, in tegra20_periph_clk_init()
833 clk = tegra_clk_register_periph_gate("dsi", "pll_d", 0, clk_base, 0, in tegra20_periph_clk_init()
839 clk = tegra_clk_register_periph_gate("pex", "clk_m", 0, clk_base, 0, 70, in tegra20_periph_clk_init()
847 clk_base, 0, 94, periph_clk_enb_refcnt); in tegra20_periph_clk_init()
854 clk_base, 0, 93, periph_clk_enb_refcnt); in tegra20_periph_clk_init()
861 clk_base, data->offset, data->flags); in tegra20_periph_clk_init()
870 clk_base, data->offset); in tegra20_periph_clk_init()
874 tegra_periph_clk_init(clk_base, pmc_base, tegra20_clks, &pll_p_params); in tegra20_periph_clk_init()
903 reg = readl(clk_base + in tegra20_wait_cpu_in_reset()
914 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET); in tegra20_put_cpu_in_reset()
921 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR); in tegra20_cpu_out_of_reset()
929 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); in tegra20_enable_cpu_clock()
931 clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); in tegra20_enable_cpu_clock()
933 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); in tegra20_enable_cpu_clock()
940 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); in tegra20_disable_cpu_clock()
942 clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); in tegra20_disable_cpu_clock()
950 cpu_rst_status = readl(clk_base + in tegra20_cpu_rail_off_ready()
960 readl(clk_base + CLK_SOURCE_CSITE); in tegra20_cpu_clock_suspend()
961 writel(3<<30, clk_base + CLK_SOURCE_CSITE); in tegra20_cpu_clock_suspend()
964 readl(clk_base + CCLK_BURST_POLICY); in tegra20_cpu_clock_suspend()
966 readl(clk_base + PLLX_BASE); in tegra20_cpu_clock_suspend()
968 readl(clk_base + PLLX_MISC); in tegra20_cpu_clock_suspend()
970 readl(clk_base + SUPER_CCLK_DIVIDER); in tegra20_cpu_clock_suspend()
978 reg = readl(clk_base + CCLK_BURST_POLICY); in tegra20_cpu_clock_resume()
991 clk_base + PLLX_MISC); in tegra20_cpu_clock_resume()
993 clk_base + PLLX_BASE); in tegra20_cpu_clock_resume()
1005 clk_base + SUPER_CCLK_DIVIDER); in tegra20_cpu_clock_resume()
1007 clk_base + CCLK_BURST_POLICY); in tegra20_cpu_clock_resume()
1010 clk_base + CLK_SOURCE_CSITE); in tegra20_cpu_clock_resume()
1095 clk_base = of_iomap(np, 0); in tegra20_clock_init()
1096 if (!clk_base) { in tegra20_clock_init()
1113 clks = tegra_clk_init(clk_base, TEGRA20_CLK_CLK_MAX, in tegra20_clock_init()
1122 tegra_super_clk_gen4_init(clk_base, pmc_base, tegra20_clks, NULL); in tegra20_clock_init()