173 static void __iomem *clk_base;  variable
882 	reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);  in tegra30_utmi_param_configure()
899 	writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);  in tegra30_utmi_param_configure()
902 	reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);  in tegra30_utmi_param_configure()
917 	writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);  in tegra30_utmi_param_configure()
927 	clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, pmc_base, 0,  in tegra30_pll_init()
933 				clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,  in tegra30_pll_init()
936 				clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT,  in tegra30_pll_init()
941 	clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, pmc_base,  in tegra30_pll_init()
948 				clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,  in tegra30_pll_init()
951 				clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |  in tegra30_pll_init()
956 	clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, pmc_base, 0,  in tegra30_pll_init()
966 	clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc_base, 0,  in tegra30_pll_init()
973 	clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc_base, 0,  in tegra30_pll_init()
983 	clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc_base, 0,  in tegra30_pll_init()
996 			       clk_base + PLLE_AUX, 2, 1, 0, NULL);  in tegra30_pll_init()
997 	clk = tegra_clk_register_plle("pll_e", "pll_e_mux", clk_base, pmc_base,  in tegra30_pll_init()
1022 				clk_base + SUPER_CCLKG_DIVIDER, 0,  in tegra30_super_clk_init()
1031 				clk_base + SUPER_CCLKG_DIVIDER, 0,  in tegra30_super_clk_init()
1040 				clk_base + SUPER_CCLKG_DIVIDER, 0,  in tegra30_super_clk_init()
1048 				  clk_base + CCLKG_BURST_POLICY,  in tegra30_super_clk_init()
1057 				clk_base + SUPER_CCLKLP_DIVIDER, 0,  in tegra30_super_clk_init()
1066 				clk_base + SUPER_CCLKG_DIVIDER, 0,  in tegra30_super_clk_init()
1075 				clk_base + SUPER_CCLKLP_DIVIDER, 0,  in tegra30_super_clk_init()
1083 				  clk_base + CCLKLP_BURST_POLICY,  in tegra30_super_clk_init()
1092 				  clk_base + SCLK_BURST_POLICY,  in tegra30_super_clk_init()
1101 	tegra_super_clk_gen4_init(clk_base, pmc_base, tegra30_clks, NULL);  in tegra30_super_clk_init()
1141 	clk = tegra_clk_register_periph_gate("dsia", "pll_d_out0", 0, clk_base,  in tegra30_periph_clk_init()
1146 	clk = tegra_clk_register_periph_gate("pcie", "clk_m", 0, clk_base, 0,  in tegra30_periph_clk_init()
1151 	clk = tegra_clk_register_periph_gate("afi", "clk_m", 0, clk_base, 0, 72,  in tegra30_periph_clk_init()
1159 			       clk_base + CLK_SOURCE_EMC,  in tegra30_periph_clk_init()
1161 	clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0,  in tegra30_periph_clk_init()
1165 	clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,  in tegra30_periph_clk_init()
1170 	clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,  in tegra30_periph_clk_init()
1175 	clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX,  in tegra30_periph_clk_init()
1183 				clk_base, data->offset, data->flags);  in tegra30_periph_clk_init()
1192 					clk_base, data->offset);  in tegra30_periph_clk_init()
1196 	tegra_periph_clk_init(clk_base, pmc_base, tegra30_clks, &pll_p_params);  in tegra30_periph_clk_init()
1205 		reg = readl(clk_base +  in tegra30_wait_cpu_in_reset()
1216 	       clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);  in tegra30_put_cpu_in_reset()
1223 	       clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);  in tegra30_cpu_out_of_reset()
1233 	       clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);  in tegra30_enable_cpu_clock()
1234 	reg = readl(clk_base +  in tegra30_enable_cpu_clock()
1243 	reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);  in tegra30_disable_cpu_clock()
1245 	       clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);  in tegra30_disable_cpu_clock()
1254 	cpu_rst_status = readl(clk_base +  in tegra30_cpu_rail_off_ready()
1270 				readl(clk_base + CLK_RESET_SOURCE_CSITE);  in tegra30_cpu_clock_suspend()
1271 	writel(3<<30, clk_base + CLK_RESET_SOURCE_CSITE);  in tegra30_cpu_clock_suspend()
1274 				readl(clk_base + CLK_RESET_CCLK_BURST);  in tegra30_cpu_clock_suspend()
1276 				readl(clk_base + CLK_RESET_PLLX_BASE);  in tegra30_cpu_clock_suspend()
1278 				readl(clk_base + CLK_RESET_PLLX_MISC);  in tegra30_cpu_clock_suspend()
1280 				readl(clk_base + CLK_RESET_CCLK_DIVIDER);  in tegra30_cpu_clock_suspend()
1288 	reg = readl(clk_base + CLK_RESET_CCLK_BURST);  in tegra30_cpu_clock_resume()
1301 					clk_base + CLK_RESET_PLLX_MISC);  in tegra30_cpu_clock_resume()
1303 					clk_base + CLK_RESET_PLLX_BASE);  in tegra30_cpu_clock_resume()
1315 					clk_base + CLK_RESET_CCLK_DIVIDER);  in tegra30_cpu_clock_resume()
1317 					clk_base + CLK_RESET_CCLK_BURST);  in tegra30_cpu_clock_resume()
1320 					clk_base + CLK_RESET_SOURCE_CSITE);  in tegra30_cpu_clock_resume()
1416 	clk_base = of_iomap(np, 0);  in tegra30_clock_init()
1417 	if (!clk_base) {  in tegra30_clock_init()
1434 	clks = tegra_clk_init(clk_base, TEGRA30_CLK_CLK_MAX,  in tegra30_clock_init()
1439 	if (tegra_osc_clk_init(clk_base, tegra30_clks, tegra30_input_freq,  in tegra30_clock_init()
1449 	tegra_audio_clk_init(clk_base, pmc_base, tegra30_clks,  in tegra30_clock_init()