139 static void __iomem *clk_base;  variable
1025 static void tegra124_utmi_param_configure(void __iomem *clk_base)  in tegra124_utmi_param_configure()  argument
1041 	reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);  in tegra124_utmi_param_configure()
1058 	writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);  in tegra124_utmi_param_configure()
1061 	reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);  in tegra124_utmi_param_configure()
1076 	writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);  in tegra124_utmi_param_configure()
1079 	reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);  in tegra124_utmi_param_configure()
1083 	writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);  in tegra124_utmi_param_configure()
1085 	reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);  in tegra124_utmi_param_configure()
1088 	writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);  in tegra124_utmi_param_configure()
1094 	reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);  in tegra124_utmi_param_configure()
1097 	writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);  in tegra124_utmi_param_configure()
1102 	reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);  in tegra124_utmi_param_configure()
1104 	writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);  in tegra124_utmi_param_configure()
1107 static __init void tegra124_periph_clk_init(void __iomem *clk_base,  in tegra124_periph_clk_init()  argument
1118 				clk_base + PLLD_MISC, 30, 0, &pll_d_lock);  in tegra124_periph_clk_init()
1122 					     clk_base, 0, 48,  in tegra124_periph_clk_init()
1127 					     clk_base, 0, 82,  in tegra124_periph_clk_init()
1131 	clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC,  in tegra124_periph_clk_init()
1136 	clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,  in tegra124_periph_clk_init()
1142 	clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX,  in tegra124_periph_clk_init()
1147 	tegra_periph_clk_init(clk_base, pmc_base, tegra124_clks, &pll_p_params);  in tegra124_periph_clk_init()
1150 static void __init tegra124_pll_init(void __iomem *clk_base,  in tegra124_pll_init()  argument
1157 	clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base,  in tegra124_pll_init()
1164 			clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,  in tegra124_pll_init()
1167 				clk_base + PLLC_OUT, 1, 0,  in tegra124_pll_init()
1179 	clk = tegra_clk_register_pllc("pll_c2", "pll_ref", clk_base, pmc, 0,  in tegra124_pll_init()
1185 	clk = tegra_clk_register_pllc("pll_c3", "pll_ref", clk_base, pmc, 0,  in tegra124_pll_init()
1191 	clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc,  in tegra124_pll_init()
1199 				clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,  in tegra124_pll_init()
1202 				clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |  in tegra124_pll_init()
1214 	val = readl(clk_base + pll_u_params.base_reg);  in tegra124_pll_init()
1216 	writel(val, clk_base + pll_u_params.base_reg);  in tegra124_pll_init()
1218 	clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc, 0,  in tegra124_pll_init()
1223 	tegra124_utmi_param_configure(clk_base);  in tegra124_pll_init()
1227 				CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,  in tegra124_pll_init()
1251 	clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0,  in tegra124_pll_init()
1263 	clk = tegra_clk_register_pllre("pll_re_vco", "pll_ref", clk_base, pmc,  in tegra124_pll_init()
1269 					 clk_base + PLLRE_BASE, 16, 4, 0,  in tegra124_pll_init()
1276 				      clk_base, 0, &pll_e_params, NULL);  in tegra124_pll_init()
1281 	clk = tegra_clk_register_pllss("pll_c4", "pll_ref", clk_base, 0,  in tegra124_pll_init()
1287 	clk = tegra_clk_register_pllss("pll_dp", "pll_ref", clk_base, 0,  in tegra124_pll_init()
1293 	clk = tegra_clk_register_pllss("pll_d2", "pll_ref", clk_base, 0,  in tegra124_pll_init()
1312 		reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);  in tegra124_wait_cpu_in_reset()
1327 				readl(clk_base + CLK_SOURCE_CSITE);  in tegra124_cpu_clock_suspend()
1328 	writel(3 << 30, clk_base + CLK_SOURCE_CSITE);  in tegra124_cpu_clock_suspend()
1331 				readl(clk_base + CCLKG_BURST_POLICY);  in tegra124_cpu_clock_suspend()
1333 				readl(clk_base + CCLKG_BURST_POLICY + 4);  in tegra124_cpu_clock_suspend()
1339 				clk_base + CLK_SOURCE_CSITE);  in tegra124_cpu_clock_resume()
1342 					clk_base + CCLKG_BURST_POLICY);  in tegra124_cpu_clock_resume()
1344 					clk_base + CCLKG_BURST_POLICY + 4);  in tegra124_cpu_clock_resume()
1446 	readl_relaxed(clk_base + RST_DFLL_DVCO);  in tegra124_car_barrier()
1458 	v = readl_relaxed(clk_base + RST_DFLL_DVCO);  in tegra124_clock_assert_dfll_dvco_reset()
1460 	writel_relaxed(v, clk_base + RST_DFLL_DVCO);  in tegra124_clock_assert_dfll_dvco_reset()
1474 	v = readl_relaxed(clk_base + RST_DFLL_DVCO);  in tegra124_clock_deassert_dfll_dvco_reset()
1476 	writel_relaxed(v, clk_base + RST_DFLL_DVCO);  in tegra124_clock_deassert_dfll_dvco_reset()
1529 	clk_base = of_iomap(np, 0);  in tegra124_132_clock_init_pre()
1530 	if (!clk_base) {  in tegra124_132_clock_init_pre()
1549 	clks = tegra_clk_init(clk_base, TEGRA124_CLK_CLK_MAX,  in tegra124_132_clock_init_pre()
1554 	if (tegra_osc_clk_init(clk_base, tegra124_clks, tegra124_input_freq,  in tegra124_132_clock_init_pre()
1560 	tegra124_pll_init(clk_base, pmc_base);  in tegra124_132_clock_init_pre()
1561 	tegra124_periph_clk_init(clk_base, pmc_base);  in tegra124_132_clock_init_pre()
1562 	tegra_audio_clk_init(clk_base, pmc_base, tegra124_clks,  in tegra124_132_clock_init_pre()
1568 	plld_base = clk_readl(clk_base + PLLD_BASE);  in tegra124_132_clock_init_pre()
1570 	clk_writel(plld_base, clk_base + PLLD_BASE);  in tegra124_132_clock_init_pre()
1585 	tegra_super_clk_gen4_init(clk_base, pmc_base, tegra124_clks,  in tegra124_132_clock_init_post()
1591 	clks[TEGRA124_CLK_EMC] = tegra_clk_register_emc(clk_base, np,  in tegra124_132_clock_init_post()