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Searched refs:c7 (Results 1 – 78 of 78) sorted by relevance

/linux-4.4.14/arch/arm/mm/
Dproc-arm1020.S99 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
100 mcr p15, 0, ip, c7, c10, 4 @ drain WB
102 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
117 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
132 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
155 mcr p15, 0, ip, c7, c10, 4 @ drain WB
158 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
159 mcr p15, 0, ip, c7, c10, 4 @ drain WB
167 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
169 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
[all …]
Dproc-mohawk.S75 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
76 mcr p15, 0, ip, c7, c10, 4 @ drain WB
77 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
94 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
95 mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt
105 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
127 mcr p15, 0, ip, c7, c14, 0 @ clean & invalidate all D cache
129 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
130 mcrne p15, 0, ip, c7, c10, 0 @ drain write buffer
151 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
[all …]
Dproc-arm926.S83 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
84 mcr p15, 0, ip, c7, c10, 4 @ drain WB
86 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
105 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
111 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
123 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
146 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
148 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate
152 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
153 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
[all …]
Dcache-fa.S48 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
69 mcr p15, 0, ip, c7, c14, 0 @ clean/invalidate D cache
71 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
72 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
73 mcrne p15, 0, ip, c7, c10, 4 @ drain write buffer
74 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
94 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I line
95 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
100 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
101 mcrne p15, 0, ip, c7, c10, 4 @ data write barrier
[all …]
Dproc-arm925.S123 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
124 mcr p15, 0, ip, c7, c10, 4 @ drain WB
126 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
143 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
146 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
157 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
180 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
184 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
189 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
190 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
[all …]
Dproc-arm920.S91 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
92 mcr p15, 0, ip, c7, c10, 4 @ drain WB
94 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
109 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
122 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
146 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
152 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
153 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
172 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
174 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
[all …]
Dcache-v6.S43 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
44 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
45 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
46 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
52 mcr p15, 0, r0, c7, c5, 0 @ invalidate I-cache
67 mcr p15, 0, r0, c7, c14, 0 @ D cache clean+invalidate
69 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
74 mcr p15, 0, r0, c7, c15, 0 @ Cache clean+invalidate
137 USER( mcr p15, 0, r0, c7, c10, 1 ) @ clean D line
144 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
[all …]
Dproc-arm922.S93 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
94 mcr p15, 0, ip, c7, c10, 4 @ drain WB
96 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
111 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
124 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
148 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
154 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
155 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
174 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
176 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
[all …]
Dproc-arm1020e.S99 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
100 mcr p15, 0, ip, c7, c10, 4 @ drain WB
102 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
117 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
132 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
155 mcr p15, 0, ip, c7, c10, 4 @ drain WB
158 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
166 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
168 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
188 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
[all …]
Dproc-arm946.S61 mcr p15, 0, ip, c7, c5, 0 @ flush I cache
62 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
63 mcr p15, 0, ip, c7, c10, 4 @ drain WB
77 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
87 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
107 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
111 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index
118 mcrne p15, 0, ip, c7, c5, 0 @ flush I cache
119 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
141 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
[all …]
Dproc-fa526.S63 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
64 mcr p15, 0, ip, c7, c10, 4 @ drain WB
66 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
88 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
92 mcr p15, 0, r0, c7, c10, 4 @ drain WB
109 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
111 mcr p15, 0, ip, c7, c14, 0 @ clean and invalidate whole D cache
113 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
114 mcr p15, 0, ip, c7, c5, 6 @ invalidate BTB since mm changed
115 mcr p15, 0, ip, c7, c10, 4 @ data write barrier
[all …]
Dproc-arm1026.S90 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
91 mcr p15, 0, ip, c7, c10, 4 @ drain WB
93 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
108 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
123 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
146 1: mrc p15, 0, r15, c7, c14, 3 @ test, clean, invalidate
151 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
153 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
173 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
180 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
[all …]
Dproc-arm1022.S90 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
91 mcr p15, 0, ip, c7, c10, 4 @ drain WB
93 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
108 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
123 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
148 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
156 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
158 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
178 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
185 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
[all …]
Dproc-feroceon.S82 mcr p15, 0, r0, c7, c10, 4 @ drain WB
104 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
105 mcr p15, 0, ip, c7, c10, 4 @ drain WB
107 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
125 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
126 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
136 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
162 2: mcr p15, 0, ip, c7, c14, 2 @ clean + invalidate D set/way
170 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
171 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
[all …]
Dproc-xsc3.S71 1: mcr p15, 0, \rd, c7, c14, 2 @ clean/invalidate L1 D line
116 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB
121 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
140 mcr p14, 0, r0, c7, c0, 0 @ go to idle
152 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
176 mcrne p15, 0, ip, c7, c5, 0 @ invalidate L1 I cache and BTB
177 mcrne p15, 0, ip, c7, c10, 4 @ data write barrier
178 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
199 mcrne p15, 0, r0, c7, c5, 1 @ invalidate L1 I line
200 mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
[all …]
Dcache-v4wb.S61 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
80 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
97 mcr p15, 0, ip, c7, c10, 4 @ drain write buffer
114 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
119 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
120 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
125 mcrne p15, 0, ip, c7, c10, 4 @ drain write buffer
166 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
167 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
172 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
[all …]
Dproc-xscale.S94 1: mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
96 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
98 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
100 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
158 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches & BTB
162 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
181 mcr p14, 0, r0, c7, c0, 0 @ Go to IDLE
193 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
217 mcrne p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB
218 mcrne p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
[all …]
Dproc-arm940.S54 mcr p15, 0, ip, c7, c5, 0 @ flush I cache
55 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
56 mcr p15, 0, ip, c7, c10, 4 @ drain WB
70 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
80 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
112 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
116 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index
123 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
124 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
166 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index
[all …]
Dproc-arm720.S80 mcr p15, 0, r1, c7, c7, 0 @ invalidate cache
82 mcr p15, 0, r1, c8, c7, 0 @ flush TLB (v4)
107 mcr p15, 0, ip, c7, c7, 0 @ invalidate cache
109 mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4)
122 mcr p15, 0, r0, c7, c7, 0 @ invalidate caches
124 mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
150 mcr p15, 0, r0, c7, c7, 0 @ invalidate caches
152 mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
Dtlb-fa.S43 mcr p15, 0, r3, c7, c10, 4 @ drain WB
46 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry
50 mcr p15, 0, r3, c7, c10, 4 @ data write barrier
56 mcr p15, 0, r3, c7, c10, 4 @ drain WB
59 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry
63 mcr p15, 0, r3, c7, c10, 4 @ data write barrier
64 mcr p15, 0, r3, c7, c5, 4 @ prefetch flush (isb)
Dcache-v4.S43 mcr p15, 0, r0, c7, c7, 0 @ flush ID cache
62 mcr p15, 0, ip, c7, c7, 0 @ flush ID cache
118 mcr p15, 0, r0, c7, c7, 0 @ flush ID cache
Dproc-sa110.S68 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
69 mcr p15, 0, ip, c7, c10, 4 @ drain WB
71 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
120 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
141 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
157 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
158 mcr p15, 0, r0, c7, c10, 4 @ drain WB
165 mcr p15, 0, r10, c7, c7 @ invalidate I,D caches on v4
166 mcr p15, 0, r10, c7, c10, 4 @ drain write buffer on v4
168 mcr p15, 0, r10, c8, c7 @ invalidate I,D TLBs on v4
Dproc-sa1100.S76 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
77 mcr p15, 0, ip, c7, c10, 4 @ drain WB
79 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
130 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
152 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
168 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
169 mcr p15, 0, r0, c7, c10, 4 @ drain WB
188 mcr p15, 0, ip, c8, c7, 0 @ flush I+D TLBs
189 mcr p15, 0, ip, c7, c7, 0 @ flush I&D cache
204 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
[all …]
Dcache-v4wt.S51 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
73 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
74 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
92 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
94 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
125 1: mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
143 mcr p15, 0, r2, c7, c5, 0 @ invalidate I cache
160 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
Dproc-v6.S64 mcr p15, 0, r1, c7, c5, 4 @ ISB
78 mcr p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode
79 mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt
83 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
105 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
106 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer
156 mcr p15, 0, ip, c7, c14, 0 @ clean+invalidate D cache
157 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
158 mcr p15, 0, ip, c7, c15, 0 @ clean+invalidate cache
159 mcr p15, 0, ip, c7, c10, 4 @ drain write buffer
[all …]
Dtlb-v6.S40 mcr p15, 0, ip, c7, c10, 4 @ drain write buffer
53 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA (was 1)
58 mcr p15, 0, ip, c7, c10, 4 @ data synchronization barrier
71 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer
81 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA
86 mcr p15, 0, r2, c7, c10, 4 @ data synchronization barrier
87 mcr p15, 0, r2, c7, c5, 4 @ prefetch flush (isb)
Dcache-v7.S58 mcr p15, 0, r5, c7, c6, 2
77 ALT_SMP(mcr p15, 0, r0, c7, c1, 0) @ invalidate I-cache inner shareable
78 ALT_UP(mcr p15, 0, r0, c7, c5, 0) @ I+BTB cache invalidate
157 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
190 ALT_SMP(mcr p15, 0, r0, c7, c1, 0) @ invalidate I-cache inner shareable
191 ALT_UP(mcr p15, 0, r0, c7, c5, 0) @ I+BTB cache invalidate
208 ALT_SMP(mcr p15, 0, r0, c7, c1, 0) @ invalidate I-cache inner shareable
209 ALT_UP(mcr p15, 0, r0, c7, c5, 0) @ I+BTB cache invalidate
281 USER( mcr p15, 0, r12, c7, c11, 1 ) @ clean D line to the point of unification
290 USER( mcr p15, 0, r12, c7, c5, 1 ) @ invalidate I line
[all …]
Dabort-ev7.S34 mcr p15, 0, r0, c7, c8, 0 @ Retranslate FAR
36 mrc p15, 0, ip, c7, c4, 0 @ Read the PAR
Dtlb-v4wb.S39 mcr p15, 0, r3, c7, c10, 4 @ drain WB
61 mcr p15, 0, r3, c7, c10, 4 @ drain WB
Dtlb-v4wbi.S38 mcr p15, 0, r3, c7, c10, 4 @ drain WB
52 mcr p15, 0, r3, c7, c10, 4 @ drain WB
Dproc-arm740.S55 mcr p15, 0, ip, c7, c0, 0 @ invalidate cache
66 mcr p15, 0, r0, c7, c0, 0 @ invalidate caches
72 mcr p15, 0, r0, c6, c7
Dtlb-v7.S54 ALT_UP(mcr p15, 0, r0, c8, c7, 1) @ TLB invalidate U MVA
83 ALT_UP(mcr p15, 0, r0, c8, c7, 1) @ TLB invalidate U MVA
Dpv-fixup-asm.S78 mcr p15, 0, ip, c7, c5, 0 @ I+BTB cache invalidate
79 mcr p15, 0, ip, c8, c7, 0 @ local_flush_tlb_all()
Dproc-v7-2level.S47 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
113 ALT_UP (mcr p15, 0, r0, c7, c10, 1) @ flush_pte
Dtlb-v4.S41 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate TLB entry
Dproc-macros.S174 mcr p15, 0, r0, c7, c10, 1 @ flush_pte
257 mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
258 mcr p15, 0, ip, c7, c10, 4 @ data write barrier
Dproc-v7.S82 2: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
120 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
127 mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs
449 mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
451 mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
Dproc-v7-3level.S99 ALT_UP (mcr p15, 0, r0, c7, c10, 1) @ flush_pte
/linux-4.4.14/arch/arm/include/asm/hardware/
Dcp14.h57 #define RCP14_DBGVCR() MRC14(0, c0, c7, 0)
72 #define RCP14_DBGBVR7() MRC14(0, c0, c7, 4)
88 #define RCP14_DBGBCR7() MRC14(0, c0, c7, 5)
104 #define RCP14_DBGWVR7() MRC14(0, c0, c7, 6)
120 #define RCP14_DBGWCR7() MRC14(0, c0, c7, 7)
137 #define RCP14_DBGBXVR7() MRC14(0, c1, c7, 1)
152 #define RCP14_DBGITCTRL() MRC14(0, c7, c0, 4)
153 #define RCP14_DBGCLAIMSET() MRC14(0, c7, c8, 6)
154 #define RCP14_DBGCLAIMCLR() MRC14(0, c7, c9, 6)
155 #define RCP14_DBGAUTHSTATUS() MRC14(0, c7, c14, 6)
[all …]
/linux-4.4.14/arch/arm/boot/compressed/
Dhead.S618 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
619 mcr p15, 0, r0, c6, c7, 1
631 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
632 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
633 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
642 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
643 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
648 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
658 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
671 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
[all …]
Dhead-xscale.S26 mcr p15, 0, r0, c7, c10, 4 @ drain WB
27 mcr p15, 0, r0, c7, c7, 0 @ flush I & D caches
/linux-4.4.14/arch/arm/mach-s3c24xx/
Dsleep-s3c2412.S52 mcr p15, 0, r0, c7, c10, 4
53 mcrne p15, 0, r0, c7, c0, 4
/linux-4.4.14/arch/arm/kvm/
Dinterrupts.S92 mcr p15, 0, r0, c7, c1, 0
446 mrrc p15, 0, r0, r1, c7 @ PAR
450 mcr p15, 0, r2, c7, c8, 0 @ ATS1CPR
452 mrrc p15, 0, r0, r1, c7 @ PAR
461 mcrr p15, 0, r0, r1, c7 @ PAR
470 mcrr p15, 0, r0, r1, c7 @ PAR
Dinit.S103 mcr p15, 4, r0, c8, c7, 0 @ TLBIALLH
Dinterrupts_head.S306 mrrc p15, 0, r4, r5, c7 @ PAR
340 mcrr p15, 0, r4, r5, c7 @ PAR
/linux-4.4.14/arch/arm/mach-omap1/
Dsleep.S73 mcr p15, 0, r0, c7, c10, 4
119 mcr p15, 0, r2, c7, c0, 4 @ wait for interrupt
202 mcr p15, 0, r2, c7, c0, 4 @ wait for interrupt
228 mcr p15, 0, r0, c7, c10, 4
268 mcr p15, 0, r2, c7, c0, 4 @ wait for interrupt
/linux-4.4.14/arch/arm/mach-omap2/
Dsleep24xx.S69 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, hope SDR/DDR finished
77 mcr p15, 0, r3, c7, c0, 4 @ wait for interrupt
Domap-smc.S52 mcr p15, 0, r7, c7, c5, 6
Dsram242x.S152 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, finish ARM SDR/DDR
181 mcr p15, 0, r3, c7, c10, 4 @ memory barrier
Dsram243x.S152 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, finish ARM SDR/DDR
181 mcr p15, 0, r3, c7, c10, 4 @ memory barrier
/linux-4.4.14/arch/arm/mach-pxa/
Dstandby.S30 1: mcr p14, 0, r2, c7, c0, 0 @ put the system into Standby
64 mcr p14, 0, r0, c7, c0, 0
Dsleep.S31 mcr p14, 0, r0, c7, c0, 0 @ enter sleep
169 mcr p14, 0, r1, c7, c0, 0 @ PWRMODE
/linux-4.4.14/arch/powerpc/crypto/
Daes-tab-4k.S62 .long R(08, 04, 04, 0c), R(95, c7, c7, 52)
114 .long R(8c, 46, 46, ca), R(c7, ee, ee, 29)
137 .long R(73, b4, b4, c7), R(97, c6, c6, 51)
231 .long R(0e, 09, 0d, 0b), R(f2, 8b, c7, ad)
242 .long R(ae, f9, 32, 11), R(c7, 29, a1, 6d)
249 .long R(87, 49, 4e, c7), R(d9, 38, d1, c1)
286 .long R(18, 14, ce, 79), R(73, c7, 37, bf)
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/
Dg98.fuc0s447 ckeyreg $c7
531 ckexp $c7 $c7
547 ckexp $c7 $c7
566 ckexp $c7 $c7
/linux-4.4.14/arch/unicore32/kernel/
Dsleep.S24 movc r3, p0.c7, #0 @ PID
174 movc p0.c7, r3, #0 @ PID
/linux-4.4.14/Documentation/zh_CN/
Doops-tracing.txt97 Code: f9 0f 8d f9 00 00 00 8d 42 0c e8 dd 26 11 c7 a1 60 ea 2b f9 8b 50 08 a1
175 Aug 29 09:51:01 blizard kernel: Code: c7 00 05 00 00 00 eb 08 90 90 90 90 90 90 90 90 89 ec 5d c3
/linux-4.4.14/tools/power/x86/turbostat/
Dturbostat.c158 unsigned long long c7; member
420 outp += sprintf(outp, "c7: %016llX\n", c->c7); in dump_counters()
565 outp += sprintf(outp, "%8.2f", 100.0 * c->c7/t->tsc); in format_counters()
720 old->c7 = new->c7 - old->c7; in delta_core()
775 if ((old->mperf + core_delta->c3 + core_delta->c6 + core_delta->c7) > old->tsc) in delta_thread()
780 - core_delta->c6 - core_delta->c7; in delta_thread()
838 c->c7 = 0; in clear_counters()
882 average.cores.c7 += c->c7; in sum_counters()
942 average.cores.c7 /= topo.num_cores; in compute_average()
1048 if (get_msr(cpu, MSR_CORE_C7_RESIDENCY, &c->c7)) in get_counters()
/linux-4.4.14/arch/arm/mach-at91/
Dpm_suspend.S65 mcr p15, 0, tmp1, c7, c0, 4
91 mcr p15, 0, tmp1, c7, c10, 4
/linux-4.4.14/Documentation/video4linux/
DCARDLIST.cx883 2 -> GDI Black Gold [14c7:0106,14c7:0107]
DCARDLIST.bttv24 23 -> Modular Technology MM201/MM202/MM205/MM210/MM215 PCTV, bt878 [14c7:0101]
/linux-4.4.14/arch/arm/mach-imx/
Dsuspend-imx6.S315 mcr p15, 0, r6, c7, c5, 0
316 mcr p15, 0, r6, c7, c5, 6
/linux-4.4.14/Documentation/
Dstatic-keys.txt206 ffffffff810442c0: 48 c7 c7 e3 54 98 81 mov $0xffffffff819854e3,%rdi
228 ffffffff81044225: 48 c7 c7 13 53 98 81 mov $0xffffffff81985313,%rdi
Doops-tracing.txt99 Code: f9 0f 8d f9 00 00 00 8d 42 0c e8 dd 26 11 c7 a1 60 ea 2b f9 8b 50 08 a1
211 Aug 29 09:51:01 blizard kernel: Code: c7 00 05 00 00 00 eb 08 90 90 90 90 90 90 90 90 89 ec 5d c3
/linux-4.4.14/arch/x86/crypto/sha-mb/
Dsha1_x8_avx2.S74 # r2 = {c7 c6 c5 c4 c3 c2 c1 c0}
89 # r7 = {h7 g7 f7 e7 d7 c7 b7 a7}
97 vshufps $0xEE, \r3, \r2, \r2 # r2 = {d7 d6 c7 c6 d3 d2 c3 c2}
100 vshufps $0xDD, \r2, \r0, \r0 # r0 = {d7 c7 b7 a7 d3 c3 b3 a3}
/linux-4.4.14/Documentation/fmc/
Dparameters.txt31 [ 6626.174019] 0020: 63 68 61 c7 70 72 6f 74 6f 2d 30 cc 45 44 41 2d
/linux-4.4.14/arch/x86/kernel/cpu/
Dperf_event_intel_cstate.c189 PMU_EVENT_ATTR_STRING(c7-residency, evattr_cstate_core_c7, "event=0x03");
326 PMU_EVENT_ATTR_STRING(c7-residency, evattr_cstate_pkg_c7, "event=0x03");
/linux-4.4.14/arch/arm/include/asm/
Dassembler.h285 mcr p15, 0, r0, c7, c5, 4
301 ALT_SMP(mcr p15, 0, r0, c7, c10, 5) @ dmb
/linux-4.4.14/Documentation/scsi/
Daacraid.txt46 9005:0285:9005:02c7 Adaptec 3085 (Marauder08ELP)
DChangeLog.1992-1997218 * 53c7,8xx.c: crash on AEN fixed, SCSI reset is no longer a NOP,
375 * 53c7,8xx.h: Change SG size to 127.
559 * 53c7,8xx.c: Fix from Linus - emulate splx.
715 * 53c7,8xx.c: Add new PCI chip ID for 815.
1120 * 53c7,8xx.c: New file from Drew. PCI driver.
1122 * 53c7,8xx.h: Likewise.
1124 * 53c7,8xx.scr: Likewise.
/linux-4.4.14/Documentation/sysctl/
Dnet.txt164 84:50:f4:00:a8:15:d1:a7:e9:7f:1d:60:35:c7:47:25:42:97:74:ca:56:bb:b6:a1:d8: ... (52 bytes total)
175 84:50:f4:00:a8:15:d1:a7:e9:7f:1d:60:35:c7:47:25:42:97:74:ca:56:bb:b6:a1:d8:43:e3:c9:0c:fd:17:55:c2:…
/linux-4.4.14/drivers/tty/vt/
Dcp437.uni153 0x80 U+00c7
/linux-4.4.14/Documentation/networking/
Dvrf.txt199 10.2.1.254 dev eth1 lladdr a6:d9:c7:4f:06:23 REACHABLE
203 2002:1::64 dev eth1 lladdr a6:d9:c7:4f:06:23 REACHABLE
/linux-4.4.14/arch/arm/mach-tegra/
Dsleep-tegra20.S300 mcr p15, 0, r1, c7, c1, 6 @ invalidate shared BTAC
/linux-4.4.14/drivers/block/paride/
DKconfig208 bool "Support c7/c8 chips"
211 This option enables support for the newer Shuttle EP1284 (aka c7 and
/linux-4.4.14/arch/arm/kernel/
Dhw_breakpoint.c986 ARM_DBG_WRITE(c0, c7, 0, 0); in reset_ctrl_regs()
/linux-4.4.14/tools/perf/util/intel-pt-decoder/
Dx86-opcode-map.txt249 c7: Grp11B Ev,Iz (1A)
546 c7: Grp9 (1A)
/linux-4.4.14/arch/x86/lib/
Dx86-opcode-map.txt249 c7: Grp11B Ev,Iz (1A)
546 c7: Grp9 (1A)
/linux-4.4.14/Documentation/kbuild/
Dmakefiles.txt392 $(obj)/53c8xx_d.h: $(src)/53c7,8xx.scr $(src)/script_asm.pl