Lines Matching refs:c7

71 1:	mcr	p15, 0, \rd, c7, c14, 2		@ clean/invalidate L1 D line
116 	mcr	p15, 0, ip, c7, c7, 0		@ invalidate L1 caches and BTB
121 	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I and D TLBs
140 	mcr	p14, 0, r0, c7, c0, 0		@ go to idle
152 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
176 	mcrne	p15, 0, ip, c7, c5, 0		@ invalidate L1 I cache and BTB
177 	mcrne	p15, 0, ip, c7, c10, 4		@ data write barrier
178 	mcrne	p15, 0, ip, c7, c5, 4		@ prefetch flush
199 	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate L1 I line
200 	mcr	p15, 0, r0, c7, c14, 1		@ clean/invalidate L1 D line
205 	mcrne	p15, 0, ip, c7, c5, 6		@ invalidate BTB
206 	mcrne	p15, 0, ip, c7, c10, 4		@ data write barrier
207 	mcrne	p15, 0, ip, c7, c5, 4		@ prefetch flush
227 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean L1 D line
232 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate L1 I cache and BTB
233 	mcr	p15, 0, r0, c7, c10, 4		@ data write barrier
234 	mcr	p15, 0, r0, c7, c5, 4		@ prefetch flush
248 1:	mcr	p15, 0, r0, c7, c14, 1		@ clean/invalidate L1 D line
253 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate L1 I cache and BTB
254 	mcr	p15, 0, r0, c7, c10, 4		@ data write barrier
255 	mcr	p15, 0, r0, c7, c5, 4		@ prefetch flush
272 	mcrne	p15, 0, r0, c7, c10, 1		@ clean L1 D line
274 	mcrne	p15, 0, r1, c7, c10, 1		@ clean L1 D line
275 1:	mcr	p15, 0, r0, c7, c6, 1		@ invalidate L1 D line
279 	mcr	p15, 0, r0, c7, c10, 4		@ data write barrier
292 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean L1 D line
296 	mcr	p15, 0, r0, c7, c10, 4		@ data write barrier
309 1:	mcr	p15, 0, r0, c7, c14, 1		@ clean/invalidate L1 D line
313 	mcr	p15, 0, r0, c7, c10, 4		@ data write barrier
347 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean L1 D line
365 	mcr	p15, 0, ip, c7, c5, 0		@ invalidate L1 I cache and BTB
366 	mcr	p15, 0, ip, c7, c10, 4		@ data write barrier
367 	mcr	p15, 0, ip, c7, c5, 4		@ prefetch flush
370 	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I and D TLBs
433 	mcr	p15, 0, ip, c7, c7, 0	@ invalidate I & D caches, BTB
434 	mcr	p15, 0, ip, c7, c10, 4	@ drain write (&fill) buffer
435 	mcr	p15, 0, ip, c7, c5, 4	@ flush prefetch buffer
436 	mcr	p15, 0, ip, c8, c7, 0	@ invalidate I & D TLBs
453 	mcr	p15, 0, ip, c7, c7, 0		@ invalidate L1 caches and BTB
454 	mcr	p15, 0, ip, c7, c10, 4		@ data write barrier
455 	mcr	p15, 0, ip, c7, c5, 4		@ prefetch flush
456 	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I and D TLBs