Lines Matching refs:c7
63 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
64 mcr p15, 0, ip, c7, c10, 4 @ drain WB
66 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
88 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
92 mcr p15, 0, r0, c7, c10, 4 @ drain WB
109 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
111 mcr p15, 0, ip, c7, c14, 0 @ clean and invalidate whole D cache
113 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
114 mcr p15, 0, ip, c7, c5, 6 @ invalidate BTB since mm changed
115 mcr p15, 0, ip, c7, c10, 4 @ data write barrier
116 mcr p15, 0, ip, c7, c5, 4 @ prefetch flush
118 mcr p15, 0, ip, c8, c7, 0 @ invalidate UTLB
132 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
134 mcr p15, 0, r0, c7, c10, 4 @ drain WB
142 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
143 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
145 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
147 mcr p15, 0, r0, c7, c5, 5 @ invalidate IScratchpad RAM
153 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB All
154 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
155 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush