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Searched refs:__raw_readl (Results 1 – 200 of 601) sorted by relevance

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/linux-4.4.14/arch/mips/sgi-ip22/
Dip22-nvram.c35 __raw_writel(__raw_readl(ptr) & ~EEPROM_DATO, ptr); \
36 __raw_writel(__raw_readl(ptr) & ~EEPROM_ECLK, ptr); \
37 __raw_writel(__raw_readl(ptr) & ~EEPROM_EPROT, ptr); \
39 __raw_writel(__raw_readl(ptr) | EEPROM_CSEL, ptr); \
40 __raw_writel(__raw_readl(ptr) | EEPROM_ECLK, ptr); })
44 __raw_writel(__raw_readl(ptr) & ~EEPROM_ECLK, ptr); \
45 __raw_writel(__raw_readl(ptr) & ~EEPROM_CSEL, ptr); \
46 __raw_writel(__raw_readl(ptr) | EEPROM_EPROT, ptr); \
47 __raw_writel(__raw_readl(ptr) | EEPROM_ECLK, ptr); })
63 __raw_writel(__raw_readl(ctrl) | EEPROM_DATO, ctrl); in eeprom_cmd()
[all …]
/linux-4.4.14/arch/arm/mach-ks8695/
Dpci.c133 cmdstat = __raw_readl(KS8695_PCI_VA + KS8695_CRCFCS); in ks8695_pci_fault()
209 printk(KERN_INFO "PCI: CRCFID = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_CRCFID)); in ks8695_show_pciregs()
210 printk(KERN_INFO "PCI: CRCFCS = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_CRCFCS)); in ks8695_show_pciregs()
211 printk(KERN_INFO "PCI: CRCFRV = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_CRCFRV)); in ks8695_show_pciregs()
212 printk(KERN_INFO "PCI: CRCFLT = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_CRCFLT)); in ks8695_show_pciregs()
213 printk(KERN_INFO "PCI: CRCBMA = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_CRCBMA)); in ks8695_show_pciregs()
214 printk(KERN_INFO "PCI: CRCSID = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_CRCSID)); in ks8695_show_pciregs()
215 printk(KERN_INFO "PCI: CRCFIT = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_CRCFIT)); in ks8695_show_pciregs()
217 printk(KERN_INFO "PCI: PBM = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_PBM)); in ks8695_show_pciregs()
218 printk(KERN_INFO "PCI: PBCS = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_PBCS)); in ks8695_show_pciregs()
[all …]
Dcpu.c50 id = __raw_readl(KS8695_MISC_VA + KS8695_DID); in ks8695_processor_info()
51 rev = __raw_readl(KS8695_MISC_VA + KS8695_RID); in ks8695_processor_info()
61 unsigned int scdc = __raw_readl(KS8695_SYS_VA + KS8695_CLKCON) & CLKCON_SCDC; in ks8695_clock_info()
Dirq.c41 inten = __raw_readl(KS8695_IRQ_VA + KS8695_INTEN); in ks8695_irq_mask()
51 inten = __raw_readl(KS8695_IRQ_VA + KS8695_INTEN); in ks8695_irq_unmask()
72 ctrl = __raw_readl(KS8695_GPIO_VA + KS8695_IOPC); in ks8695_irq_set_type()
/linux-4.4.14/arch/arm/mach-iop13xx/
Dpci.c155 if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX) in iop13xx_atu_function()
161 if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX) in iop13xx_atu_function()
245 status = __raw_readl(IOP13XX_ATUX_ATUISR); in iop13xx_atux_pci_status()
286 __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3, in iop13xx_atux_read_config()
355 status = __raw_readl(IOP13XX_ATUE_ATUISR); in iop13xx_atue_pci_status()
366 status = __raw_readl(IOP13XX_ATUE_PIE_STS) & in iop13xx_atue_pci_status()
367 ~(__raw_readl(IOP13XX_ATUE_PIE_MSK)); in iop13xx_atue_pci_status()
371 __raw_readl(IOP13XX_ATUE_PIE_STS)); in iop13xx_atue_pci_status()
375 __raw_readl(IOP13XX_ATUE_PIE_STS)); in iop13xx_atue_pci_status()
377 __raw_readl(IOP13XX_ATUE_PIE_MSK)); in iop13xx_atue_pci_status()
[all …]
/linux-4.4.14/arch/sh/boards/mach-dreamcast/
Drtc.c38 val1 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) | in aica_rtc_gettimeofday()
39 (__raw_readl(AICA_RTC_SECS_L) & 0xffff); in aica_rtc_gettimeofday()
41 val2 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) | in aica_rtc_gettimeofday()
42 (__raw_readl(AICA_RTC_SECS_L) & 0xffff); in aica_rtc_gettimeofday()
66 val1 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) | in aica_rtc_settimeofday()
67 (__raw_readl(AICA_RTC_SECS_L) & 0xffff); in aica_rtc_settimeofday()
69 val2 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) | in aica_rtc_settimeofday()
70 (__raw_readl(AICA_RTC_SECS_L) & 0xffff); in aica_rtc_settimeofday()
/linux-4.4.14/arch/mips/alchemy/common/
Dusb.c101 r = __raw_readl(base + USB_DWC_CTRL2); in __au1300_usb_phyctl()
102 s = __raw_readl(base + USB_DWC_CTRL3); in __au1300_usb_phyctl()
130 r = __raw_readl(base + USB_DWC_CTRL3); /* enable OHCI block */ in __au1300_ohci_control()
138 r = __raw_readl(base + USB_INT_ENABLE); in __au1300_ohci_control()
147 r = __raw_readl(base + USB_INT_ENABLE); in __au1300_ohci_control()
152 r = __raw_readl(base + USB_DWC_CTRL3); in __au1300_ohci_control()
167 r = __raw_readl(base + USB_DWC_CTRL3); in __au1300_ehci_control()
172 r = __raw_readl(base + USB_DWC_CTRL1); in __au1300_ehci_control()
179 r = __raw_readl(base + USB_INT_ENABLE); in __au1300_ehci_control()
184 r = __raw_readl(base + USB_INT_ENABLE); in __au1300_ehci_control()
[all …]
Ddma.c144 __raw_readl(chan->io + DMA_MODE_SET)); in dump_au1000_dma_channel()
146 __raw_readl(chan->io + DMA_PERIPHERAL_ADDR)); in dump_au1000_dma_channel()
148 __raw_readl(chan->io + DMA_BUFFER0_START)); in dump_au1000_dma_channel()
150 __raw_readl(chan->io + DMA_BUFFER1_START)); in dump_au1000_dma_channel()
152 __raw_readl(chan->io + DMA_BUFFER0_COUNT)); in dump_au1000_dma_channel()
154 __raw_readl(chan->io + DMA_BUFFER1_COUNT)); in dump_au1000_dma_channel()
Dirq.c520 l = __raw_readl(r + AU1300_GPIC_PINCFG); in au1300_gpic_chgcfg()
586 r = __raw_readl(AU1300_GPIC_ADDR + AU1300_GPIC_DMASEL); in au1300_set_dbdma_gpio()
735 d[0] = __raw_readl(base + IC_CFG0RD); in alchemy_ic_suspend_one()
736 d[1] = __raw_readl(base + IC_CFG1RD); in alchemy_ic_suspend_one()
737 d[2] = __raw_readl(base + IC_CFG2RD); in alchemy_ic_suspend_one()
738 d[3] = __raw_readl(base + IC_SRCRD); in alchemy_ic_suspend_one()
739 d[4] = __raw_readl(base + IC_ASSIGNRD); in alchemy_ic_suspend_one()
740 d[5] = __raw_readl(base + IC_WAKERD); in alchemy_ic_suspend_one()
741 d[6] = __raw_readl(base + IC_MASKRD); in alchemy_ic_suspend_one()
784 alchemy_gpic_pmdata[0] = __raw_readl(base + AU1300_GPIC_IEN + 0x0); in alchemy_gpic_suspend()
[all …]
Ddbdma.c988 alchemy_dbdma_pm_data[0][0] = __raw_readl(addr + 0x00); in alchemy_dbdma_suspend()
989 alchemy_dbdma_pm_data[0][1] = __raw_readl(addr + 0x04); in alchemy_dbdma_suspend()
990 alchemy_dbdma_pm_data[0][2] = __raw_readl(addr + 0x08); in alchemy_dbdma_suspend()
991 alchemy_dbdma_pm_data[0][3] = __raw_readl(addr + 0x0c); in alchemy_dbdma_suspend()
996 alchemy_dbdma_pm_data[i][0] = __raw_readl(addr + 0x00); in alchemy_dbdma_suspend()
997 alchemy_dbdma_pm_data[i][1] = __raw_readl(addr + 0x04); in alchemy_dbdma_suspend()
998 alchemy_dbdma_pm_data[i][2] = __raw_readl(addr + 0x08); in alchemy_dbdma_suspend()
999 alchemy_dbdma_pm_data[i][3] = __raw_readl(addr + 0x0c); in alchemy_dbdma_suspend()
1000 alchemy_dbdma_pm_data[i][4] = __raw_readl(addr + 0x10); in alchemy_dbdma_suspend()
1001 alchemy_dbdma_pm_data[i][5] = __raw_readl(addr + 0x14); in alchemy_dbdma_suspend()
[all …]
/linux-4.4.14/arch/arm/plat-samsung/
Dpm-gpio.c35 chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON); in samsung_gpio_pm_1bit_save()
36 chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT); in samsung_gpio_pm_1bit_save()
42 u32 old_gpcon = __raw_readl(base + OFFS_CON); in samsung_gpio_pm_1bit_resume()
43 u32 old_gpdat = __raw_readl(base + OFFS_DAT); in samsung_gpio_pm_1bit_resume()
72 chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON); in samsung_gpio_pm_2bit_save()
73 chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT); in samsung_gpio_pm_2bit_save()
74 chip->pm_save[2] = __raw_readl(chip->base + OFFS_UP); in samsung_gpio_pm_2bit_save()
129 u32 old_gpcon = __raw_readl(base + OFFS_CON); in samsung_gpio_pm_2bit_resume()
130 u32 old_gpdat = __raw_readl(base + OFFS_DAT); in samsung_gpio_pm_2bit_resume()
200 chip->pm_save[1] = __raw_readl(chip->base + OFFS_CON); in samsung_gpio_pm_4bit_save()
[all …]
Dpm-debug.c71 save->ulcon = __raw_readl(regs + S3C2410_ULCON); in s3c_pm_save_uarts()
72 save->ucon = __raw_readl(regs + S3C2410_UCON); in s3c_pm_save_uarts()
73 save->ufcon = __raw_readl(regs + S3C2410_UFCON); in s3c_pm_save_uarts()
74 save->umcon = __raw_readl(regs + S3C2410_UMCON); in s3c_pm_save_uarts()
75 save->ubrdiv = __raw_readl(regs + S3C2410_UBRDIV); in s3c_pm_save_uarts()
78 save->udivslot = __raw_readl(regs + S3C2443_DIVSLOT); in s3c_pm_save_uarts()
Dcpu.c32 samsung_cpu_id = __raw_readl(S3C_VA_SYS + 0x118); in s3c64xx_init_cpu()
39 samsung_cpu_id = __raw_readl(S3C_VA_SYS + 0xA1C); in s3c64xx_init_cpu()
49 samsung_cpu_id = __raw_readl(cpuid_addr); in s5p_init_cpu()
Dwakeup-mask.c28 val = __raw_readl(reg); in samsung_sync_wakemask()
45 printk(KERN_INFO "wakemask %08x => %08x\n", __raw_readl(reg), val); in samsung_sync_wakemask()
Dpm-common.c34 ptr->val = __raw_readl(ptr->reg); in s3c_pm_do_save()
54 ptr->reg, ptr->val, __raw_readl(ptr->reg)); in s3c_pm_do_restore()
/linux-4.4.14/arch/arm/mach-pxa/
Dsmemc.c21 msc[0] = __raw_readl(MSC0); in pxa3xx_smemc_suspend()
22 msc[1] = __raw_readl(MSC1); in pxa3xx_smemc_suspend()
23 sxcnfg = __raw_readl(SXCNFG); in pxa3xx_smemc_suspend()
24 memclkcfg = __raw_readl(MEMCLKCFG); in pxa3xx_smemc_suspend()
25 csadrcfg[0] = __raw_readl(CSADRCFG0); in pxa3xx_smemc_suspend()
26 csadrcfg[1] = __raw_readl(CSADRCFG1); in pxa3xx_smemc_suspend()
27 csadrcfg[2] = __raw_readl(CSADRCFG2); in pxa3xx_smemc_suspend()
28 csadrcfg[3] = __raw_readl(CSADRCFG3); in pxa3xx_smemc_suspend()
Dirq.c71 uint32_t icmr = __raw_readl(base + ICMR); in pxa_mask_irq()
81 uint32_t icmr = __raw_readl(base + ICMR); in pxa_unmask_irq()
99 icip = __raw_readl(pxa_irq_base + ICIP); in icip_handle_irq()
100 icmr = __raw_readl(pxa_irq_base + ICMR); in icip_handle_irq()
191 saved_icmr[i] = __raw_readl(base + ICMR); in pxa_irq_suspend()
197 saved_ipr[i] = __raw_readl(pxa_irq_base + IPR(i)); in pxa_irq_suspend()
Dcm-x2xx-pci.c58 sleep_save_ite[0] = __raw_readl(IT8152_INTC_PDCNIMR); in __cmx2xx_pci_suspend()
59 sleep_save_ite[1] = __raw_readl(IT8152_INTC_LPCNIMR); in __cmx2xx_pci_suspend()
60 sleep_save_ite[2] = __raw_readl(IT8152_INTC_LPNIAR); in __cmx2xx_pci_suspend()
132 if (__raw_readl(IT8152_PCI_CFG_DATA) == 0x81521283) { in cmx2xx_pci_preinit()
Dxcep.c173 __raw_writel((__raw_readl(MSC1) & 0xffff) | 0xD5540000, MSC1); in xcep_init()
175 __raw_writel((__raw_readl(MSC2) & 0xffff) | 0x72A00000, MSC2); in xcep_init()
/linux-4.4.14/arch/arm/mach-s3c24xx/include/mach/
Dpm-core.h21 unsigned long tmp = __raw_readl(S3C2410_CLKCON); in s3c_pm_debug_init_uart()
39 __raw_writel(__raw_readl(S3C2410_EINTPEND), S3C2410_EINTPEND); in s3c_pm_arch_prepare_irqs()
40 __raw_writel(__raw_readl(S3C2410_INTPND), S3C2410_INTPND); in s3c_pm_arch_prepare_irqs()
41 __raw_writel(__raw_readl(S3C2410_SRCPND), S3C2410_SRCPND); in s3c_pm_arch_prepare_irqs()
71 __raw_readl(S3C2410_SRCPND), in s3c_pm_arch_show_resume_irqs()
72 __raw_readl(S3C2410_EINTPEND)); in s3c_pm_arch_show_resume_irqs()
74 s3c_pm_show_resume_irqs(IRQ_EINT0, __raw_readl(S3C2410_SRCPND), in s3c_pm_arch_show_resume_irqs()
77 s3c_pm_show_resume_irqs(IRQ_EINT4-4, __raw_readl(S3C2410_EINTPEND), in s3c_pm_arch_show_resume_irqs()
/linux-4.4.14/arch/arm/mach-mmp/
Dpm-mmp2.c49 data |= __raw_readl(MPMU_WUCRM_PJ); in mmp2_set_wake()
54 data = ~data & __raw_readl(MPMU_WUCRM_PJ); in mmp2_set_wake()
70 val = __raw_readl(CIU_REG(0x1c)); in pm_scu_clk_disable()
86 val = __raw_readl(CIU_REG(0x1c)); in pm_scu_clk_enable()
107 val = __raw_readl(MPMU_PLL2_CTRL1); in pm_mpmu_clk_enable()
118 idle_cfg = __raw_readl(APMU_PJ_IDLE_CFG); in mmp2_pm_enter_lowpower_mode()
119 apcr = __raw_readl(MPMU_PCR_PJ); in mmp2_pm_enter_lowpower_mode()
164 temp = __raw_readl(MMP2_ICU_INT4_MASK); in mmp2_pm_enter()
170 temp = __raw_readl(APMU_SRAM_PWR_DWN); in mmp2_pm_enter()
239 __raw_writel(__raw_readl(CIU_REG(0x8)) & ~(0x1 << 23), CIU_REG(0x8)); in mmp2_pm_init()
[all …]
Dpm-pxa910.c114 awucrm |= __raw_readl(MPMU_AWUCRM); in pxa910_set_wake()
118 apcr = ~apcr & __raw_readl(MPMU_APCR); in pxa910_set_wake()
123 awucrm = ~awucrm & __raw_readl(MPMU_AWUCRM); in pxa910_set_wake()
127 apcr |= __raw_readl(MPMU_APCR); in pxa910_set_wake()
138 idle_cfg = __raw_readl(APMU_MOH_IDLE_CFG); in pxa910_pm_enter_lowpower_mode()
139 apcr = __raw_readl(MPMU_APCR); in pxa910_pm_enter_lowpower_mode()
194 reg = __raw_readl(ICU_INT_CONF(IRQ_PXA910_PMIC_INT)); in pxa910_pm_enter()
198 idle_cfg = __raw_readl(APMU_MOH_IDLE_CFG); in pxa910_pm_enter()
217 idle_cfg = __raw_readl(APMU_MOH_IDLE_CFG); in pxa910_pm_enter()
264 __raw_writel(__raw_readl(APMU_SQU_CLK_GATE_CTRL) | (1 << 30), in pxa910_pm_init()
[all …]
Dclock-mmp2.c51 clk_rst = __raw_readl(clk->clk_rst); in sdhc_clk_enable()
60 clk_rst = __raw_readl(clk->clk_rst); in sdhc_clk_disable()
/linux-4.4.14/arch/mips/pci/
Dops-tx4927.c73 __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff) in mkaddr()
84 while (__raw_readl(&pcicptr->pcicstatus) & TX4927_PCIC_PCICSTATUS_IWB) in check_abort()
86 if (__raw_readl(&pcicptr->pcistatus) in check_abort()
88 __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff) in check_abort()
114 return __raw_readl(&pcicptr->g2pcfgdata); in icd_readl()
234 __raw_readl(&pcicptr->pciid) >> 16, in tx4927_pcic_setup()
235 __raw_readl(&pcicptr->pciid) & 0xffff, in tx4927_pcic_setup()
236 __raw_readl(&pcicptr->pciccrev) & 0xff, in tx4927_pcic_setup()
243 __raw_writel(__raw_readl(&pcicptr->pciccfg) in tx4927_pcic_setup()
311 __raw_writel(__raw_readl(&pcicptr->pciccfg) in tx4927_pcic_setup()
[all …]
Dpci-ar724x.c59 reset = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_RESET); in ar724x_pci_check_link()
85 data = __raw_readl(base + (where & ~3)); in ar724x_pci_local_write()
107 __raw_readl(base + (where & ~3)); in ar724x_pci_local_write()
127 data = __raw_readl(base + (where & ~3)); in ar724x_pci_read()
196 data = __raw_readl(base + (where & ~3)); in ar724x_pci_write()
218 __raw_readl(base + (where & ~3)); in ar724x_pci_write()
237 pending = __raw_readl(base + AR724X_PCI_REG_INT_STATUS) & in ar724x_pci_irq_handler()
238 __raw_readl(base + AR724X_PCI_REG_INT_MASK); in ar724x_pci_irq_handler()
260 t = __raw_readl(base + AR724X_PCI_REG_INT_MASK); in ar724x_pci_irq_unmask()
264 __raw_readl(base + AR724X_PCI_REG_INT_MASK); in ar724x_pci_irq_unmask()
[all …]
Dpci-alchemy.c113 r = __raw_readl(ctx->regs + PCI_REG_STATCMD) & 0x0000ffff; in config_access()
156 *data = __raw_readl(ctx->pci_cfg_vm->addr + offset); in config_access()
163 status = __raw_readl(ctx->regs + PCI_REG_STATCMD); in config_access()
312 ctx->pm[0] = __raw_readl(ctx->regs + PCI_REG_CMEM); in alchemy_pci_suspend()
313 ctx->pm[1] = __raw_readl(ctx->regs + PCI_REG_CONFIG) & 0x0009ffff; in alchemy_pci_suspend()
314 ctx->pm[2] = __raw_readl(ctx->regs + PCI_REG_B2BMASK_CCH); in alchemy_pci_suspend()
315 ctx->pm[3] = __raw_readl(ctx->regs + PCI_REG_B2BBASE0_VID); in alchemy_pci_suspend()
316 ctx->pm[4] = __raw_readl(ctx->regs + PCI_REG_B2BBASE1_SID); in alchemy_pci_suspend()
317 ctx->pm[5] = __raw_readl(ctx->regs + PCI_REG_MWMASK_DEV); in alchemy_pci_suspend()
318 ctx->pm[6] = __raw_readl(ctx->regs + PCI_REG_MWBASE_REV_CCL); in alchemy_pci_suspend()
[all …]
Dpci-ar71xx.c116 pci_err = __raw_readl(base + AR71XX_PCI_REG_PCI_ERR) & 3; in ar71xx_pci_check_error()
121 addr = __raw_readl(base + AR71XX_PCI_REG_PCI_ERR_ADDR); in ar71xx_pci_check_error()
130 ahb_err = __raw_readl(base + AR71XX_PCI_REG_AHB_ERR) & 1; in ar71xx_pci_check_error()
135 addr = __raw_readl(base + AR71XX_PCI_REG_AHB_ERR_ADDR); in ar71xx_pci_check_error()
196 data = __raw_readl(base + AR71XX_PCI_REG_CFG_RDDATA); in ar71xx_pci_read_config()
237 pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) & in ar71xx_pci_irq_handler()
238 __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); in ar71xx_pci_irq_handler()
266 t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); in ar71xx_pci_irq_unmask()
270 __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); in ar71xx_pci_irq_unmask()
283 t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); in ar71xx_pci_irq_mask()
[all …]
/linux-4.4.14/drivers/cpufreq/
Ds5pv210-cpufreq.c302 reg = __raw_readl(S5P_CLK_DIV2); in s5pv210_target()
310 reg = __raw_readl(S5P_CLKDIV_STAT0); in s5pv210_target()
317 reg = __raw_readl(S5P_CLK_SRC2); in s5pv210_target()
324 reg = __raw_readl(S5P_CLKMUX_STAT1); in s5pv210_target()
336 reg = __raw_readl(S5P_CLK_SRC0); in s5pv210_target()
342 reg = __raw_readl(S5P_CLKMUX_STAT0); in s5pv210_target()
348 reg = __raw_readl(S5P_CLK_DIV0); in s5pv210_target()
367 reg = __raw_readl(S5P_CLKDIV_STAT0); in s5pv210_target()
371 reg = __raw_readl(S5P_ARM_MCS_CON); in s5pv210_target()
395 reg = __raw_readl(S5P_APLL_CON); in s5pv210_target()
[all …]
Dexynos5440-cpufreq.c175 tmp = __raw_readl(dvfs_info->base + XMU_PMUEVTEN); in exynos_enable_dvfs()
180 tmp = __raw_readl(dvfs_info->base + XMU_PMUIRQEN); in exynos_enable_dvfs()
200 tmp = __raw_readl(dvfs_info->base + XMU_C0_3_PSTATE + cpu * 4); in exynos_enable_dvfs()
226 tmp = __raw_readl(dvfs_info->base + XMU_C0_3_PSTATE + i * 4); in exynos_target()
249 cur_pstate = __raw_readl(dvfs_info->base + XMU_P_STATUS); in exynos_cpufreq_work()
273 tmp = __raw_readl(dvfs_info->base + XMU_PMUIRQ); in exynos_cpufreq_irq()
Dintegrator-cpufreq.c99 cm_osc = __raw_readl(cm_base + INTEGRATOR_HDR_OSC_OFFSET); in integrator_set_target()
126 cm_osc = __raw_readl(cm_base + INTEGRATOR_HDR_OSC_OFFSET); in integrator_set_target()
163 cm_osc = __raw_readl(cm_base + INTEGRATOR_HDR_OSC_OFFSET); in integrator_get()
/linux-4.4.14/arch/arm/common/
Dit8152.c40 __raw_writel((__raw_readl(IT8152_INTC_LDCNIMR) | in it8152_mask_irq()
44 __raw_writel((__raw_readl(IT8152_INTC_LPCNIMR) | in it8152_mask_irq()
48 __raw_writel((__raw_readl(IT8152_INTC_PDCNIMR) | in it8152_mask_irq()
59 __raw_writel((__raw_readl(IT8152_INTC_LDCNIMR) & in it8152_unmask_irq()
63 __raw_writel((__raw_readl(IT8152_INTC_LPCNIMR) & in it8152_unmask_irq()
67 __raw_writel((__raw_readl(IT8152_INTC_PDCNIMR) & in it8152_unmask_irq()
105 bits_pd = __raw_readl(IT8152_INTC_PDCNIRR); in it8152_irq_demux()
106 bits_lp = __raw_readl(IT8152_INTC_LPCNIRR); in it8152_irq_demux()
107 bits_ld = __raw_readl(IT8152_INTC_LDCNIRR); in it8152_irq_demux()
117 bits_pd = __raw_readl(IT8152_INTC_PDCNIRR); in it8152_irq_demux()
[all …]
/linux-4.4.14/arch/arm/mach-davinci/
Dpsc.c44 mdstat = __raw_readl(psc_base + MDSTAT + 4 * id); in davinci_psc_is_clk_active()
100 mdctl = __raw_readl(psc_base + MDCTL + 4 * id); in davinci_psc_config()
107 pdstat = __raw_readl(psc_base + PDSTAT + 4 * domain); in davinci_psc_config()
109 pdctl = __raw_readl(psc_base + PDCTL + 4 * domain); in davinci_psc_config()
117 epcpr = __raw_readl(psc_base + EPCPR); in davinci_psc_config()
120 pdctl = __raw_readl(psc_base + PDCTL + 4 * domain); in davinci_psc_config()
129 ptstat = __raw_readl(psc_base + PTSTAT); in davinci_psc_config()
133 mdstat = __raw_readl(psc_base + MDSTAT + 4 * id); in davinci_psc_config()
Dpm.c47 val = __raw_readl(pdata->cpupll_reg_base + PLLCTL); in davinci_pm_suspend()
54 val = __raw_readl(pdata->cpupll_reg_base + PLLCTL); in davinci_pm_suspend()
60 val = __raw_readl(pdata->deepsleep_reg); in davinci_pm_suspend()
71 val = __raw_readl(pdata->cpupll_reg_base + PLLCTL); in davinci_pm_suspend()
76 val = __raw_readl(pdata->cpupll_reg_base + PLLCTL); in davinci_pm_suspend()
84 val = __raw_readl(pdata->cpupll_reg_base + PLLCTL); in davinci_pm_suspend()
92 val = __raw_readl(pdata->cpupll_reg_base + PLLCTL); in davinci_pm_suspend()
Dclock.c317 v = __raw_readl(pll->base + clk->div_reg); in clk_sysclk_recalc()
380 v = __raw_readl(pll->base + PLLSTAT); in davinci_set_sysclk_rate()
383 v = __raw_readl(pll->base + clk->div_reg); in davinci_set_sysclk_rate()
388 v = __raw_readl(pll->base + PLLCMD); in davinci_set_sysclk_rate()
393 v = __raw_readl(pll->base + PLLSTAT); in davinci_set_sysclk_rate()
421 ctrl = __raw_readl(pll->base + PLLCTL); in clk_pllclk_recalc()
426 mult = __raw_readl(pll->base + PLLM); in clk_pllclk_recalc()
435 prediv = __raw_readl(pll->base + PREDIV); in clk_pllclk_recalc()
447 postdiv = __raw_readl(pll->base + POSTDIV); in clk_pllclk_recalc()
514 ctrl = __raw_readl(pll->base + PLLCTL); in davinci_set_pllrate()
/linux-4.4.14/drivers/devfreq/exynos/
Dexynos4_bus.c309 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_DMC0); in exynos4210_set_busclk()
318 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_TOP); in exynos4210_set_busclk()
322 tmp = __raw_readl(EXYNOS4_CLKDIV_LEFTBUS); in exynos4210_set_busclk()
334 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_LEFTBUS); in exynos4210_set_busclk()
338 tmp = __raw_readl(EXYNOS4_CLKDIV_RIGHTBUS); in exynos4210_set_busclk()
350 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_RIGHTBUS); in exynos4210_set_busclk()
375 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_DMC0); in exynos4x12_set_busclk()
379 tmp = __raw_readl(EXYNOS4_CLKDIV_DMC1); in exynos4x12_set_busclk()
395 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_DMC1); in exynos4x12_set_busclk()
399 tmp = __raw_readl(EXYNOS4_CLKDIV_TOP); in exynos4x12_set_busclk()
[all …]
Dexynos_ppmu.c50 total = ((__raw_readl(ppmu_base + PMCNT_OFFSET(ch)) << 8) | in exynos_ppmu_read()
51 __raw_readl(ppmu_base + PMCNT_OFFSET(ch + 1))); in exynos_ppmu_read()
53 total = __raw_readl(ppmu_base + PMCNT_OFFSET(ch)); in exynos_ppmu_read()
88 ppmu_data->ppmu[i].ccnt = __raw_readl(ppmu_base + PPMU_CCNT); in exynos_read_ppmu()
/linux-4.4.14/arch/arm/mach-cns3xxx/
Dpm.c20 u32 reg = __raw_readl(PM_CLK_GATE_REG); in cns3xxx_pwr_clk_en()
29 u32 reg = __raw_readl(PM_CLK_GATE_REG); in cns3xxx_pwr_clk_dis()
38 u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG); in cns3xxx_pwr_power_up()
50 u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG); in cns3xxx_pwr_power_down()
60 u32 reg = __raw_readl(PM_SOFT_RST_REG); in cns3xxx_pwr_soft_rst_force()
108 u32 reg = __raw_readl(PM_CLK_CTRL_REG); in cns3xxx_cpu_clock()
Ddevices.c57 tmp = __raw_readl(MISC_SATA_POWER_MODE); in cns3xxx_ahci_init()
101 u32 gpioa_pins = __raw_readl(gpioa); in cns3xxx_sdhci_init()
/linux-4.4.14/drivers/gpio/
Dgpio-ks8695.c50 x = __raw_readl(KS8695_GPIO_VA + KS8695_IOPC); in ks8695_gpio_mode()
76 x = __raw_readl(KS8695_GPIO_VA + KS8695_IOPM); in ks8695_gpio_interrupt()
112 x = __raw_readl(KS8695_GPIO_VA + KS8695_IOPM); in ks8695_gpio_direction_input()
139 x = __raw_readl(KS8695_GPIO_VA + KS8695_IOPD); in ks8695_gpio_direction_output()
147 x = __raw_readl(KS8695_GPIO_VA + KS8695_IOPM); in ks8695_gpio_direction_output()
171 x = __raw_readl(KS8695_GPIO_VA + KS8695_IOPD); in ks8695_gpio_set_value()
192 x = __raw_readl(KS8695_GPIO_VA + KS8695_IOPD); in ks8695_gpio_get_value()
252 mode = __raw_readl(KS8695_GPIO_VA + KS8695_IOPM); in ks8695_gpio_show()
253 ctrl = __raw_readl(KS8695_GPIO_VA + KS8695_IOPC); in ks8695_gpio_show()
254 data = __raw_readl(KS8695_GPIO_VA + KS8695_IOPD); in ks8695_gpio_show()
Dgpio-samsung.c50 pup = __raw_readl(reg); in samsung_gpio_setpull_updown()
63 u32 pup = __raw_readl(reg); in samsung_gpio_getpull_updown()
116 u32 pup = __raw_readl(reg); in s3c24xx_gpio_setpull_1()
134 u32 pup = __raw_readl(reg); in s3c24xx_gpio_getpull_1()
193 con = __raw_readl(reg); in samsung_gpio_setcfg_2bit()
216 con = __raw_readl(chip->base); in samsung_gpio_getcfg_2bit()
256 con = __raw_readl(reg); in samsung_gpio_setcfg_4bit()
286 con = __raw_readl(reg); in samsung_gpio_getcfg_4bit()
324 con = __raw_readl(reg); in s3c24xx_gpio_setcfg_abank()
349 con = __raw_readl(chip->base); in s3c24xx_gpio_getcfg_abank()
[all …]
Dgpio-ath79.c44 return (__raw_readl(ctrl->base + AR71XX_GPIO_REG_IN) >> gpio) & 1; in ath79_gpio_get_value()
56 __raw_readl(ctrl->base + AR71XX_GPIO_REG_OE) & ~BIT(offset), in ath79_gpio_direction_input()
78 __raw_readl(ctrl->base + AR71XX_GPIO_REG_OE) | BIT(offset), in ath79_gpio_direction_output()
94 __raw_readl(ctrl->base + AR71XX_GPIO_REG_OE) | BIT(offset), in ar934x_gpio_direction_input()
116 __raw_readl(ctrl->base + AR71XX_GPIO_REG_OE) & ~BIT(offset), in ar934x_gpio_direction_output()
/linux-4.4.14/arch/sh/kernel/cpu/sh4a/
Dubc.c53 __raw_writel(__raw_readl(UBC_CBR(i)) | UBC_CBR_CE, in sh4a_ubc_enable_all()
62 __raw_writel(__raw_readl(UBC_CBR(i)) & ~UBC_CBR_CE, in sh4a_ubc_disable_all()
72 if (__raw_readl(UBC_CBR(i)) & UBC_CBR_CE) in sh4a_ubc_active_mask()
80 return __raw_readl(UBC_CCMFR); in sh4a_ubc_triggered_mask()
85 __raw_writel(__raw_readl(UBC_CCMFR) & ~mask, UBC_CCMFR); in sh4a_ubc_clear_triggered_mask()
124 (void)__raw_readl(UBC_CRR(i)); in sh4a_ubc_init()
Dsmp-shx3.c37 x = __raw_readl(0xfe410070 + offs); /* C0INITICI..CnINTICI */ in ipi_interrupt_handler()
54 __raw_writel(__raw_readl(STBCR_REG(cpu)) | STBCR_LTSLP, STBCR_REG(cpu)); in shx3_smp_setup()
95 if (!(__raw_readl(STBCR_REG(cpu)) & STBCR_MSTP)) in shx3_start_cpu()
98 while (!(__raw_readl(STBCR_REG(cpu)) & STBCR_MSTP)) in shx3_start_cpu()
107 return __raw_readl(0xff000048); /* CPIDR */ in shx3_smp_processor_id()
122 while (!(__raw_readl(STBCR_REG(cpu)) & STBCR_MSTP)) in shx3_update_boot_vector()
Dclock-sh7780.c27 clk->rate *= pfc_divisors[__raw_readl(FRQCR) & 0x0003]; in master_clk_init()
36 int idx = (__raw_readl(FRQCR) & 0x0003); in module_clk_recalc()
46 int idx = ((__raw_readl(FRQCR) >> 16) & 0x0007); in bus_clk_recalc()
56 int idx = ((__raw_readl(FRQCR) >> 24) & 0x0001); in cpu_clk_recalc()
79 int idx = ((__raw_readl(FRQCR) >> 20) & 0x0007); in shyway_clk_recalc()
Dperf_event.c232 return __raw_readl(PPC_PMCTR(idx)); in sh4a_pmu_read()
239 tmp = __raw_readl(PPC_CCBR(idx)); in sh4a_pmu_disable()
248 tmp = __raw_readl(PPC_PMCAT); in sh4a_pmu_enable()
253 tmp = __raw_readl(PPC_CCBR(idx)); in sh4a_pmu_enable()
257 __raw_writel(__raw_readl(PPC_CCBR(idx)) | CCBR_DUC, PPC_CCBR(idx)); in sh4a_pmu_enable()
265 __raw_writel(__raw_readl(PPC_CCBR(i)) & ~CCBR_DUC, PPC_CCBR(i)); in sh4a_pmu_disable_all()
273 __raw_writel(__raw_readl(PPC_CCBR(i)) | CCBR_DUC, PPC_CCBR(i)); in sh4a_pmu_enable_all()
Dclock-sh7770.c24 clk->rate *= pfc_divisors[(__raw_readl(FRQCR) >> 28) & 0x000f]; in master_clk_init()
33 int idx = ((__raw_readl(FRQCR) >> 28) & 0x000f); in module_clk_recalc()
43 int idx = (__raw_readl(FRQCR) & 0x000f); in bus_clk_recalc()
53 int idx = ((__raw_readl(FRQCR) >> 24) & 0x000f); in cpu_clk_recalc()
Dclock-sh7763.c27 clk->rate *= p0fc_divisors[(__raw_readl(FRQCR) >> 4) & 0x07]; in master_clk_init()
36 int idx = ((__raw_readl(FRQCR) >> 4) & 0x07); in module_clk_recalc()
46 int idx = ((__raw_readl(FRQCR) >> 16) & 0x07); in bus_clk_recalc()
73 int idx = ((__raw_readl(FRQCR) >> 20) & 0x07); in shyway_clk_recalc()
Dclock-sh7722.c59 if (__raw_readl(PLLCR) & 0x1000) in dll_recalc()
60 mult = __raw_readl(DLLFRQ); in dll_recalc()
82 if (__raw_readl(PLLCR) & 0x4000) in pll_recalc()
83 mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1); in pll_recalc()
237 if (__raw_readl(PLLCR) & 0x1000) in arch_clk_init()
Dclock-sh7724.c64 if (__raw_readl(PLLCR) & 0x1000) in fll_recalc()
65 mult = __raw_readl(FLLFRQ) & 0x3ff; in fll_recalc()
67 if (__raw_readl(FLLFRQ) & 0x4000) in fll_recalc()
87 if (__raw_readl(PLLCR) & 0x4000) in pll_recalc()
88 mult = (((__raw_readl(FRQCRA) >> 24) & 0x3f) + 1) * 2; in pll_recalc()
143 value = __raw_readl(FRQCRA); in div4_kick()
359 if (__raw_readl(PLLCR) & 0x1000) in arch_clk_init()
Dsetup-sh7724.c1172 sh7724_rstandby_state.mmselr = __raw_readl(0xff800020); /* MMSELR */ in sh7724_pre_sleep_notifier_call()
1174 sh7724_rstandby_state.cs0bcr = __raw_readl(0xfec10004); /* CS0BCR */ in sh7724_pre_sleep_notifier_call()
1175 sh7724_rstandby_state.cs4bcr = __raw_readl(0xfec10010); /* CS4BCR */ in sh7724_pre_sleep_notifier_call()
1176 sh7724_rstandby_state.cs5abcr = __raw_readl(0xfec10014); /* CS5ABCR */ in sh7724_pre_sleep_notifier_call()
1177 sh7724_rstandby_state.cs5bbcr = __raw_readl(0xfec10018); /* CS5BBCR */ in sh7724_pre_sleep_notifier_call()
1178 sh7724_rstandby_state.cs6abcr = __raw_readl(0xfec1001c); /* CS6ABCR */ in sh7724_pre_sleep_notifier_call()
1179 sh7724_rstandby_state.cs6bbcr = __raw_readl(0xfec10020); /* CS6BBCR */ in sh7724_pre_sleep_notifier_call()
1180 sh7724_rstandby_state.cs4wcr = __raw_readl(0xfec10030); /* CS4WCR */ in sh7724_pre_sleep_notifier_call()
1181 sh7724_rstandby_state.cs5awcr = __raw_readl(0xfec10034); /* CS5AWCR */ in sh7724_pre_sleep_notifier_call()
1182 sh7724_rstandby_state.cs5bwcr = __raw_readl(0xfec10038); /* CS5BWCR */ in sh7724_pre_sleep_notifier_call()
[all …]
Dclock-sh7366.c56 if (__raw_readl(PLLCR) & 0x1000) in dll_recalc()
57 mult = __raw_readl(DLLFRQ); in dll_recalc()
79 if (__raw_readl(PLLCR) & 0x4000) in pll_recalc()
80 mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1); in pll_recalc()
262 if (__raw_readl(PLLCR) & 0x1000) in arch_clk_init()
Dclock-sh7343.c56 if (__raw_readl(PLLCR) & 0x1000) in dll_recalc()
57 mult = __raw_readl(DLLFRQ); in dll_recalc()
78 if (__raw_readl(PLLCR) & 0x4000) in pll_recalc()
79 mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1); in pll_recalc()
269 if (__raw_readl(PLLCR) & 0x1000) in arch_clk_init()
Dclock-sh7723.c60 if (__raw_readl(PLLCR) & 0x1000) in dll_recalc()
61 mult = __raw_readl(DLLFRQ); in dll_recalc()
83 if (__raw_readl(PLLCR) & 0x4000) in pll_recalc()
84 mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1); in pll_recalc()
285 if (__raw_readl(PLLCR) & 0x1000) in arch_clk_init()
/linux-4.4.14/drivers/devfreq/event/
Dexynos-ppmu.c125 pmnc = __raw_readl(info->ppmu.base + PPMU_PMNC); in exynos_ppmu_disable()
142 cntens = __raw_readl(info->ppmu.base + PPMU_CNTENS); in exynos_ppmu_set_event()
151 pmnc = __raw_readl(info->ppmu.base + PPMU_PMNC); in exynos_ppmu_set_event()
174 pmnc = __raw_readl(info->ppmu.base + PPMU_PMNC); in exynos_ppmu_get_event()
179 edata->total_count = __raw_readl(info->ppmu.base + PPMU_CCNT); in exynos_ppmu_get_event()
187 = __raw_readl(info->ppmu.base + PPMU_PMNCT(id)); in exynos_ppmu_get_event()
191 ((__raw_readl(info->ppmu.base + PPMU_PMCNT3_HIGH) << 8) in exynos_ppmu_get_event()
192 | __raw_readl(info->ppmu.base + PPMU_PMCNT3_LOW)); in exynos_ppmu_get_event()
199 cntenc = __raw_readl(info->ppmu.base + PPMU_CNTENC); in exynos_ppmu_get_event()
248 pmnc = __raw_readl(info->ppmu.base + PPMU_V2_PMNC); in exynos_ppmu_v2_disable()
[all …]
/linux-4.4.14/arch/mips/loongson32/common/
Dirq.c32 __raw_writel(__raw_readl(LS1X_INTC_INTCLR(n)) in ls1x_irq_ack()
41 __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n)) in ls1x_irq_mask()
50 __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n)) in ls1x_irq_mask_ack()
52 __raw_writel(__raw_readl(LS1X_INTC_INTCLR(n)) in ls1x_irq_mask_ack()
61 __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n)) in ls1x_irq_unmask()
78 int_status = __raw_readl(LS1X_INTC_INTISR(n)) & in ls1x_irq_dispatch()
79 __raw_readl(LS1X_INTC_INTIEN(n)); in ls1x_irq_dispatch()
/linux-4.4.14/drivers/char/hw_random/
Dmxc-rnga.c76 int level = (__raw_readl(mxc_rng->mem + RNGA_STATUS) & in mxc_rnga_data_present()
92 *data = __raw_readl(mxc_rng->mem + RNGA_OUTPUT_FIFO); in mxc_rnga_data_read()
95 err = __raw_readl(mxc_rng->mem + RNGA_STATUS) & RNGA_STATUS_ERROR_INT; in mxc_rnga_data_read()
100 ctrl = __raw_readl(mxc_rng->mem + RNGA_CONTROL); in mxc_rnga_data_read()
114 ctrl = __raw_readl(mxc_rng->mem + RNGA_CONTROL); in mxc_rnga_init()
118 osc = __raw_readl(mxc_rng->mem + RNGA_STATUS); in mxc_rnga_init()
125 ctrl = __raw_readl(mxc_rng->mem + RNGA_CONTROL); in mxc_rnga_init()
136 ctrl = __raw_readl(mxc_rng->mem + RNGA_CONTROL); in mxc_rnga_cleanup()
Dbcm63xx-rng.c44 val = __raw_readl(priv->regs + RNG_CTRL); in bcm63xx_rng_init()
56 val = __raw_readl(priv->regs + RNG_CTRL); in bcm63xx_rng_cleanup()
67 return __raw_readl(priv->regs + RNG_STAT) & RNG_AVAIL_MASK; in bcm63xx_rng_data_present()
74 *data = __raw_readl(priv->regs + RNG_DATA); in bcm63xx_rng_data_read()
Dbcm2835-rng.c34 while ((__raw_readl(rng_base + RNG_STATUS) >> 24) == 0) { in bcm2835_rng_read()
40 *(u32 *)buf = __raw_readl(rng_base + RNG_DATA); in bcm2835_rng_read()
/linux-4.4.14/arch/sh/boards/mach-cayman/
Dirq.c68 mask = __raw_readl(reg); in enable_cayman_irq()
86 mask = __raw_readl(reg); in disable_cayman_irq()
106 status = __raw_readl(EPLD_STATUS_BASE) & in cayman_irq_demux()
107 __raw_readl(EPLD_MASK_BASE) & 0xff; in cayman_irq_demux()
123 status = __raw_readl(EPLD_STATUS_BASE + 3 * sizeof(u32)) & in cayman_irq_demux()
124 __raw_readl(EPLD_MASK_BASE + 3 * sizeof(u32)) & 0xff; in cayman_irq_demux()
/linux-4.4.14/drivers/clk/samsung/
Dclk-pll.c82 pll_con = __raw_readl(pll->con_reg); in samsung_pll2126_recalc_rate()
115 pll_con = __raw_readl(pll->con_reg); in samsung_pll3000_recalc_rate()
152 pll_con = __raw_readl(pll->con_reg); in samsung_pll35xx_recalc_rate()
189 tmp = __raw_readl(pll->con_reg); in samsung_pll35xx_set_rate()
216 tmp = __raw_readl(pll->con_reg); in samsung_pll35xx_set_rate()
256 pll_con0 = __raw_readl(pll->con_reg); in samsung_pll36xx_recalc_rate()
257 pll_con1 = __raw_readl(pll->con_reg + 4); in samsung_pll36xx_recalc_rate()
297 pll_con0 = __raw_readl(pll->con_reg); in samsung_pll36xx_set_rate()
298 pll_con1 = __raw_readl(pll->con_reg + 4); in samsung_pll36xx_set_rate()
328 tmp = __raw_readl(pll->con_reg); in samsung_pll36xx_set_rate()
[all …]
/linux-4.4.14/arch/arm/mach-lpc32xx/
Dclock.c137 reg = __raw_readl(LPC32XX_CLKPWR_PLL397_CTRL); in local_pll397_enable()
148 while (((__raw_readl(LPC32XX_CLKPWR_PLL397_CTRL) & in local_pll397_enable()
153 if ((__raw_readl(LPC32XX_CLKPWR_PLL397_CTRL) & in local_pll397_enable()
166 reg = __raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL); in local_oscmain_enable()
177 while (((__raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL) & in local_oscmain_enable()
182 if ((__raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL) & in local_oscmain_enable()
263 pllreg = __raw_readl(LPC32XX_CLKPWR_HCLKPLL_CTRL) & 0x1FFFF; in local_update_armpll_rate()
379 reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL) & ~0x1FFFF; in local_clk_usbpll_setup()
393 reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL); in local_usbpll_enable()
425 reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL); in local_usbpll_enable()
[all …]
Dcommon.c43 devid[i] = __raw_readl(LPC32XX_CLKPWR_DEVID(i << 2)); in lpc32xx_get_uid()
52 if ((__raw_readl(LPC32XX_CLKPWR_SYSCLK_CTRL) & in clk_is_sysclk_mainosc()
72 savedval1 = __raw_readl(iramptr1); in lpc32xx_return_iram_size()
73 savedval2 = __raw_readl(iramptr2); in lpc32xx_return_iram_size()
77 if (__raw_readl(iramptr1) == savedval2 + 1) in lpc32xx_return_iram_size()
162 return 1 + ((__raw_readl(LPC32XX_CLKPWR_HCLK_DIV) >> 2) & 0x1F); in clk_get_pclk_div()
Dirq.c216 reg = __raw_readl(LPC32XX_INTC_MASK(ctrl)) & ~mask; in lpc32xx_mask_irq()
226 reg = __raw_readl(LPC32XX_INTC_MASK(ctrl)) | mask; in lpc32xx_unmask_irq()
252 reg = __raw_readl(LPC32XX_INTC_POLAR(ctrl)); in __lpc32xx_set_irq_type()
260 reg = __raw_readl(LPC32XX_INTC_ACT_TYPE(ctrl)); in __lpc32xx_set_irq_type()
269 reg = __raw_readl(lpc32xx_events[irq].event_group->edge_reg); in __lpc32xx_set_irq_type()
320 eventreg = __raw_readl(lpc32xx_events[d->hwirq]. in lpc32xx_irq_wake()
375 unsigned long ints = __raw_readl(LPC32XX_INTC_STAT(LPC32XX_SIC1_BASE)); in lpc32xx_sic1_handler()
388 unsigned long ints = __raw_readl(LPC32XX_INTC_STAT(LPC32XX_SIC2_BASE)); in lpc32xx_sic2_handler()
461 __raw_writel(__raw_readl(LPC32XX_CLKPWR_PIN_RS), in lpc32xx_init_irq()
463 __raw_writel(__raw_readl(LPC32XX_CLKPWR_INT_RS), in lpc32xx_init_irq()
Dserial.c103 tmp = __raw_readl( in lpc32xx_serial_init()
117 tmp = __raw_readl(LPC32XX_UART_DLL_FIFO(puart)); in lpc32xx_serial_init()
122 tmp = __raw_readl(LPC32XX_UARTCTL_CTRL); in lpc32xx_serial_init()
127 tmp = __raw_readl(LPC32XX_UARTCTL_CTRL); in lpc32xx_serial_init()
/linux-4.4.14/drivers/edac/
Dcpc925_edac.c340 mbmr = __raw_readl(pdata->vbase + REG_MBMR_OFFSET + in cpc925_init_csrows()
342 mbbar = __raw_readl(pdata->vbase + REG_MBBAR_OFFSET + in cpc925_init_csrows()
400 apimask = __raw_readl(pdata->vbase + REG_APIMASK_OFFSET); in cpc925_mc_init()
407 mccr = __raw_readl(pdata->vbase + REG_MCCR_OFFSET); in cpc925_mc_init()
542 apiexcp = __raw_readl(pdata->vbase + REG_APIEXCP_OFFSET); in cpc925_mc_check()
546 mesr = __raw_readl(pdata->vbase + REG_MESR_OFFSET); in cpc925_mc_check()
549 mear = __raw_readl(pdata->vbase + REG_MEAR_OFFSET); in cpc925_mc_check()
573 __raw_readl(pdata->vbase + REG_APIMASK_OFFSET)); in cpc925_mc_check()
577 __raw_readl(pdata->vbase + REG_MSCR_OFFSET)); in cpc925_mc_check()
579 __raw_readl(pdata->vbase + REG_MSRSR_OFFSET)); in cpc925_mc_check()
[all …]
/linux-4.4.14/arch/arm/mach-s5pv210/
Dpm.c74 tmp = __raw_readl(S5P_SLEEP_CFG); in s5pv210_pm_prepare()
79 tmp = __raw_readl(S5P_PWR_CFG); in s5pv210_pm_prepare()
85 tmp = __raw_readl(S5P_OTHERS); in s5pv210_pm_prepare()
125 __raw_readl(S5P_WAKEUP_STAT)); in s5pv210_suspend_enter()
160 tmp = __raw_readl(S5P_OTHERS); in s5pv210_pm_resume()
/linux-4.4.14/sound/soc/au1x/
Dpsc-ac97.c96 if (__raw_readl(AC97_EVNT(pscdata)) & PSC_AC97EVNT_CD) in au1xpsc_ac97_read()
100 data = __raw_readl(AC97_CDC(pscdata)); in au1xpsc_ac97_read()
136 if (__raw_readl(AC97_EVNT(pscdata)) & PSC_AC97EVNT_CD) in au1xpsc_ac97_write()
183 while (!((__raw_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_SR)) && (--i)) in au1xpsc_ac97_cold_reset()
197 while (!((__raw_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR)) && (--i)) in au1xpsc_ac97_cold_reset()
221 r = ro = __raw_readl(AC97_CFG(pscdata)); in au1xpsc_ac97_hw_params()
222 stat = __raw_readl(AC97_STAT(pscdata)); in au1xpsc_ac97_hw_params()
260 while ((__raw_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR) && --t) in au1xpsc_ac97_hw_params()
276 while ((!(__raw_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR)) && --t) in au1xpsc_ac97_hw_params()
313 while (__raw_readl(AC97_STAT(pscdata)) & AC97STAT_BUSY(stype)) in au1xpsc_ac97_trigger()
[all …]
Dpsc-i2s.c123 stat = __raw_readl(I2S_STAT(pscdata)); in au1xpsc_i2s_hw_params()
126 cfgbits = __raw_readl(I2S_CFG(pscdata)); in au1xpsc_i2s_hw_params()
156 while (!(__raw_readl(I2S_STAT(pscdata)) & PSC_I2SSTAT_SR) && tmo) in au1xpsc_i2s_configure()
169 while (!(__raw_readl(I2S_STAT(pscdata)) & PSC_I2SSTAT_DR) && tmo) in au1xpsc_i2s_configure()
190 stat = __raw_readl(I2S_STAT(pscdata)); in au1xpsc_i2s_start()
204 while (!(__raw_readl(I2S_STAT(pscdata)) & I2SSTAT_BUSY(stype)) && tmo) in au1xpsc_i2s_start()
225 while ((__raw_readl(I2S_STAT(pscdata)) & I2SSTAT_BUSY(stype)) && tmo) in au1xpsc_i2s_stop()
229 stat = __raw_readl(I2S_STAT(pscdata)); in au1xpsc_i2s_stop()
324 sel = __raw_readl(PSC_SEL(wd)) & PSC_SEL_CLK_MASK; in au1xpsc_i2s_drvprobe()
370 wd->pm[0] = __raw_readl(PSC_SEL(wd)); in au1xpsc_i2s_drvsuspend()
/linux-4.4.14/arch/arm/mach-imx/
Dtzic.c68 value = __raw_readl(tzic_base + TZIC_INTSEC0(index)) | mask; in tzic_set_irq_fiq()
92 __raw_writel(__raw_readl(tzic_base + TZIC_ENSET0(idx)), in tzic_irq_resume()
138 stat = __raw_readl(tzic_base + TZIC_HIPND(i)) & in tzic_handle_irq()
139 __raw_readl(tzic_base + TZIC_INTSEC0(i)); in tzic_handle_irq()
169 i = __raw_readl(tzic_base + TZIC_INTCNTL); in tzic_init_irq()
218 if (unlikely(__raw_readl(tzic_base + TZIC_DSMINT) == 0)) in tzic_enable_wake()
222 __raw_writel(__raw_readl(tzic_base + TZIC_ENSET0(i)), in tzic_enable_wake()
Davic.c69 irqt = __raw_readl(avic_base + AVIC_INTTYPEL) & ~(1 << irq); in avic_set_irq_fiq()
73 irqt = __raw_readl(avic_base + AVIC_INTTYPEH) & ~(1 << irq); in avic_set_irq_fiq()
97 avic_saved_mask_reg[idx] = __raw_readl(avic_base + ct->regs.mask); in avic_irq_suspend()
143 nivector = __raw_readl(avic_base + AVIC_NIVECSR) >> 16; in avic_handle_irq()
Depit.c67 val = __raw_readl(timer_base + EPITCR); in epit_irq_disable()
76 val = __raw_readl(timer_base + EPITCR); in epit_irq_enable()
101 tcmp = __raw_readl(timer_base + EPITCNR); in epit_set_next_event()
Diomux-imx31.c60 l = __raw_readl(reg); in mxc_iomux_mode()
85 l = __raw_readl(reg); in mxc_iomux_set_pad()
166 l = __raw_readl(IOMUXGPR); in mxc_iomux_set_gpr()
Dpm-imx5.c156 plat_lpc = __raw_readl(cortex_base + MXC_CORTEXA8_PLAT_LPC) & in mx5_cpu_lp_set()
158 ccm_clpcr = __raw_readl(ccm_base + MXC_CCM_CLPCR) & in mx5_cpu_lp_set()
160 arm_srpgcr = __raw_readl(gpc_base + MXC_SRPG_ARM_SRPGCR) & in mx5_cpu_lp_set()
162 empgc0 = __raw_readl(gpc_base + MXC_SRPG_EMPGC0_SRPGCR) & in mx5_cpu_lp_set()
164 empgc1 = __raw_readl(gpc_base + MXC_SRPG_EMPGC1_SRPGCR) & in mx5_cpu_lp_set()
/linux-4.4.14/arch/arm/mach-s3c24xx/
Dpm-s3c2410.c50 S3C_PMDBG("GSTATUS3 0x%08x\n", __raw_readl(S3C2410_GSTATUS3)); in s3c2410_pm_prepare()
51 S3C_PMDBG("GSTATUS4 0x%08x\n", __raw_readl(S3C2410_GSTATUS4)); in s3c2410_pm_prepare()
61 calc += __raw_readl(base+ptr); in s3c2410_pm_prepare()
77 calc += __raw_readl(base+ptr); in s3c2410_pm_prepare()
106 tmp = __raw_readl(S3C2410_GSTATUS2); in s3c2410_pm_resume()
Dsimtec-pm.c58 gstatus4 = (__raw_readl(S3C2410_BANKCON7) & 0x3) << 30; in pm_simtec_init()
59 gstatus4 |= (__raw_readl(S3C2410_BANKCON6) & 0x3) << 28; in pm_simtec_init()
60 gstatus4 |= (__raw_readl(S3C2410_BANKSIZE) & S3C2410_BANKSIZE_MASK); in pm_simtec_init()
Diotiming-s3c2412.c212 bt->idcy = s3c2412_decode_timing(clk, __raw_readl(regs + SMBIDCYR)); in s3c2412_iotiming_getbank()
213 bt->wstrd = s3c2412_decode_timing(clk, __raw_readl(regs + SMBWSTRDR)); in s3c2412_iotiming_getbank()
214 bt->wstoen = s3c2412_decode_timing(clk, __raw_readl(regs + SMBWSTOENR)); in s3c2412_iotiming_getbank()
215 bt->wstwen = s3c2412_decode_timing(clk, __raw_readl(regs + SMBWSTWENR)); in s3c2412_iotiming_getbank()
216 bt->wstbrd = s3c2412_decode_timing(clk, __raw_readl(regs + SMBWSTBRDR)); in s3c2412_iotiming_getbank()
236 u32 bankcfg = __raw_readl(S3C2412_EBI_BANKCFG); in s3c2412_iotiming_get()
Dirq-pm.c78 save_extint[i] = __raw_readl(S3C24XX_EXTINT0 + (i*4)); in s3c24xx_irq_suspend()
81 save_eintflt[i] = __raw_readl(S3C24XX_EINFLT0 + (i*4)); in s3c24xx_irq_suspend()
84 save_eintmask = __raw_readl(S3C24XX_EINTMASK); in s3c24xx_irq_suspend()
Dcommon.c168 u32 gs = __raw_readl(S3C24XX_GSTATUS1); in s3c24xx_read_idcode_v5()
176 return __raw_readl(S3C2412_GSTATUS1); in s3c24xx_read_idcode_v5()
184 return __raw_readl(S3C2410_GSTATUS1); in s3c24xx_read_idcode_v4()
198 __raw_writel(__raw_readl(S3C2410_CLKCON) | S3C2410_CLKCON_IDLE, in s3c24xx_default_idle()
203 tmp += __raw_readl(S3C2410_CLKCON); /* ensure loop not optimised out */ in s3c24xx_default_idle()
207 __raw_writel(__raw_readl(S3C2410_CLKCON) & ~S3C2410_CLKCON_IDLE, in s3c24xx_default_idle()
Dpm-s3c2412.c45 tmp = __raw_readl(S3C2412_PWRCFG); in s3c2412_cpu_suspend()
120 tmp = __raw_readl(S3C2412_PWRCFG); in s3c2412_pm_resume()
/linux-4.4.14/arch/sh/kernel/cpu/sh3/
Dprobe.c33 data0 = __raw_readl(addr0); in cpu_probe()
35 data1 = __raw_readl(addr1); in cpu_probe()
39 data0 = __raw_readl(addr0); in cpu_probe()
42 data1 = __raw_readl(addr1); in cpu_probe()
45 data3 = __raw_readl(addr0); in cpu_probe()
/linux-4.4.14/arch/mips/mti-sead3/
Dsead3-display.c31 do { } while (__raw_readl(display + DISPLAY_CPLDSTATUS) & 1); in lcd_wait()
34 __raw_readl(display + DISPLAY_LCDINSTRUCTION); in lcd_wait()
37 do { } while (__raw_readl(display + DISPLAY_CPLDSTATUS) & 1); in lcd_wait()
38 } while (__raw_readl(display + DISPLAY_CPLDDATA) & LCD_IR_BF); in lcd_wait()
/linux-4.4.14/drivers/rtc/
Drtc-nuc900.c67 rtc_irq = __raw_readl(rtc->rtc_reg + REG_RTC_RIIR); in nuc900_rtc_interrupt()
95 while (!(__raw_readl(nuc900_rtc->rtc_reg + REG_RTC_AER) & AERRWENB) in check_rtc_access_enable()
142 __raw_writel(__raw_readl(rtc->rtc_reg + REG_RTC_RIER)| in nuc900_alarm_irq_enable()
145 __raw_writel(__raw_readl(rtc->rtc_reg + REG_RTC_RIER)& in nuc900_alarm_irq_enable()
156 timeval = __raw_readl(rtc->rtc_reg + REG_RTC_TLR); in nuc900_rtc_read_time()
157 clrval = __raw_readl(rtc->rtc_reg + REG_RTC_CLR); in nuc900_rtc_read_time()
189 timeval = __raw_readl(rtc->rtc_reg + REG_RTC_TAR); in nuc900_rtc_read_alarm()
190 carval = __raw_readl(rtc->rtc_reg + REG_RTC_CAR); in nuc900_rtc_read_alarm()
249 __raw_writel(__raw_readl(nuc900_rtc->rtc_reg + REG_RTC_TSSR) | MODE24, in nuc900_rtc_probe()
Drtc-tx4939.c36 while (__raw_readl(&rtcreg->ctl) & TX4939_RTCCTL_BUSY) { in tx4939_rtc_cmd()
64 (__raw_readl(&rtcreg->ctl) & TX4939_RTCCTL_ALME)); in tx4939_rtc_set_mmss()
80 (__raw_readl(&rtcreg->ctl) & TX4939_RTCCTL_ALME)); in tx4939_rtc_read_time()
87 buf[i] = __raw_readl(&rtcreg->dat); in tx4939_rtc_read_time()
138 (__raw_readl(&rtcreg->ctl) & TX4939_RTCCTL_ALME)); in tx4939_rtc_read_alarm()
145 buf[i] = __raw_readl(&rtcreg->dat); in tx4939_rtc_read_alarm()
146 ctl = __raw_readl(&rtcreg->ctl); in tx4939_rtc_read_alarm()
174 if (__raw_readl(&rtcreg->ctl) & TX4939_RTCCTL_ALMD) { in tx4939_rtc_interrupt()
204 *buf++ = __raw_readl(&rtcreg->dat); in tx4939_rtc_nvram_read()
/linux-4.4.14/drivers/net/ethernet/xilinx/
Dxilinx_emaclite.c161 reg_data = __raw_readl(drvdata->base_addr + XEL_TSR_OFFSET); in xemaclite_enable_interrupts()
187 reg_data = __raw_readl(drvdata->base_addr + XEL_TSR_OFFSET); in xemaclite_disable_interrupts()
192 reg_data = __raw_readl(drvdata->base_addr + XEL_RSR_OFFSET); in xemaclite_disable_interrupts()
326 reg_data = __raw_readl(addr + XEL_TSR_OFFSET); in xemaclite_send_data()
339 reg_data = __raw_readl(addr + XEL_TSR_OFFSET); in xemaclite_send_data()
357 reg_data = __raw_readl(addr + XEL_TSR_OFFSET); in xemaclite_send_data()
384 reg_data = __raw_readl(addr + XEL_RSR_OFFSET); in xemaclite_recv_data()
401 reg_data = __raw_readl(addr + XEL_RSR_OFFSET); in xemaclite_recv_data()
408 proto_type = ((ntohl(__raw_readl(addr + XEL_HEADER_OFFSET + in xemaclite_recv_data()
417 length = ((ntohl(__raw_readl(addr + in xemaclite_recv_data()
[all …]
/linux-4.4.14/arch/sh/drivers/pci/
Dpci-sh7751.c27 word = __raw_readl(SH7751_BCR1); in __area_sdram_check()
97 reg = __raw_readl(SH7751_BCR1); in sh7751_pci_init()
159 word = __raw_readl(SH7751_WCR1); in sh7751_pci_init()
161 word = __raw_readl(SH7751_WCR2); in sh7751_pci_init()
163 word = __raw_readl(SH7751_WCR3); in sh7751_pci_init()
165 word = __raw_readl(SH7751_MCR); in sh7751_pci_init()
Dfixups-landisk.c45 bcr1 = __raw_readl(SH7751_BCR1); in pci_fixup_pcic()
49 mcr = __raw_readl(SH7751_MCR); in pci_fixup_pcic()
Dfixups-rts7751r2d.c46 bcr1 = __raw_readl(SH7751_BCR1); in pci_fixup_pcic()
57 mcr = __raw_readl(SH7751_MCR); in pci_fixup_pcic()
Dpci-sh7780.c103 addr = __raw_readl(hose->reg_base + SH4_PCIALR); in sh7780_pci_err_irq()
122 status = __raw_readl(hose->reg_base + SH4_PCIAINT); in sh7780_pci_err_irq()
135 status = __raw_readl(hose->reg_base + SH4_PCIINT); in sh7780_pci_err_irq()
232 tmp = __raw_readl(hose->reg_base + SH4_PCICR); in sh7780_pci66_init()
242 tmp = __raw_readl(hose->reg_base + SH4_PCICR); in sh7780_pci66_init()
/linux-4.4.14/drivers/clk/imx/
Dclk-pllv2.c117 dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL); in clk_pllv2_recalc_rate()
118 dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP); in clk_pllv2_recalc_rate()
119 dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD); in clk_pllv2_recalc_rate()
120 dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN); in clk_pllv2_recalc_rate()
169 dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL); in clk_pllv2_set_rate()
198 reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) | MXC_PLL_DP_CTL_UPEN; in clk_pllv2_prepare()
203 reg = __raw_readl(pllbase + MXC_PLL_DP_CTL); in clk_pllv2_prepare()
225 reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) & ~MXC_PLL_DP_CTL_UPEN; in clk_pllv2_unprepare()
/linux-4.4.14/drivers/spi/
Dspi-nuc900.c80 val = __raw_readl(hw->regs + USI_SSR); in nuc900_slave_select()
94 val = __raw_readl(hw->regs + USI_CNT); in nuc900_slave_select()
126 val = __raw_readl(hw->regs + USI_CNT) & ~TXNUM; in nuc900_spi_setup_txnum()
145 val = __raw_readl(hw->regs + USI_CNT) & ~TXBITLEN; in nuc900_spi_setup_txbitlen()
161 val = __raw_readl(hw->regs + USI_CNT); in nuc900_spi_gobusy()
199 status = __raw_readl(hw->regs + USI_CNT); in nuc900_spi_irq()
206 hw->rx[count] = __raw_readl(hw->regs + USI_RX0); in nuc900_spi_irq()
230 val = __raw_readl(hw->regs + USI_CNT); in nuc900_tx_edge()
248 val = __raw_readl(hw->regs + USI_CNT); in nuc900_rx_edge()
266 val = __raw_readl(hw->regs + USI_CNT); in nuc900_send_first()
[all …]
Dspi-bcm63xx-hsspi.c115 reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG); in bcm63xx_hsspi_set_cs()
135 reg = __raw_readl(bs->regs + HSSPI_PROFILE_SIGNAL_CTRL_REG(profile)); in bcm63xx_hsspi_set_clk()
144 reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG); in bcm63xx_hsspi_set_clk()
225 reg = __raw_readl(bs->regs + in bcm63xx_hsspi_setup()
236 reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG); in bcm63xx_hsspi_setup()
299 reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG); in bcm63xx_hsspi_transfer_one()
315 if (__raw_readl(bs->regs + HSSPI_INT_STATUS_MASKED_REG) == 0) in bcm63xx_hsspi_interrupt()
395 reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG); in bcm63xx_hsspi_probe()
/linux-4.4.14/arch/sparc/lib/
DPeeCeeI.c151 *pi++ = __raw_readl(addr); in insl()
161 l = __raw_readl(addr); in insl()
165 l2 = __raw_readl(addr); in insl()
176 l = __raw_readl(addr); in insl()
182 l2 = __raw_readl(addr); in insl()
193 l = __raw_readl(addr); in insl()
197 l2 = __raw_readl(addr); in insl()
/linux-4.4.14/drivers/input/keyboard/
Dgoldfish_events.c49 type = __raw_readl(edev->addr + REG_READ); in events_interrupt()
50 code = __raw_readl(edev->addr + REG_READ); in events_interrupt()
51 value = __raw_readl(edev->addr + REG_READ); in events_interrupt()
68 size = __raw_readl(addr + REG_LEN) * 8; in events_import_bits()
91 count = __raw_readl(addr + REG_LEN) / sizeof(val); in events_import_abs_params()
101 val[j] = __raw_readl(edev->addr + REG_DATA + offset); in events_import_abs_params()
133 keymapnamelen = __raw_readl(addr + REG_LEN); in events_probe()
/linux-4.4.14/arch/arm/mach-gemini/
Dgpio.c53 reg = __raw_readl(base + GPIO_INT_EN); in _set_gpio_irqenable()
89 reg_type = __raw_readl(base + GPIO_INT_TYPE); in gpio_set_irq_type()
90 reg_level = __raw_readl(base + GPIO_INT_LEVEL); in gpio_set_irq_type()
91 reg_both = __raw_readl(base + GPIO_INT_BOTH_EDGE); in gpio_set_irq_type()
134 irq_stat = __raw_readl(GPIO_BASE(port) + GPIO_INT_STAT); in gpio_irq_handler()
160 reg = __raw_readl(base + GPIO_DIR); in _set_gpio_direction()
182 return (__raw_readl(base + GPIO_DATA_IN) >> (offset % 32)) & 1; in gemini_gpio_get()
Ddevices.c70 reg = __raw_readl(IO_ADDRESS(GEMINI_GLOBAL_BASE) + GLOBAL_STATUS); in platform_register_pflash()
81 reg = __raw_readl(IO_ADDRESS(GEMINI_GLOBAL_BASE) + GLOBAL_MISC_CTRL); in platform_register_pflash()
Dirq.c47 mask = __raw_readl(IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); in gemini_mask_irq()
56 mask = __raw_readl(IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); in gemini_unmask_irq()
/linux-4.4.14/arch/arm/mach-w90x900/
Dtime.c53 unsigned int val = __raw_readl(REG_TCSR0) & ~(0x03 << 27); in nuc900_clockevent_shutdown()
61 unsigned int val = __raw_readl(REG_TCSR0) & ~(0x03 << 27); in nuc900_clockevent_set_oneshot()
71 unsigned int val = __raw_readl(REG_TCSR0) & ~(0x03 << 27); in nuc900_clockevent_set_periodic()
86 val = __raw_readl(REG_TCSR0); in nuc900_clockevent_setnextevent()
161 val = __raw_readl(REG_TCSR1); in nuc900_clocksource_init()
Dgpio.c60 regval = __raw_readl(pio); in nuc900_gpio_get()
75 regval = __raw_readl(pio); in nuc900_gpio_set()
96 regval = __raw_readl(pio); in nuc900_dir_input()
115 regval = __raw_readl(pio); in nuc900_dir_output()
119 regval = __raw_readl(outreg); in nuc900_dir_output()
Dmfp.c62 mfpen = __raw_readl(REG_MFSEL); in mfp_set_groupf()
86 mfpen = __raw_readl(REG_MFSEL); in mfp_set_groupc()
116 mfpen = __raw_readl(REG_MFSEL); in mfp_set_groupi()
147 mfpen = __raw_readl(REG_MFSEL); in mfp_set_groupg()
188 mfpen = __raw_readl(REG_MFSEL); in mfp_set_groupd()
Dclock.c69 clken = __raw_readl(W90X900_VA_CLKPWR); in nuc900_clk_enable()
84 clken = __raw_readl(W90X900_VA_CLKPWR + SUBCLK); in nuc900_subclk_enable()
Dcpu.c167 val = __raw_readl(REG_CLKDIV); in nuc900_set_clkval()
190 val = __raw_readl(REG_CKSKEW); in nuc900_set_cpufreq()
211 idcode = __raw_readl(NUC900PDID); in nuc900_map_io()
/linux-4.4.14/arch/arm/mach-ixp4xx/
Dixp4xx_npe.c171 return (__raw_readl(&npe->regs->exec_status_cmd) & STAT_RUN) != 0; in npe_running()
188 __raw_readl(&npe->regs->exec_data); in npe_cmd_read()
189 __raw_readl(&npe->regs->exec_data); in npe_cmd_read()
190 return __raw_readl(&npe->regs->exec_data); in npe_cmd_read()
243 wc = __raw_readl(&npe->regs->watch_count); in npe_debug_instr()
250 if (wc != __raw_readl(&npe->regs->watch_count)) in npe_debug_instr()
295 ctl = (__raw_readl(&npe->regs->messaging_control) | 0x3F000000) & in npe_reset()
303 exec_count = __raw_readl(&npe->regs->exec_count); in npe_reset()
312 while (__raw_readl(&npe->regs->watchpoint_fifo) & WFIFO_VALID) in npe_reset()
314 while (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_OFNE) in npe_reset()
[all …]
Dixp4xx_qmgr.c40 __raw_writel((__raw_readl(reg) & ~(7 << bit)) | (src << bit), in qmgr_set_irq()
99 u32 req_bitmap = __raw_readl(&qmgr_regs->irqstat[half]); in qmgr_irq()
122 __raw_writel(__raw_readl(&qmgr_regs->irqen[half]) | mask, in qmgr_enable_irq()
134 __raw_writel(__raw_readl(&qmgr_regs->irqen[half]) & ~mask, in qmgr_disable_irq()
197 if (__raw_readl(&qmgr_regs->sram[queue])) { in qmgr_request_queue()
246 cfg = __raw_readl(&qmgr_regs->sram[queue]); in qmgr_release_queue()
/linux-4.4.14/arch/score/kernel/
Dirq.c60 __raw_writel((__raw_readl(SCORE_PIC + INT_MASKL) | \ in score_mask()
63 __raw_writel((__raw_readl(SCORE_PIC + INT_MASKH) | \ in score_mask()
72 __raw_writel((__raw_readl(SCORE_PIC + INT_MASKL) & \ in score_unmask()
75 __raw_writel((__raw_readl(SCORE_PIC + INT_MASKH) & \ in score_unmask()
/linux-4.4.14/sound/soc/mxs/
Dmxs-saif.c114 scr = __raw_readl(master_saif->base + SAIF_CTRL); in mxs_saif_set_clk()
213 stat = __raw_readl(saif->base + SAIF_STAT); in mxs_saif_put_mclk()
263 stat = __raw_readl(saif->base + SAIF_STAT); in mxs_saif_get_mclk()
296 stat = __raw_readl(saif->base + SAIF_STAT); in mxs_saif_set_dai_fmt()
302 scr0 = __raw_readl(saif->base + SAIF_CTRL); in mxs_saif_set_dai_fmt()
410 stat = __raw_readl(saif->base + SAIF_STAT); in mxs_saif_hw_params()
446 scr = __raw_readl(saif->base + SAIF_CTRL); in mxs_saif_hw_params()
556 __raw_readl(saif->base + SAIF_DATA); in mxs_saif_trigger()
557 __raw_readl(saif->base + SAIF_DATA); in mxs_saif_trigger()
564 __raw_readl(saif->base + SAIF_CTRL), in mxs_saif_trigger()
[all …]
/linux-4.4.14/arch/mips/ath79/
Dirq.c34 pending = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS) & in ath79_misc_irq_handler()
35 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); in ath79_misc_irq_handler()
56 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); in ar71xx_misc_irq_unmask()
60 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); in ar71xx_misc_irq_unmask()
69 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); in ar71xx_misc_irq_mask()
73 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); in ar71xx_misc_irq_mask()
82 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS); in ar724x_misc_irq_ack()
86 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS); in ar724x_misc_irq_ack()
Dearly_printk.c28 t = __raw_readl(reg); in prom_putchar_wait()
67 id = __raw_readl(base + AR71XX_RESET_REG_REV_ID); in prom_putchar_init()
Dcommon.c65 while (__raw_readl(flush_reg) & 0x1) in ath79_ddr_wb_flush()
70 while (__raw_readl(flush_reg) & 0x1) in ath79_ddr_wb_flush()
/linux-4.4.14/drivers/input/mouse/
Dpxa930_trkball.c61 tbcntr = __raw_readl(trkball->mmio_base + TBCNTR); in pxa930_trkball_interrupt()
63 if (tbcntr == __raw_readl(trkball->mmio_base + TBCNTR)) { in pxa930_trkball_interrupt()
86 if (__raw_readl(trkball->mmio_base + TBCR) == v) in write_tbcr()
104 tbcr = __raw_readl(trkball->mmio_base + TBCR); in pxa930_trkball_config()
110 tbcr = __raw_readl(trkball->mmio_base + TBCR); in pxa930_trkball_config()
118 __raw_readl(trkball->mmio_base + TBCR)); in pxa930_trkball_config()
132 uint32_t tbcr = __raw_readl(trkball->mmio_base + TBCR); in pxa930_trkball_disable()
/linux-4.4.14/drivers/tty/serial/
Dapbuart.h52 #define UART_GET_CHAR(port) (__raw_readl(APBBASE_DATA_P(port)))
54 #define UART_GET_STATUS(port) (__raw_readl(APBBASE_STATUS_P(port)))
56 #define UART_GET_CTRL(port) (__raw_readl(APBBASE_CTRL_P(port)))
58 #define UART_GET_SCAL(port) (__raw_readl(APBBASE_SCALAR_P(port)))
Dserial_ks8695.c47 #define UART_GET_CHAR(p) (__raw_readl((p)->membase + KS8695_URRB) & 0xFF)
49 #define UART_GET_FCR(p) __raw_readl((p)->membase + KS8695_URFC)
51 #define UART_GET_MSR(p) __raw_readl((p)->membase + KS8695_URMS)
52 #define UART_GET_LSR(p) __raw_readl((p)->membase + KS8695_URLS)
53 #define UART_GET_LCR(p) __raw_readl((p)->membase + KS8695_URLC)
55 #define UART_GET_MCR(p) __raw_readl((p)->membase + KS8695_URMC)
57 #define UART_GET_BRDR(p) __raw_readl((p)->membase + KS8695_URBD)
/linux-4.4.14/arch/mips/kernel/
Dgpio_txx9.c24 return __raw_readl(&txx9_pioptr->din) & (1 << offset); in txx9_gpio_get()
30 val = __raw_readl(&txx9_pioptr->dout); in txx9_gpio_set_raw()
52 __raw_writel(__raw_readl(&txx9_pioptr->dir) & ~(1 << offset), in txx9_gpio_dir_in()
65 __raw_writel(__raw_readl(&txx9_pioptr->dir) | (1 << offset), in txx9_gpio_dir_out()
Dirq_txx9.c72 __raw_writel((__raw_readl(ilrp) & ~(0xff << ofs)) in txx9_irq_unmask()
88 __raw_writel((__raw_readl(ilrp) & ~(0xff << ofs)) in txx9_irq_mask()
96 __raw_readl(&txx9_ircptr->ssr); in txx9_irq_mask()
131 cr = __raw_readl(crp); in txx9_irq_set_type()
186 u32 csr = __raw_readl(&txx9_ircptr->csr); in txx9_irq()
/linux-4.4.14/drivers/input/touchscreen/
Dw90p910_ts.c65 __raw_readl(w90p910_ts->ts_reg + 0x0c)); in w90p910_report_event()
67 __raw_readl(w90p910_ts->ts_reg + 0x10)); in w90p910_report_event()
79 ctlreg = __raw_readl(w90p910_ts->ts_reg); in w90p910_prepare_x_reading()
92 ctlreg = __raw_readl(w90p910_ts->ts_reg); in w90p910_prepare_y_reading()
104 ctlreg = __raw_readl(w90p910_ts->ts_reg); in w90p910_prepare_next_packet()
157 !(__raw_readl(w90p910_ts->ts_reg + 0x04) & ADC_DOWN)) { in w90p910_check_pen_up()
179 val = __raw_readl(w90p910_ts->ts_reg + 0x04); in w90p910_open()
187 val = __raw_readl(w90p910_ts->ts_reg); in w90p910_open()
205 val = __raw_readl(w90p910_ts->ts_reg); in w90p910_close()
/linux-4.4.14/arch/sh/mm/
Dtlb-debugfs.c48 mmucr = __raw_readl(MMUCR); in tlb_seq_show()
100 val = __raw_readl(addr1 | (entry << MMU_TLB_ENTRY_SHIFT)); in tlb_seq_show()
105 val = __raw_readl(addr2 | (entry << MMU_TLB_ENTRY_SHIFT)); in tlb_seq_show()
109 val = __raw_readl(data1 | (entry << MMU_TLB_ENTRY_SHIFT)); in tlb_seq_show()
113 val = __raw_readl(data2 | (entry << MMU_TLB_ENTRY_SHIFT)); in tlb_seq_show()
Dtlb-urb.c27 status = __raw_readl(MMUCR); in tlb_wire_entry()
50 status = __raw_readl(MMUCR); in tlb_wire_entry()
76 status = __raw_readl(MMUCR); in tlb_unwire_entry()
Dcache-sh2a.c32 data = __raw_readl(CACHE_OC_ADDRESS_ARRAY | addr); in sh2a_flush_oc_line()
72 unsigned long data = __raw_readl(v); in sh2a__flush_wback_region()
137 __raw_writel(__raw_readl(SH_CCR) | CCR_OCACHE_INVALIDATE, in sh2a__flush_invalidate_region()
171 __raw_writel(__raw_readl(SH_CCR) | CCR_ICACHE_INVALIDATE, in sh2a_flush_icache_range()
Dcache-sh4.c136 ccr = __raw_readl(SH_CCR); in flush_icache_all()
381 __raw_readl(CCN_PVR), in sh4_cache_init()
382 __raw_readl(CCN_CVR), in sh4_cache_init()
383 __raw_readl(CCN_PRR)); in sh4_cache_init()
Dcache-sh2.c31 unsigned long data = __raw_readl(addr | (way << 12)); in sh2__flush_wback_region()
66 ccr = __raw_readl(SH_CCR); in sh2__flush_invalidate_region()
Dcache-debugfs.c39 ccr = __raw_readl(SH_CCR); in cache_seq_show()
77 unsigned long data = __raw_readl(addr); in cache_seq_show()
Dpmb.c316 addr_val = __raw_readl(addr); in __clear_pmb_entry()
317 data_val = __raw_readl(data); in __clear_pmb_entry()
587 addr_val = __raw_readl(addr); in pmb_synchronize()
588 data_val = __raw_readl(data); in pmb_synchronize()
812 return (__raw_readl(PMB_PASCR) & PASCR_SE) == 0; in __in_29bit_mode()
828 addr = __raw_readl(mk_pmb_addr(i)); in pmb_seq_show()
829 data = __raw_readl(mk_pmb_data(i)); in pmb_seq_show()
Dcache-sh7705.c51 data = __raw_readl(addr); in cache_wback_all()
118 data = __raw_readl(addr) & (0x1ffffC00 | SH_CACHE_VALID); in __flush_dcache_page()
/linux-4.4.14/arch/arm/mach-s3c64xx/
Dirq-pm.c76 irq_uart_mask[i] = __raw_readl(S3C_VA_UARTx(i) + S3C64XX_UINTM); in s3c64xx_irq_pm_suspend()
79 grp->con = __raw_readl(S3C64XX_EINT12CON + (i * 4)); in s3c64xx_irq_pm_suspend()
80 grp->mask = __raw_readl(S3C64XX_EINT12MASK + (i * 4)); in s3c64xx_irq_pm_suspend()
81 grp->fltcon = __raw_readl(S3C64XX_EINT12FLTCON + (i * 4)); in s3c64xx_irq_pm_suspend()
Dpm.c52 val = __raw_readl(S3C64XX_NORMAL_CFG); in s3c64xx_pd_off()
67 val = __raw_readl(S3C64XX_NORMAL_CFG); in s3c64xx_pd_on()
75 if (__raw_readl(S3C64XX_BLK_PWR_STAT) & pd->pwr_stat) in s3c64xx_pd_on()
255 tmp = __raw_readl(S3C64XX_PWR_CFG); in s3c64xx_cpu_suspend()
262 __raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT), in s3c64xx_cpu_suspend()
309 __raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT), S3C64XX_WAKEUP_STAT); in s3c64xx_pm_prepare()
Dcommon.c255 mask = __raw_readl(S3C64XX_EINT0MASK); in s3c_irq_eint_mask()
264 mask = __raw_readl(S3C64XX_EINT0MASK); in s3c_irq_eint_unmask()
334 ctrl = __raw_readl(reg); in s3c_irq_eint_set_type()
375 u32 status = __raw_readl(S3C64XX_EINT0PEND); in s3c_irq_demux_eint()
376 u32 mask = __raw_readl(S3C64XX_EINT0MASK); in s3c_irq_demux_eint()
Dmach-real6410.c219 tmp = __raw_readl(S3C64XX_SPCON); in real6410_map_io()
225 tmp = __raw_readl(S3C64XX_MODEM_MIFPCON); in real6410_map_io()
308 cs1 = __raw_readl(S3C64XX_SROM_BW) & in real6410_machine_init()
Dmach-mini6410.c249 tmp = __raw_readl(S3C64XX_SPCON); in mini6410_map_io()
255 tmp = __raw_readl(S3C64XX_MODEM_MIFPCON); in mini6410_map_io()
339 cs1 = __raw_readl(S3C64XX_SROM_BW) & in mini6410_machine_init()
Dmach-anw6410.c94 tmp = __raw_readl(S3C64XX_SPCON); in anw6410_lcd_mode_set()
100 tmp = __raw_readl(S3C64XX_MODEM_MIFPCON); in anw6410_lcd_mode_set()
/linux-4.4.14/arch/arm/mach-versatile/
Dpci.c119 v = __raw_readl(addr); in versatile_read_config()
126 v = __raw_readl(addr); in versatile_read_config()
132 v = __raw_readl(addr); in versatile_read_config()
242 val = __raw_readl(SYS_PCICTL); in pci_versatile_setup()
269 if ((__raw_readl(VERSATILE_PCI_VIRT_BASE+(i<<11)+DEVICE_ID_OFFSET) == VP_PCI_DEVICE_ID) && in pci_versatile_setup()
270 (__raw_readl(VERSATILE_PCI_VIRT_BASE+(i<<11)+CLASS_ID_OFFSET) == VP_PCI_CLASS_ID)) { in pci_versatile_setup()
286 val = __raw_readl(local_pci_cfg_base + CSR_OFFSET); in pci_versatile_setup()
/linux-4.4.14/arch/arm/mach-ep93xx/include/mach/
Duncompress.h19 static unsigned int __raw_readl(unsigned int ptr) in __raw_readl() function
70 v = __raw_readl(PHYS_ETH_SELF_CTL); in ethernet_reset()
74 while (__raw_readl(PHYS_ETH_SELF_CTL) & ETH_SELF_CTL_RESET) in ethernet_reset()
/linux-4.4.14/arch/arm/mach-ixp4xx/include/mach/
Dqmgr.h103 val = __raw_readl(&qmgr_regs->acc[queue][0]); in qmgr_get_entry()
116 return (__raw_readl(&qmgr_regs->stat1[queue >> 3]) in __qmgr_get_stat1()
124 return (__raw_readl(&qmgr_regs->stat2[queue >> 4]) in __qmgr_get_stat2()
150 return (__raw_readl(&qmgr_regs->statne_h) >> in qmgr_stat_below_low_watermark()
177 return (__raw_readl(&qmgr_regs->statf_h) >> in qmgr_stat_full()
/linux-4.4.14/sound/soc/txx9/
Dtxx9aclc-ac97.c44 return __raw_readl(drvdata->base + ACINTSTS) & ACINT_REGACCRDY; in txx9aclc_regready()
55 if (!(__raw_readl(base + ACINTSTS) & ACINT_CODECRDY(ac97->num))) in txx9aclc_ac97_read()
67 dat = __raw_readl(base + ACREGACC); in txx9aclc_ac97_read()
111 (__raw_readl(base + ACINTSTS) & ready) == ready, in txx9aclc_ac97_cold_reset()
115 __raw_readl(base + ACINTSTS)); in txx9aclc_ac97_cold_reset()
133 __raw_writel(__raw_readl(base + ACINTMSTS), base + ACINTDIS); in txx9aclc_ac97_irq()
/linux-4.4.14/arch/sh/drivers/dma/
Ddmabrg.c90 dcr = __raw_readl(DMABRGCR); in dmabrg_irq()
113 dcr = __raw_readl(DMABRGCR); in dmabrg_disable_irq()
121 dcr = __raw_readl(DMABRGCR); in dmabrg_enable_irq()
174 or = __raw_readl(DMAOR); in dmabrg_init()
Ddma-sh.c96 u32 chcr = __raw_readl(dma_base_addr(chan->chan) + CHCR); in calc_xmit_shift()
114 chcr = __raw_readl(dma_base_addr(chan->chan) + CHCR); in dma_tei()
165 chcr = __raw_readl(dma_base_addr(chan->chan) + CHCR); in sh_dmac_enable_dma()
189 chcr = __raw_readl(dma_base_addr(chan->chan) + CHCR); in sh_dmac_disable_dma()
237 if (!(__raw_readl(dma_base_addr(chan->chan) + CHCR) & CHCR_DE)) in sh_dmac_get_dma_residue()
240 return __raw_readl(dma_base_addr(chan->chan) + TCR) in sh_dmac_get_dma_residue()
/linux-4.4.14/arch/arc/include/asm/
Dio.h38 #define ioread32be(p) ({ u32 __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(); __v; })
74 #define __raw_readl __raw_readl macro
75 static inline u32 __raw_readl(const volatile void __iomem *addr) in __raw_readl() function
153 __raw_readl(c)); __r; })
/linux-4.4.14/arch/arm/mach-s3c64xx/include/mach/
Dpm-core.h24 u32 tmp = __raw_readl(S3C_PCLK_GATE); in s3c_pm_debug_init_uart()
46 __raw_writel(__raw_readl(S3C64XX_EINT0PEND), S3C64XX_EINT0PEND); in s3c_pm_arch_prepare_irqs()
66 u32 ucon = __raw_readl(regs + S3C2410_UCON); in s3c_pm_arch_update_uart()
/linux-4.4.14/arch/metag/include/asm/
Dio.h38 #define __raw_readl __raw_readl macro
39 static inline u32 __raw_readl(const volatile void __iomem *addr) in __raw_readl() function
124 #define metag_in32(addr) __raw_readl((volatile void __iomem *)(addr))
/linux-4.4.14/drivers/ptp/
Dptp_ixp46x.c59 lo = __raw_readl(&regs->systime_lo); in ixp_systime_read()
60 hi = __raw_readl(&regs->systime_hi); in ixp_systime_read()
92 val = __raw_readl(&regs->event); in isr()
97 hi = __raw_readl(&regs->asms_hi); in isr()
98 lo = __raw_readl(&regs->asms_lo); in isr()
111 hi = __raw_readl(&regs->amms_hi); in isr()
112 lo = __raw_readl(&regs->amms_lo); in isr()
/linux-4.4.14/drivers/mmc/host/
Dau1xmmc.c167 u32 val = __raw_readl(HOST_CONFIG(host)); in IRQ_ON()
175 u32 val = __raw_readl(HOST_CONFIG2(host)); in FLUSH_FIFO()
190 u32 val = __raw_readl(HOST_CONFIG(host)); in IRQ_OFF()
203 config2 = __raw_readl(HOST_CONFIG2(host)); in SEND_STOP()
313 while (__raw_readl(HOST_CMD(host)) & SD_CMD_GO) in au1xmmc_send_command()
318 u32 status = __raw_readl(HOST_STATUS(host)); in au1xmmc_send_command()
321 status = __raw_readl(HOST_STATUS(host)); in au1xmmc_send_command()
346 status = __raw_readl(HOST_STATUS(host)); in au1xmmc_data_complete()
350 status = __raw_readl(HOST_STATUS(host)); in au1xmmc_data_complete()
387 u32 status = __raw_readl(HOST_STATUS(host)); in au1xmmc_tasklet_data()
[all …]
/linux-4.4.14/arch/sh/kernel/cpu/sh4/
Dclock-sh4-202.c27 int idx = __raw_readl(CPG2_FRQCR3) & 0x0007; in emi_clk_recalc()
55 int idx = (__raw_readl(CPG2_FRQCR3) >> 3) & 0x0007; in femi_clk_recalc()
93 int idx = (__raw_readl(CPG2_FRQCR3) >> 6) & 0x0007; in shoc_clk_recalc()
123 frqcr3 = __raw_readl(CPG2_FRQCR3); in shoc_clk_set_rate()
Dprobe.c31 pvr = (__raw_readl(CCN_PVR) >> 8) & 0xffffff; in cpu_probe()
32 prr = (__raw_readl(CCN_PRR) >> 4) & 0xff; in cpu_probe()
33 cvr = (__raw_readl(CCN_CVR)); in cpu_probe()
/linux-4.4.14/arch/arm/mach-shmobile/
Dpm-rmobile.c60 if (__raw_readl(rmobile_pd->base + PSTR) & mask) { in rmobile_pd_power_down()
65 if (!(__raw_readl(rmobile_pd->base + SPDCR) & mask)) in rmobile_pd_power_down()
74 __raw_readl(rmobile_pd->base + PSTR)); in rmobile_pd_power_down()
90 if (__raw_readl(rmobile_pd->base + PSTR) & mask) in __rmobile_pd_power_up()
96 if (!(__raw_readl(rmobile_pd->base + SWUCR) & mask)) in __rmobile_pd_power_up()
109 __raw_readl(rmobile_pd->base + PSTR)); in __rmobile_pd_power_up()
/linux-4.4.14/drivers/net/ethernet/ti/
Ddavinci_mdio.c148 ver = __raw_readl(&data->regs->version); in davinci_mdio_reset()
156 phy_mask = __raw_readl(&data->regs->alive); in davinci_mdio_reset()
179 reg = __raw_readl(&regs->user[0].access); in wait_for_user_access()
183 reg = __raw_readl(&regs->control); in wait_for_user_access()
197 reg = __raw_readl(&regs->user[0].access); in wait_for_user_access()
212 if (__raw_readl(&regs->control) & CONTROL_IDLE) in wait_for_idle()
253 reg = __raw_readl(&data->regs->user[0].access); in davinci_mdio_read()
435 ctrl = __raw_readl(&data->regs->control); in davinci_mdio_suspend()
/linux-4.4.14/arch/arm/include/asm/
Dcti.h89 val = __raw_readl(base + CTIINEN + trig_in * 4); in cti_map_trigger()
93 val = __raw_readl(base + CTIOUTEN + trig_out * 4); in cti_map_trigger()
131 val = __raw_readl(base + CTIINTACK); in cti_irq_ack()
Dio.h115 #define __raw_readl __raw_readl macro
116 static inline u32 __raw_readl(const volatile void __iomem *addr) in __raw_readl() function
258 __raw_readl(__io(p))); __iormb(); __v; })
293 __raw_readl(c)); __r; })
409 #define ioread32be(p) ({ __u32 __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(); __v; …
/linux-4.4.14/drivers/usb/host/
Dohci-pxa27x.c142 uint32_t uhcrhda = __raw_readl(pxa_ohci->mmio_base + UHCRHDA); in pxa27x_ohci_select_pmm()
143 uint32_t uhcrhdb = __raw_readl(pxa_ohci->mmio_base + UHCRHDB); in pxa27x_ohci_select_pmm()
223 uint32_t uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR); in pxa27x_setup_hc()
224 uint32_t uhcrhda = __raw_readl(pxa_ohci->mmio_base + UHCRHDA); in pxa27x_setup_hc()
262 uint32_t uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR); in pxa27x_reset_hc()
288 uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR) | UHCHR_FSBIR; in pxa27x_start_hc()
291 while (__raw_readl(pxa_ohci->mmio_base + UHCHR) & UHCHR_FSBIR) in pxa27x_start_hc()
305 uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR) & ~UHCHR_SSE; in pxa27x_start_hc()
331 uhccoms = __raw_readl(pxa_ohci->mmio_base + UHCCOMS) | 0x01; in pxa27x_stop_hc()
Dohci-nxp.c121 __raw_writel(__raw_readl(USB_CTRL) | USB_HOST_NEED_CLK_EN, USB_CTRL); in isp1301_configure_lpc32xx()
151 unsigned long tmp = __raw_readl(USB_OTG_STAT_CONTROL) | HOST_EN; in ohci_nxp_start_hc()
160 tmp = __raw_readl(USB_OTG_STAT_CONTROL) & ~HOST_EN; in ohci_nxp_stop_hc()
240 __raw_writel(__raw_readl(USB_CTRL) | USB_HOST_NEED_CLK_EN, USB_CTRL); in ohci_hcd_nxp_probe()
Dehci-w90x900.c69 val = __raw_readl(ehci->regs+PHY0_CTR); in usb_w90x900_probe()
73 val = __raw_readl(ehci->regs+PHY1_CTR); in usb_w90x900_probe()
/linux-4.4.14/arch/arm/mach-ks8695/include/mach/
Duncompress.h22 while (!(__raw_readl((void __iomem*)KS8695_UART_PA + KS8695_URLS) & URLS_URTHRE)) in putc()
30 while (!(__raw_readl((void __iomem*)KS8695_UART_PA + KS8695_URLS) & URLS_URTE)) in flush()
/linux-4.4.14/arch/m68k/coldfire/
Dintc.c72 imr = __raw_readl(MCFSIM_IMR); in mcf_setimr()
79 imr = __raw_readl(MCFSIM_IMR); in mcf_clrimr()
86 imr = __raw_readl(MCFSIM_IMR); in mcf_maskimr()
Dsltimers.c106 scnt = __raw_readl(TA(MCFSLT_SCNT)); in mcfslt_read_clk()
108 if (__raw_readl(TA(MCFSLT_SSR)) & MCFSLT_SSR_TE) { in mcfslt_read_clk()
110 scnt = __raw_readl(TA(MCFSLT_SCNT)); in mcfslt_read_clk()
Ddma_timer.c39 return __raw_readl(DTCN0); in cf_dt_get_cycles()
78 unsigned long cycl = __raw_readl(DTCN0); in sched_clock()
/linux-4.4.14/arch/mips/include/asm/mach-au1x00/
Dau1000_dma.h202 if (__raw_readl(chan->io + DMA_MODE_READ) & DMA_HALT) in halt_dma()
227 return (__raw_readl(chan->io + DMA_MODE_READ) & DMA_HALT) ? 1 : 0; in dma_halted()
286 return (__raw_readl(chan->io + DMA_MODE_READ) & DMA_AB) ? 1 : 0; in get_dma_active_buffer()
413 return __raw_readl(chan->io + DMA_MODE_READ) & (DMA_D0 | DMA_D1); in get_dma_buffer_done()
440 curBufCntReg = (__raw_readl(chan->io + DMA_MODE_READ) & DMA_AB) ? in get_dma_residue()
443 count = __raw_readl(chan->io + curBufCntReg) & DMA_COUNT_MASK; in get_dma_residue()
Dgpio-au1300.h36 return __raw_readl(roff + AU1300_GPIC_PINVAL) & bit; in au1300_gpio_get_value()
118 v = __raw_readl(roff + AU1300_GPIC_RSTVAL); in au1300_gpio_getinitlvl()
/linux-4.4.14/drivers/i2c/busses/
Di2c-iop3xx.c102 unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET); in iop3xx_i2c_transaction_cleanup()
118 u32 sr = __raw_readl(iop3xx_adap->ioaddr + SR_OFFSET); in iop3xx_i2c_irq_handler()
238 unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET); in iop3xx_i2c_send_target_addr()
264 unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET); in iop3xx_i2c_write_byte()
286 unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET); in iop3xx_i2c_read_byte()
302 *byte = __raw_readl(iop3xx_adap->ioaddr + DBR_OFFSET); in iop3xx_i2c_read_byte()
403 unsigned long cr = __raw_readl(adapter_data->ioaddr + CR_OFFSET); in iop3xx_i2c_remove()
/linux-4.4.14/arch/arm64/include/asm/
Dio.h87 #define __raw_readl __raw_readl macro
88 static inline u32 __raw_readl(const volatile void __iomem *addr) in __raw_readl() function
122 #define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32)__raw_readl(c)); __r; })
180 #define ioread32be(p) ({ __u32 __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(); __v; …
/linux-4.4.14/arch/arm/mach-lpc32xx/include/mach/
Duncompress.h43 while ((__raw_readl(_UARTREG(LPC32XX_UART_LSR_O)) & in putc()
52 __raw_writel(__raw_readl(_UARTREG(LPC32XX_UART_IIRFCR_O)) | in flush()
/linux-4.4.14/arch/mips/ralink/
Drt288x.c100 n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0); in prom_soc_init()
101 n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1); in prom_soc_init()
102 id = __raw_readl(sysc + SYSC_REG_CHIP_ID); in prom_soc_init()
Dmt7620.c524 n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0); in prom_soc_init()
525 n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1); in prom_soc_init()
526 rev = __raw_readl(sysc + SYSC_REG_CHIP_REV); in prom_soc_init()
540 u32 efuse = __raw_readl(sysc + SYSC_REG_EFUSE_CFG); in prom_soc_init()
560 cfg0 = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG0); in prom_soc_init()
573 pmu0 = __raw_readl(sysc + PMU0_CFG); in prom_soc_init()
574 pmu1 = __raw_readl(sysc + PMU1_CFG); in prom_soc_init()
Drt3883.c134 n0 = __raw_readl(sysc + RT3883_SYSC_REG_CHIPID0_3); in prom_soc_init()
135 n1 = __raw_readl(sysc + RT3883_SYSC_REG_CHIPID4_7); in prom_soc_init()
136 id = __raw_readl(sysc + RT3883_SYSC_REG_REVID); in prom_soc_init()
Dearly_printk.c43 return __raw_readl(uart_membase + reg); in uart_r32()
49 (__raw_readl(chipid_membase) == MT7628_CHIP_NAME1); in soc_is_mt7628()
Drt305x.c109 t = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG); in rt5350_get_mem_size()
229 n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0); in prom_soc_init()
230 n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1); in prom_soc_init()
261 id = __raw_readl(sysc + SYSC_REG_CHIP_ID); in prom_soc_init()
/linux-4.4.14/arch/arm/mach-ep93xx/
Dclock.c248 v = __raw_readl(clk->enable_reg); in __clk_enable()
279 v = __raw_readl(clk->enable_reg); in __clk_disable()
310 value = __raw_readl(EP93XX_SYSCON_PWRCNT); in get_uart_rate()
331 val = __raw_readl(clk->enable_reg); in set_keytchclk_rate()
420 val = __raw_readl(clk->enable_reg); in set_div_rate()
433 unsigned val = __raw_readl(clk->enable_reg); in set_i2s_sclk_rate()
450 unsigned val = __raw_readl(clk->enable_reg) & in set_i2s_lrclk_rate()
522 value = __raw_readl(EP93XX_SYSCON_CLKSET1); in ep93xx_clock_init()
535 value = __raw_readl(EP93XX_SYSCON_CLKSET2); in ep93xx_clock_init()
Dcore.c114 val = __raw_readl(EP93XX_SYSCON_DEVCFG); in ep93xx_devcfg_set_clear()
132 v = __raw_readl(EP93XX_SYSCON_SYSCFG); in ep93xx_chip_revision()
672 val = __raw_readl(EP93XX_SYSCON_I2SCLKDIV); in ep93xx_i2s_acquire()
854 if (__raw_readl(EP93XX_SECURITY_UNIQVAL) != 1) in ep93xx_get_soc_id()
857 id = __raw_readl(EP93XX_SECURITY_UNIQID); in ep93xx_get_soc_id()
858 id2 = __raw_readl(EP93XX_SECURITY_UNIQID2); in ep93xx_get_soc_id()
859 id3 = __raw_readl(EP93XX_SECURITY_UNIQID3); in ep93xx_get_soc_id()
860 id4 = __raw_readl(EP93XX_SECURITY_UNIQID4); in ep93xx_get_soc_id()
861 id5 = __raw_readl(EP93XX_SECURITY_UNIQID5); in ep93xx_get_soc_id()
/linux-4.4.14/arch/sh/kernel/cpu/
Dinit.c65 __raw_writel(__raw_readl(CPUOPM) & ~CPUOPM_RABD, CPUOPM); in speculative_execution_init()
68 (void)__raw_readl(CPUOPM); in speculative_execution_init()
83 unsigned long expmask = __raw_readl(EXPMASK); in expmask_init()
115 ccr = __raw_readl(SH_CCR); in cache_init()
/linux-4.4.14/drivers/watchdog/
Dks8695_wdt.c72 tmcon = __raw_readl(KS8695_TMR_VA + KS8695_TMCON); in ks8695_wdt_stop()
87 tmcon = __raw_readl(KS8695_TMR_VA + KS8695_TMCON); in ks8695_wdt_start()
94 tmcon = __raw_readl(KS8695_TMR_VA + KS8695_TMCON); in ks8695_wdt_start()
108 tmcon = __raw_readl(KS8695_TMR_VA + KS8695_TMCON); in ks8695_wdt_reload()
Dm54xx_wdt.c49 gms0 = __raw_readl(MCF_GPT_GMS0); in wdt_enable()
67 gms0 = __raw_readl(MCF_GPT_GMS0); in wdt_disable()
76 gms0 = __raw_readl(MCF_GPT_GMS0); in wdt_keepalive()
Dnuc900_wdt.c81 val = __raw_readl(nuc900_wdt->wdt_base + REG_WTCR); in nuc900_wdt_keepalive()
94 val = __raw_readl(nuc900_wdt->wdt_base + REG_WTCR); in nuc900_wdt_start()
114 val = __raw_readl(nuc900_wdt->wdt_base + REG_WTCR); in nuc900_wdt_stop()
/linux-4.4.14/arch/mips/txx9/generic/
Dirq_tx4939.c66 __raw_writel((__raw_readl(lvlp) & ~(0xff << ofs)) in tx4939_irq_unmask()
84 __raw_writel((__raw_readl(lvlp) & ~(0xff << ofs)) in tx4939_irq_mask()
138 cr = __raw_readl(crp); in tx4939_irq_set_type()
211 u32 csr = __raw_readl(&tx4939_ircptr->cs.r); in tx4939_irq()
/linux-4.4.14/arch/sh/include/asm/
Dmmu_context_32.h21 return __raw_readl(MMU_PTEAEX) & MMU_CONTEXT_ASID_MASK; in get_asid()
57 return (pgd_t *)__raw_readl(MMU_TTB); in get_TTB()
Dwatchdog.h73 return __raw_readl(WTCNT_R); in sh_wdt_read_cnt()
106 return __raw_readl(WTCSR_R); in sh_wdt_read_csr()
/linux-4.4.14/arch/arm/mach-iop13xx/include/mach/
Dadma.h157 return __raw_readl(ADMA_ADAR(chan)); in iop_chan_get_current_descriptor()
170 if (__raw_readl(ADMA_ACSR(chan)) & in iop_chan_is_busy()
532 adma_accr = __raw_readl(ADMA_ACCR(chan)); in iop_chan_append()
539 return __raw_readl(ADMA_ACSR(chan)); in iop_chan_get_status()
544 u32 adma_chan_ctrl = __raw_readl(ADMA_ACCR(chan)); in iop_chan_disable()
553 adma_chan_ctrl = __raw_readl(ADMA_ACCR(chan)); in iop_chan_enable()
560 u32 status = __raw_readl(ADMA_ACSR(chan)); in iop_adma_device_clear_eot_status()
567 u32 status = __raw_readl(ADMA_ACSR(chan)); in iop_adma_device_clear_eoc_status()
574 u32 status = __raw_readl(ADMA_ACSR(chan)); in iop_adma_device_clear_err_status()
Dtime.h29 unsigned long freq = __raw_readl(IOP13XX_PROCESSOR_FREQ); in iop13xx_core_freq()
54 unsigned long ratio = __raw_readl(IOP13XX_PROCESSOR_FREQ); in iop13xx_xsi_bus_ratio()
/linux-4.4.14/arch/sh/boot/romimage/
Dmmcif-sh7724.c36 __raw_writel(__raw_readl(MSTPCR2) & ~0x20000000, MSTPCR2); in mmcif_loader()
69 __raw_writel(__raw_readl(MSTPCR2) | 0x20000000, MSTPCR2); in mmcif_loader()
/linux-4.4.14/arch/mips/include/asm/mach-rc32434/
Ddma_v.h28 if (__raw_readl(&ch->dmac) & DMA_CHAN_RUN_BIT) { in rc32434_halt_dma()
31 if (__raw_readl(&ch->dmas) & DMA_STAT_HALT) { in rc32434_halt_dma()
/linux-4.4.14/drivers/sh/intc/
Daccess.c93 return intc_get_field_from_handle(__raw_readl(ptr), h); in test_32()
119 (void)__raw_readl(ptr); /* Defeat write posting */ in write_32()
158 value = intc_set_field_from_handle(__raw_readl(ptr), data, h); in modify_32()
160 (void)__raw_readl(ptr); /* Defeat write posting */ in modify_32()
/linux-4.4.14/arch/mips/ath25/
Dar5312.c40 return __raw_readl(ar5312_rst_base + reg); in ar5312_rst_reg_read()
191 ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL0); in ar5312_flash_init()
216 ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL1); in ar5312_flash_init()
219 ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL2); in ar5312_flash_init()
363 memcfg = __raw_readl(sdram_base + AR5312_MEM_CFG1); in ar5312_plat_mem_setup()
/linux-4.4.14/arch/sh/lib/
Dio.c22 *data++ = __raw_readl(addr); in __raw_readsl()
62 *data++ = __raw_readl(addr); in __raw_readsl()
/linux-4.4.14/arch/mips/include/asm/mach-ralink/
Dralink_regs.h43 return __raw_readl(rt_sysc_membase + reg); in rt_sysc_r32()
60 return __raw_readl(rt_memc_membase + reg); in rt_memc_r32()
/linux-4.4.14/drivers/clocksource/
Dtcb_clksrc.c51 upper = __raw_readl(tcaddr + ATMEL_TC_REG(1, CV)); in tc_get_cycles()
52 lower = __raw_readl(tcaddr + ATMEL_TC_REG(0, CV)); in tc_get_cycles()
53 } while (upper != __raw_readl(tcaddr + ATMEL_TC_REG(1, CV))); in tc_get_cycles()
61 return __raw_readl(tcaddr + ATMEL_TC_REG(0, CV)); in tc_get_cycles32()
182 sr = __raw_readl(dev->regs + ATMEL_TC_REG(2, SR)); in ch2_irq()
/linux-4.4.14/arch/sh/include/mach-common/mach/
Dmagicpanelr2.h24 #define SETBITS_OUTL(mask, reg) __raw_writel(__raw_readl(reg) | mask, reg)
27 #define CLRBITS_OUTL(mask, reg) __raw_writel(__raw_readl(reg) & ~mask, reg)
/linux-4.4.14/arch/arm/include/asm/hardware/
Diop3xx-adma.h265 return __raw_readl(DMA_DAR(chan)); in iop_chan_get_current_descriptor()
267 return __raw_readl(AAU_ADAR(chan)); in iop_chan_get_current_descriptor()
298 u32 status = __raw_readl(DMA_CSR(chan)); in iop_chan_is_busy()
815 dma_chan_ctrl = __raw_readl(DMA_CCR(chan)); in iop_chan_append()
822 return __raw_readl(DMA_CSR(chan)); in iop_chan_get_status()
827 u32 dma_chan_ctrl = __raw_readl(DMA_CCR(chan)); in iop_chan_disable()
834 u32 dma_chan_ctrl = __raw_readl(DMA_CCR(chan)); in iop_chan_enable()
842 u32 status = __raw_readl(DMA_CSR(chan)); in iop_adma_device_clear_eot_status()
849 u32 status = __raw_readl(DMA_CSR(chan)); in iop_adma_device_clear_eoc_status()
856 u32 status = __raw_readl(DMA_CSR(chan)); in iop_adma_device_clear_err_status()
/linux-4.4.14/arch/arm/mach-exynos/
Dfirmware.c118 *boot_addr = __raw_readl(boot_reg); in exynos_get_cpu_boot_addr()
239 tmp = __raw_readl(REG_CPU_STATE_ADDR + cpu * 4); in exynos_set_boot_flag()
252 tmp = __raw_readl(REG_CPU_STATE_ADDR + cpu * 4); in exynos_clear_boot_flag()
/linux-4.4.14/drivers/usb/musb/
Ddavinci.c69 u32 phy_ctrl = __raw_readl(USB_PHY_CTRL); in phy_on()
77 while ((__raw_readl(USB_PHY_CTRL) & USBPHY_PHYCLKGD) == 0) in phy_on()
83 u32 phy_ctrl = __raw_readl(USB_PHY_CTRL); in phy_off()
405 u32 phy_ctrl = __raw_readl(USB_PHY_CTRL); in davinci_musb_init()
416 u32 deepsleep = __raw_readl(DM355_DEEPSLEEP); in davinci_musb_init()
432 revision, __raw_readl(USB_PHY_CTRL), in davinci_musb_init()
451 u32 deepsleep = __raw_readl(DM355_DEEPSLEEP); in davinci_musb_exit()
Dda8xx.c101 u32 cfgchip2 = __raw_readl(CFGCHIP2); in phy_on()
111 while (!(__raw_readl(CFGCHIP2) & CFGCHIP2_PHYCLKGD)) in phy_on()
117 u32 cfgchip2 = __raw_readl(CFGCHIP2); in phy_off()
388 u32 cfgchip2 = __raw_readl(CFGCHIP2); in da8xx_musb_set_mode()
440 rev, __raw_readl(CFGCHIP2), in da8xx_musb_init()
/linux-4.4.14/drivers/pwm/
Dpwm-atmel-tcb.c92 cmr = __raw_readl(regs + ATMEL_TC_REG(group, CMR)); in atmel_tcb_pwm_request()
100 __raw_readl(regs + ATMEL_TC_REG(group, RA)); in atmel_tcb_pwm_request()
103 __raw_readl(regs + ATMEL_TC_REG(group, RB)); in atmel_tcb_pwm_request()
106 tcbpwm->period = __raw_readl(regs + ATMEL_TC_REG(group, RC)); in atmel_tcb_pwm_request()
155 cmr = __raw_readl(regs + ATMEL_TC_REG(group, CMR)); in atmel_tcb_pwm_disable()
211 cmr = __raw_readl(regs + ATMEL_TC_REG(group, CMR)); in atmel_tcb_pwm_enable()
/linux-4.4.14/arch/sparc/include/asm/
Dio_64.h43 #define __raw_readl __raw_readl macro
44 static inline u32 __raw_readl(const volatile void __iomem *addr) in __raw_readl() function
294 return __raw_readl(addr); in sbus_readl()
415 #define ioread32be __raw_readl
/linux-4.4.14/drivers/mtd/nand/
Dnuc900_nand.c46 __raw_readl((dev)->reg + REG_SMDATA)
118 val = __raw_readl(REG_SMISR); in nuc900_check_rb()
225 val = __raw_readl(nand->reg + REG_FMICSR); in nuc900_nand_enable()
230 val = __raw_readl(nand->reg + REG_SMCSR); in nuc900_nand_enable()
/linux-4.4.14/arch/mips/include/asm/mach-ath79/
Dath79.h130 return __raw_readl(ath79_pll_base + reg); in ath79_pll_rr()
140 return __raw_readl(ath79_reset_base + reg); in ath79_reset_rr()
/linux-4.4.14/arch/mips/include/asm/
Dbmips.h136 cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG); in bmips_post_dma_flush()
138 __raw_readl(cbr + BMIPS_RAC_CONFIG); in bmips_post_dma_flush()
/linux-4.4.14/sound/pci/mixart/
Dmixart_hwdep.h29 #define readl_be(x) be32_to_cpu(__raw_readl(x))
37 #define readl_le(x) le32_to_cpu(__raw_readl(x))
/linux-4.4.14/arch/mips/vdso/
Dgettimeofday.c87 hi = __raw_readl(gic + GIC_UMV_SH_COUNTER_63_32_OFS); in read_gic_count()
88 lo = __raw_readl(gic + GIC_UMV_SH_COUNTER_31_00_OFS); in read_gic_count()
89 hi2 = __raw_readl(gic + GIC_UMV_SH_COUNTER_63_32_OFS); in read_gic_count()
/linux-4.4.14/arch/microblaze/include/asm/
Dio.h53 #define in_be32(a) __raw_readl((const void __iomem __force *)(a))
63 #define in_le32(a) __le32_to_cpu(__raw_readl(a))
/linux-4.4.14/drivers/net/ethernet/nuvoton/
Dw90p910_ether.c182 val = __raw_readl(ether->reg + REG_MCMDR); in update_linkspeed_register()
357 val = __raw_readl(ether->reg + REG_MCMDR); in w90p910_return_default_idle()
392 *val = __raw_readl(ether->reg + REG_MISTA); in w90p910_get_and_clear_int()
401 val = __raw_readl(ether->reg + REG_MCMDR); in w90p910_set_global_maccmd()
413 val = __raw_readl(ether->reg + REG_CAMEN); in w90p910_enable_cam()
432 val = __raw_readl(ether->reg + REG_MCMDR); in w90p910_enable_tx()
447 val = __raw_readl(ether->reg + REG_MCMDR); in w90p910_enable_rx()
515 if ((__raw_readl(ether->reg + REG_MIIDA) & PHYBUSY) == 0) in w90p910_mdio_write()
536 if ((__raw_readl(ether->reg + REG_MIIDA) & PHYBUSY) == 0) in w90p910_mdio_read()
544 data = __raw_readl(ether->reg + REG_MIID); in w90p910_mdio_read()
[all …]
/linux-4.4.14/include/asm-generic/
Dio.h52 #ifndef __raw_readl
53 #define __raw_readl __raw_readl macro
54 static inline u32 __raw_readl(const volatile void __iomem *addr) in __raw_readl() function
129 return __le32_to_cpu(__raw_readl(addr)); in readl()
259 u32 x = __raw_readl(addr); in readsl()
624 return __be32_to_cpu(__raw_readl(addr)); in ioread32be()
/linux-4.4.14/drivers/net/phy/
Dmdio-bcm-unimac.c50 reg = __raw_readl(priv->base + MDIO_CMD); in unimac_mdio_start()
57 return __raw_readl(priv->base + MDIO_CMD) & MDIO_START_BUSY; in unimac_mdio_busy()
83 cmd = __raw_readl(priv->base + MDIO_CMD); in unimac_mdio_read()
/linux-4.4.14/arch/sh/drivers/superhyway/
Dops-sh4-202.c137 vcrh = __raw_readl(base); in sh4202_read_vcr()
138 vcrl = __raw_readl(base + sizeof(u32)); in sh4202_read_vcr()
/linux-4.4.14/arch/mips/mti-malta/
Dmalta-int.c76 irq = __raw_readl((u32 *)_pcictrl_bonito_pcicfg); in mips_pcibios_iack()
299 (__raw_readl(_msc01_biu_base + MSC01_SC_CFG_OFS) & in arch_init_irq()
339 i = __raw_readl(_msc01_biu_base + MSC01_SC_CFG_OFS); in arch_init_irq()
/linux-4.4.14/drivers/usb/gadget/udc/
Dat91_udc.c94 __raw_readl((udc)->udp_baseaddr + (reg))
122 csr = __raw_readl(ep->creg); in proc_ep_show()
342 csr = __raw_readl(creg); in read_fifo()
390 csr = __raw_readl(creg); in read_fifo()
404 u32 csr = __raw_readl(creg); in write_fifo()
426 csr = __raw_readl(creg); in write_fifo()
690 tmp = __raw_readl(ep->creg); in at91_ep_queue()
765 csr = __raw_readl(creg); in at91_ep_set_halt()
1024 u32 csr = __raw_readl(creg); in handle_ep()
1049 csr = __raw_readl(creg); in handle_ep()
[all …]
/linux-4.4.14/arch/arm/mach-integrator/
Dpci_v3.c305 #define v3_readl(o) (__raw_readl(pci_v3_base + (unsigned int)(o)))
521 …addr, fsr, pc, instr, __raw_readl(ap_syscon_base + INTEGRATOR_SC_LBFADDR_OFFSET), __raw_readl(ap_s… in v3_pci_fault()
569 __raw_readl(ap_syscon_base + INTEGRATOR_SC_LBFADDR_OFFSET), in v3_irq()
570 __raw_readl(ap_syscon_base + INTEGRATOR_SC_LBFCODE_OFFSET) & 255, in v3_irq()

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