1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Parts of this file are based on Ralink's 2.6.21 BSP
7 *
8 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
9 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
10 * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/module.h>
16
17#include <asm/mipsregs.h>
18#include <asm/mach-ralink/ralink_regs.h>
19#include <asm/mach-ralink/rt3883.h>
20#include <asm/mach-ralink/pinmux.h>
21
22#include "common.h"
23
24static struct rt2880_pmx_func i2c_func[] =  { FUNC("i2c", 0, 1, 2) };
25static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
26static struct rt2880_pmx_func uartf_func[] = {
27	FUNC("uartf", RT3883_GPIO_MODE_UARTF, 7, 8),
28	FUNC("pcm uartf", RT3883_GPIO_MODE_PCM_UARTF, 7, 8),
29	FUNC("pcm i2s", RT3883_GPIO_MODE_PCM_I2S, 7, 8),
30	FUNC("i2s uartf", RT3883_GPIO_MODE_I2S_UARTF, 7, 8),
31	FUNC("pcm gpio", RT3883_GPIO_MODE_PCM_GPIO, 11, 4),
32	FUNC("gpio uartf", RT3883_GPIO_MODE_GPIO_UARTF, 7, 4),
33	FUNC("gpio i2s", RT3883_GPIO_MODE_GPIO_I2S, 7, 4),
34};
35static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) };
36static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) };
37static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
38static struct rt2880_pmx_func lna_a_func[] = { FUNC("lna a", 0, 32, 3) };
39static struct rt2880_pmx_func lna_g_func[] = { FUNC("lna a", 0, 35, 3) };
40static struct rt2880_pmx_func pci_func[] = {
41	FUNC("pci-dev", 0, 40, 32),
42	FUNC("pci-host2", 1, 40, 32),
43	FUNC("pci-host1", 2, 40, 32),
44	FUNC("pci-fnc", 3, 40, 32)
45};
46static struct rt2880_pmx_func ge1_func[] = { FUNC("ge1", 0, 72, 12) };
47static struct rt2880_pmx_func ge2_func[] = { FUNC("ge1", 0, 84, 12) };
48
49static struct rt2880_pmx_group rt3883_pinmux_data[] = {
50	GRP("i2c", i2c_func, 1, RT3883_GPIO_MODE_I2C),
51	GRP("spi", spi_func, 1, RT3883_GPIO_MODE_SPI),
52	GRP("uartf", uartf_func, RT3883_GPIO_MODE_UART0_MASK,
53		RT3883_GPIO_MODE_UART0_SHIFT),
54	GRP("uartlite", uartlite_func, 1, RT3883_GPIO_MODE_UART1),
55	GRP("jtag", jtag_func, 1, RT3883_GPIO_MODE_JTAG),
56	GRP("mdio", mdio_func, 1, RT3883_GPIO_MODE_MDIO),
57	GRP("lna a", lna_a_func, 1, RT3883_GPIO_MODE_LNA_A),
58	GRP("lna g", lna_g_func, 1, RT3883_GPIO_MODE_LNA_G),
59	GRP("pci", pci_func, RT3883_GPIO_MODE_PCI_MASK,
60		RT3883_GPIO_MODE_PCI_SHIFT),
61	GRP("ge1", ge1_func, 1, RT3883_GPIO_MODE_GE1),
62	GRP("ge2", ge2_func, 1, RT3883_GPIO_MODE_GE2),
63	{ 0 }
64};
65
66static void rt3883_wdt_reset(void)
67{
68	u32 t;
69
70	/* enable WDT reset output on GPIO 2 */
71	t = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG1);
72	t |= RT3883_SYSCFG1_GPIO2_AS_WDT_OUT;
73	rt_sysc_w32(t, RT3883_SYSC_REG_SYSCFG1);
74}
75
76void __init ralink_clk_init(void)
77{
78	unsigned long cpu_rate, sys_rate;
79	u32 syscfg0;
80	u32 clksel;
81	u32 ddr2;
82
83	syscfg0 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG0);
84	clksel = ((syscfg0 >> RT3883_SYSCFG0_CPUCLK_SHIFT) &
85		RT3883_SYSCFG0_CPUCLK_MASK);
86	ddr2 = syscfg0 & RT3883_SYSCFG0_DRAM_TYPE_DDR2;
87
88	switch (clksel) {
89	case RT3883_SYSCFG0_CPUCLK_250:
90		cpu_rate = 250000000;
91		sys_rate = (ddr2) ? 125000000 : 83000000;
92		break;
93	case RT3883_SYSCFG0_CPUCLK_384:
94		cpu_rate = 384000000;
95		sys_rate = (ddr2) ? 128000000 : 96000000;
96		break;
97	case RT3883_SYSCFG0_CPUCLK_480:
98		cpu_rate = 480000000;
99		sys_rate = (ddr2) ? 160000000 : 120000000;
100		break;
101	case RT3883_SYSCFG0_CPUCLK_500:
102		cpu_rate = 500000000;
103		sys_rate = (ddr2) ? 166000000 : 125000000;
104		break;
105	}
106
107	ralink_clk_add("cpu", cpu_rate);
108	ralink_clk_add("10000100.timer", sys_rate);
109	ralink_clk_add("10000120.watchdog", sys_rate);
110	ralink_clk_add("10000500.uart", 40000000);
111	ralink_clk_add("10000b00.spi", sys_rate);
112	ralink_clk_add("10000c00.uartlite", 40000000);
113	ralink_clk_add("10100000.ethernet", sys_rate);
114	ralink_clk_add("10180000.wmac", 40000000);
115}
116
117void __init ralink_of_remap(void)
118{
119	rt_sysc_membase = plat_of_remap_node("ralink,rt3883-sysc");
120	rt_memc_membase = plat_of_remap_node("ralink,rt3883-memc");
121
122	if (!rt_sysc_membase || !rt_memc_membase)
123		panic("Failed to remap core resources");
124}
125
126void prom_soc_init(struct ralink_soc_info *soc_info)
127{
128	void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT3883_SYSC_BASE);
129	const char *name;
130	u32 n0;
131	u32 n1;
132	u32 id;
133
134	n0 = __raw_readl(sysc + RT3883_SYSC_REG_CHIPID0_3);
135	n1 = __raw_readl(sysc + RT3883_SYSC_REG_CHIPID4_7);
136	id = __raw_readl(sysc + RT3883_SYSC_REG_REVID);
137
138	if (n0 == RT3883_CHIP_NAME0 && n1 == RT3883_CHIP_NAME1) {
139		soc_info->compatible = "ralink,rt3883-soc";
140		name = "RT3883";
141	} else {
142		panic("rt3883: unknown SoC, n0:%08x n1:%08x", n0, n1);
143	}
144
145	snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
146		"Ralink %s ver:%u eco:%u",
147		name,
148		(id >> RT3883_REVID_VER_ID_SHIFT) & RT3883_REVID_VER_ID_MASK,
149		(id & RT3883_REVID_ECO_ID_MASK));
150
151	soc_info->mem_base = RT3883_SDRAM_BASE;
152	soc_info->mem_size_min = RT3883_MEM_SIZE_MIN;
153	soc_info->mem_size_max = RT3883_MEM_SIZE_MAX;
154
155	rt2880_pinmux_data = rt3883_pinmux_data;
156
157	ralink_soc == RT3883_SOC;
158}
159