1/* 2 * Copyright (c) 2006-2008 Simtec Electronics 3 * http://armlinux.simtec.co.uk/ 4 * Ben Dooks <ben@simtec.co.uk> 5 * 6 * S3C2412/S3C2443 (PL093 based) IO timing support 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11*/ 12 13#include <linux/init.h> 14#include <linux/module.h> 15#include <linux/interrupt.h> 16#include <linux/ioport.h> 17#include <linux/cpufreq.h> 18#include <linux/seq_file.h> 19#include <linux/device.h> 20#include <linux/delay.h> 21#include <linux/clk.h> 22#include <linux/err.h> 23#include <linux/slab.h> 24 25#include <linux/amba/pl093.h> 26 27#include <asm/mach/arch.h> 28#include <asm/mach/map.h> 29 30#include <plat/cpu.h> 31#include <plat/cpu-freq-core.h> 32 33#include <mach/s3c2412.h> 34 35#define print_ns(x) ((x) / 10), ((x) % 10) 36 37/** 38 * s3c2412_print_timing - print timing infromation via printk. 39 * @pfx: The prefix to print each line with. 40 * @iot: The IO timing information 41 */ 42static void s3c2412_print_timing(const char *pfx, struct s3c_iotimings *iot) 43{ 44 struct s3c2412_iobank_timing *bt; 45 unsigned int bank; 46 47 for (bank = 0; bank < MAX_BANKS; bank++) { 48 bt = iot->bank[bank].io_2412; 49 if (!bt) 50 continue; 51 52 printk(KERN_DEBUG "%s: %d: idcy=%d.%d wstrd=%d.%d wstwr=%d,%d" 53 "wstoen=%d.%d wstwen=%d.%d wstbrd=%d.%d\n", pfx, bank, 54 print_ns(bt->idcy), 55 print_ns(bt->wstrd), 56 print_ns(bt->wstwr), 57 print_ns(bt->wstoen), 58 print_ns(bt->wstwen), 59 print_ns(bt->wstbrd)); 60 } 61} 62 63/** 64 * to_div - turn a cycle length into a divisor setting. 65 * @cyc_tns: The cycle time in 10ths of nanoseconds. 66 * @clk_tns: The clock period in 10ths of nanoseconds. 67 */ 68static inline unsigned int to_div(unsigned int cyc_tns, unsigned int clk_tns) 69{ 70 return cyc_tns ? DIV_ROUND_UP(cyc_tns, clk_tns) : 0; 71} 72 73/** 74 * calc_timing - calculate timing divisor value and check in range. 75 * @hwtm: The hardware timing in 10ths of nanoseconds. 76 * @clk_tns: The clock period in 10ths of nanoseconds. 77 * @err: Pointer to err variable to update in event of failure. 78 */ 79static unsigned int calc_timing(unsigned int hwtm, unsigned int clk_tns, 80 unsigned int *err) 81{ 82 unsigned int ret = to_div(hwtm, clk_tns); 83 84 if (ret > 0xf) 85 *err = -EINVAL; 86 87 return ret; 88} 89 90/** 91 * s3c2412_calc_bank - calculate the bank divisor settings. 92 * @cfg: The current frequency configuration. 93 * @bt: The bank timing. 94 */ 95static int s3c2412_calc_bank(struct s3c_cpufreq_config *cfg, 96 struct s3c2412_iobank_timing *bt) 97{ 98 unsigned int hclk = cfg->freq.hclk_tns; 99 int err = 0; 100 101 bt->smbidcyr = calc_timing(bt->idcy, hclk, &err); 102 bt->smbwstrd = calc_timing(bt->wstrd, hclk, &err); 103 bt->smbwstwr = calc_timing(bt->wstwr, hclk, &err); 104 bt->smbwstoen = calc_timing(bt->wstoen, hclk, &err); 105 bt->smbwstwen = calc_timing(bt->wstwen, hclk, &err); 106 bt->smbwstbrd = calc_timing(bt->wstbrd, hclk, &err); 107 108 return err; 109} 110 111/** 112 * s3c2412_iotiming_debugfs - debugfs show io bank timing information 113 * @seq: The seq_file to write output to using seq_printf(). 114 * @cfg: The current configuration. 115 * @iob: The IO bank information to decode. 116*/ 117void s3c2412_iotiming_debugfs(struct seq_file *seq, 118 struct s3c_cpufreq_config *cfg, 119 union s3c_iobank *iob) 120{ 121 struct s3c2412_iobank_timing *bt = iob->io_2412; 122 123 seq_printf(seq, 124 "\tRead: idcy=%d.%d wstrd=%d.%d wstwr=%d,%d" 125 "wstoen=%d.%d wstwen=%d.%d wstbrd=%d.%d\n", 126 print_ns(bt->idcy), 127 print_ns(bt->wstrd), 128 print_ns(bt->wstwr), 129 print_ns(bt->wstoen), 130 print_ns(bt->wstwen), 131 print_ns(bt->wstbrd)); 132} 133 134/** 135 * s3c2412_iotiming_calc - calculate all the bank divisor settings. 136 * @cfg: The current frequency configuration. 137 * @iot: The bank timing information. 138 * 139 * Calculate the timing information for all the banks that are 140 * configured as IO, using s3c2412_calc_bank(). 141 */ 142int s3c2412_iotiming_calc(struct s3c_cpufreq_config *cfg, 143 struct s3c_iotimings *iot) 144{ 145 struct s3c2412_iobank_timing *bt; 146 int bank; 147 int ret; 148 149 for (bank = 0; bank < MAX_BANKS; bank++) { 150 bt = iot->bank[bank].io_2412; 151 if (!bt) 152 continue; 153 154 ret = s3c2412_calc_bank(cfg, bt); 155 if (ret) { 156 printk(KERN_ERR "%s: cannot calculate bank %d io\n", 157 __func__, bank); 158 goto err; 159 } 160 } 161 162 return 0; 163 err: 164 return ret; 165} 166 167/** 168 * s3c2412_iotiming_set - set the timing information 169 * @cfg: The current frequency configuration. 170 * @iot: The bank timing information. 171 * 172 * Set the IO bank information from the details calculated earlier from 173 * calling s3c2412_iotiming_calc(). 174 */ 175void s3c2412_iotiming_set(struct s3c_cpufreq_config *cfg, 176 struct s3c_iotimings *iot) 177{ 178 struct s3c2412_iobank_timing *bt; 179 void __iomem *regs; 180 int bank; 181 182 /* set the io timings from the specifier */ 183 184 for (bank = 0; bank < MAX_BANKS; bank++) { 185 bt = iot->bank[bank].io_2412; 186 if (!bt) 187 continue; 188 189 regs = S3C2412_SSMC_BANK(bank); 190 191 __raw_writel(bt->smbidcyr, regs + SMBIDCYR); 192 __raw_writel(bt->smbwstrd, regs + SMBWSTRDR); 193 __raw_writel(bt->smbwstwr, regs + SMBWSTWRR); 194 __raw_writel(bt->smbwstoen, regs + SMBWSTOENR); 195 __raw_writel(bt->smbwstwen, regs + SMBWSTWENR); 196 __raw_writel(bt->smbwstbrd, regs + SMBWSTBRDR); 197 } 198} 199 200static inline unsigned int s3c2412_decode_timing(unsigned int clock, u32 reg) 201{ 202 return (reg & 0xf) * clock; 203} 204 205static void s3c2412_iotiming_getbank(struct s3c_cpufreq_config *cfg, 206 struct s3c2412_iobank_timing *bt, 207 unsigned int bank) 208{ 209 unsigned long clk = cfg->freq.hclk_tns; /* ssmc clock??? */ 210 void __iomem *regs = S3C2412_SSMC_BANK(bank); 211 212 bt->idcy = s3c2412_decode_timing(clk, __raw_readl(regs + SMBIDCYR)); 213 bt->wstrd = s3c2412_decode_timing(clk, __raw_readl(regs + SMBWSTRDR)); 214 bt->wstoen = s3c2412_decode_timing(clk, __raw_readl(regs + SMBWSTOENR)); 215 bt->wstwen = s3c2412_decode_timing(clk, __raw_readl(regs + SMBWSTWENR)); 216 bt->wstbrd = s3c2412_decode_timing(clk, __raw_readl(regs + SMBWSTBRDR)); 217} 218 219/** 220 * bank_is_io - return true if bank is (possibly) IO. 221 * @bank: The bank number. 222 * @bankcfg: The value of S3C2412_EBI_BANKCFG. 223 */ 224static inline bool bank_is_io(unsigned int bank, u32 bankcfg) 225{ 226 if (bank < 2) 227 return true; 228 229 return !(bankcfg & (1 << bank)); 230} 231 232int s3c2412_iotiming_get(struct s3c_cpufreq_config *cfg, 233 struct s3c_iotimings *timings) 234{ 235 struct s3c2412_iobank_timing *bt; 236 u32 bankcfg = __raw_readl(S3C2412_EBI_BANKCFG); 237 unsigned int bank; 238 239 /* look through all banks to see what is currently set. */ 240 241 for (bank = 0; bank < MAX_BANKS; bank++) { 242 if (!bank_is_io(bank, bankcfg)) 243 continue; 244 245 bt = kzalloc(sizeof(struct s3c2412_iobank_timing), GFP_KERNEL); 246 if (!bt) { 247 printk(KERN_ERR "%s: no memory for bank\n", __func__); 248 return -ENOMEM; 249 } 250 251 timings->bank[bank].io_2412 = bt; 252 s3c2412_iotiming_getbank(cfg, bt, bank); 253 } 254 255 s3c2412_print_timing("get", timings); 256 return 0; 257} 258 259/* this is in here as it is so small, it doesn't currently warrant a file 260 * to itself. We expect that any s3c24xx needing this is going to also 261 * need the iotiming support. 262 */ 263void s3c2412_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg) 264{ 265 struct s3c_cpufreq_board *board = cfg->board; 266 u32 refresh; 267 268 WARN_ON(board == NULL); 269 270 /* Reduce both the refresh time (in ns) and the frequency (in MHz) 271 * down to ensure that we do not overflow 32 bit numbers. 272 * 273 * This should work for HCLK up to 133MHz and refresh period up 274 * to 30usec. 275 */ 276 277 refresh = (cfg->freq.hclk / 100) * (board->refresh / 10); 278 refresh = DIV_ROUND_UP(refresh, (1000 * 1000)); /* apply scale */ 279 refresh &= ((1 << 16) - 1); 280 281 s3c_freq_dbg("%s: refresh value %u\n", __func__, (unsigned int)refresh); 282 283 __raw_writel(refresh, S3C2412_REFRESH); 284} 285