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Searched refs:REG_READ (Results 1 – 129 of 129) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/gma500/
Dcdv_device.c47 REG_READ(vga_reg); in cdv_disable_vga()
62 if (REG_READ(SDVOB) & SDVO_DETECTED) { in cdv_output_init()
64 if (REG_READ(DP_B) & DP_DETECTED) in cdv_output_init()
68 if (REG_READ(SDVOC) & SDVO_DETECTED) { in cdv_output_init()
70 if (REG_READ(DP_C) & DP_DETECTED) in cdv_output_init()
86 return REG_READ(BLC_PWM_CTL2) & PWM_LEGACY_MODE; in cdv_backlight_combination_mode()
91 u32 max = REG_READ(BLC_PWM_CTL); in cdv_get_max_backlight()
109 u32 val = REG_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; in cdv_get_brightness()
145 blc_pwm_ctl = REG_READ(BLC_PWM_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK; in cdv_set_brightness()
274 regs->cdv.saveDSPCLK_GATE_D = REG_READ(DSPCLK_GATE_D); in cdv_save_display_registers()
[all …]
Dmdfld_intel_display.c73 temp = REG_READ(map->conf); in mdfldWaitForPipeDisable()
101 temp = REG_READ(map->conf); in mdfldWaitForPipeEnable()
115 pfit_control = REG_READ(PFIT_CONTROL); in psb_intel_panel_fitter_pipe()
133 dspcntr = REG_READ(dspcntr_reg); in mdfld__intel_plane_set_alpha()
202 dspcntr = REG_READ(map->cntr); in mdfld__intel_pipe_set_base()
225 REG_READ(map->linoff); in mdfld__intel_pipe_set_base()
227 REG_READ(map->surf); in mdfld__intel_pipe_set_base()
252 temp = REG_READ(map->cntr); in mdfld_disable_crtc()
257 REG_WRITE(map->base, REG_READ(map->base)); in mdfld_disable_crtc()
258 REG_READ(map->base); in mdfld_disable_crtc()
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Dgma_display.c88 dspcntr = REG_READ(map->cntr); in gma_pipe_set_base()
120 REG_READ(map->base); in gma_pipe_set_base()
123 REG_READ(map->base); in gma_pipe_set_base()
125 REG_READ(map->surf); in gma_pipe_set_base()
226 temp = REG_READ(map->dpll); in gma_crtc_dpms()
229 REG_READ(map->dpll); in gma_crtc_dpms()
233 REG_READ(map->dpll); in gma_crtc_dpms()
237 REG_READ(map->dpll); in gma_crtc_dpms()
243 temp = REG_READ(map->cntr); in gma_crtc_dpms()
248 REG_WRITE(map->base, REG_READ(map->base)); in gma_crtc_dpms()
[all …]
Dcdv_intel_display.c143 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); in cdv_sb_read()
155 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); in cdv_sb_read()
161 *val = REG_READ(SB_DATA); in cdv_sb_read()
178 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); in cdv_sb_write()
191 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); in cdv_sb_write()
212 REG_READ(DPIO_CFG); in cdv_sb_reset()
479 if (REG_READ(FW_BLC_SELF) & FW_BLC_SELF_EN) { in cdv_disable_sr()
482 REG_WRITE(FW_BLC_SELF, (REG_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN)); in cdv_disable_sr()
483 REG_READ(FW_BLC_SELF); in cdv_disable_sr()
491 REG_READ(OV_OVADD); in cdv_disable_sr()
[all …]
Doaktrail_hdmi.c291 dpll = REG_READ(DPLL_CTRL); in oaktrail_crtc_hdmi_mode_set()
307 dpll = REG_READ(DPLL_CTRL); in oaktrail_crtc_hdmi_mode_set()
355 dspcntr = REG_READ(dspcntr_reg); in oaktrail_crtc_hdmi_mode_set()
361 pipeconf = REG_READ(pipeconf_reg); in oaktrail_crtc_hdmi_mode_set()
365 REG_READ(pipeconf_reg); in oaktrail_crtc_hdmi_mode_set()
368 REG_READ(PCH_PIPEBCONF); in oaktrail_crtc_hdmi_mode_set()
391 temp = REG_READ(DSPBCNTR); in oaktrail_crtc_hdmi_dpms()
394 REG_READ(DSPBCNTR); in oaktrail_crtc_hdmi_dpms()
396 REG_WRITE(DSPBSURF, REG_READ(DSPBSURF)); in oaktrail_crtc_hdmi_dpms()
397 REG_READ(DSPBSURF); in oaktrail_crtc_hdmi_dpms()
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Dpsb_lid.c40 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | POWER_TARGET_ON); in psb_lid_timer_func()
42 pp_status = REG_READ(PP_STATUS); in psb_lid_timer_func()
46 if (REG_READ(PP_STATUS) & PP_ON) { in psb_lid_timer_func()
56 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & ~POWER_TARGET_ON); in psb_lid_timer_func()
58 pp_status = REG_READ(PP_STATUS); in psb_lid_timer_func()
Dpsb_intel_lvds.c77 ret = REG_READ(BLC_PWM_CTL); in psb_intel_lvds_get_max_backlight()
89 REG_READ(BLC_PWM_CTL), dev_priv->regs.saveBLC_PWM_CTL); in psb_intel_lvds_get_max_backlight()
201 blc_pwm_ctl = REG_READ(BLC_PWM_CTL); in psb_intel_lvds_set_backlight()
232 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | in psb_intel_lvds_set_power()
235 pp_status = REG_READ(PP_STATUS); in psb_intel_lvds_set_power()
243 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & in psb_intel_lvds_set_power()
246 pp_status = REG_READ(PP_STATUS); in psb_intel_lvds_set_power()
274 lvds_priv->savePP_ON = REG_READ(LVDSPP_ON); in psb_intel_lvds_save()
275 lvds_priv->savePP_OFF = REG_READ(LVDSPP_OFF); in psb_intel_lvds_save()
276 lvds_priv->saveLVDS = REG_READ(LVDS); in psb_intel_lvds_save()
[all …]
Dpsb_intel_display.c93 pfit_control = REG_READ(PFIT_CONTROL); in psb_intel_panel_fitter_pipe()
202 pipeconf = REG_READ(map->conf); in psb_intel_crtc_mode_set()
226 REG_READ(map->dpll); in psb_intel_crtc_mode_set()
235 u32 lvds = REG_READ(LVDS); in psb_intel_crtc_mode_set()
256 REG_READ(LVDS); in psb_intel_crtc_mode_set()
261 REG_READ(map->dpll); in psb_intel_crtc_mode_set()
268 REG_READ(map->dpll); in psb_intel_crtc_mode_set()
293 REG_READ(map->conf); in psb_intel_crtc_mode_set()
322 dpll = REG_READ(map->dpll); in psb_intel_crtc_clock_get()
324 fp = REG_READ(map->fp0); in psb_intel_crtc_clock_get()
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Dcdv_intel_dp.c390 pp = REG_READ(PP_CONTROL); in cdv_intel_edp_panel_vdd_on()
394 REG_READ(PP_CONTROL); in cdv_intel_edp_panel_vdd_on()
404 pp = REG_READ(PP_CONTROL); in cdv_intel_edp_panel_vdd_off()
408 REG_READ(PP_CONTROL); in cdv_intel_edp_panel_vdd_off()
423 pp = REG_READ(PP_CONTROL); in cdv_intel_edp_panel_on()
428 REG_READ(PP_CONTROL); in cdv_intel_edp_panel_on()
430 if (wait_for(((REG_READ(PP_STATUS) & idle_on_mask) == idle_on_mask), 1000)) { in cdv_intel_edp_panel_on()
431 DRM_DEBUG_KMS("Error in Powering up eDP panel, status %x\n", REG_READ(PP_STATUS)); in cdv_intel_edp_panel_on()
448 pp = REG_READ(PP_CONTROL); in cdv_intel_edp_panel_off()
461 REG_READ(PP_CONTROL); in cdv_intel_edp_panel_off()
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Dmdfld_dsi_dpi.c46 (REG_READ(gen_fifo_stat_reg) & DSI_FIFO_GEN_HS_DATA_FULL)) { in mdfld_wait_for_HS_DATA_FIFO()
63 while ((timeout < 20000) && (REG_READ(gen_fifo_stat_reg) in mdfld_wait_for_HS_CTRL_FIFO()
80 while ((timeout < 20000) && ((REG_READ(gen_fifo_stat_reg) & in mdfld_wait_for_DPI_CTRL_FIFO()
98 while ((timeout < 20000) && (!(REG_READ(intr_stat_reg) in mdfld_wait_for_SPL_PKG_SENT()
147 REG_READ(MIPI_DEVICE_READY_REG(pipe)); /* posted write? */ in dsi_set_pipe_plane_enable_state()
151 REG_READ(MIPI_PORT_CONTROL(pipe)); /* posted write? */ in dsi_set_pipe_plane_enable_state()
157 REG_WRITE(dspbase_reg, REG_READ(dspbase_reg)); in dsi_set_pipe_plane_enable_state()
158 REG_READ(dspbase_reg); in dsi_set_pipe_plane_enable_state()
573 if (REG_READ(MIPI_INTR_STAT_REG(pipe)) & DSI_INTR_STATE_SPL_PKG_SENT) in mdfld_dsi_dpi_turn_on()
583 if (REG_READ(MIPI_INTR_STAT_REG(pipe)) & DSI_INTR_STATE_SPL_PKG_SENT) in mdfld_dsi_dpi_turn_on()
[all …]
Dintel_i2c.c39 val = REG_READ(chan->reg); in get_clock()
49 val = REG_READ(chan->reg); in get_data()
61 REG_READ(chan->reg) & (GPIO_DATA_PULLUP_DISABLE | in set_clock()
81 REG_READ(chan->reg) & (GPIO_DATA_PULLUP_DISABLE | in set_data()
Dcdv_intel_crt.c45 temp = REG_READ(reg); in cdv_intel_crt_dpms()
108 dpll_md = REG_READ(dpll_md_reg); in cdv_intel_crt_mode_set()
148 orig = hotplug_en = REG_READ(PORT_HOTPLUG_EN); in cdv_intel_crt_detect_hotplug()
162 if (!(REG_READ(PORT_HOTPLUG_EN) & in cdv_intel_crt_detect_hotplug()
169 if ((REG_READ(PORT_HOTPLUG_STAT) & CRT_HOTPLUG_MONITOR_MASK) != in cdv_intel_crt_detect_hotplug()
Doaktrail_lvds.c56 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | in oaktrail_lvds_set_power()
59 pp_status = REG_READ(PP_STATUS); in oaktrail_lvds_set_power()
67 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & in oaktrail_lvds_set_power()
70 pp_status = REG_READ(PP_STATUS); in oaktrail_lvds_set_power()
112 lvds_port = (REG_READ(LVDS) & in oaktrail_lvds_mode_set()
174 mode_dev->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL); in oaktrail_lvds_prepare()
187 ret = ((REG_READ(BLC_PWM_CTL) & in oaktrail_lvds_get_max_backlight()
Dcdv_intel_lvds.c75 retval = ((REG_READ(BLC_PWM_CTL) & in cdv_intel_lvds_get_max_backlight()
183 REG_READ(BLC_PWM_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK; in cdv_intel_lvds_set_backlight()
209 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | in cdv_intel_lvds_set_power()
212 pp_status = REG_READ(PP_STATUS); in cdv_intel_lvds_set_power()
220 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & in cdv_intel_lvds_set_power()
223 pp_status = REG_READ(PP_STATUS); in cdv_intel_lvds_set_power()
331 mode_dev->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL); in cdv_intel_lvds_prepare()
741 lvds = REG_READ(LVDS); in cdv_intel_lvds_init()
766 pwm = REG_READ(BLC_PWM_CTL2); in cdv_intel_lvds_init()
Dmdfld_dsi_pkg_sender.c88 if ((mask & REG_READ(gen_fifo_stat_reg)) == mask) in wait_for_gen_fifo_empty()
92 DRM_ERROR("fifo is NOT empty 0x%08x\n", REG_READ(gen_fifo_stat_reg)); in wait_for_gen_fifo_empty()
186 if (mask & REG_READ(intr_stat_reg)) in handle_dsi_error()
201 intr_stat = REG_READ(intr_stat_reg); in dsi_error_handler()
543 if ((REG_READ(sender->mipi_intr_stat_reg) & BIT(29))) in __read_panel_data()
550 while (retry && !(REG_READ(sender->mipi_intr_stat_reg) & BIT(29))) { in __read_panel_data()
569 *(data_out + i) = REG_READ(gen_data_reg); in __read_panel_data()
657 REG_READ(MIPI_PORT_CONTROL(pipe)); in mdfld_dsi_pkg_sender_init()
Dcdv_intel_hdmi.c89 REG_READ(hdmi_priv->hdmi_reg); in cdv_hdmi_mode_set()
99 hdmib = REG_READ(hdmi_priv->hdmi_reg); in cdv_hdmi_dpms()
105 REG_READ(hdmi_priv->hdmi_reg); in cdv_hdmi_dpms()
114 hdmi_priv->save_HDMIB = REG_READ(hdmi_priv->hdmi_reg); in cdv_hdmi_save()
124 REG_READ(hdmi_priv->hdmi_reg); in cdv_hdmi_restore()
Doaktrail_crtc.c308 REG_READ(map->base), i); in oaktrail_crtc_dpms()
343 REG_WRITE(DSPCHICKENBIT, REG_READ(DSPCHICKENBIT) | 0xc040); in oaktrail_crtc_dpms()
356 pfit_control = REG_READ(PFIT_CONTROL); in oaktrail_panel_fitter_pipe()
492 pipeconf = REG_READ(map->conf); in oaktrail_crtc_mode_set()
495 dspcntr = REG_READ(map->cntr); in oaktrail_crtc_mode_set()
624 dspcntr = REG_READ(map->cntr); in oaktrail_pipe_set_base()
649 REG_READ(map->base); in oaktrail_pipe_set_base()
651 REG_READ(map->surf); in oaktrail_pipe_set_base()
Dpsb_irq.c299 REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT)); in psb_irq_handler()
526 reg_val = REG_READ(pipeconf_reg); in psb_enable_vblank()
585 reg_val = REG_READ(pipeconf_reg); in mdfld_enable_te()
654 reg_val = REG_READ(pipeconf_reg); in psb_get_vblank_counter()
668 high1 = ((REG_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >> in psb_get_vblank_counter()
670 low = ((REG_READ(low_frame) & PIPE_FRAME_LOW_MASK) >> in psb_get_vblank_counter()
672 high2 = ((REG_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >> in psb_get_vblank_counter()
Dmdfld_device.c383 temp = REG_READ(mipi_reg); in mdfld_restore_display_registers()
390 temp = REG_READ(device_ready_reg); in mdfld_restore_display_registers()
397 temp = REG_READ(device_ready_reg); in mdfld_restore_display_registers()
Dmdfld_dsi_output.h51 REG_WRITE(reg, FLD_MOD(REG_READ(reg), val, start, end))
58 while (FLD_GET(REG_READ(reg), start, end) != val) { in REGISTER_FLD_WAIT()
Doaktrail_device.c78 max_pwm_blc = REG_READ(BLC_PWM_CTL) >> 16; in oaktrail_set_brightness()
94 REG_WRITE(BLC_PWM_CTL2, (0x80000000 | REG_READ(BLC_PWM_CTL2))); in oaktrail_set_brightness()
135 REG_WRITE(BLC_PWM_CTL2, (0x80000000 | REG_READ(BLC_PWM_CTL2))); in device_backlight_init()
Dpsb_drv.h835 #define REG_READ(reg) REGISTER_READ(dev, (reg)) macro
847 val = REG_READ(reg); in REGISTER_READ_WITH_AUX()
Dmdfld_dsi_output.c75 if ((REG_READ(gen_fifo_stat_reg) & fifo_stat) == fifo_stat) in mdfld_dsi_gen_fifo_ready()
Dpsb_intel_sdvo.c1069 sdvox = REG_READ(psb_intel_sdvo->sdvo_reg); in psb_intel_sdvo_mode_set()
1123 temp = REG_READ(psb_intel_sdvo->sdvo_reg); in psb_intel_sdvo_dpms()
1136 temp = REG_READ(psb_intel_sdvo->sdvo_reg); in psb_intel_sdvo_dpms()
1811 sdvo->saveSDVO = REG_READ(sdvo->sdvo_reg); in psb_intel_sdvo_save()
/linux-4.4.14/drivers/net/wireless/ath/ath9k/
Dar9002_calib.c87 if (!(REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) & in ar9002_hw_per_calibration()
122 REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); in ar9002_hw_iqcal_collect()
124 REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); in ar9002_hw_iqcal_collect()
126 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); in ar9002_hw_iqcal_collect()
141 REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); in ar9002_hw_adc_gaincal_collect()
143 REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); in ar9002_hw_adc_gaincal_collect()
145 REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); in ar9002_hw_adc_gaincal_collect()
147 REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); in ar9002_hw_adc_gaincal_collect()
165 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); in ar9002_hw_adc_dccal_collect()
167 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); in ar9002_hw_adc_dccal_collect()
[all …]
Dar9003_wow.c48 REG_READ(ah, AR_CR), REG_READ(ah, AR_DIAG_SW)); in ath9k_hw_set_powermode_wow_sleep()
53 if (!REG_READ(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL)) in ath9k_hw_set_powermode_wow_sleep()
56 if (!(REG_READ(ah, AR_NDP2_TIMER_MODE) & in ath9k_hw_set_powermode_wow_sleep()
192 rval = REG_READ(ah, AR_WOW_PATTERN); in ath9k_hw_wow_wakeup()
213 rval = REG_READ(ah, AR_MAC_PCU_WOW4); in ath9k_hw_wow_wakeup()
236 AR_WOW_CLEAR_EVENTS(REG_READ(ah, AR_WOW_PATTERN))); in ath9k_hw_wow_wakeup()
238 AR_WOW_CLEAR_EVENTS2(REG_READ(ah, AR_MAC_PCU_WOW4))); in ath9k_hw_wow_wakeup()
256 u32 dc = REG_READ(ah, AR_DIRECT_CONNECT); in ath9k_hw_wow_wakeup()
281 wa_reg = REG_READ(ah, AR_WA); in ath9k_hw_wow_set_arwr_reg()
364 keep_alive = REG_READ(ah, AR_WOW_KEEP_ALIVE); in ath9k_hw_wow_enable()
[all …]
Dar9003_calib.c84 if (!(REG_READ(ah, AR_PHY_TIMING4) & AR_PHY_TIMING4_DO_CAL)) { in ar9003_hw_per_calibration()
184 REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); in ar9003_hw_iqcal_collect()
186 REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); in ar9003_hw_iqcal_collect()
188 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); in ar9003_hw_iqcal_collect()
272 REG_READ(ah, offset_array[i])); in ar9003_hw_iqcalibrate()
289 REG_READ(ah, offset_array[i])); in ar9003_hw_iqcalibrate()
294 REG_READ(ah, offset_array[i])); in ar9003_hw_iqcalibrate()
307 REG_READ(ah, AR_PHY_RX_IQCAL_CORR_B0)); in ar9003_hw_iqcalibrate()
355 REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_CAL); in ar9003_hw_dynamic_osdac_selection()
385 osdac_ch0 = (REG_READ(ah, AR_PHY_65NM_CH0_BB1) >> 30) & 0x3; in ar9003_hw_dynamic_osdac_selection()
[all …]
Dar9002_mac.c43 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) { in ar9002_hw_get_isr()
44 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) in ar9002_hw_get_isr()
46 isr = REG_READ(ah, AR_ISR); in ar9002_hw_get_isr()
50 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) & in ar9002_hw_get_isr()
59 isr = REG_READ(ah, AR_ISR); in ar9002_hw_get_isr()
65 isr2 = REG_READ(ah, AR_ISR_S2); in ar9002_hw_get_isr()
88 isr = REG_READ(ah, AR_ISR_RAC); in ar9002_hw_get_isr()
109 s0_s = REG_READ(ah, AR_ISR_S0_S); in ar9002_hw_get_isr()
110 s1_s = REG_READ(ah, AR_ISR_S1_S); in ar9002_hw_get_isr()
112 s0_s = REG_READ(ah, AR_ISR_S0); in ar9002_hw_get_isr()
[all …]
Dar9002_phy.c76 reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL); in ar9002_hw_set_channel()
98 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL); in ar9002_hw_set_channel()
224 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0)); in ar9002_hw_spur_mitigate()
297 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4), in ar9002_olc_init()
335 nf = MS(REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR); in ar9002_hw_do_getnf()
338 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR9280_PHY_EXT_MINCCA_PWR); in ar9002_hw_do_getnf()
345 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR9280_PHY_CH1_MINCCA_PWR); in ar9002_hw_do_getnf()
348 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR9280_PHY_CH1_EXT_MINCCA_PWR); in ar9002_hw_do_getnf()
382 regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); in ar9002_hw_antdiv_comb_conf_get()
399 regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); in ar9002_hw_antdiv_comb_conf_set()
[all …]
Dar9003_mci.c39 if (!(REG_READ(ah, address) & bit_position)) { in ar9003_mci_wait_for_interrupt()
71 REG_READ(ah, AR_MCI_INTERRUPT_RAW), in ar9003_mci_wait_for_interrupt()
72 REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW)); in ar9003_mci_wait_for_interrupt()
232 saved_mci_int_en = REG_READ(ah, AR_MCI_INTERRUPT_EN); in ar9003_mci_prep_interface()
236 REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW)); in ar9003_mci_prep_interface()
238 REG_READ(ah, AR_MCI_INTERRUPT_RAW)); in ar9003_mci_prep_interface()
351 intr = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW); in ar9003_mci_check_int()
375 rx_msg_intr = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW); in ar9003_mci_get_isr()
376 raw_intr = REG_READ(ah, AR_MCI_INTERRUPT_RAW); in ar9003_mci_get_isr()
387 mci->cont_status = REG_READ(ah, AR_MCI_CONT_STATUS); in ar9003_mci_get_isr()
[all …]
Dmac.c48 return REG_READ(ah, AR_QTXDP(q)); in ath9k_hw_gettxbuf()
69 npend = REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT; in ath9k_hw_numtxpending()
72 if (REG_READ(ah, AR_Q_TXE) & (1 << q)) in ath9k_hw_numtxpending()
114 txcfg = REG_READ(ah, AR_TXCFG); in ath9k_hw_updatetxtriglevel()
652 reg = REG_READ(ah, AR_OBS_BUS_1); in ath9k_hw_setrxabort()
709 if ((REG_READ(ah, AR_CR) & AR_CR_RXE) == 0) in ath9k_hw_stopdmarecv()
713 mac_status = REG_READ(ah, AR_DMADBG_7) & 0x7f0; in ath9k_hw_stopdmarecv()
729 REG_READ(ah, AR_CR), in ath9k_hw_stopdmarecv()
730 REG_READ(ah, AR_DIAG_SW), in ath9k_hw_stopdmarecv()
731 REG_READ(ah, AR_DMADBG_7)); in ath9k_hw_stopdmarecv()
[all …]
Dhw.c84 if ((REG_READ(ah, reg) & mask) == val) in ath9k_hw_wait()
92 timeout, reg, REG_READ(ah, reg), mask, val); in ath9k_hw_wait()
267 val = REG_READ(ah, AR_SREV); in ath9k_hw_read_revisions()
285 val = REG_READ(ah, AR_SREV) & AR_SREV_ID; in ath9k_hw_read_revisions()
288 val = REG_READ(ah, AR_SREV); in ath9k_hw_read_revisions()
352 regHold[i] = REG_READ(ah, addr); in ath9k_hw_chip_test()
356 rdData = REG_READ(ah, addr); in ath9k_hw_chip_test()
367 rdData = REG_READ(ah, addr); in ath9k_hw_chip_test()
593 ah->WARegVal = REG_READ(ah, AR_WA); in __ath9k_hw_init()
624 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); in __ath9k_hw_init()
[all …]
Dar9003_mac.c195 async_cause = REG_READ(ah, AR_INTR_ASYNC_CAUSE); in ar9003_hw_get_isr()
198 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) in ar9003_hw_get_isr()
200 isr = REG_READ(ah, AR_ISR); in ar9003_hw_get_isr()
204 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) & AR_INTR_SYNC_DEFAULT; in ar9003_hw_get_isr()
214 isr2 = REG_READ(ah, AR_ISR_S2); in ar9003_hw_get_isr()
240 isr = REG_READ(ah, AR_ISR_RAC); in ar9003_hw_get_isr()
268 s0 = REG_READ(ah, AR_ISR_S0); in ar9003_hw_get_isr()
270 s1 = REG_READ(ah, AR_ISR_S1); in ar9003_hw_get_isr()
282 s5 = REG_READ(ah, AR_ISR_S5_S); in ar9003_hw_get_isr()
284 s5 = REG_READ(ah, AR_ISR_S5); in ar9003_hw_get_isr()
[all …]
Dar9003_phy.c643 (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO); in ar9003_hw_set_channel_regs()
661 phymode |= REG_READ(ah, AR_PHY_GEN_CTRL); in ar9003_hw_set_channel_regs()
686 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; in ar9003_hw_init_bb()
729 val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE); in ar9003_hw_override_ini()
747 if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE) in ar9003_hw_override_ini()
1079 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; in ar9003_hw_rfbus_done()
1373 nf = MS(REG_READ(ah, ah->nf_regs[i]), in ar9003_hw_do_getnf()
1380 nf = MS(REG_READ(ah, ah->nf_regs[ext_idx]), in ar9003_hw_do_getnf()
1430 val = REG_READ(ah, AR_PHY_SFCORR); in ar9003_hw_ani_cache_ini_regs()
1435 val = REG_READ(ah, AR_PHY_SFCORR_LOW); in ar9003_hw_ani_cache_ini_regs()
[all …]
Dar5008_phy.c215 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL); in ar5008_hw_set_channel()
449 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0)); in ar5008_hw_spur_mitigate()
570 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; in ar5008_hw_init_bb()
617 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001); in ar5008_hw_init_chain_masks()
640 val = REG_READ(ah, AR_PCU_MISC_MODE2) & in ar5008_hw_override_ini()
667 val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS); in ar5008_hw_override_ini()
680 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) & in ar5008_hw_set_channel_regs()
881 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; in ar5008_hw_rfbus_done()
1127 nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR); in ar5008_hw_do_getnf()
1130 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR_PHY_CH1_MINCCA_PWR); in ar5008_hw_do_getnf()
[all …]
Dar9003_aic.c248 (REG_READ(ah, ATH_AIC_BT_JUPITER_CTRL) | in ar9003_aic_cal_start()
251 aic->aic_cal_start_time = REG_READ(ah, AR_TSF_L32); in ar9003_aic_cal_start()
442 (REG_READ(ah, ATH_AIC_BT_JUPITER_CTRL) & in ar9003_aic_cal_done()
467 if ((REG_READ(ah, AR_PHY_AIC_CTRL_0_B1) & in ar9003_aic_cal_continue()
479 if ((REG_READ(ah, AR_PHY_AIC_CTRL_0_B1) & in ar9003_aic_cal_continue()
491 value = REG_READ(ah, AR_PHY_AIC_SRAM_DATA_B1); in ar9003_aic_cal_continue()
Dcalib.c284 if ((REG_READ(ah, AR_PHY_AGC_CONTROL) & in ath9k_hw_loadnf()
302 REG_READ(ah, AR_PHY_AGC_CONTROL)); in ath9k_hw_loadnf()
369 if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) { in ath9k_hw_getnf()
438 else if (!(REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF)) in ath9k_hw_bstuck_nfcal()
Deeprom_9287.c375 tmpVal = REG_READ(ah, 0xa270); in ar9287_eeprom_olpc_set_pdadcs()
382 tmpVal = REG_READ(ah, 0xb270); in ar9287_eeprom_olpc_set_pdadcs()
390 tmpVal = REG_READ(ah, 0xa398); in ar9287_eeprom_olpc_set_pdadcs()
400 tmpVal = REG_READ(ah, 0xb398); in ar9287_eeprom_olpc_set_pdadcs()
430 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5), in ath9k_hw_set_ar9287_power_cal_table()
927 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) in ath9k_hw_ar9287_set_board_values()
976 regval = REG_READ(ah, AR9287_AN_RF2G3_CH0); in ath9k_hw_ar9287_set_board_values()
992 regval = REG_READ(ah, AR9287_AN_RF2G3_CH1); in ath9k_hw_ar9287_set_board_values()
Dar9002_hw.c256 val = REG_READ(ah, AR_WA); in ar9002_hw_configpcipowersave()
339 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff; in ar9002_hw_get_radiorev()
446 val_orig = REG_READ(ah, reg); in ar9002_hw_load_ani_reg()
Dar9003_hw.c1103 dma_dbg_chain = REG_READ(ah, AR_DMADBG_4); in ath9k_hw_verify_hang()
1105 dma_dbg_chain = REG_READ(ah, AR_DMADBG_5); in ath9k_hw_verify_hang()
1107 dma_dbg_complete = REG_READ(ah, AR_DMADBG_6); in ath9k_hw_verify_hang()
1130 dma_dbg_4 = REG_READ(ah, AR_DMADBG_4); in ar9003_hw_detect_mac_hang()
1131 dma_dbg_5 = REG_READ(ah, AR_DMADBG_5); in ar9003_hw_detect_mac_hang()
1132 dma_dbg_6 = REG_READ(ah, AR_DMADBG_6); in ar9003_hw_detect_mac_hang()
Deeprom_4k.c373 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5), in ath9k_hw_set_4k_power_cal_table()
854 regVal = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); in ath9k_hw_4k_set_board_values()
870 regVal = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); in ath9k_hw_4k_set_board_values()
871 regVal = REG_READ(ah, AR_PHY_CCK_DETECT); in ath9k_hw_4k_set_board_values()
877 regVal = REG_READ(ah, AR_PHY_CCK_DETECT); in ath9k_hw_4k_set_board_values()
884 regVal = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); in ath9k_hw_4k_set_board_values()
Dar9003_eeprom.c3088 REG_READ(ah, AR9300_OTP_BASE + (4 * addr)); in ar9300_otp_read_word()
3094 *data = REG_READ(ah, AR9300_OTP_READ_DATA); in ar9300_otp_read_word()
3660 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); in ar9003_hw_ant_ctrl_apply()
3696 regval = REG_READ(ah, AR_PHY_CCK_DETECT); in ar9003_hw_ant_ctrl_apply()
3707 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); in ar9003_hw_ant_ctrl_apply()
3737 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS1); in ar9003_hw_drive_strength_apply()
3747 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS2); in ar9003_hw_drive_strength_apply()
3760 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS4); in ar9003_hw_drive_strength_apply()
3873 while (pmu_set != REG_READ(ah, pmu_reg)) { in is_pmu_set()
3893 reg_pmu_set = REG_READ(ah, AR_PHY_PMU2) & ~AR_PHY_PMU2_PGM; in ar9003_hw_internal_regulator_apply()
[all …]
Dani.c405 phyCnt1 = REG_READ(ah, AR_PHY_ERR_1); in ath9k_hw_ani_read_counters()
406 phyCnt2 = REG_READ(ah, AR_PHY_ERR_2); in ath9k_hw_ani_read_counters()
Dar9003_rtt.c162 val = MS(REG_READ(ah, AR_PHY_RTT_TABLE_SW_INTF_1_B(chain)), in ar9003_hw_rtt_fill_hist_entry()
Dar9003_paprd.c299 entry[i] = REG_READ(ah, reg); in ar9003_paprd_get_gain_table()
940 data_L[i] = REG_READ(ah, reg + (i << 2)); in ar9003_paprd_create_curve()
946 data_U[i] = REG_READ(ah, reg + (i << 2)); in ar9003_paprd_create_curve()
Dhtc_drv_init.c500 val = REG_READ(ah, reg_offset); in ath9k_reg_rmw()
525 (void)REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S)); in ath_usb_eeprom_read()
534 *data = MS(REG_READ(ah, AR_EEPROM_STATUS_DATA), in ath_usb_eeprom_read()
Dbtcoex.c287 val = REG_READ(ah, 0x50040); in ath9k_hw_btcoex_enable_3wire()
Dhw.h82 #define REG_READ(_ah, _reg) \ macro
126 (((REG_READ(_a, _r) & _f) >> _f##_S))
Deeprom_def.c542 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) & in ath9k_hw_def_set_board_values()
837 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5), in ath9k_hw_set_def_power_cal_table()
Dreg.h931 ((REG_READ(_ah, AR_AN_SYNTH9) & 0x7) == 0x1))
Dchannel.c561 sc->sched.next_tbtt = REG_READ(ah, AR_NEXT_TBTT_TIMER); in ath_chanctx_event()
Ddebug.c932 "0x%06x 0x%08x\n", i << 2, REG_READ(sc->sc_ah, i << 2)); in open_file_regdump()
/linux-4.4.14/drivers/net/wireless/ath/
Dhw.c23 #define REG_READ (common->ops->read) macro
124 id1 = REG_READ(ah, AR_STA_ID1) & ~AR_STA_ID1_SADH_MASK; in ath_hw_setbssidmask()
151 cycles = REG_READ(ah, AR_CCCNT); in ath_hw_cycle_counters_update()
152 busy = REG_READ(ah, AR_RCCNT); in ath_hw_cycle_counters_update()
153 rx = REG_READ(ah, AR_RFCNT); in ath_hw_cycle_counters_update()
154 tx = REG_READ(ah, AR_TFCNT); in ath_hw_cycle_counters_update()
Dkey.c25 #define REG_READ (common->ops->read) macro
53 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry)); in ath_hw_keyreset()
/linux-4.4.14/arch/cris/include/arch-v32/arch/hwregs/
Dmarb_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
278 REG_READ( reg_##scope##_##reg, \
290 REG_READ( reg_##scope##_##reg, \
304 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
314 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
Dirq_nmi_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
Dstrcop_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
Dconfig_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
Dreg_rdwr.h8 #ifndef REG_READ
9 #define REG_READ(type, addr) (*((volatile type *) (addr))) macro
Drt_trace_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
Dmarb_bp_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
Data_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
Dbif_slave_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
Dser_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
Dbif_core_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
Deth_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
Dsser_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
Ddma_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
Dextmem_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
Dbif_dma_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
/linux-4.4.14/arch/cris/include/arch-v32/mach-fs/mach/hwregs/
Dmarb_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
278 REG_READ( reg_##scope##_##reg, \
290 REG_READ( reg_##scope##_##reg, \
304 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
314 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
Dstrmux_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
Dconfig_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
Dmarb_bp_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
Dtimer_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
Dintr_vect_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
Dbif_slave_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
Dgio_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
Dbif_core_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
Dpinmux_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
Dbif_dma_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
/linux-4.4.14/arch/cris/include/arch-v32/mach-a3/mach/hwregs/
Dmarb_bar_defs.h16 REG_READ( reg_##scope##_##reg, \
28 REG_READ( reg_##scope##_##reg, \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
300 REG_READ( reg_##scope##_##reg, \
312 REG_READ( reg_##scope##_##reg, \
326 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
336 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
Dstrmux_defs.h16 REG_READ( reg_##scope##_##reg, \
28 REG_READ( reg_##scope##_##reg, \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
Dl2cache_defs.h16 REG_READ( reg_##scope##_##reg, \
28 REG_READ( reg_##scope##_##reg, \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
Dclkgen_defs.h16 REG_READ( reg_##scope##_##reg, \
28 REG_READ( reg_##scope##_##reg, \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
Dmarb_foo_defs.h16 REG_READ( reg_##scope##_##reg, \
28 REG_READ( reg_##scope##_##reg, \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
426 REG_READ( reg_##scope##_##reg, \
438 REG_READ( reg_##scope##_##reg, \
452 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
462 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
Dtimer_defs.h16 REG_READ( reg_##scope##_##reg, \
28 REG_READ( reg_##scope##_##reg, \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
Dddr2_defs.h16 REG_READ( reg_##scope##_##reg, \
28 REG_READ( reg_##scope##_##reg, \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
Dpinmux_defs.h16 REG_READ( reg_##scope##_##reg, \
28 REG_READ( reg_##scope##_##reg, \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
Dpio_defs.h16 REG_READ( reg_##scope##_##reg, \
28 REG_READ( reg_##scope##_##reg, \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
Dintr_vect_defs.h16 REG_READ( reg_##scope##_##reg, \
28 REG_READ( reg_##scope##_##reg, \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
Dgio_defs.h16 REG_READ( reg_##scope##_##reg, \
28 REG_READ( reg_##scope##_##reg, \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
/linux-4.4.14/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/
Diop_version_defs.h16 REG_READ( reg_##scope##_##reg, \
28 REG_READ( reg_##scope##_##reg, \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
Diop_sap_in_defs.h16 REG_READ( reg_##scope##_##reg, \
28 REG_READ( reg_##scope##_##reg, \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
Diop_sap_out_defs.h16 REG_READ( reg_##scope##_##reg, \
28 REG_READ( reg_##scope##_##reg, \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
Diop_sw_spu_defs.h16 REG_READ( reg_##scope##_##reg, \
28 REG_READ( reg_##scope##_##reg, \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
Diop_sw_cpu_defs.h16 REG_READ( reg_##scope##_##reg, \
28 REG_READ( reg_##scope##_##reg, \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
Diop_sw_mpu_defs.h16 REG_READ( reg_##scope##_##reg, \
28 REG_READ( reg_##scope##_##reg, \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
Diop_sw_cfg_defs.h16 REG_READ( reg_##scope##_##reg, \
28 REG_READ( reg_##scope##_##reg, \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
/linux-4.4.14/arch/cris/include/arch-v32/arch/hwregs/iop/
Diop_version_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
Diop_scrc_in_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
Diop_scrc_out_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
Diop_trigger_grp_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
Diop_fifo_in_extra_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
Diop_fifo_out_extra_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
Diop_sap_in_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
Diop_mpu_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
Diop_crc_par_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
Diop_fifo_in_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
Diop_timer_grp_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
Diop_fifo_out_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
Diop_sap_out_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
Diop_dmc_out_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
Diop_dmc_in_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
Diop_spu_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
Diop_sw_spu_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
Diop_sw_cpu_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
Diop_sw_mpu_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
Diop_sw_cfg_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
/linux-4.4.14/drivers/input/keyboard/
Dgoldfish_events.c27 REG_READ = 0x00, enumerator
49 type = __raw_readl(edev->addr + REG_READ); in events_interrupt()
50 code = __raw_readl(edev->addr + REG_READ); in events_interrupt()
51 value = __raw_readl(edev->addr + REG_READ); in events_interrupt()
/linux-4.4.14/drivers/net/dsa/
Dmv88e6060.c30 #define REG_READ(addr, reg) \ macro
90 ret = REG_READ(REG_PORT(i), PORT_CONTROL); in mv88e6060_switch_reset()
107 ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS); in mv88e6060_switch_reset()
Dmv88e6xxx.c209 ret = REG_READ(REG_GLOBAL2, GLOBAL2_SWITCH_MAC); in mv88e6xxx_set_addr_indirect()
241 ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL); in mv88e6xxx_ppu_disable()
247 ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS); in mv88e6xxx_ppu_disable()
262 ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL); in mv88e6xxx_ppu_enable()
267 ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS); in mv88e6xxx_ppu_enable()
2195 ps->id = REG_READ(REG_PORT(0), PORT_SWITCH_ID) & 0xfff0; in mv88e6xxx_setup_common()
2332 ret = REG_READ(REG_PORT(i), PORT_CONTROL); in mv88e6xxx_switch_reset()
2351 ret = REG_READ(REG_GLOBAL, 0x00); in mv88e6xxx_switch_reset()
Dmv88e6xxx.h505 #define REG_READ(addr, reg) \ macro
/linux-4.4.14/arch/x86/mm/
Dpf_in.h28 REG_READ, /* read from addr to reg */ enumerator
Dmmio-mod.c181 case REG_READ: in pre()
222 case REG_READ: in post()
Dpf_in.c155 CHECK_OP_TYPE(opcode, reg_rop, REG_READ); in get_ins_type()
/linux-4.4.14/drivers/media/usb/dvb-usb-v2/
Dce6230.h46 REG_READ = 0xde, /* rd e */ enumerator
Dce6230.c43 case REG_READ: in ce6230_ctrl_msg()
/linux-4.4.14/drivers/net/wireless/cw1200/
Dfwio.c89 #define REG_READ(reg, val) \ in cw1200_load_firmware_cw1200() macro
139 REG_READ(ST90TDS_CONFIG_REG_ID, val32); in cw1200_load_firmware_cw1200()
264 #undef REG_READ in cw1200_load_firmware_cw1200()