84 		if ((REG_READ(ah, reg) & mask) == val)  in ath9k_hw_wait()
92 		timeout, reg, REG_READ(ah, reg), mask, val);  in ath9k_hw_wait()
267 			val = REG_READ(ah, AR_SREV);  in ath9k_hw_read_revisions()
285 	val = REG_READ(ah, AR_SREV) & AR_SREV_ID;  in ath9k_hw_read_revisions()
288 		val = REG_READ(ah, AR_SREV);  in ath9k_hw_read_revisions()
352 		regHold[i] = REG_READ(ah, addr);  in ath9k_hw_chip_test()
356 			rdData = REG_READ(ah, addr);  in ath9k_hw_chip_test()
367 			rdData = REG_READ(ah, addr);  in ath9k_hw_chip_test()
593 		ah->WARegVal = REG_READ(ah, AR_WA);  in __ath9k_hw_init()
624 	ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);  in __ath9k_hw_init()
733 	while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) {  in ar9003_get_pll_sqsum_dvc()
745 	return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;  in ar9003_get_pll_sqsum_dvc()
855 		regval = REG_READ(ah, AR_PHY_PLL_MODE);  in ath9k_hw_init_pll()
867 		regval = REG_READ(ah, AR_PHY_PLL_MODE);  in ath9k_hw_init_pll()
893 				  REG_READ(ah, AR_PHY_PLL_MODE) & 0xffbfffff);  in ath9k_hw_init_pll()
896 				  REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);  in ath9k_hw_init_pll()
1072 			eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/  in ath9k_hw_init_global_settings()
1074 			reg = REG_READ(ah, AR_USEC);  in ath9k_hw_init_global_settings()
1322 		(void)REG_READ(ah, AR_RTC_DERIVED_CLK);  in ath9k_hw_set_reset()
1339 		tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);  in ath9k_hw_set_reset()
1477 	} else if (ah->chip_fullsleep || REG_READ(ah, AR_Q_TXE) ||  in ath9k_hw_chip_reset()
1478 		   (REG_READ(ah, AR_CR) & AR_CR_RXE))  in ath9k_hw_chip_reset()
1585 	val = REG_READ(ah, AR_NAV);  in ath9k_hw_check_nav()
1604 	last_val = REG_READ(ah, AR_OBS_BUS_1);  in ath9k_hw_check_alive()
1606 		reg = REG_READ(ah, AR_OBS_BUS_1);  in ath9k_hw_check_alive()
1703 		mask = REG_READ(ah, AR_CFG);  in ath9k_hw_init_desc()
1711 				REG_READ(ah, AR_CFG));  in ath9k_hw_init_desc()
1861 	saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);  in ath9k_hw_reset()
1865 	macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;  in ath9k_hw_reset()
1871 	saveLedState = REG_READ(ah, AR_CFG_LED) &  in ath9k_hw_reset()
2137 	if ((REG_READ(ah, AR_RTC_STATUS) &  in ath9k_hw_set_power_awake()
2157 		val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;  in ath9k_hw_set_power_awake()
2535 		ah->ent_mode = REG_READ(ah, AR_ENT_OTP);  in ath9k_hw_fill_cap_info()
2625 		tmp = REG_READ(ah, addr);  in ath9k_hw_gpio_cfg_output_mux()
2658 	(MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))  in ath9k_hw_gpio_get()
2665 		val = REG_READ(ah, AR7010_GPIO_IN);  in ath9k_hw_gpio_get()
2668 		return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &  in ath9k_hw_gpio_get()
2746 	u32 bits = REG_READ(ah, AR_RX_FILTER);  in ath9k_hw_getrxfilter()
2747 	u32 phybits = REG_READ(ah, AR_PHY_ERR);  in ath9k_hw_getrxfilter()
2896 	tsf_upper1 = REG_READ(ah, AR_TSF_U32);  in ath9k_hw_gettsf64()
2898 		tsf_lower = REG_READ(ah, AR_TSF_L32);  in ath9k_hw_gettsf64()
2899 		tsf_upper2 = REG_READ(ah, AR_TSF_U32);  in ath9k_hw_gettsf64()
2983 	return REG_READ(ah, AR_TSF_L32);  in ath9k_hw_gettsf32()