Lines Matching refs:REG_READ

143 	ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);  in cdv_sb_read()
155 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); in cdv_sb_read()
161 *val = REG_READ(SB_DATA); in cdv_sb_read()
178 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); in cdv_sb_write()
191 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); in cdv_sb_write()
212 REG_READ(DPIO_CFG); in cdv_sb_reset()
479 if (REG_READ(FW_BLC_SELF) & FW_BLC_SELF_EN) { in cdv_disable_sr()
482 REG_WRITE(FW_BLC_SELF, (REG_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN)); in cdv_disable_sr()
483 REG_READ(FW_BLC_SELF); in cdv_disable_sr()
491 REG_READ(OV_OVADD); in cdv_disable_sr()
507 fw = REG_READ(DSPFW1); in cdv_update_wm()
514 fw = REG_READ(DSPFW2); in cdv_update_wm()
543 REG_READ(FW_BLC_SELF); in cdv_update_wm()
570 pfit_control = REG_READ(PFIT_CONTROL); in cdv_intel_panel_fitter_pipe()
698 pipeconf = REG_READ(map->conf); in cdv_intel_crtc_mode_set()
718 if ((REG_READ(LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP) in cdv_intel_crtc_mode_set()
737 REG_READ(map->dpll); in cdv_intel_crtc_mode_set()
749 u32 lvds = REG_READ(LVDS); in cdv_intel_crtc_mode_set()
769 REG_READ(LVDS); in cdv_intel_crtc_mode_set()
782 (REG_READ(map->dpll) & ~DPLL_LOCK) | DPLL_VCO_ENABLE); in cdv_intel_crtc_mode_set()
783 REG_READ(map->dpll); in cdv_intel_crtc_mode_set()
787 if (!(REG_READ(map->dpll) & DPLL_LOCK)) { in cdv_intel_crtc_mode_set()
818 REG_READ(map->conf); in cdv_intel_crtc_mode_set()
863 dpll = REG_READ(map->dpll); in cdv_intel_crtc_clock_get()
865 fp = REG_READ(map->fp0); in cdv_intel_crtc_clock_get()
867 fp = REG_READ(map->fp1); in cdv_intel_crtc_clock_get()
868 is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN); in cdv_intel_crtc_clock_get()
943 htot = REG_READ(map->htotal); in cdv_intel_crtc_mode_get()
944 hsync = REG_READ(map->hsync); in cdv_intel_crtc_mode_get()
945 vtot = REG_READ(map->vtotal); in cdv_intel_crtc_mode_get()
946 vsync = REG_READ(map->vsync); in cdv_intel_crtc_mode_get()