| /linux-4.4.14/drivers/tty/serial/ |
| D | etraxfs-uart.c | 62 tr_dma_en = old = REG_RD(ser, up->regi_ser, rw_tr_dma_en); in cris_console_write()
73 stat = REG_RD(ser, up->regi_ser, r_stat_din); in cris_console_write()
79 stat = REG_RD(ser, up->regi_ser, r_stat_din); in cris_console_write()
144 reg_ser_r_stat_din rstat = REG_RD(ser, regi_ser, r_stat_din); in crisv32_serial_get_rts()
162 rec_ctrl = REG_RD(ser, regi_ser, rw_rec_ctrl); in crisv32_serial_set_rts()
175 reg_ser_r_stat_din rstat = REG_RD(ser, regi_ser, r_stat_din); in crisv32_serial_get_cts()
211 prev_tr_ctrl = tr_ctrl = REG_RD(ser, regi_ser, rw_tr_ctrl); in etraxfs_uart_send_xchar()
212 rstat = REG_RD(ser, regi_ser, r_stat_din); in etraxfs_uart_send_xchar()
235 rstat = REG_RD(ser, up->regi_ser, r_stat_din); in etraxfs_uart_send_xchar()
246 tr_dma_en = REG_RD(ser, regi_ser, rw_tr_dma_en); in etraxfs_uart_send_xchar()
[all …]
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| /linux-4.4.14/arch/cris/arch-v32/mach-a3/ |
| D | arbiter.c | 527 REG_RD(marb_foo, regi_marb_foo, r_masked_intr); in crisv32_foo_arbiter_irq()
540 masked_intr = REG_RD(marb_foo, regi_marb_foo, r_masked_intr); in crisv32_foo_arbiter_irq()
554 r_clients = REG_RD(marb_foo_bp, watch->instance, r_brk_clients); in crisv32_foo_arbiter_irq()
555 r_addr = REG_RD(marb_foo_bp, watch->instance, r_brk_addr); in crisv32_foo_arbiter_irq()
556 r_op = REG_RD(marb_foo_bp, watch->instance, r_brk_op); in crisv32_foo_arbiter_irq()
557 r_first = REG_RD(marb_foo_bp, watch->instance, r_brk_first_client); in crisv32_foo_arbiter_irq()
558 r_size = REG_RD(marb_foo_bp, watch->instance, r_brk_size); in crisv32_foo_arbiter_irq()
583 REG_RD(marb_bar, regi_marb_bar, r_masked_intr); in crisv32_bar_arbiter_irq()
596 masked_intr = REG_RD(marb_bar, regi_marb_bar, r_masked_intr); in crisv32_bar_arbiter_irq()
610 r_clients = REG_RD(marb_bar_bp, watch->instance, r_brk_clients); in crisv32_bar_arbiter_irq()
[all …]
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| D | dma.c | 47 clk_ctrl = REG_RD(clkgen, regi_clkgen, rw_clk_ctrl); in crisv32_request_dma()
48 strmux_cfg = REG_RD(strmux, regi_strmux, rw_cfg); in crisv32_request_dma()
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| D | pinmux.c | 98 hwprot = REG_RD(pinmux, regi_pinmux, rw_hwprot); in crisv32_pinmux_alloc_fixed()
99 clk_ctrl = REG_RD(clkgen, regi_clkgen, rw_clk_ctrl); in crisv32_pinmux_alloc_fixed()
275 hwprot = REG_RD(pinmux, regi_pinmux, rw_hwprot); in crisv32_pinmux_dealloc_fixed()
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| /linux-4.4.14/arch/cris/include/arch-v32/arch/hwregs/ |
| D | dma.h | 76 do { reg_dma_rw_cfg e = REG_RD( dma, inst, rw_cfg );\
82 do { reg_dma_rw_cfg r = REG_RD( dma, inst, rw_cfg );\
88 do { reg_dma_rw_cfg s = REG_RD( dma, inst, rw_cfg );\
94 do { reg_dma_rw_cfg c = REG_RD( dma, inst, rw_cfg );\
101 do { __x = REG_RD(dma, inst, rw_stream_cmd); } while (__x.busy); \
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| D | marb_defs.h | 17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
276 #ifndef REG_RD
277 #define REG_RD( scope, inst, reg ) \ macro
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| D | irq_nmi_defs.h | 17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
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| D | strcop_defs.h | 17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
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| D | config_defs.h | 17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
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| D | rt_trace_defs.h | 17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
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| D | marb_bp_defs.h | 17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
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| D | ata_defs.h | 17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
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| D | bif_slave_defs.h | 17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
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| D | ser_defs.h | 17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
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| D | bif_core_defs.h | 17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
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| D | eth_defs.h | 17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
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| D | sser_defs.h | 17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
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| D | dma_defs.h | 17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
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| D | extmem_defs.h | 17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
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| D | bif_dma_defs.h | 17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
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| /linux-4.4.14/arch/cris/boot/compressed/ |
| D | misc.c | 134 rs = REG_RD(ser, regi_ser, rs_stat_din); in serout()
243 xoff = REG_RD(ser, regi_ser, rw_xoff); in serial_setup()
251 tr_ctrl = REG_RD(ser, regi_ser, rw_tr_ctrl); in serial_setup()
252 rec_ctrl = REG_RD(ser, regi_ser, rw_rec_ctrl); in serial_setup()
253 tr_baud = REG_RD(ser, regi_ser, rw_tr_baud_div); in serial_setup()
254 rec_baud = REG_RD(ser, regi_ser, rw_rec_baud_div); in serial_setup()
295 clk_ctrl = REG_RD(clkgen, regi_clkgen, rw_clk_ctrl); in decompress_kernel()
301 hwprot = REG_RD(pinmux, regi_pinmux, rw_hwprot); in decompress_kernel()
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| /linux-4.4.14/arch/cris/arch-v32/mach-fs/ |
| D | arbiter.c | 282 REG_RD(marb, regi_marb, rw_intr_mask); in crisv32_arbiter_watch()
319 reg_marb_rw_intr_mask intr_mask = REG_RD(marb, regi_marb, rw_intr_mask); in crisv32_arbiter_unwatch()
352 REG_RD(marb, regi_marb, r_masked_intr); in crisv32_arbiter_irq()
381 r_clients = REG_RD(marb_bp, watch->instance, r_brk_clients); in crisv32_arbiter_irq()
382 r_addr = REG_RD(marb_bp, watch->instance, r_brk_addr); in crisv32_arbiter_irq()
383 r_op = REG_RD(marb_bp, watch->instance, r_brk_op); in crisv32_arbiter_irq()
384 r_first = REG_RD(marb_bp, watch->instance, r_brk_first_client); in crisv32_arbiter_irq()
385 r_size = REG_RD(marb_bp, watch->instance, r_brk_size); in crisv32_arbiter_irq()
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| D | dma.c | 49 clk_ctrl = REG_RD(config, regi_config, rw_clk_ctrl); in crisv32_request_dma()
50 strmux_cfg = REG_RD(strmux, regi_strmux, rw_cfg); in crisv32_request_dma()
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| D | pinmux.c | 58 reg_pinmux_rw_pa pa = REG_RD(pinmux, regi_pinmux, rw_pa); in crisv32_pinmux_init()
107 hwprot = REG_RD(pinmux, regi_pinmux, rw_hwprot); in crisv32_pinmux_alloc_fixed()
242 hwprot = REG_RD(pinmux, regi_pinmux, rw_hwprot); in crisv32_pinmux_dealloc_fixed()
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| /linux-4.4.14/arch/cris/arch-v32/kernel/ |
| D | time.c | 64 data = REG_RD(timer, regi_timer0, r_tmr0_data); in get_ns_in_jiffie()
152 REG_RD(clkgen, regi_clkgen, rw_clk_ctrl); in handle_watchdog_bite()
213 intr = REG_RD(timer, timer_base, r_masked_intr); in crisv32_timer_interrupt()
250 return REG_RD(timer, timer_base, r_time); in crisv32_timer_sched_clock()
263 timer_intr_mask = REG_RD(timer, timer_base, rw_intr_mask); in crisv32_timer_init()
337 data = REG_RD(timer, timer_regs[freqs->cpu], in cris_time_freq_notifier()
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| D | debugport.c | 164 stat = REG_RD(ser, kgdb_port->instance, rs_stat_din); in getDebugChar()
179 stat = REG_RD(ser, kgdb_port->instance, r_stat_din); in putDebugChar()
190 stat = REG_RD(ser, port->instance, r_stat_din); in early_putch()
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| D | kgdb.c | 1529 intr_mask = REG_RD(intr_vect, regi_irq, rw_mask); in kgdb_init()
1533 ser_intr_mask = REG_RD(ser, regi_ser0, rw_intr_mask); in kgdb_init()
1541 intr_mask = REG_RD(intr_vect, regi_irq, rw_mask); in kgdb_init()
1545 ser_intr_mask = REG_RD(ser, regi_ser1, rw_intr_mask); in kgdb_init()
1553 intr_mask = REG_RD(intr_vect, regi_irq, rw_mask); in kgdb_init()
1557 ser_intr_mask = REG_RD(ser, regi_ser2, rw_intr_mask); in kgdb_init()
1565 intr_mask = REG_RD(intr_vect, regi_irq, rw_mask); in kgdb_init()
1569 ser_intr_mask = REG_RD(ser, regi_ser3, rw_intr_mask); in kgdb_init()
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| D | fasttimer.c | 139 r_time0 = REG_RD(timer, regi_timer0, r_time); in start_timer_trig()
144 intr_mask = REG_RD(timer, regi_timer0, rw_intr_mask); in start_timer_trig()
165 r_time1 = REG_RD(timer, regi_timer0, r_time); in start_timer_trig()
170 intr_mask = REG_RD(timer, regi_timer0, rw_intr_mask); in start_timer_trig()
312 masked_intr = REG_RD(timer, regi_timer0, r_masked_intr); in timer_trig_interrupt()
337 intr_mask = REG_RD(timer, regi_timer0, rw_intr_mask); in timer_trig_handler()
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| D | traps.c | 125 r = REG_RD(intr_vect, regi_irq, r_nmi); in handle_nmi()
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| /linux-4.4.14/arch/cris/arch-v32/drivers/mach-fs/ |
| D | nandflash.c | 60 dout = REG_RD(gio, regi_gio, rw_pa_dout); in crisv32_hwcontrol()
93 reg_gio_r_pa_din din = REG_RD(gio, regi_gio, r_pa_din); in crisv32_device_ready()
105 reg_bif_core_rw_grp3_cfg bif_cfg = REG_RD(bif_core, regi_bif_core, in crisv32_nand_flash_probe()
107 reg_gio_rw_pa_oe pa_oe = REG_RD(gio, regi_gio, rw_pa_oe); in crisv32_nand_flash_probe()
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| /linux-4.4.14/drivers/cpufreq/ |
| D | cris-artpec3-cpufreq.c | 26 clk_ctrl = REG_RD(clkgen, regi_clkgen, rw_clk_ctrl); in cris_freq_get_cpu_frequency()
33 clk_ctrl = REG_RD(clkgen, regi_clkgen, rw_clk_ctrl); in cris_freq_target()
81 REG_RD(ddr2, regi_ddr2_ctrl, rw_cfg); in cris_sdram_freq_notifier()
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| D | cris-etraxfs-cpufreq.c | 26 clk_ctrl = REG_RD(config, regi_config, rw_clk_ctrl); in cris_freq_get_cpu_frequency()
33 clk_ctrl = REG_RD(config, regi_config, rw_clk_ctrl); in cris_freq_target()
81 REG_RD(bif_core, regi_bif_core, rw_sdram_timing); in cris_sdram_freq_notifier()
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| /linux-4.4.14/arch/cris/arch-v32/lib/ |
| D | delay.c | 24 u32 t0 = REG_RD(timer, regi_timer0, r_time); in cris_delay10ns()
25 while (REG_RD(timer, regi_timer0, r_time) - t0 < n10ns) in cris_delay10ns()
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| /linux-4.4.14/drivers/net/ethernet/broadcom/bnx2x/ |
| D | bnx2x_link.c | 228 u32 val = REG_RD(bp, reg); in bnx2x_bits_en()
237 u32 val = REG_RD(bp, reg); in bnx2x_bits_dis()
260 REG_RD(bp, params->lfa_base + in bnx2x_check_lfa()
275 link_status = REG_RD(bp, params->shmem_base + in bnx2x_check_lfa()
304 saved_val = REG_RD(bp, params->lfa_base + in bnx2x_check_lfa()
313 saved_val = REG_RD(bp, params->lfa_base + in bnx2x_check_lfa()
322 saved_val = REG_RD(bp, params->lfa_base + in bnx2x_check_lfa()
332 cur_speed_cap_mask = REG_RD(bp, params->lfa_base + in bnx2x_check_lfa()
345 REG_RD(bp, params->lfa_base + in bnx2x_check_lfa()
355 eee_status = REG_RD(bp, params->shmem2_base + in bnx2x_check_lfa()
[all …]
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| D | bnx2x_main.c | 619 data[i] = REG_RD(bp, src_addr + i*4); in bnx2x_read_dmae()
727 regs[j] = REG_RD(bp, bar_storm_intmem[storm] + in bnx2x_mc_assert()
776 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER); in bnx2x_fw_dump_lvl()
777 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER)) in bnx2x_fw_dump_lvl()
797 mark = REG_RD(bp, addr); in bnx2x_fw_dump_lvl()
805 mark = REG_RD(bp, addr); in bnx2x_fw_dump_lvl()
818 data[word] = htonl(REG_RD(bp, offset + 4*word)); in bnx2x_fw_dump_lvl()
826 data[word] = htonl(REG_RD(bp, offset + 4*word)); in bnx2x_fw_dump_lvl()
842 u32 val = REG_RD(bp, addr); in bnx2x_hc_int_disable()
872 if (REG_RD(bp, addr) != val) in bnx2x_hc_int_disable()
[all …]
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| D | bnx2x_init.h | 210 u32 curr_cos = REG_RD(bp, QM_REG_QVOQIDX_0 + q_num * 4); in bnx2x_map_q_cos()
237 reg_bit_map = REG_RD(bp, reg_addr); in bnx2x_map_q_cos()
242 reg_bit_map = REG_RD(bp, reg_addr); in bnx2x_map_q_cos()
250 reg_bit_map = REG_RD(bp, reg_addr); in bnx2x_map_q_cos()
682 reg_val = REG_RD(bp, mcp_attn_ctl_regs[i].addr); in bnx2x_set_mcp_parity()
745 reg_val = REG_RD(bp, bnx2x_blocks_parity_data[i]. in bnx2x_clear_blocks_parity()
756 reg_val = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_MCP); in bnx2x_clear_blocks_parity()
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| D | bnx2x_ethtool.c | 859 *p++ = REG_RD(bp, addr); in bnx2x_read_pages_regs()
888 *p++ = REG_RD(bp, idle_reg_addrs[i].addr + j*4); in __bnx2x_get_preset_regs()
897 *p++ = REG_RD(bp, reg_addrs[i].addr + j*4); in __bnx2x_get_preset_regs()
905 *p++ = REG_RD(bp, wreg_addr_p->addr + i*4); in __bnx2x_get_preset_regs()
912 *p++ = REG_RD(bp, addr + j*4); in __bnx2x_get_preset_regs()
1224 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB); in bnx2x_acquire_nvram_lock()
1257 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB); in bnx2x_release_nvram_lock()
1279 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE); in bnx2x_enable_nvram_access()
1291 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE); in bnx2x_disable_nvram_access()
1328 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND); in bnx2x_nvram_read_dword()
[all …]
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| D | bnx2x_init_ops.h | 262 REG_RD(bp, addr); in bnx2x_init_block()
518 val = REG_RD(bp, write_arb_addr[i].l); in bnx2x_init_pxp_arb()
522 val = REG_RD(bp, write_arb_addr[i].add); in bnx2x_init_pxp_arb()
526 val = REG_RD(bp, write_arb_addr[i].ubound); in bnx2x_init_pxp_arb()
587 val = REG_RD(bp, PCIE_REG_PCIER_TL_HDR_FC_ST); in bnx2x_init_pxp_arb()
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| D | bnx2x.h | 165 #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset)) macro
200 #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field))
205 #define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field))
212 #define MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field))
215 #define MF2_CFG_RD(bp, field) REG_RD(bp, MF2_CFG_ADDR(bp, field))
221 #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg)
2167 val = REG_RD(bp, reg); in reg_poll()
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| D | bnx2x_cmn.h | 707 u32 result = REG_RD(bp, hc_addr); in bnx2x_hc_ack_int()
716 u32 result = REG_RD(bp, igu_addr); in bnx2x_igu_ack_int()
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| D | bnx2x_stats.c | 860 estats->eee_tx_lpi += REG_RD(bp, lpi_reg); in bnx2x_hw_stats_update()
1630 REG_RD(bp, NIG_REG_STAT0_BRB_DISCARD + port*0x38); in bnx2x_stats_init()
1632 REG_RD(bp, NIG_REG_STAT0_BRB_TRUNCATE + port*0x38); in bnx2x_stats_init()
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| D | bnx2x_sriov.c | 749 val = REG_RD(bp, IGU_REG_VF_CONFIGURATION); in bnx2x_vf_igu_reset()
1088 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + sb_id * 4); in bnx2x_get_vf_igu_cam_info()
1157 val = REG_RD(bp, PCICFG_OFFSET + GRC_CONFIG_REG_PF_INIT_VF); in bnx2x_sriov_info()
1973 val = REG_RD(bp, IGU_REG_VF_CONFIGURATION); in bnx2x_vf_igu_disable()
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| D | bnx2x_dcb.c | 60 *buff = REG_RD(bp, addr + i); in bnx2x_read_data()
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| D | bnx2x_cmn.c | 2384 u32 loaded_fw = REG_RD(bp, XSEM_REG_PRAM); in bnx2x_compare_fw_ver()
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| /linux-4.4.14/arch/cris/arch-v32/drivers/ |
| D | sync_serial.c | 313 reg_sser_rw_cfg cfg = REG_RD(sser, port->regi_sser, rw_cfg); in sync_serial_start_port()
315 REG_RD(sser, port->regi_sser, rw_tr_cfg); in sync_serial_start_port()
317 REG_RD(sser, port->regi_sser, rw_rec_cfg); in sync_serial_start_port()
760 tr_cfg = REG_RD(sser, port->regi_sser, rw_tr_cfg); in sync_serial_ioctl_unlocked()
761 rec_cfg = REG_RD(sser, port->regi_sser, rw_rec_cfg); in sync_serial_ioctl_unlocked()
762 frm_cfg = REG_RD(sser, port->regi_sser, rw_frm_cfg); in sync_serial_ioctl_unlocked()
763 gen_cfg = REG_RD(sser, port->regi_sser, rw_cfg); in sync_serial_ioctl_unlocked()
764 intr_mask = REG_RD(sser, port->regi_sser, rw_intr_mask); in sync_serial_ioctl_unlocked()
1143 reg_sser_rw_cfg cfg = REG_RD(sser, port->regi_sser, rw_cfg); in sync_serial_write()
1145 REG_RD(sser, port->regi_sser, rw_rec_cfg); in sync_serial_write()
[all …]
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| D | iop_fw_load.c | 41 mpu_stat = REG_RD(iop_mpu, regi_iop_mpu, r_stat); in wait_mpu_idle()
99 mc_stat = REG_RD(iop_sw_cpu, regi_iop_sw_cpu, r_mc_stat); in iop_fw_load_spu()
122 (void) REG_RD(iop_sw_cpu, regi_iop_sw_cpu, rs_mc_data); in iop_fw_load_spu()
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| D | cryptocop.c | 2081 dma_out_cfg = REG_RD(dma, OUT_DMA_INST, rw_cfg); in cryptocop_job_queue_close()
2085 dma_in_cfg = REG_RD(dma, IN_DMA_INST, rw_cfg); in cryptocop_job_queue_close()
2090 rw_cfg = REG_RD(strcop, regi_strcop, rw_cfg); in cryptocop_job_queue_close()
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| /linux-4.4.14/drivers/media/radio/wl128x/ |
| D | fmdrv_rx.c | 83 ret = fmc_send_cmd(fmdev, FLAG_GET, REG_RD, NULL, 2, NULL, NULL); in fm_rx_set_freq()
115 ret = fmc_send_cmd(fmdev, FREQ_SET, REG_RD, NULL, 2, &curr_frq, &resp_len); in fm_rx_set_freq()
187 ret = fmc_send_cmd(fmdev, FREQ_SET, REG_RD, NULL, in fm_rx_seek()
227 ret = fmc_send_cmd(fmdev, FLAG_GET, REG_RD, NULL, 2, NULL, NULL); in fm_rx_seek()
283 ret = fmc_send_cmd(fmdev, FREQ_SET, REG_RD, NULL, 2, in fm_rx_seek()
529 ret = fmc_send_cmd(fmdev, RSSI_LVL_GET, REG_RD, NULL, 2, in fm_rx_get_rssi_level()
620 ret = fmc_send_cmd(fmdev, MOST_MODE_SET, REG_RD, NULL, 2, in fm_rx_get_stereo_mono()
700 ret = fmc_send_cmd(fmdev, FLAG_GET, REG_RD, NULL, 2, in fm_rx_set_rds_mode()
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| D | fmdrv_common.c | 580 if (!fm_send_cmd(fmdev, FLAG_GET, REG_RD, NULL, sizeof(flag), NULL)) in fm_irq_send_flag_getcmd()
630 if (!fm_send_cmd(fmdev, RDS_DATA_GET, REG_RD, NULL, in fm_irq_send_rdsdata_getcmd()
973 if (!fm_send_cmd(fmdev, FREQ_SET, REG_RD, NULL, sizeof(payload), NULL)) in fm_irq_afjump_rd_freq()
1345 if (fmc_send_cmd(fmdev, ASIC_ID_GET, REG_RD, NULL, in fm_power_up()
1349 if (fmc_send_cmd(fmdev, ASIC_VER_GET, REG_RD, NULL, in fm_power_up()
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| D | fmdrv_common.h | 28 #define REG_RD 0x1 macro
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| D | fmdrv_tx.c | 372 ret = fmc_send_cmd(fmdev, READ_FMANT_TUNE_VALUE, REG_RD, in fm_tx_get_tune_cap_val()
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| /linux-4.4.14/arch/cris/include/arch-v32/mach-fs/mach/hwregs/ |
| D | marb_defs.h | 17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
276 #ifndef REG_RD
277 #define REG_RD( scope, inst, reg ) \ macro
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| D | strmux_defs.h | 17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
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| D | config_defs.h | 17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
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| D | marb_bp_defs.h | 17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
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| D | timer_defs.h | 17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
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| D | intr_vect_defs.h | 17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
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| D | bif_slave_defs.h | 17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
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| D | gio_defs.h | 17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
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| D | bif_core_defs.h | 17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
|
| D | pinmux_defs.h | 17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
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| D | bif_dma_defs.h | 17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
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| /linux-4.4.14/arch/cris/include/arch-v32/mach-a3/mach/hwregs/ |
| D | marb_bar_defs.h | 14 #ifndef REG_RD
15 #define REG_RD( scope, inst, reg ) \ macro
298 #ifndef REG_RD
299 #define REG_RD( scope, inst, reg ) \ macro
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| D | strmux_defs.h | 14 #ifndef REG_RD
15 #define REG_RD( scope, inst, reg ) \ macro
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| D | l2cache_defs.h | 14 #ifndef REG_RD
15 #define REG_RD( scope, inst, reg ) \ macro
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| D | clkgen_defs.h | 14 #ifndef REG_RD
15 #define REG_RD( scope, inst, reg ) \ macro
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| D | marb_foo_defs.h | 14 #ifndef REG_RD
15 #define REG_RD( scope, inst, reg ) \ macro
424 #ifndef REG_RD
425 #define REG_RD( scope, inst, reg ) \ macro
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| D | timer_defs.h | 14 #ifndef REG_RD
15 #define REG_RD( scope, inst, reg ) \ macro
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| D | ddr2_defs.h | 14 #ifndef REG_RD
15 #define REG_RD( scope, inst, reg ) \ macro
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| D | pinmux_defs.h | 14 #ifndef REG_RD
15 #define REG_RD( scope, inst, reg ) \ macro
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| D | pio_defs.h | 14 #ifndef REG_RD
15 #define REG_RD( scope, inst, reg ) \ macro
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| D | intr_vect_defs.h | 14 #ifndef REG_RD
15 #define REG_RD( scope, inst, reg ) \ macro
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| D | gio_defs.h | 14 #ifndef REG_RD
15 #define REG_RD( scope, inst, reg ) \ macro
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| /linux-4.4.14/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/ |
| D | iop_version_defs.h | 14 #ifndef REG_RD
15 #define REG_RD( scope, inst, reg ) \ macro
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| D | iop_sap_in_defs.h | 14 #ifndef REG_RD
15 #define REG_RD( scope, inst, reg ) \ macro
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| D | iop_sap_out_defs.h | 14 #ifndef REG_RD
15 #define REG_RD( scope, inst, reg ) \ macro
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| D | iop_sw_spu_defs.h | 14 #ifndef REG_RD
15 #define REG_RD( scope, inst, reg ) \ macro
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| D | iop_sw_cpu_defs.h | 14 #ifndef REG_RD
15 #define REG_RD( scope, inst, reg ) \ macro
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| D | iop_sw_mpu_defs.h | 14 #ifndef REG_RD
15 #define REG_RD( scope, inst, reg ) \ macro
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| D | iop_sw_cfg_defs.h | 14 #ifndef REG_RD
15 #define REG_RD( scope, inst, reg ) \ macro
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| /linux-4.4.14/arch/cris/include/arch-v32/arch/hwregs/iop/ |
| D | iop_version_defs.h | 17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
|
| D | iop_scrc_in_defs.h | 17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
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| D | iop_scrc_out_defs.h | 17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
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| D | iop_trigger_grp_defs.h | 17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
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| D | iop_fifo_in_extra_defs.h | 17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
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| D | iop_fifo_out_extra_defs.h | 17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
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| D | iop_sap_in_defs.h | 17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
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| D | iop_mpu_defs.h | 17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
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| D | iop_crc_par_defs.h | 17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
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| D | iop_fifo_in_defs.h | 17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
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| D | iop_timer_grp_defs.h | 17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
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| D | iop_fifo_out_defs.h | 17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
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| D | iop_sap_out_defs.h | 17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
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| D | iop_dmc_out_defs.h | 17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
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| D | iop_dmc_in_defs.h | 17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
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| D | iop_spu_defs.h | 17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
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| D | iop_sw_spu_defs.h | 17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
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| D | iop_sw_cpu_defs.h | 17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
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| D | iop_sw_mpu_defs.h | 17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
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| D | iop_sw_cfg_defs.h | 17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
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| /linux-4.4.14/arch/cris/arch-v32/drivers/mach-a3/ |
| D | nandflash.c | 61 dout = REG_RD(pio, regi_pio, rw_dout); in crisv32_hwcontrol()
98 reg_pio_r_din din = REG_RD(pio, regi_pio, r_din); in crisv32_device_ready()
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| /linux-4.4.14/arch/cris/include/arch-v32/arch/ |
| D | timex.h | 21 ((TIMER0_DIV - REG_RD(timer, regi_timer0, r_tmr0_data)) / 100)
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| /linux-4.4.14/drivers/net/ethernet/qlogic/qed/ |
| D | qed_dev.c | 366 if (REG_RD(p_hwfn, addr)) { in qed_final_cleanup()
380 while (!REG_RD(p_hwfn, addr) && count--) in qed_final_cleanup()
383 if (REG_RD(p_hwfn, addr)) in qed_final_cleanup()
990 p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR); in get_function_id()
992 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR); in get_function_id()
1340 if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) { in qed_hw_prepare_single()
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| D | qed.h | 479 #define REG_RD(cdev, offset) readl(REG_ADDR(cdev, offset)) macro
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| D | qed_int.c | 1055 intr_status_lo = REG_RD(p_hwfn, in qed_int_igu_read_sisr_reg()
1058 intr_status_hi = REG_RD(p_hwfn, in qed_int_igu_read_sisr_reg()
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| D | qed_hw.c | 215 u32 val = REG_RD(p_hwfn, bar_addr); in qed_rd()
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| /linux-4.4.14/arch/x86/crypto/ |
| D | sha1_avx2_x86_64_asm.S | 88 #define REG_RD %rax macro
111 .set RD, REG_RD
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| /linux-4.4.14/drivers/scsi/bnx2i/ |
| D | bnx2i.h | 128 #define REG_RD(__hba, offset) \ macro
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| D | bnx2i_hwi.c | 2750 config2 = REG_RD(ep->hba, BNX2_MQ_CONFIG2); in bnx2i_map_ep_dbell_regs()
|