228 	u32 val = REG_RD(bp, reg);  in bnx2x_bits_en()
237 	u32 val = REG_RD(bp, reg);  in bnx2x_bits_dis()
260 		REG_RD(bp, params->lfa_base +  in bnx2x_check_lfa()
275 	link_status = REG_RD(bp, params->shmem_base +  in bnx2x_check_lfa()
304 	saved_val = REG_RD(bp, params->lfa_base +  in bnx2x_check_lfa()
313 	saved_val = REG_RD(bp, params->lfa_base +  in bnx2x_check_lfa()
322 	saved_val = REG_RD(bp, params->lfa_base +  in bnx2x_check_lfa()
332 		cur_speed_cap_mask = REG_RD(bp, params->lfa_base +  in bnx2x_check_lfa()
345 		REG_RD(bp, params->lfa_base +  in bnx2x_check_lfa()
355 	eee_status = REG_RD(bp, params->shmem2_base +  in bnx2x_check_lfa()
386 	gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);  in bnx2x_get_epio()
389 	*en = (REG_RD(bp, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin;  in bnx2x_get_epio()
403 	gp_output = REG_RD(bp, MCP_REG_MCPR_GP_OUTPUTS);  in bnx2x_set_epio()
412 	gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);  in bnx2x_set_epio()
1431 	cur_mode = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);  in bnx2x_set_mdio_clk()
1468 	port4mode_ovwr_val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);  in bnx2x_is_4_port_mode()
1474 	return (u8)REG_RD(bp, MISC_REG_PORT4MODE_EN);  in bnx2x_is_4_port_mode()
1495 	val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);  in bnx2x_emac_init()
1500 		val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);  in bnx2x_emac_init()
1541 	if (!(REG_RD(bp, MISC_REG_RESET_REG_2) &  in bnx2x_set_umac_rxtx()
1544 	val = REG_RD(bp, umac_base + UMAC_REG_COMMAND_CONFIG);  in bnx2x_set_umac_rxtx()
1669 	    (REG_RD(bp, MISC_REG_RESET_REG_2) &  in bnx2x_xmac_init()
1723 	if (REG_RD(bp, MISC_REG_RESET_REG_2) &  in bnx2x_set_xmac_rxtx()
1729 		pfc_ctrl = REG_RD(bp, xmac_base + XMAC_REG_PFC_CTRL_HI);  in bnx2x_set_xmac_rxtx()
1735 		val = REG_RD(bp, xmac_base + XMAC_REG_CTRL);  in bnx2x_set_xmac_rxtx()
1878 	val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);  in bnx2x_emac_enable()
1907 	val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);  in bnx2x_emac_enable()
2146 	xcm_mask = REG_RD(bp, port ? NIG_REG_LLH1_XCM_MASK :  in bnx2x_update_pfc_nig()
2255 		val = REG_RD(bp, MISC_REG_RESET_REG_2);  in bnx2x_update_pfc()
2457 	u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);  in bnx2x_set_bmac_rx()
2464 	if (REG_RD(bp, MISC_REG_RESET_REG_2) &  in bnx2x_set_bmac_rx()
2490 	init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);  in bnx2x_pbf_update()
2491 	crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);  in bnx2x_pbf_update()
2496 		crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);  in bnx2x_pbf_update()
2499 	crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);  in bnx2x_pbf_update()
2571 		if (REG_RD(bp, NIG_REG_PORT_SWAP))  in bnx2x_get_emac_base()
2577 		if (REG_RD(bp, NIG_REG_PORT_SWAP))  in bnx2x_get_emac_base()
2606 	mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);  in bnx2x_cl22_write()
2619 		tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);  in bnx2x_cl22_write()
2642 	mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);  in bnx2x_cl22_read()
2655 		val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);  in bnx2x_cl22_read()
2683 		chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |  in bnx2x_cl45_read()
2684 			  ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);  in bnx2x_cl45_read()
2700 		val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);  in bnx2x_cl45_read()
2721 			val = REG_RD(bp, phy->mdio_ctrl +  in bnx2x_cl45_read()
2758 		chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |  in bnx2x_cl45_write()
2759 			  ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);  in bnx2x_cl45_write()
2776 		tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);  in bnx2x_cl45_write()
2796 			tmp = REG_RD(bp, phy->mdio_ctrl +  in bnx2x_cl45_write()
2830 	if (REG_RD(bp, params->shmem2_base) <=  in bnx2x_eee_has_cap()
2895 		eee_mode = ((REG_RD(bp, params->shmem_base +  in bnx2x_eee_calc_timer()
3072 	board_cfg = REG_RD(bp, params->shmem_base +  in bnx2x_bsc_module_sel()
3080 	sfp_ctrl = REG_RD(bp, params->shmem_base +  in bnx2x_bsc_module_sel()
3111 	val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);  in bnx2x_bsc_read()
3128 	val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);  in bnx2x_bsc_read()
3131 		val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);  in bnx2x_bsc_read()
3152 	val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);  in bnx2x_bsc_read()
3155 		val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);  in bnx2x_bsc_read()
3166 		data_array[i] = REG_RD(bp, (MCP_REG_MCPR_IMC_DATAREG0 + i*4));  in bnx2x_bsc_read()
3242 		path_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR);  in bnx2x_get_warpcore_lane()
3246 			path_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP);  in bnx2x_get_warpcore_lane()
3252 		port_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR);  in bnx2x_get_warpcore_lane()
3256 			port_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP);  in bnx2x_get_warpcore_lane()
3266 			REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP_OVWR);  in bnx2x_get_warpcore_lane()
3271 				REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP);  in bnx2x_get_warpcore_lane()
3818 	if (REG_RD(bp, params->shmem_base +  in bnx2x_warpcore_enable_AN_KR()
3858 		wc_lane_config = REG_RD(bp, params->shmem_base +  in bnx2x_warpcore_enable_AN_KR()
4010 		cfg_tap_val = REG_RD(bp, params->shmem_base +  in bnx2x_warpcore_set_10G_XFI()
4343 		cfg_pin = (REG_RD(bp, shmem_base +  in bnx2x_get_mod_abs_int_cfg()
4420 		serdes_net_if = (REG_RD(bp, params->shmem_base +  in bnx2x_warpcore_config_runtime()
4483 	cfg_pin = REG_RD(bp, params->shmem_base +  in bnx2x_sfp_e3_set_transmitter()
4504 	serdes_net_if = (REG_RD(bp, params->shmem_base +  in bnx2x_warpcore_config_init()
4819 	vars->link_status = REG_RD(bp, params->shmem_base +  in bnx2x_link_status_update()
4829 		vars->eee_status = REG_RD(bp, params->shmem2_base +  in bnx2x_link_status_update()
4839 	media_types = REG_RD(bp, sync_offset);  in bnx2x_link_status_update()
4857 	vars->aeu_int_mask = REG_RD(bp, sync_offset);  in bnx2x_link_status_update()
6086 		 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));  in bnx2x_link_int_enable()
6088 		 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),  in bnx2x_link_int_enable()
6089 		 REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),  in bnx2x_link_int_enable()
6090 		 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));  in bnx2x_link_int_enable()
6092 	   REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),  in bnx2x_link_int_enable()
6093 	   REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));  in bnx2x_link_int_enable()
6106 	latch_status = REG_RD(bp,  in bnx2x_rearm_latch_signal()
6230 	spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr);  in bnx2x_get_ext_phy_fw_version()
6240 		spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr);  in bnx2x_get_ext_phy_fw_version()
6269 			md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD +  in bnx2x_set_xgxs_loopback()
6797 		val = REG_RD(bp, addr) + 1;  in bnx2x_chng_link_count()
6845 		 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));  in bnx2x_link_update()
6847 	is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT +  in bnx2x_link_update()
6850 		 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),  in bnx2x_link_update()
6852 		 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));  in bnx2x_link_update()
6855 	  REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),  in bnx2x_link_update()
6856 	  REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));  in bnx2x_link_update()
7432 	if (REG_RD(bp, params->shmem_base +  in bnx2x_8073_config_init()
7792 	swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);  in bnx2x_get_gpio_port()
7793 	swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);  in bnx2x_get_gpio_port()
7807 	tx_en_mode = REG_RD(bp, params->shmem_base +  in bnx2x_sfp_e1e2_set_transmitter()
7939 	pin_cfg = (REG_RD(bp, params->shmem_base +  in bnx2x_warpcore_power_module()
8238 	media_types = REG_RD(bp, sync_offset);  in bnx2x_get_edc_mode()
8283 	val = REG_RD(bp, params->shmem_base +  in bnx2x_verify_sfp_module()
8548 	u32 fault_led_gpio = REG_RD(bp, params->shmem_base +  in bnx2x_set_e1e2_module_fault_led()
8581 	pin_cfg = (REG_RD(bp, params->shmem_base +  in bnx2x_set_e3_module_fault_led()
8703 	u32 val = REG_RD(bp, params->shmem_base +  in bnx2x_sfp_module_detection()
8997 	tx_en_mode = REG_RD(bp, params->shmem_base +  in bnx2x_8706_config_init()
9245 	swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);  in bnx2x_8727_hw_reset()
9246 	swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);  in bnx2x_8727_hw_reset()
9370 	tx_en_mode = REG_RD(bp, params->shmem_base +  in bnx2x_8727_config_init()
9400 	u32 val = REG_RD(bp, params->shmem_base +  in bnx2x_8727_handle_mod_abs()
10101 	    (REG_RD(bp, params->shmem2_base +  in bnx2x_848xx_cmd_hdlr()
10123 	pair_swap = REG_RD(bp, params->shmem_base +  in bnx2x_848xx_pair_swap_cfg()
10154 			reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +  in bnx2x_84833_get_reset_gpios()
10167 			reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +  in bnx2x_84833_get_reset_gpios()
10186 	u32 other_shmem_base_addr = REG_RD(bp, params->shmem2_base +  in bnx2x_84833_hw_reset_phy()
10375 		u32 cms_enable = REG_RD(bp, params->shmem_base +  in bnx2x_848x3_config_init()
10699 				if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 +  in bnx2x_848xx_set_link_led()
10767 				if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 +  in bnx2x_848xx_set_link_led()
10934 	cfg_pin = (REG_RD(bp, params->shmem_base +  in bnx2x_54618se_config_init()
11175 	cfg_pin = (REG_RD(bp, params->shmem_base +  in bnx2x_54618se_link_reset()
12042 			rx = REG_RD(bp, shmem_base +  in bnx2x_populate_preemphasis()
12046 			tx = REG_RD(bp, shmem_base +  in bnx2x_populate_preemphasis()
12050 			rx = REG_RD(bp, shmem_base +  in bnx2x_populate_preemphasis()
12054 			tx = REG_RD(bp, shmem_base +  in bnx2x_populate_preemphasis()
12073 		ext_phy_config = REG_RD(bp, shmem_base +  in bnx2x_get_ext_phy_config()
12078 		ext_phy_config = REG_RD(bp, shmem_base +  in bnx2x_get_ext_phy_config()
12094 	u32 switch_cfg = (REG_RD(bp, shmem_base +  in bnx2x_populate_int_phy()
12098 	chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |  in bnx2x_populate_int_phy()
12099 		((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);  in bnx2x_populate_int_phy()
12104 		phy_addr = REG_RD(bp,  in bnx2x_populate_int_phy()
12107 		if (REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR) == 0x3)  in bnx2x_populate_int_phy()
12112 		serdes_net_if = (REG_RD(bp, shmem_base +  in bnx2x_populate_int_phy()
12194 			phy_addr = REG_RD(bp,  in bnx2x_populate_int_phy()
12200 			phy_addr = REG_RD(bp,  in bnx2x_populate_int_phy()
12308 	config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region,  in bnx2x_populate_ext_phy()
12319 		u32 size = REG_RD(bp, shmem2_base);  in bnx2x_populate_ext_phy()
12340 		u32 raw_ver = REG_RD(bp, phy->ver_addr);  in bnx2x_populate_ext_phy()
12374 		link_config = REG_RD(bp, params->shmem_base +  in bnx2x_phy_def_cfg()
12377 		phy->speed_cap_mask = REG_RD(bp, params->shmem_base +  in bnx2x_phy_def_cfg()
12382 		link_config = REG_RD(bp, params->shmem_base +  in bnx2x_phy_def_cfg()
12385 		phy->speed_cap_mask = REG_RD(bp, params->shmem_base +  in bnx2x_phy_def_cfg()
12521 		media_types = REG_RD(bp, sync_offset);  in bnx2x_phy_probe()
12722 	lfa_sts = REG_RD(bp, params->lfa_base +  in bnx2x_avoid_link_flap()
12801 	tmp_val = REG_RD(bp, params->lfa_base +  in bnx2x_cannot_avoid_link_flap()
12809 	lfa_sts = REG_RD(bp, params->lfa_base +  in bnx2x_cannot_avoid_link_flap()
13001 		if (REG_RD(bp, MISC_REG_RESET_REG_2) &  in bnx2x_link_reset()
13076 	swap_val = REG_RD(bp,  NIG_REG_PORT_SWAP);  in bnx2x_8073_common_init_phy()
13077 	swap_override = REG_RD(bp,  NIG_REG_STRAP_OVERRIDE);  in bnx2x_8073_common_init_phy()
13201 	val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);  in bnx2x_8726_common_init_phy()
13244 	u32 phy_gpio_reset = REG_RD(bp, shmem_base +  in bnx2x_get_ext_phy_reset_gpio()
13296 	swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);  in bnx2x_8727_common_init_phy()
13297 	swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);  in bnx2x_8727_common_init_phy()
13469 		val = REG_RD(bp, MISC_REG_GEN_PURP_HWG);  in bnx2x_common_init_phy()
13473 	phy_ver = REG_RD(bp, shmem_base_path[0] +  in bnx2x_common_init_phy()
13505 	cfg_pin = (REG_RD(bp, params->shmem_base +  in bnx2x_check_over_curr()
13621 	    (REG_RD(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4)))  in bnx2x_check_half_open_conn()
13625 	    (REG_RD(bp, MISC_REG_RESET_REG_2) &  in bnx2x_check_half_open_conn()
13639 		if (REG_RD(bp, mac_base + XMAC_REG_RX_LSS_STATUS))  in bnx2x_check_half_open_conn()
13645 	} else if (REG_RD(bp, MISC_REG_RESET_REG_2) &  in bnx2x_check_half_open_conn()
13676 	cfg_pin = (REG_RD(bp, params->shmem_base + offsetof(struct shmem_region,  in bnx2x_sfp_tx_fault_detection()
13817 		if ((REG_RD(bp, params->shmem_base +  in bnx2x_period_func()
13917 	swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);  in bnx2x_init_mod_abs_int()
13918 	swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);  in bnx2x_init_mod_abs_int()
13938 	aeu_mask = REG_RD(bp, offset);  in bnx2x_init_mod_abs_int()
13943 	val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);  in bnx2x_init_mod_abs_int()