619 				data[i] = REG_RD(bp, src_addr + i*4);  in bnx2x_read_dmae()
727 				regs[j] = REG_RD(bp, bar_storm_intmem[storm] +  in bnx2x_mc_assert()
776 	val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);  in bnx2x_fw_dump_lvl()
777 	if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))  in bnx2x_fw_dump_lvl()
797 	mark = REG_RD(bp, addr);  in bnx2x_fw_dump_lvl()
805 	mark = REG_RD(bp, addr);  in bnx2x_fw_dump_lvl()
818 			data[word] = htonl(REG_RD(bp, offset + 4*word));  in bnx2x_fw_dump_lvl()
826 			data[word] = htonl(REG_RD(bp, offset + 4*word));  in bnx2x_fw_dump_lvl()
842 	u32 val = REG_RD(bp, addr);  in bnx2x_hc_int_disable()
872 	if (REG_RD(bp, addr) != val)  in bnx2x_hc_int_disable()
878 	u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);  in bnx2x_igu_int_disable()
890 	if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)  in bnx2x_igu_int_disable()
946 				REG_RD(bp, BAR_CSTRORM_INTMEM + cstorm_offset +  in bnx2x_panic_dump()
1043 			*(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +  in bnx2x_panic_dump()
1215 	crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);  in bnx2x_pbf_pN_buf_flushed()
1216 	crd = crd_start = REG_RD(bp, regs->crd);  in bnx2x_pbf_pN_buf_flushed()
1217 	init_crd = REG_RD(bp, regs->init_crd);  in bnx2x_pbf_pN_buf_flushed()
1227 			crd = REG_RD(bp, regs->crd);  in bnx2x_pbf_pN_buf_flushed()
1228 			crd_freed = REG_RD(bp, regs->crd_freed);  in bnx2x_pbf_pN_buf_flushed()
1250 	occup = to_free = REG_RD(bp, regs->lines_occup);  in bnx2x_pbf_pN_cmd_flushed()
1251 	freed = freed_start = REG_RD(bp, regs->lines_freed);  in bnx2x_pbf_pN_cmd_flushed()
1259 			occup = REG_RD(bp, regs->lines_occup);  in bnx2x_pbf_pN_cmd_flushed()
1260 			freed = REG_RD(bp, regs->lines_freed);  in bnx2x_pbf_pN_cmd_flushed()
1281 	while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)  in bnx2x_flr_clnup_reg_poll()
1391 	if (REG_RD(bp, comp_addr)) {  in bnx2x_send_final_clnup()
1407 		   (REG_RD(bp, comp_addr)));  in bnx2x_send_final_clnup()
1476 	val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);  in bnx2x_hw_enable_status()
1479 	val = REG_RD(bp, PBF_REG_DISABLE_PF);  in bnx2x_hw_enable_status()
1482 	val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);  in bnx2x_hw_enable_status()
1485 	val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);  in bnx2x_hw_enable_status()
1488 	val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);  in bnx2x_hw_enable_status()
1491 	val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);  in bnx2x_hw_enable_status()
1494 	val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);  in bnx2x_hw_enable_status()
1497 	val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);  in bnx2x_hw_enable_status()
1550 	u32 val = REG_RD(bp, addr);  in bnx2x_hc_int_enable()
1622 	val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);  in bnx2x_igu_int_enable()
1745 	lock_status = REG_RD(bp, hw_lock_control_reg);  in bnx2x_trylock_hw_lock()
2009 	lock_status = REG_RD(bp, hw_lock_control_reg);  in bnx2x_acquire_hw_lock()
2020 		lock_status = REG_RD(bp, hw_lock_control_reg);  in bnx2x_acquire_hw_lock()
2057 	lock_status = REG_RD(bp, hw_lock_control_reg);  in bnx2x_release_hw_lock()
2071 	int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&  in bnx2x_get_gpio()
2072 			 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;  in bnx2x_get_gpio()
2085 	gpio_reg = REG_RD(bp, MISC_REG_GPIO);  in bnx2x_get_gpio()
2099 	int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&  in bnx2x_set_gpio()
2100 			 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;  in bnx2x_set_gpio()
2113 	gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);  in bnx2x_set_gpio()
2161 	gpio_reg = REG_RD(bp, MISC_REG_GPIO);  in bnx2x_set_mult_gpio()
2202 	int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&  in bnx2x_set_gpio_int()
2203 			 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;  in bnx2x_set_gpio_int()
2216 	gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);  in bnx2x_set_gpio_int()
2259 	spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);  in bnx2x_set_spio()
3720 	SHMEM2_WR(bp, drv_info.fw_ver, REG_RD(bp, XSEM_REG_PRAM));  in bnx2x_update_mfw_dump()
3942 		val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK);  in bnx2x_acquire_alr()
4005 	aeu_mask = REG_RD(bp, aeu_addr);  in bnx2x_attn_int_asserted()
4025 			nig_mask = REG_RD(bp, nig_int_mask_addr);  in bnx2x_attn_int_asserted()
4098 				igu_acked = REG_RD(bp,  in bnx2x_attn_int_asserted()
4148 		val = REG_RD(bp, reg_offset);  in bnx2x_attn_int_deasserted0()
4167 		val = REG_RD(bp, reg_offset);  in bnx2x_attn_int_deasserted0()
4183 		val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);  in bnx2x_attn_int_deasserted1()
4198 		val = REG_RD(bp, reg_offset);  in bnx2x_attn_int_deasserted1()
4214 		val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);  in bnx2x_attn_int_deasserted2()
4222 		val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);  in bnx2x_attn_int_deasserted2()
4229 			val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);  in bnx2x_attn_int_deasserted2()
4242 		val = REG_RD(bp, reg_offset);  in bnx2x_attn_int_deasserted2()
4341 					REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);  in bnx2x_attn_int_deasserted3()
4346 					REG_RD(bp, MISC_REG_GRC_RSV_ATTN);  in bnx2x_attn_int_deasserted3()
4386 	val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);  in bnx2x_set_reset_global()
4400 	val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);  in bnx2x_clear_reset_global()
4412 	u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);  in bnx2x_reset_is_global()
4429 	val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);  in bnx2x_set_reset_done()
4449 	val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);  in bnx2x_set_reset_in_progress()
4463 	u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);  in bnx2x_reset_is_done()
4485 	val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);  in bnx2x_set_pf_load()
4523 	val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);  in bnx2x_clear_pf_load()
4554 	u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);  in bnx2x_get_load_status()
4568 	pr_cont(" [0x%08x] ", REG_RD(bp, reg));  in _print_parity()
5004 	attn.sig[0] = REG_RD(bp,  in bnx2x_chk_parity_attn()
5007 	attn.sig[1] = REG_RD(bp,  in bnx2x_chk_parity_attn()
5010 	attn.sig[2] = REG_RD(bp,  in bnx2x_chk_parity_attn()
5013 	attn.sig[3] = REG_RD(bp,  in bnx2x_chk_parity_attn()
5019 	attn.sig[3] &= ((REG_RD(bp,  in bnx2x_chk_parity_attn()
5026 		attn.sig[4] = REG_RD(bp,  in bnx2x_chk_parity_attn()
5038 		val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);  in bnx2x_attn_int_deasserted4()
5062 		val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);  in bnx2x_attn_int_deasserted4()
5116 	attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);  in bnx2x_attn_int_deasserted()
5117 	attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);  in bnx2x_attn_int_deasserted()
5118 	attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);  in bnx2x_attn_int_deasserted()
5119 	attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);  in bnx2x_attn_int_deasserted()
5122 		      REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);  in bnx2x_attn_int_deasserted()
5172 	aeu_mask = REG_RD(bp, reg_addr);  in bnx2x_attn_int_deasserted()
6051 			   REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);  in bnx2x_init_def_sb()
6059 			bp->attn_group[index].sig[4] = REG_RD(bp,  in bnx2x_init_def_sb()
6545 		REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &  in bnx2x_post_irq_nic_init()
6716 		val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);  in bnx2x_int_mem_test()
6770 	val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);  in bnx2x_int_mem_test()
6780 	val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);  in bnx2x_int_mem_test()
6786 		REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);  in bnx2x_int_mem_test()
6787 	val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);  in bnx2x_int_mem_test()
6955 	val = REG_RD(bp, MISC_REG_SPIO_INT);  in bnx2x_setup_fan_failure_detection()
6960 	val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);  in bnx2x_setup_fan_failure_detection()
6967 	u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);  in bnx2x_pf_disable()
7102 	val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);  in bnx2x_init_hw_common()
7107 	val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);  in bnx2x_init_hw_common()
7224 			val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);  in bnx2x_init_hw_common()
7456 	REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);  in bnx2x_init_hw_common()
7468 		SHMEM2_WR(bp, netproc_fw_ver, REG_RD(bp, XSEM_REG_PRAM));  in bnx2x_init_hw_common()
7645 	       REG_RD(bp, reg) &  in bnx2x_init_hw_port()
7650 	       REG_RD(bp, reg) &  in bnx2x_init_hw_port()
7705 	val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);  in bnx2x_init_hw_port()
7709 		val = REG_RD(bp, reg_addr);  in bnx2x_init_hw_port()
7767 	while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)  in bnx2x_igu_clear_sb_gen()
7770 	if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {  in bnx2x_igu_clear_sb_gen()
7832 		vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN :  in bnx2x_reset_nic_mode()
7837 			mac_en[i] = REG_RD(bp, port ?  in bnx2x_reset_nic_mode()
7954 		val = REG_RD(bp, addr);  in bnx2x_init_hw_func()
8211 		val = REG_RD(bp, main_mem_prty_clr);  in bnx2x_init_hw_func()
8226 		REG_RD(bp, main_mem_prty_clr);  in bnx2x_init_hw_func()
8985 			if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))  in bnx2x_reset_func()
9034 	val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);  in bnx2x_reset_port()
9441 		val = REG_RD(bp, addr);  in bnx2x_disable_close_the_gate()
9445 		val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);  in bnx2x_disable_close_the_gate()
9468 		val = REG_RD(bp, HC_REG_CONFIG_1);  in bnx2x_set_234_gates()
9473 		val = REG_RD(bp, HC_REG_CONFIG_0);  in bnx2x_set_234_gates()
9479 		val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);  in bnx2x_set_234_gates()
9536 	shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);  in bnx2x_reset_mcp_prep()
9572 		bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);  in bnx2x_init_shmem()
9731 		pend_bits  = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);  in bnx2x_er_poll_igu_vq()
9757 		sr_cnt  = REG_RD(bp, PXP2_REG_RD_SR_CNT);  in bnx2x_process_kill()
9758 		blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);  in bnx2x_process_kill()
9759 		port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);  in bnx2x_process_kill()
9760 		port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);  in bnx2x_process_kill()
9761 		pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);  in bnx2x_process_kill()
9763 			tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32);  in bnx2x_process_kill()
10362 	vals->umac_val[port] = REG_RD(bp, vals->umac_addr[port]);  in bnx2x_prev_unload_close_umac()
10378 	reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);  in bnx2x_prev_unload_close_mac()
10381 		val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);  in bnx2x_prev_unload_close_mac()
10397 			wb_data[0] = REG_RD(bp, base_addr + offset);  in bnx2x_prev_unload_close_mac()
10398 			wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);  in bnx2x_prev_unload_close_mac()
10408 		vals->emac_val = REG_RD(bp, vals->emac_addr);  in bnx2x_prev_unload_close_mac()
10415 			val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);  in bnx2x_prev_unload_close_mac()
10421 			vals->xmac_val = REG_RD(bp, vals->xmac_addr);  in bnx2x_prev_unload_close_mac()
10452 	if (!(REG_RD(bp, MISC_REG_RESET_REG_1) &  in bnx2x_prev_is_after_undi()
10456 	if (REG_RD(bp, DORQ_REG_NORM_CID_OFST) == 0x7) {  in bnx2x_prev_is_after_undi()
10474 	tmp_reg = REG_RD(bp, addr);  in bnx2x_prev_unload_undi_inc()
10716 	reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);  in bnx2x_prev_unload_common()
10737 			REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0);  in bnx2x_prev_unload_common()
10744 		tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);  in bnx2x_prev_unload_common()
10748 			tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);  in bnx2x_prev_unload_common()
10812 	hw_lock_val = REG_RD(bp, hw_lock_reg);  in bnx2x_prev_unload()
10825 	if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {  in bnx2x_prev_unload()
10886 	val = REG_RD(bp, MISC_REG_CHIP_NUM);  in bnx2x_get_common_hwinfo()
10888 	val = REG_RD(bp, MISC_REG_CHIP_REV);  in bnx2x_get_common_hwinfo()
10894 	val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3);  in bnx2x_get_common_hwinfo()
10896 	val = REG_RD(bp, MISC_REG_BOND_ID);  in bnx2x_get_common_hwinfo()
10901 	if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {  in bnx2x_get_common_hwinfo()
10915 		val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);  in bnx2x_get_common_hwinfo()
10917 			val = REG_RD(bp, MISC_REG_PORT4MODE_EN);  in bnx2x_get_common_hwinfo()
10939 	val = (REG_RD(bp, 0x2874) & 0x55);  in bnx2x_get_common_hwinfo()
10946 	val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);  in bnx2x_get_common_hwinfo()
10954 	bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?  in bnx2x_get_common_hwinfo()
10963 		REG_RD(bp, bp->common.shmem2_base +  in bnx2x_get_common_hwinfo()
11091 		val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);  in bnx2x_get_igu_cam_info()
11170 		bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);  in bnx2x_link_settings_supported()
11174 			bp->port.phy_addr = REG_RD(  in bnx2x_link_settings_supported()
11178 			bp->port.phy_addr = REG_RD(  in bnx2x_link_settings_supported()
11869 	if (REG_RD(bp, MISC_REG_CHIP_NUM) == 0xffffffff) {  in bnx2x_get_hwinfo()
11891 		val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);  in bnx2x_get_hwinfo()
11902 			while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {  in bnx2x_get_hwinfo()
11907 			if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {  in bnx2x_get_hwinfo()
15061 	REG_RD(bp, pretend_reg);  in bnx2x_pretend_func()
15074 	val_seq = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :  in bnx2x_ptp_task()
15078 		timestamp = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_MSB :  in bnx2x_ptp_task()
15081 		timestamp |= REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_LSB :  in bnx2x_ptp_task()
15108 	timestamp = REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_MSB :  in bnx2x_set_rx_ts()
15111 	timestamp |= REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_LSB :  in bnx2x_set_rx_ts()