Searched refs:R1 (Results 1 - 200 of 223) sorted by relevance

12

/linux-4.4.14/arch/blackfin/lib/
H A Dsmulsi3_highpart.S18 R2 = R1.L * R0.L (FU);
19 R3 = R1.H * R0.L (IS,M);
20 R0 = R0.H * R1.H, R1 = R0.H * R1.L (IS,M);
22 R1.L = R2.H + R1.L;
26 R1.L = R1.L + R3.L;
28 R1 >>>= 16;
30 R1 = R1 + R3; define
31 R1 = R1 + R2; define
33 R1 = R1 + R2; define
35 R0 = R0 + R1;
H A Dumulsi3_highpart.S18 R2 = R1.H * R0.H, R3 = R1.L * R0.H (FU);
19 R0 = R1.L * R0.L, R1 = R1.H * R0.L (FU);
24 R0 = R0 + R1;
26 R1 = cc; define
27 R1 = PACK(R1.l,R0.h); define
28 R0 = R1 + R2;
H A Dmemmove.S14 * R1 = From Address
22 P3 = R1; /* P3 = From Address */
27 CC = R1 < R0 (IU); /* From < To */
29 R3 = R1 + R2;
36 R3 = R1 | R0; /* OR addresses together */
47 R1 = [I0++]; define
52 [P0++] = R1;
54 R1 = [I0++]; define
58 MNOP || [P0++] = R1 || R1 = [I0++];
60 [P0++] = R1;
69 .Lbyte2_s: R1 = B[P3++](Z);
70 .Lbyte2_e: B[P0++] = R1;
79 R1 = B[P3--] (Z); define
87 .Lol_s: B[P0--] = R1;
88 .Lol_e: R1 = B[P3--] (Z);
89 .Lno_loop: B[P0] = R1;
H A Dmuldi3.S18 R1:R0 * R3:R2
19 = R1.h:R1.l:R0.h:R0.l * R3.h:R3.l:R2.h:R2.l
20 [X] = (R1.h * R3.h) * 2^96
21 [X] + (R1.h * R3.l + R1.l * R3.h) * 2^80
22 [X] + (R1.h * R2.h + R1.l * R3.l + R3.h * R0.h) * 2^64
23 [T1] + (R1.h * R2.l + R3.h * R0.l + R1.l * R2.h + R3.l * R0.h) * 2^48
24 [T2] + (R1.l * R2.l + R3.l * R0.l + R0.h * R2.h) * 2^32
32 [E1] = R1.h * R2.l + R3.h * R0.l + R1.l * R2.h + R3.l * R0.h
33 [E2] = R1.l * R2.l + R3.l * R0.l + R0.h * R2.h
42 multiplications involving R1.h and R3.h, but only the top 16 bit of
43 the 32 bit result depend on the sign, and since R1.h and R3.h only
51 A0 = R2.H * R1.L, A1 = R2.L * R1.H (FU) || R3 = [SP + 12]; /* E1 */
56 A0 += R2.l * R1.l (FU); /* E2 */
66 R1 = A0.w; define
71 R1.h = R1.h + R4.l (NS) || R4 = [SP];
H A Dstrcpy.S11 * R1 = address (src)
26 P1 = R1 ; /* src*/
29 R1 = B [P1++] (Z); define
30 B [P0++] = R1;
31 CC = R1;
H A Ddivsi3.S20 * R1 - Denominator (i)
39 R3 = R0 ^ R1;
57 DIVS(R0, R1);
58 DIVQ(R0, R1);
59 DIVQ(R0, R1);
60 DIVQ(R0, R1);
61 DIVQ(R0, R1);
62 DIVQ(R0, R1);
63 DIVQ(R0, R1);
64 DIVQ(R0, R1);
65 DIVQ(R0, R1);
66 DIVQ(R0, R1);
67 DIVQ(R0, R1);
68 DIVQ(R0, R1);
69 DIVQ(R0, R1);
70 DIVQ(R0, R1);
71 DIVQ(R0, R1);
72 DIVQ(R0, R1);
73 DIVQ(R0, R1);
88 CC = R1 == 0; /* check for divide by zero */
94 CC = R0 == R1; /* check for identical operands */
97 CC = R1 == 1; /* check for divide by 1 */
100 R2.L = ONES R1;
112 R2 = -R1;
115 R6 = R0 ^ R1; /* Get sign */
120 R6 = R0 ^ R1; /* Get new quotient bit */
129 IF CC R5 = R1; /* or we might be adding divisor (AQ==1)*/
131 R6 = R0 ^ R1; /* Generate next quotient bit */
148 CC = R1 == 0; /* check for divide by zero => 0x7fffffff */
153 CC = R0 == R1; /* check for identical operands => 1 */
181 CC = R1 < 0;
184 R1.l = SIGNBITS R1;
185 R1 = R1.L (Z); define
186 R1 += -30;
187 R0 = LSHIFT R0 by R1.L;
H A Dmemcmp.S11 * R1 = Second Address (s2)
24 P3 = R1; /* P3 = s2 Address */
28 I0 = R1; /* s2 */
29 R1 = R1 | R0; /* OR addresses together */ define
30 R1 <<= 30; /* check bottom two bits */
43 R1 = [I0++]; define
45 MNOP || R0 = [P0++] || R1 = [I0++];
47 CC = R0 == R1;
60 R1 = B[P3++](Z); /* *s2 */ define
62 CC = R0 == R1;
68 R0 = R0 - R1;
H A Dmemset.S20 * R1 = filler byte
32 R1 = R1.B (Z); /* R1 = fill char */ define
40 R2 = R1 << 8; /* create quad filler */
41 R2.L = R2.L + R1.L(NS);
42 R2.H = R2.L + R1.H(NS);
66 B[P0++] = R1;
78 B[P0++] = R1;
83 B[P0++] = R1;
84 B[P0++] = R1;
H A Dudivsi3.S20 CC = R0 < R1 (IU); /* If X < Y, always return 0 */
23 R2 = R1 << 16;
28 R3 = R1 >> 15; /* and Y is a 15-bit number */
47 DIVQ(R0, R1); // 1
48 DIVQ(R0, R1); // 2
49 DIVQ(R0, R1); // 3
50 DIVQ(R0, R1); // 4
51 DIVQ(R0, R1); // 5
52 DIVQ(R0, R1); // 6
53 DIVQ(R0, R1); // 7
54 DIVQ(R0, R1); // 8
55 DIVQ(R0, R1); // 9
56 DIVQ(R0, R1); // 10
57 DIVQ(R0, R1); // 11
58 DIVQ(R0, R1); // 12
59 DIVQ(R0, R1); // 13
60 DIVQ(R0, R1); // 14
61 DIVQ(R0, R1); // 15
62 DIVQ(R0, R1); // 16
89 R3 = R1 >> 1; /* Pre-scaled divisor for primitive case */
106 CC = R0 == R1; /* X==Y => 1 */
108 CC = R1 == 1; /* X/1 => X */
111 R2.L = ONES R1;
124 P2 = R1;
125 /* If either R0 or R1 have sign set, */
128 CC = R1 < 0;
129 R2 = R1 >> 1;
130 IF CC R1 = R2; /* Possibly-shifted R1 */
131 IF !CC R6 = R3; /* R1 doesn't, so at most 1 shifted */
134 R3 = -R1;
156 IF CC R5 = R1; /* and if AQ==1, we'll add it. */
158 R7 = R3 ^ R1; /* Generate next quotient bit */
169 IF !CC R1 = P2; /* if 2, restore stored divisor */
172 R3 *= R1; /* Q * divisor */
174 CC = R1 <= R5 (IU); /* Check if divisor <= Z? */
184 CC = R0 < R1 (IU); /* If X < Y, always return 0 */
188 CC = R1 == 0;
191 CC = R0 == R1; /* X==Y => 1 */
214 CC = R1 < 0;
217 R1.l = SIGNBITS R1;
218 R1 = R1.L (Z); define
219 R1 += -30;
220 R0 = LSHIFT R0 by R1.L;
234 // R3 is already R1 >> 1
263 R2 *= R1; /* M = Q * Y */
273 R1 = R0 - R3; define
274 IF CC R0 = R1;
H A Dmemchr.S11 * R1 = sought byte (c)
24 R1 = R1.B(Z); define
33 CC = R3 == R1;
H A Dstrcmp.S11 * R1 = address (s2)
28 P1 = R1 ; /* s2 */
32 R1 = B[P1++] (Z); /* get *s2 */ define
33 CC = R0 == R1; /* compare a byte */
39 R0 = R0 - R1; /* *s1 - *s2 */
H A Dstrncmp.S11 * R1 = address (src)
29 P1 = R1 ; /* s2 */
32 R1 = B[P1++] (Z); /* get *s2 */ define
33 CC = R0 == R1; /* compare a byte */
44 R0 = R0 - R1; /* *s1 - *s2 */
H A Dumodsi3.S23 CC= R1==0;
25 CC=R0==R1;
27 CC = R1 == 1;
29 CC = R0<R1 (IU);
35 R6 = R1;
H A Dstrncpy.S12 * R1 = address (src)
32 P1 = R1 ; /* src*/
36 R1 = B [P1++] (Z); define
37 B [P0++] = R1;
38 CC = R1 == 0;
64 * R1 = filler byte (this case it's zero, set above)
81 B [P0++] = R1;
H A Dmemcpy.S17 * R1 = From Address (src)
36 P1 = R1 ; /* src*/
40 CC = R1 < R0; /* src < dst */
42 R3 = R1 + R2;
49 R3 = R1 | R0;
50 R1 = 0x3; define
51 R3 = R3 & R1;
99 R1 = B[P1++] (X); define
101 B[P0++] = R1;
118 R1 = B[P1--] (X); define
120 B[P0--] = R1;
H A Dmodsi3.S4 * Registers in: R0, R1 = Numerator/ Denominator
27 CC=R1==0;
29 CC=R0==R1;
31 CC = R1 == 1;
33 CC = R1 == -1;
42 R6 = R1; /* Save for later */
H A Douts.S19 P1 = R1; /* P1 = address */
32 P1 = R1; /* P1 = address */
45 P1 = R1; /* P1 = address */
58 P1 = R1; /* P1 = address */
62 .Lword8_loop_s: R1 = B[P1++];
65 R0 = R0 + R1;
H A Dins.S78 P1 = R1; /* P1 = address */ \
/linux-4.4.14/arch/x86/crypto/
H A Dtwofish-x86_64-asm_64.S47 #define R1 %rbx define
219 pushq R1
228 movq (R3), R1
230 input_whitening(R1,%r11,a_offset)
234 shr $32, R1
239 encrypt_round(R0,R1,R2,R3,0);
240 encrypt_round(R2,R3,R0,R1,8);
241 encrypt_round(R0,R1,R2,R3,2*8);
242 encrypt_round(R2,R3,R0,R1,3*8);
243 encrypt_round(R0,R1,R2,R3,4*8);
244 encrypt_round(R2,R3,R0,R1,5*8);
245 encrypt_round(R0,R1,R2,R3,6*8);
246 encrypt_round(R2,R3,R0,R1,7*8);
247 encrypt_round(R0,R1,R2,R3,8*8);
248 encrypt_round(R2,R3,R0,R1,9*8);
249 encrypt_round(R0,R1,R2,R3,10*8);
250 encrypt_round(R2,R3,R0,R1,11*8);
251 encrypt_round(R0,R1,R2,R3,12*8);
252 encrypt_round(R2,R3,R0,R1,13*8);
253 encrypt_round(R0,R1,R2,R3,14*8);
254 encrypt_last_round(R2,R3,R0,R1,15*8);
260 shl $32, R1
261 xor R0, R1
263 output_whitening(R1,%r11,c_offset)
264 movq R1, 8(%rsi)
266 popq R1
272 pushq R1
281 movq (R3), R1
283 output_whitening(R1,%r11,a_offset)
286 shr $32, R1
292 decrypt_round(R0,R1,R2,R3,15*8);
293 decrypt_round(R2,R3,R0,R1,14*8);
294 decrypt_round(R0,R1,R2,R3,13*8);
295 decrypt_round(R2,R3,R0,R1,12*8);
296 decrypt_round(R0,R1,R2,R3,11*8);
297 decrypt_round(R2,R3,R0,R1,10*8);
298 decrypt_round(R0,R1,R2,R3,9*8);
299 decrypt_round(R2,R3,R0,R1,8*8);
300 decrypt_round(R0,R1,R2,R3,7*8);
301 decrypt_round(R2,R3,R0,R1,6*8);
302 decrypt_round(R0,R1,R2,R3,5*8);
303 decrypt_round(R2,R3,R0,R1,4*8);
304 decrypt_round(R0,R1,R2,R3,3*8);
305 decrypt_round(R2,R3,R0,R1,2*8);
306 decrypt_round(R0,R1,R2,R3,1*8);
307 decrypt_last_round(R2,R3,R0,R1,0);
312 shl $32, R1
313 xor R0, R1
315 input_whitening(R1,%r11,c_offset)
316 movq R1, 8(%rsi)
318 popq R1
H A Dtwofish-i586-asm_32.S244 encrypt_round(R0,R1,R2,R3,0);
245 encrypt_round(R2,R3,R0,R1,8);
246 encrypt_round(R0,R1,R2,R3,2*8);
247 encrypt_round(R2,R3,R0,R1,3*8);
248 encrypt_round(R0,R1,R2,R3,4*8);
249 encrypt_round(R2,R3,R0,R1,5*8);
250 encrypt_round(R0,R1,R2,R3,6*8);
251 encrypt_round(R2,R3,R0,R1,7*8);
252 encrypt_round(R0,R1,R2,R3,8*8);
253 encrypt_round(R2,R3,R0,R1,9*8);
254 encrypt_round(R0,R1,R2,R3,10*8);
255 encrypt_round(R2,R3,R0,R1,11*8);
256 encrypt_round(R0,R1,R2,R3,12*8);
257 encrypt_round(R2,R3,R0,R1,13*8);
258 encrypt_round(R0,R1,R2,R3,14*8);
259 encrypt_last_round(R2,R3,R0,R1,15*8);
301 decrypt_round(R0,R1,R2,R3,15*8);
302 decrypt_round(R2,R3,R0,R1,14*8);
303 decrypt_round(R0,R1,R2,R3,13*8);
304 decrypt_round(R2,R3,R0,R1,12*8);
305 decrypt_round(R0,R1,R2,R3,11*8);
306 decrypt_round(R2,R3,R0,R1,10*8);
307 decrypt_round(R0,R1,R2,R3,9*8);
308 decrypt_round(R2,R3,R0,R1,8*8);
309 decrypt_round(R0,R1,R2,R3,7*8);
310 decrypt_round(R2,R3,R0,R1,6*8);
311 decrypt_round(R0,R1,R2,R3,5*8);
312 decrypt_round(R2,R3,R0,R1,4*8);
313 decrypt_round(R0,R1,R2,R3,3*8);
314 decrypt_round(R2,R3,R0,R1,2*8);
315 decrypt_round(R0,R1,R2,R3,1*8);
316 decrypt_last_round(R2,R3,R0,R1,0);
H A Daes-x86_64-asm_64.S21 #define R1 %rax define
134 prologue(FUNC,KEY,B128,B192,R2,R8,R7,R9,R1,R3,R4,R6,R10,R5,R11)
139 round(TAB,OFFSET,R1,R2,R3,R4,R5,R6,R7,R10,R5,R6,R3,R4) \
140 move_regs(R1,R2,R5,R6)
143 round(TAB,OFFSET,R1,R2,R3,R4,R5,R6,R7,R10,R5,R6,R3,R4)
146 round(TAB,OFFSET,R2,R1,R4,R3,R6,R5,R7,R10,R5,R6,R3,R4) \
147 move_regs(R1,R2,R5,R6)
150 round(TAB,OFFSET,R2,R1,R4,R3,R6,R5,R7,R10,R5,R6,R3,R4)
/linux-4.4.14/include/linux/mmc/
H A Dsd.h20 #define SD_SWITCH_VOLTAGE 11 /* ac R1 */
23 #define SD_SWITCH 6 /* adtc [31:0] See below R1 */
26 #define SD_ERASE_WR_BLK_START 32 /* ac [31:0] data addr R1 */
27 #define SD_ERASE_WR_BLK_END 33 /* ac [31:0] data addr R1 */
30 #define SD_APP_SET_BUS_WIDTH 6 /* ac [1:0] bus width R1 */
31 #define SD_APP_SD_STATUS 13 /* adtc R1 */
32 #define SD_APP_SEND_NUM_WR_BLKS 22 /* adtc R1 */
34 #define SD_APP_SEND_SCR 51 /* adtc R1 */
H A Dmmc.h32 #define MMC_SET_RELATIVE_ADDR 3 /* ac [31:16] RCA R1 */
36 #define MMC_SELECT_CARD 7 /* ac [31:16] RCA R1 */
37 #define MMC_SEND_EXT_CSD 8 /* adtc R1 */
40 #define MMC_READ_DAT_UNTIL_STOP 11 /* adtc [31:0] dadr R1 */
42 #define MMC_SEND_STATUS 13 /* ac [31:16] RCA R1 */
43 #define MMC_BUS_TEST_R 14 /* adtc R1 */
45 #define MMC_BUS_TEST_W 19 /* adtc R1 */
50 #define MMC_SET_BLOCKLEN 16 /* ac [31:0] block len R1 */
51 #define MMC_READ_SINGLE_BLOCK 17 /* adtc [31:0] data addr R1 */
52 #define MMC_READ_MULTIPLE_BLOCK 18 /* adtc [31:0] data addr R1 */
53 #define MMC_SEND_TUNING_BLOCK 19 /* adtc R1 */
54 #define MMC_SEND_TUNING_BLOCK_HS200 21 /* adtc R1 */
57 #define MMC_WRITE_DAT_UNTIL_STOP 20 /* adtc [31:0] data addr R1 */
60 #define MMC_SET_BLOCK_COUNT 23 /* adtc [31:0] data addr R1 */
61 #define MMC_WRITE_BLOCK 24 /* adtc [31:0] data addr R1 */
62 #define MMC_WRITE_MULTIPLE_BLOCK 25 /* adtc R1 */
63 #define MMC_PROGRAM_CID 26 /* adtc R1 */
64 #define MMC_PROGRAM_CSD 27 /* adtc R1 */
69 #define MMC_SEND_WRITE_PROT 30 /* adtc [31:0] wpdata addr R1 */
72 #define MMC_ERASE_GROUP_START 35 /* ac [31:0] data addr R1 */
73 #define MMC_ERASE_GROUP_END 36 /* ac [31:0] data addr R1 */
84 #define MMC_APP_CMD 55 /* ac [31:16] RCA R1 */
85 #define MMC_GEN_CMD 56 /* adtc [0] RD/WR R1 */
105 MMC status in R1, for native mode (SPI bits are different)
156 * MMC/SD in SPI mode reports R1 status always, and R2 for SEND_STATUS
157 * R1 is the low order byte; R2 is the next highest byte, when present.
166 /* R1 bit 7 is always zero */
H A Dcore.h62 * Commands return R1, with maybe more info. Zero is an error type;
/linux-4.4.14/arch/blackfin/kernel/
H A Dfixed_code.S36 * R1: value to store
41 [P0] = R1;
49 * R1: compare value
57 CC = R0 == R1;
70 * R1: previous contents of the memory address.
73 R1 = [P0]; define
74 R0 = R1 + R0;
85 * R1: previous contents of the memory address.
88 R1 = [P0]; define
89 R0 = R1 - R0;
100 * R1: previous contents of the memory address.
103 R1 = [P0]; define
104 R0 = R1 | R0;
115 * R1: previous contents of the memory address.
118 R1 = [P0]; define
119 R0 = R1 & R0;
130 * R1: previous contents of the memory address.
133 R1 = [P0]; define
134 R0 = R1 ^ R0;
H A Dpseudodbg.c13 "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7",
H A Dtrace.c959 pr_notice(" R0 : %08lx R1 : %08lx R2 : %08lx R3 : %08lx\n", show_regs()
/linux-4.4.14/arch/s390/include/uapi/asm/
H A Dswab.h48 " icm %0,8,%O1+3(%R1)\n" __arch_swab32p()
49 " icm %0,4,%O1+2(%R1)\n" __arch_swab32p()
50 " icm %0,2,%O1+1(%R1)\n" __arch_swab32p()
78 " icm %0,2,%O1+1(%R1)\n" __arch_swab16p()
/linux-4.4.14/arch/blackfin/mach-common/
H A Ddpmc_modes.S21 R1 = W[P0](z); define
22 BITSET (R1, 3);
23 W[P0] = R1.L;
33 R1 = IWR_DISABLE_ALL; define
72 R1 = IWR_DISABLE_ALL; define
96 P4 = R1;
100 R1 = IWR_DISABLE_ALL; define
126 R1 = 0x6; define
127 R1 <<= 16;
129 R1 = R1|R2; define
131 R2 = DEPOSIT(R7, R1);
140 R1 = P4; define
155 R1 = IWR_DISABLE_ALL; define
262 [P0 + (SIC_IWR1 - SYSMMR_BASE)] = R1;
299 R1.H = 0xDEAD; /* Hibernate Magic */
300 R1.L = 0xBEEF;
303 [P0++] = R1; /* Store Hibernate Magic */
H A Dcache.S27 * R1 = end address
37 R1 += -1;
38 R1 = R1 & R2; define
39 R1 += L1_CACHE_BYTES;
42 R2 = R1 - R0;
H A Dinterrupt.S35 * R0 contains the interrupt number, while R1 may contain the value of IPEND,
82 [--sp] = r1; /* IPEND - R1 may or may not be set up before jumping here. */
169 R1 = [P0]; define
170 CC = BITTST(R1, EVT_IVHW_P);
173 R1 = EVT_IVHW_P; define
174 [P0] = R1;
176 CC = R1 == R2;
188 R1.L = LO(VEC_HWERR);
189 R1.H = HI(VEC_HWERR);
190 R0 = R0 | R1;
H A Dentry.S92 /* We must load R1 here, _before_ DEBUG_HWTRACE_SAVE, since that
95 R1 = SP; define
/linux-4.4.14/lib/
H A Dtest_bpf.c46 #define R1 BPF_REG_1 macro
398 insn[i++] = BPF_MOV64_REG(R6, R1); bpf_fill_ld_abs_vlan_push_pop()
404 insn[i++] = BPF_MOV64_REG(R1, R6); bpf_fill_ld_abs_vlan_push_pop()
417 insn[i++] = BPF_MOV64_REG(R1, R6); bpf_fill_ld_abs_vlan_push_pop()
1056 BPF_ALU64_IMM(BPF_MOV, R1, 1),
1057 BPF_ALU64_IMM(BPF_ADD, R1, 2),
1059 BPF_ALU64_REG(BPF_SUB, R1, R2),
1060 BPF_ALU64_IMM(BPF_ADD, R1, -1),
1061 BPF_ALU64_IMM(BPF_MUL, R1, 3),
1062 BPF_ALU64_REG(BPF_MOV, R0, R1),
1073 BPF_ALU64_IMM(BPF_MOV, R1, -1),
1075 BPF_ALU64_REG(BPF_MUL, R1, R2),
1076 BPF_JMP_IMM(BPF_JEQ, R1, 0xfffffffd, 1),
1089 BPF_ALU32_IMM(BPF_MOV, R1, -1),
1091 BPF_ALU64_REG(BPF_MUL, R1, R2),
1092 BPF_ALU64_IMM(BPF_RSH, R1, 8),
1093 BPF_JMP_IMM(BPF_JEQ, R1, 0x2ffffff, 1),
1106 BPF_ALU64_IMM(BPF_MOV, R1, -1),
1108 BPF_ALU32_REG(BPF_MUL, R1, R2),
1109 BPF_ALU64_IMM(BPF_RSH, R1, 8),
1110 BPF_JMP_IMM(BPF_JEQ, R1, 0xffffff, 1),
1127 BPF_ALU64_IMM(BPF_MOV, R1, 1),
1137 BPF_ALU64_IMM(BPF_ADD, R1, 20),
1147 BPF_ALU64_IMM(BPF_SUB, R1, 10),
1157 BPF_ALU64_REG(BPF_ADD, R0, R1),
1168 BPF_ALU64_REG(BPF_ADD, R1, R0),
1169 BPF_ALU64_REG(BPF_ADD, R1, R1),
1170 BPF_ALU64_REG(BPF_ADD, R1, R2),
1171 BPF_ALU64_REG(BPF_ADD, R1, R3),
1172 BPF_ALU64_REG(BPF_ADD, R1, R4),
1173 BPF_ALU64_REG(BPF_ADD, R1, R5),
1174 BPF_ALU64_REG(BPF_ADD, R1, R6),
1175 BPF_ALU64_REG(BPF_ADD, R1, R7),
1176 BPF_ALU64_REG(BPF_ADD, R1, R8),
1177 BPF_ALU64_REG(BPF_ADD, R1, R9), /* R1 == 456 */
1178 BPF_JMP_IMM(BPF_JEQ, R1, 456, 1),
1181 BPF_ALU64_REG(BPF_ADD, R2, R1),
1193 BPF_ALU64_REG(BPF_ADD, R3, R1),
1205 BPF_ALU64_REG(BPF_ADD, R4, R1),
1217 BPF_ALU64_REG(BPF_ADD, R5, R1),
1229 BPF_ALU64_REG(BPF_ADD, R6, R1),
1241 BPF_ALU64_REG(BPF_ADD, R7, R1),
1253 BPF_ALU64_REG(BPF_ADD, R8, R1),
1265 BPF_ALU64_REG(BPF_ADD, R9, R1),
1285 BPF_ALU32_IMM(BPF_MOV, R1, 1),
1294 BPF_ALU64_IMM(BPF_ADD, R1, 10),
1303 BPF_ALU32_REG(BPF_ADD, R0, R1),
1314 BPF_ALU32_REG(BPF_ADD, R1, R0),
1315 BPF_ALU32_REG(BPF_ADD, R1, R1),
1316 BPF_ALU32_REG(BPF_ADD, R1, R2),
1317 BPF_ALU32_REG(BPF_ADD, R1, R3),
1318 BPF_ALU32_REG(BPF_ADD, R1, R4),
1319 BPF_ALU32_REG(BPF_ADD, R1, R5),
1320 BPF_ALU32_REG(BPF_ADD, R1, R6),
1321 BPF_ALU32_REG(BPF_ADD, R1, R7),
1322 BPF_ALU32_REG(BPF_ADD, R1, R8),
1323 BPF_ALU32_REG(BPF_ADD, R1, R9), /* R1 == 456 */
1324 BPF_JMP_IMM(BPF_JEQ, R1, 456, 1),
1327 BPF_ALU32_REG(BPF_ADD, R2, R1),
1339 BPF_ALU32_REG(BPF_ADD, R3, R1),
1351 BPF_ALU32_REG(BPF_ADD, R4, R1),
1363 BPF_ALU32_REG(BPF_ADD, R5, R1),
1375 BPF_ALU32_REG(BPF_ADD, R6, R1),
1387 BPF_ALU32_REG(BPF_ADD, R7, R1),
1399 BPF_ALU32_REG(BPF_ADD, R8, R1),
1411 BPF_ALU32_REG(BPF_ADD, R9, R1),
1431 BPF_ALU64_IMM(BPF_MOV, R1, 1),
1441 BPF_ALU64_REG(BPF_SUB, R0, R1),
1453 BPF_ALU64_REG(BPF_SUB, R1, R0),
1454 BPF_ALU64_REG(BPF_SUB, R1, R2),
1455 BPF_ALU64_REG(BPF_SUB, R1, R3),
1456 BPF_ALU64_REG(BPF_SUB, R1, R4),
1457 BPF_ALU64_REG(BPF_SUB, R1, R5),
1458 BPF_ALU64_REG(BPF_SUB, R1, R6),
1459 BPF_ALU64_REG(BPF_SUB, R1, R7),
1460 BPF_ALU64_REG(BPF_SUB, R1, R8),
1461 BPF_ALU64_REG(BPF_SUB, R1, R9),
1462 BPF_ALU64_IMM(BPF_SUB, R1, 10),
1464 BPF_ALU64_REG(BPF_SUB, R2, R1),
1474 BPF_ALU64_REG(BPF_SUB, R3, R1),
1484 BPF_ALU64_REG(BPF_SUB, R4, R1),
1494 BPF_ALU64_REG(BPF_SUB, R5, R1),
1504 BPF_ALU64_REG(BPF_SUB, R6, R1),
1514 BPF_ALU64_REG(BPF_SUB, R7, R1),
1524 BPF_ALU64_REG(BPF_SUB, R8, R1),
1534 BPF_ALU64_REG(BPF_SUB, R9, R1),
1545 BPF_ALU64_REG(BPF_SUB, R0, R1),
1564 BPF_ALU64_REG(BPF_XOR, R1, R1),
1565 BPF_JMP_REG(BPF_JEQ, R0, R1, 1),
1568 BPF_ALU64_IMM(BPF_MOV, R1, -1),
1569 BPF_ALU64_REG(BPF_SUB, R1, R1),
1571 BPF_JMP_REG(BPF_JEQ, R1, R2, 1),
1576 BPF_ALU64_IMM(BPF_MOV, R1, -1),
1594 BPF_ALU64_IMM(BPF_MOV, R1, 1),
1614 BPF_ALU64_REG(BPF_SUB, R1, R1),
1630 BPF_ALU64_IMM(BPF_MOV, R1, 1),
1640 BPF_ALU64_REG(BPF_MUL, R0, R1),
1652 BPF_ALU64_REG(BPF_MUL, R1, R0),
1653 BPF_ALU64_REG(BPF_MUL, R1, R2),
1654 BPF_ALU64_REG(BPF_MUL, R1, R3),
1655 BPF_ALU64_REG(BPF_MUL, R1, R4),
1656 BPF_ALU64_REG(BPF_MUL, R1, R5),
1657 BPF_ALU64_REG(BPF_MUL, R1, R6),
1658 BPF_ALU64_REG(BPF_MUL, R1, R7),
1659 BPF_ALU64_REG(BPF_MUL, R1, R8),
1660 BPF_ALU64_REG(BPF_MUL, R1, R9),
1661 BPF_ALU64_IMM(BPF_MUL, R1, 10),
1662 BPF_ALU64_REG(BPF_MOV, R2, R1),
1666 BPF_ALU64_IMM(BPF_LSH, R1, 32),
1667 BPF_ALU64_IMM(BPF_ARSH, R1, 32),
1668 BPF_JMP_IMM(BPF_JEQ, R1, 0xebb90000, 1),
1671 BPF_ALU64_REG(BPF_MUL, R2, R1),
1712 BPF_MOV64_IMM(R1, 1),
1713 BPF_ALU32_REG(BPF_RSH, R0, R1),
1749 BPF_ALU64_REG(BPF_MOV, R6, R1),
1766 BPF_ALU64_REG(BPF_MOV, R6, R1),
2105 BPF_LD_IMM64(R1, 0x567800001234LL),
2106 BPF_MOV64_REG(R2, R1),
2127 BPF_MOV64_REG(R6, R1),
2171 BPF_ALU32_IMM(BPF_MOV, R1, 2),
2172 BPF_ALU32_REG(BPF_MOV, R0, R1),
2182 BPF_ALU32_IMM(BPF_MOV, R1, 4294967295U),
2183 BPF_ALU32_REG(BPF_MOV, R0, R1),
2193 BPF_ALU32_IMM(BPF_MOV, R1, 2),
2194 BPF_ALU64_REG(BPF_MOV, R0, R1),
2204 BPF_ALU32_IMM(BPF_MOV, R1, 4294967295U),
2205 BPF_ALU64_REG(BPF_MOV, R0, R1),
2306 BPF_ALU32_IMM(BPF_MOV, R1, 2),
2307 BPF_ALU32_REG(BPF_ADD, R0, R1),
2318 BPF_ALU32_IMM(BPF_MOV, R1, 4294967294U),
2319 BPF_ALU32_REG(BPF_ADD, R0, R1),
2330 BPF_ALU32_IMM(BPF_MOV, R1, 2),
2331 BPF_ALU64_REG(BPF_ADD, R0, R1),
2342 BPF_ALU32_IMM(BPF_MOV, R1, 4294967294U),
2343 BPF_ALU64_REG(BPF_ADD, R0, R1),
2481 BPF_ALU32_IMM(BPF_MOV, R1, 1),
2482 BPF_ALU32_REG(BPF_SUB, R0, R1),
2493 BPF_ALU32_IMM(BPF_MOV, R1, 4294967294U),
2494 BPF_ALU32_REG(BPF_SUB, R0, R1),
2505 BPF_ALU32_IMM(BPF_MOV, R1, 1),
2506 BPF_ALU64_REG(BPF_SUB, R0, R1),
2517 BPF_ALU32_IMM(BPF_MOV, R1, 4294967294U),
2518 BPF_ALU64_REG(BPF_SUB, R0, R1),
2608 BPF_ALU32_IMM(BPF_MOV, R1, 3),
2609 BPF_ALU32_REG(BPF_MUL, R0, R1),
2620 BPF_ALU32_IMM(BPF_MOV, R1, 0x7FFFFFF8),
2621 BPF_ALU32_REG(BPF_MUL, R0, R1),
2632 BPF_ALU32_IMM(BPF_MOV, R1, -1),
2633 BPF_ALU32_REG(BPF_MUL, R0, R1),
2644 BPF_ALU32_IMM(BPF_MOV, R1, 3),
2645 BPF_ALU64_REG(BPF_MUL, R0, R1),
2656 BPF_ALU32_IMM(BPF_MOV, R1, 2147483647),
2657 BPF_ALU64_REG(BPF_MUL, R0, R1),
2779 BPF_ALU32_IMM(BPF_MOV, R1, 2),
2780 BPF_ALU32_REG(BPF_DIV, R0, R1),
2791 BPF_ALU32_IMM(BPF_MOV, R1, 4294967295U),
2792 BPF_ALU32_REG(BPF_DIV, R0, R1),
2803 BPF_ALU32_IMM(BPF_MOV, R1, 2),
2804 BPF_ALU64_REG(BPF_DIV, R0, R1),
2815 BPF_ALU32_IMM(BPF_MOV, R1, 2147483647),
2816 BPF_ALU64_REG(BPF_DIV, R0, R1),
2944 BPF_ALU32_IMM(BPF_MOV, R1, 2),
2945 BPF_ALU32_REG(BPF_MOD, R0, R1),
2956 BPF_ALU32_IMM(BPF_MOV, R1, 4294967293U),
2957 BPF_ALU32_REG(BPF_MOD, R0, R1),
2968 BPF_ALU32_IMM(BPF_MOV, R1, 2),
2969 BPF_ALU64_REG(BPF_MOD, R0, R1),
2980 BPF_ALU32_IMM(BPF_MOV, R1, 2147483645),
2981 BPF_ALU64_REG(BPF_MOD, R0, R1),
3060 BPF_ALU32_IMM(BPF_MOV, R1, 2),
3061 BPF_ALU32_REG(BPF_AND, R0, R1),
3072 BPF_ALU32_IMM(BPF_MOV, R1, 0xffffffff),
3073 BPF_ALU32_REG(BPF_AND, R0, R1),
3084 BPF_ALU32_IMM(BPF_MOV, R1, 2),
3085 BPF_ALU64_REG(BPF_AND, R0, R1),
3096 BPF_ALU32_IMM(BPF_MOV, R1, 0xffffffff),
3097 BPF_ALU64_REG(BPF_AND, R0, R1),
3202 BPF_ALU32_IMM(BPF_MOV, R1, 2),
3203 BPF_ALU32_REG(BPF_OR, R0, R1),
3214 BPF_ALU32_IMM(BPF_MOV, R1, 0xffffffff),
3215 BPF_ALU32_REG(BPF_OR, R0, R1),
3226 BPF_ALU32_IMM(BPF_MOV, R1, 2),
3227 BPF_ALU64_REG(BPF_OR, R0, R1),
3238 BPF_ALU32_IMM(BPF_MOV, R1, 0xffffffff),
3239 BPF_ALU64_REG(BPF_OR, R0, R1),
3344 BPF_ALU32_IMM(BPF_MOV, R1, 6),
3345 BPF_ALU32_REG(BPF_XOR, R0, R1),
3356 BPF_ALU32_IMM(BPF_MOV, R1, 0xffffffff),
3357 BPF_ALU32_REG(BPF_XOR, R0, R1),
3368 BPF_ALU32_IMM(BPF_MOV, R1, 6),
3369 BPF_ALU64_REG(BPF_XOR, R0, R1),
3380 BPF_ALU32_IMM(BPF_MOV, R1, 0xffffffff),
3381 BPF_ALU64_REG(BPF_XOR, R0, R1),
3486 BPF_ALU32_IMM(BPF_MOV, R1, 1),
3487 BPF_ALU32_REG(BPF_LSH, R0, R1),
3498 BPF_ALU32_IMM(BPF_MOV, R1, 31),
3499 BPF_ALU32_REG(BPF_LSH, R0, R1),
3510 BPF_ALU32_IMM(BPF_MOV, R1, 1),
3511 BPF_ALU64_REG(BPF_LSH, R0, R1),
3522 BPF_ALU32_IMM(BPF_MOV, R1, 31),
3523 BPF_ALU64_REG(BPF_LSH, R0, R1),
3580 BPF_ALU32_IMM(BPF_MOV, R1, 1),
3581 BPF_ALU32_REG(BPF_RSH, R0, R1),
3592 BPF_ALU32_IMM(BPF_MOV, R1, 31),
3593 BPF_ALU32_REG(BPF_RSH, R0, R1),
3604 BPF_ALU32_IMM(BPF_MOV, R1, 1),
3605 BPF_ALU64_REG(BPF_RSH, R0, R1),
3616 BPF_ALU32_IMM(BPF_MOV, R1, 31),
3617 BPF_ALU64_REG(BPF_RSH, R0, R1),
3674 BPF_ALU32_IMM(BPF_MOV, R1, 40),
3675 BPF_ALU64_REG(BPF_ARSH, R0, R1),
3756 BPF_ALU64_REG(BPF_MOV, R1, R0),
3757 BPF_ALU64_IMM(BPF_RSH, R1, 32),
3758 BPF_ALU32_REG(BPF_ADD, R0, R1), /* R1 = 0 */
3793 BPF_ALU64_REG(BPF_MOV, R1, R0),
3794 BPF_ALU64_IMM(BPF_RSH, R1, 32),
3795 BPF_ALU32_REG(BPF_ADD, R0, R1), /* R1 = 0 */
3842 BPF_LD_IMM64(R1, 0xffLL),
3843 BPF_STX_MEM(BPF_B, R10, R1, -40),
3879 BPF_LD_IMM64(R1, 0xffffLL),
3880 BPF_STX_MEM(BPF_H, R10, R1, -40),
3916 BPF_LD_IMM64(R1, 0xffffffffLL),
3917 BPF_STX_MEM(BPF_W, R10, R1, -40),
3970 BPF_LD_IMM64(R1, 0xffffffffffffffffLL),
3971 BPF_STX_MEM(BPF_W, R10, R1, -40),
4037 BPF_LD_IMM64(R1, 0xffffffffffffffffLL),
4038 BPF_JMP_IMM(BPF_JSGT, R1, -2, 1),
4051 BPF_LD_IMM64(R1, 0xffffffffffffffffLL),
4052 BPF_JMP_IMM(BPF_JSGT, R1, -1, 1),
4066 BPF_LD_IMM64(R1, 0xffffffffffffffffLL),
4067 BPF_JMP_IMM(BPF_JSGE, R1, -2, 1),
4080 BPF_LD_IMM64(R1, 0xffffffffffffffffLL),
4081 BPF_JMP_IMM(BPF_JSGE, R1, -1, 1),
4095 BPF_LD_IMM64(R1, 3),
4096 BPF_JMP_IMM(BPF_JGT, R1, 2, 1),
4110 BPF_LD_IMM64(R1, 3),
4111 BPF_JMP_IMM(BPF_JGE, R1, 2, 1),
4128 BPF_LD_IMM64(R1, 3), /* note: this takes 2 insns */
4129 BPF_JMP_IMM(BPF_JGT, R1, 2, -6), /* goto out */
4140 BPF_LD_IMM64(R1, 3),
4141 BPF_JMP_IMM(BPF_JGE, R1, 3, 1),
4155 BPF_LD_IMM64(R1, 3),
4156 BPF_JMP_IMM(BPF_JNE, R1, 2, 1),
4170 BPF_LD_IMM64(R1, 3),
4171 BPF_JMP_IMM(BPF_JEQ, R1, 3, 1),
4185 BPF_LD_IMM64(R1, 3),
4186 BPF_JMP_IMM(BPF_JNE, R1, 2, 1),
4199 BPF_LD_IMM64(R1, 3),
4200 BPF_JMP_IMM(BPF_JNE, R1, 0xffffffff, 1),
4214 BPF_LD_IMM64(R1, -1),
4216 BPF_JMP_REG(BPF_JSGT, R1, R2, 1),
4229 BPF_LD_IMM64(R1, -1),
4231 BPF_JMP_REG(BPF_JSGT, R1, R2, 1),
4245 BPF_LD_IMM64(R1, -1),
4247 BPF_JMP_REG(BPF_JSGE, R1, R2, 1),
4260 BPF_LD_IMM64(R1, -1),
4262 BPF_JMP_REG(BPF_JSGE, R1, R2, 1),
4276 BPF_LD_IMM64(R1, 3),
4278 BPF_JMP_REG(BPF_JGT, R1, R2, 1),
4292 BPF_LD_IMM64(R1, 3),
4294 BPF_JMP_REG(BPF_JGE, R1, R2, 1),
4307 BPF_LD_IMM64(R1, 3),
4309 BPF_JMP_REG(BPF_JGE, R1, R2, 1),
4323 BPF_LD_IMM64(R1, 3),
4325 BPF_JMP_REG(BPF_JNE, R1, R2, 1),
4339 BPF_LD_IMM64(R1, 3),
4341 BPF_JMP_REG(BPF_JEQ, R1, R2, 1),
4355 BPF_LD_IMM64(R1, 3),
4357 BPF_JMP_REG(BPF_JNE, R1, R2, 1),
4370 BPF_LD_IMM64(R1, 3),
4372 BPF_JMP_REG(BPF_JNE, R1, R2, 1),
/linux-4.4.14/arch/hexagon/kernel/
H A Dvm_entry.S206 * of pt_regs in HVM mode. Save R0/R1, set handler's address in R1.
213 * Need to save off R0, R1, R2, R3 immediately.
220 memd(R29 + #(_PT_R0100 + -_PT_REGS_SIZE)) = R1:0; \
227 memd(R29 + #_PT_ER_VMEL) = R1:0; \
229 R1.L = #LO(CHandler); \
233 R1.H = #HI(CHandler); \
243 memd(R29 + #(_PT_R0100 + -_PT_REGS_SIZE)) = R1:0; \
252 R1:0 = G1:0; \
254 memd(R29 + #_PT_ER_VMEL) = R1:0; \
255 R1 = # ## #(CHandler); \ define
315 R1 = memw(THREADINFO_REG + #_THREAD_INFO_FLAGS); define
334 R1:0 = memd(R29 + #_PT_ER_VMEL);
340 G1:0 = R1:0;
347 R1:0 = memd(R29 + #_PT_R0100);
H A Dvm_switch.S71 R29 = memw(R1 + #(_TASK_STRUCT_THREAD + _THREAD_STRUCT_SWITCH_SP));
88 THREADINFO_REG = memw(R1 + #_TASK_THREAD_INFO);
H A Dhead.S109 R1.H = #HI(PAGE_OFFSET >> (22 - 2))
110 R1.L = #LO(PAGE_OFFSET >> (22 - 2))
132 * Note that in this version, R1 and R2 get "clobbered"; see
167 memw(R1 ++ #4) = R0
/linux-4.4.14/arch/blackfin/include/asm/
H A Dentry.h32 R1 = [P0];
113 R1 = ASTAT; \
123 ASTAT = R1; \
130 1: ASTAT = R1; \
143 R1 = ASTAT; \
153 ASTAT = R1; \
159 1: ASTAT = R1; \
H A Ddpmc.h19 #define PM_REG6 R1
/linux-4.4.14/arch/blackfin/mach-bf609/
H A Ddpm.S134 R1.H = 0xDEAD;
135 R1.L = 0xBEEF;
138 [P0++] = R1;
/linux-4.4.14/arch/powerpc/kvm/
H A Dbook3s_32_sr.S31 * R1 = host R1
87 * R1 = host R1
H A Dbook3s_64_slb.S36 * R1 = host R1
102 * R1 = host R1
H A Dbook3s_segment.S60 * R1 = host R1
81 /* Save R1/R2 in the PACA (64-bit) or shadow_vcpu (32-bit) */
201 /* Restore R1/R2 so we can handle faults */
358 * R1 = host R1
H A Dbook3s_hv_interrupts.S144 * R1 = host R1
H A Dbook3s_interrupts.S150 * R1 = host R1
H A Dbooke_interrupts.S219 stw r1, VCPU_GPR(R1)(r4)
449 lwz r1, VCPU_GPR(R1)(r4)
H A Dbookehv_interrupts.S73 PPC_STL r1, VCPU_GPR(R1)(r4)
650 PPC_LL r1, VCPU_GPR(R1)(r4)
H A Dbook3s_hv_rmhandlers.S486 * R1 = host R1
494 /* Save R1 in the PACA */
1043 ld r1, VCPU_GPR(R1)(r4)
1127 std r1, VCPU_GPR(R1)(r9)
1152 /* Restore R1/R2 so we can handle faults */
H A Dbooke.c1371 /* Initial guest state: 16MB mapping 0 -> 0, PC = 0, MSR = 0, R1 = 16MB */ kvm_arch_vcpu_setup()
/linux-4.4.14/sound/pci/oxygen/
H A Dwm8785.h27 /* R1 */
/linux-4.4.14/tools/perf/arch/arm/util/
H A Dunwind-libdw.c18 dwarf_regs[1] = REG(R1); libdw__arch_set_initial_registers()
/linux-4.4.14/drivers/net/wan/
H A Dz85230.c278 read_zsreg(c, R1); z8530_flush_fifo()
279 read_zsreg(c, R1); z8530_flush_fifo()
280 read_zsreg(c, R1); z8530_flush_fifo()
281 read_zsreg(c, R1); z8530_flush_fifo()
284 read_zsreg(c, R1); z8530_flush_fifo()
285 read_zsreg(c, R1); z8530_flush_fifo()
286 read_zsreg(c, R1); z8530_flush_fifo()
287 read_zsreg(c, R1); z8530_flush_fifo()
345 stat=read_zsreg(c, R1); z8530_rx()
515 status=read_zsreg(chan, R1); z8530_dma_rx()
637 stat=read_zsreg(c, R1); z8530_rx_clear()
808 c->regs[R1]|=TxINT_ENAB; z8530_sync_open()
809 write_zsreg(c, R1, c->regs[R1]); z8530_sync_open()
914 c->regs[R1]&= ~TxINT_ENAB; z8530_sync_dma_open()
915 write_zsreg(c, R1, c->regs[R1]); z8530_sync_dma_open()
921 c->regs[R1]|= WT_FN_RDYFN; z8530_sync_dma_open()
922 c->regs[R1]|= WT_RDY_RT; z8530_sync_dma_open()
923 c->regs[R1]|= INT_ERR_Rx; z8530_sync_dma_open()
924 c->regs[R1]&= ~TxINT_ENAB; z8530_sync_dma_open()
925 write_zsreg(c, R1, c->regs[R1]); z8530_sync_dma_open()
926 c->regs[R1]|= WT_RDY_ENAB; z8530_sync_dma_open()
927 write_zsreg(c, R1, c->regs[R1]); z8530_sync_dma_open()
1013 c->regs[R1]&= ~WT_RDY_ENAB; z8530_sync_dma_close()
1014 write_zsreg(c, R1, c->regs[R1]); z8530_sync_dma_close()
1015 c->regs[R1]&= ~(WT_RDY_RT|WT_FN_RDYFN|INT_ERR_Rx); z8530_sync_dma_close()
1016 c->regs[R1]|= INT_ALL_Rx; z8530_sync_dma_close()
1017 write_zsreg(c, R1, c->regs[R1]); z8530_sync_dma_close()
1110 c->regs[R1]&= ~TxINT_ENAB; z8530_sync_txdma_open()
1111 write_zsreg(c, R1, c->regs[R1]); z8530_sync_txdma_open()
1182 c->regs[R1]&= ~WT_RDY_ENAB; z8530_sync_txdma_close()
1183 write_zsreg(c, R1, c->regs[R1]); z8530_sync_txdma_close()
1184 c->regs[R1]&= ~(WT_RDY_RT|WT_FN_RDYFN|INT_ERR_Rx); z8530_sync_txdma_close()
1185 c->regs[R1]|= INT_ALL_Rx; z8530_sync_txdma_close()
1186 write_zsreg(c, R1, c->regs[R1]); z8530_sync_txdma_close()
H A Dz85230.h26 #define R1 1 macro
/linux-4.4.14/tools/perf/arch/arm/tests/
H A Dregs_load.S4 #define R1 0x08 define
41 str r1, [r0, #R1]
/linux-4.4.14/arch/sparc/net/
H A Dbpf_jit_comp.c298 #define emit_cmp(R1, R2) \
299 *prog++ = (SUBCC | RS1(R1) | RS2(R2) | RD(G0))
301 #define emit_cmpi(R1, IMM) \
302 *prog++ = (SUBCC | IMMED | RS1(R1) | S13(IMM) | RD(G0));
304 #define emit_btst(R1, R2) \
305 *prog++ = (ANDCC | RS1(R1) | RS2(R2) | RD(G0))
307 #define emit_btsti(R1, IMM) \
308 *prog++ = (ANDCC | IMMED | RS1(R1) | S13(IMM) | RD(G0));
310 #define emit_sub(R1, R2, R3) \
311 *prog++ = (SUB | RS1(R1) | RS2(R2) | RD(R3))
313 #define emit_subi(R1, IMM, R3) \
314 *prog++ = (SUB | IMMED | RS1(R1) | S13(IMM) | RD(R3))
316 #define emit_add(R1, R2, R3) \
317 *prog++ = (ADD | RS1(R1) | RS2(R2) | RD(R3))
319 #define emit_addi(R1, IMM, R3) \
320 *prog++ = (ADD | IMMED | RS1(R1) | S13(IMM) | RD(R3))
322 #define emit_and(R1, R2, R3) \
323 *prog++ = (AND | RS1(R1) | RS2(R2) | RD(R3))
325 #define emit_andi(R1, IMM, R3) \
326 *prog++ = (AND | IMMED | RS1(R1) | S13(IMM) | RD(R3))
/linux-4.4.14/drivers/media/usb/dvb-usb/
H A Ddigitv.h23 * <cmdbyte> VV <len> R0 R1 R2 R3
/linux-4.4.14/arch/sh/include/asm/
H A Duaccess_32.h130 "mov.l %R1,%2\n\t" \
153 "mov.l %R1,%T2\n\t" \
H A Dsyscall_32.h61 /* Argument pattern is: R4, R5, R6, R7, R0, R1 */ syscall_get_arguments()
/linux-4.4.14/sound/soc/codecs/
H A Drt5651.c456 SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_STO_DAC_MIXER,
461 SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_STO_DAC_MIXER,
479 SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_DD_MIXER,
534 SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_OUT_R3_MIXER,
548 SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_LOUT_MIXER,
637 SOC_DAPM_ENUM("Stereo1 ADC R1 source", rt5651_stereo1_adc1_enum);
935 SND_SOC_DAPM_INPUT("DMIC R1"),
981 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
987 SND_SOC_DAPM_MUX("Stereo2 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1075 SND_SOC_DAPM_DAC("DAC R1", NULL, SND_SOC_NOPM, 0, 0),
1078 SND_SOC_DAPM_SUPPLY("DAC R1 Power", RT5651_PWR_DIG1,
1177 {"DMIC R1", NULL, "DMIC CLK"},
1184 {"Stereo1 ADC R1 Mux", "ADC", "ADC R"},
1185 {"Stereo1 ADC R1 Mux", "DD MIX", "DD MIXR"},
1186 {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"},
1194 {"Stereo2 ADC R1 Mux", "DD MIXR", "DD MIXR"},
1195 {"Stereo2 ADC R1 Mux", "ADCR", "ADC R"},
1196 {"Stereo2 ADC R2 Mux", "DMIC R", "DMIC R1"},
1205 {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
1215 {"Stereo2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC R1 Mux"},
1264 {"Stereo DAC MIXL", "DAC R1 Switch", "DAC MIXR"},
1267 {"Stereo DAC MIXR", "DAC R1 Switch", "Audio DSP"},
1281 {"DAC R1", NULL, "Stereo DAC MIXR"},
1282 {"DAC R1", NULL, "PLL1", is_sysclk_from_pll},
1283 {"DAC R1", NULL, "DAC R1 Power"},
1290 {"DD MIXR", "DAC R1 Switch", "DAC MIXR"},
1305 {"OUT MIXR", "DAC R1 Switch", "DAC R1"},
1315 {"HPOR MIX", "HPO MIX DAC1 Switch", "DAC R1"},
1320 {"LOUT MIX", "DAC R1 Switch", "DAC R1"},
H A Drt5640.c544 SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_STO_DAC_MIXER,
560 SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_STO_DAC_MIXER,
576 SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_MONO_DAC_MIXER,
592 SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_DIG_MIXER,
648 SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_SPK_R_MIXER,
688 SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_OUT_R3_MIXER,
712 SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_OUT_R3_MIXER,
717 SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_SPO_L_MIXER,
730 SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_SPO_R_MIXER,
757 SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_LOUT_MIXER,
847 "DMIC R1", "DMIC R2", "Mono DAC MIXR"
1078 SND_SOC_DAPM_PGA("DMIC R1", SND_SOC_NOPM, 0, 0, NULL, 0),
1117 SND_SOC_DAPM_MUX("Stereo ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1123 SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1196 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5640_PWR_DIG1,
1327 {"DMIC R1", NULL, "DMIC1"},
1360 {"DMIC R1", NULL, "DMIC CLK"},
1361 {"DMIC R1", NULL, "DMIC1 Power"},
1373 {"Stereo ADC R1 Mux", "ADC", "ADC R"},
1374 {"Stereo ADC R1 Mux", "DIG MIX", "DIG MIXR"},
1375 {"Stereo ADC R2 Mux", "DMIC1", "DMIC R1"},
1385 {"Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR"},
1386 {"Mono ADC R1 Mux", "ADCR", "ADC R"},
1387 {"Mono ADC R2 Mux", "DMIC R1", "DMIC R1"},
1396 {"Stereo ADC MIXR", "ADC1 Switch", "Stereo ADC R1 Mux"},
1406 {"Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux"},
1468 {"Stereo DAC MIXR", "DAC R1 Switch", "DAC MIXR"},
1471 {"Mono DAC MIXR", "DAC R1 Switch", "DAC MIXR"},
1474 {"DIG MIXR", "DAC R1 Switch", "DAC MIXR"},
1478 {"DAC R1", NULL, "Stereo DAC MIXR"},
1479 {"DAC R1", NULL, "PLL1", is_sys_clk_from_pll},
1487 {"SPK MIXR", "DAC R1 Switch", "DAC R1"},
1499 {"OUT MIXR", "DAC R1 Switch", "DAC R1"},
1508 {"SPOL MIX", "DAC R1 Switch", "DAC R1"},
1513 {"SPOR MIX", "DAC R1 Switch", "DAC R1"},
1520 {"HPO MIX R", "HPO MIX DAC1 Switch", "DAC R1"},
1525 {"LOUT MIX", "DAC R1 Switch", "DAC R1"},
H A Drt5645.c889 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER,
894 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER,
912 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_MONO_DAC_MIXER,
977 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPK_R_MIXER,
1005 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_OUT_R1_MIXER,
1010 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER,
1021 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER,
1059 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_LOUT_MIXER,
1807 SND_SOC_DAPM_INPUT("DMIC R1"),
1860 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1870 SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1981 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R1_BIT,
2114 { "DMIC1", NULL, "DMIC R1" },
2147 {"DMIC R1", NULL, "DMIC CLK"},
2148 {"DMIC R1", NULL, "DMIC1 Power"},
2162 { "Mono DMIC R Mux", "DMIC1", "DMIC R1" },
2171 { "Stereo1 ADC R1 Mux", "ADC", "ADC R" },
2172 { "Stereo1 ADC R1 Mux", "DAC MIX", "DAC MIXR" },
2181 { "Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
2182 { "Mono ADC R1 Mux", "ADC", "ADC R" },
2188 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux" },
2204 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux" },
2267 { "Stereo DAC MIXL", "DAC R1 Switch", "DAC1 MIXR" },
2270 { "Stereo DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
2279 { "Mono DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
2292 { "DAC R1", NULL, "PLL1", is_sys_clk_from_pll },
2302 { "SPK MIXR", "DAC R1 Switch", "DAC R1" },
2313 { "OUT MIXR", "DAC R1 Switch", "DAC R1" },
2320 { "HPOVOL MIXR", "DAC1 Switch", "DAC R1" },
2329 { "DAC 1", NULL, "DAC R1" },
2340 { "SPOL MIX", "DAC R1 Switch", "DAC R1" },
2344 { "SPOR MIX", "DAC R1 Switch", "DAC R1" },
2348 { "LOUT MIX", "DAC R1 Switch", "DAC R1" },
2394 { "DAC R1", NULL, "A DAC1 R Mux" },
2475 { "DAC R1", NULL, "Stereo DAC MIXR" },
H A Drt5670.c919 SOC_DAPM_SINGLE("DAC R1 Switch", RT5670_STO_DAC_MIXER,
924 SOC_DAPM_SINGLE("DAC R1 Switch", RT5670_STO_DAC_MIXER,
942 SOC_DAPM_SINGLE("DAC R1 Switch", RT5670_DD_MIXER,
1005 SOC_DAPM_SINGLE("DAC R1 Switch", RT5670_OUT_R1_MIXER,
1033 SOC_DAPM_SINGLE("DAC R1 Switch", RT5670_LOUT_MIXER,
1049 SOC_DAPM_SINGLE("DAC R1 Switch", RT5670_HPO_MIXER,
1157 SOC_DAPM_ENUM("Stereo1 ADC R1 source", rt5670_stereo1_adc1_enum);
1166 SOC_DAPM_ENUM("Stereo2 ADC R1 source", rt5670_stereo2_adc1_enum);
1587 SND_SOC_DAPM_INPUT("DMIC R1"),
1649 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1659 SND_SOC_DAPM_MUX("Stereo2 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1671 SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1835 SND_SOC_DAPM_SUPPLY("DAC R1 Power", RT5670_PWR_DIG1,
1838 SND_SOC_DAPM_DAC("DAC R1", NULL, SND_SOC_NOPM, 0, 0),
1936 { "DMIC1", NULL, "DMIC R1" },
1968 { "DMIC R1", NULL, "DMIC CLK" },
1969 { "DMIC R1", NULL, "DMIC1 Power" },
1991 { "Mono DMIC R Mux", "DMIC1", "DMIC R1" },
2003 { "Stereo1 ADC R1 Mux", "ADC", "ADC 1_2" },
2004 { "Stereo1 ADC R1 Mux", "DAC MIX", "DAC MIXR" },
2013 { "Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
2014 { "Mono ADC R1 Mux", "ADC2", "ADC 2" },
2020 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux" },
2036 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux" },
2046 { "Stereo2 ADC R1 Mux", "ADC", "ADC 1_2" },
2047 { "Stereo2 ADC R1 Mux", "DAC MIX", "DAC MIXR" },
2053 { "Sto2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC R1 Mux" },
2207 { "Stereo DAC MIXL", "DAC R1 Switch", "DAC1 MIXR" },
2211 { "Stereo DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
2215 { "Stereo DAC MIXR", NULL, "DAC R1 Power" },
2221 { "Mono DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
2235 { "DAC R1", NULL, "DAC R1 Power" },
2236 { "DAC R1", NULL, "Stereo DAC MIXR" },
2248 { "OUT MIXR", "DAC R1 Switch", "DAC R1" },
2252 { "HPOVOL MIXR", "DAC1 Switch", "DAC R1" },
2258 { "DAC 1", NULL, "DAC R1" },
2265 { "LOUT MIX", "DAC R1 Switch", "DAC R1" },
H A Dwm8523.h46 * R1 (0x01) - REVISION
H A Dwm8741.h52 * R1 (0x01) - DACLMSB_ATTENUATION
H A Dtwl4030.c1226 SND_SOC_DAPM_MIXER("Digital R1 Playback Mixer",
1238 SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer",
1400 {"Digital R1 Playback Mixer", NULL, "DAC Right1"},
1418 {"Analog R1 Playback Mixer", NULL, "Digital R1 Playback Mixer"},
1428 {"Earpiece Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1438 {"PredriveR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1449 {"HeadsetR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1459 {"CarkitR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1471 {"HandsfreeR Mux", "AudioR1", "Analog R1 Playback Mixer"},
1564 {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
H A Dsta529.c99 { 1, 0xc8 }, /* R1 - FFX Configuration reg 1 */
H A Dwm8737.h55 * R1 (0x01) - Right PGA volume
H A Dwm9090.c38 { 1, 0x0006 }, /* R1 - Power Management (1) */
H A Dwm8737.c51 { 1, 0x00C3 }, /* R1 - Right PGA volume */
H A Dwm8741.c53 { 1, 0x0000 }, /* R1 - DACLMSB Attenuation */
H A Dwm8993.c45 { 1, 0x0000 }, /* R1 - Power Management (1) */
762 SOC_ENUM("DRC R1", drc_r1),
H A Dwm8961.c37 { 1, 0x009F }, /* R1 - Right Input volume */
H A Dwm8961.h116 * R1 (0x01) - Right Input volume
H A Dwm8990.h95 * R1 (0x01) - Power Management (1)
H A Dwm8991.h93 * R1 (0x01) - Power Management (1)
H A Dwm9090.h85 * R1 (0x01) - Power Management (1)
H A Dwm8903.h123 * R1 (0x01) - Revision Number
H A Dwm8983.c32 { 0x01, 0x0000 }, /* R1 - Power management 1 */
H A Dwm8983.h89 * R1 (0x01) - Power management 1
H A Dwm8985.c44 { 1, 0x0000 }, /* R1 - Power management 1 */
H A Dwm8985.h87 * R1 (0x01) - Power management 1
H A Dwm8990.c50 { 1, 0x0000 }, /* R1 - Power Management (1) */
H A Dwm8991.c40 { 1, 0x0000 }, /* R1 - Power Management (1) */
H A Drt5677.c2669 SND_SOC_DAPM_INPUT("DMIC R1"),
3208 { "DMIC1", NULL, "DMIC R1" },
3217 { "DMIC R1", NULL, "DMIC CLK" },
3226 { "DMIC R1", NULL, "DMIC1 power" },
H A Dwm8904.h146 * R1 (0x01) - Revision
/linux-4.4.14/samples/bpf/
H A Dtest_verifier.c106 .errstr_unpriv = "R1 pointer comparison",
120 .errstr_unpriv = "R1 pointer comparison",
231 .errstr_unpriv = "R1 pointer comparison",
296 /* spill R1(ctx) into stack */
314 /* spill R1(ctx) into stack */
317 /* mess up with R1 pointer on stack */
512 .errstr_unpriv = "R1 pointer comparison",
540 .errstr_unpriv = "R1 pointer comparison",
576 .errstr_unpriv = "R1 pointer comparison",
626 .errstr_unpriv = "R1 pointer comparison",
667 .errstr_unpriv = "R1 pointer comparison",
726 .errstr_unpriv = "R1 pointer comparison",
748 .errstr_unpriv = "R1 pointer comparison",
771 .errstr_unpriv = "R1 pointer comparison",
782 .errstr_unpriv = "R1 leaks addr",
793 .errstr_unpriv = "R1 leaks addr",
804 .errstr_unpriv = "R1 leaks addr",
837 .errstr_unpriv = "R1 leaks addr",
938 .errstr_unpriv = "R1 pointer arithmetic",
949 .errstr_unpriv = "R1 pointer arithmetic",
960 .errstr_unpriv = "R1 pointer arithmetic",
971 .errstr_unpriv = "R1 pointer comparison",
1075 .errstr_unpriv = "R1 leaks addr",
1132 .errstr_unpriv = "R1 pointer comparison",
/linux-4.4.14/drivers/misc/echo/
H A Dfir.h129 "R0.L = W[I0++] || R1.L = W[I1++];\n\t" dot_asm()
132 "A0 += R0.L * R1.L (IS) || R0.L = W[I0++] || R1.L = W[I1++];\n\t" dot_asm()
134 "A0 += R0.L*R1.L (IS);\n\t" dot_asm()
139 : "I0", "I1", "A1", "A0", "R0", "R1" dot_asm()
H A Decho.c156 R1 = W [P1] (X) || lms_adapt_bg()
159 R0 = R0 + R1; lms_adapt_bg()
/linux-4.4.14/arch/tile/include/asm/
H A Dsyscall.h67 /* R0 is the passed-in negative error, R1 is positive. */ syscall_set_return_value()
71 /* R1 set to zero to indicate no error. */ syscall_set_return_value()
/linux-4.4.14/arch/powerpc/include/asm/
H A Dkgdb.h59 /* CR/LR, R1, R2, R13-R31 inclusive. */
H A Dreg_booke.h308 #define HID1_R1DPE 0x00008000 /* R1 data bus parity enable */
/linux-4.4.14/arch/powerpc/lib/
H A Dldstfp.S333 STXVD2X(0,R1,R8)
339 LXVD2X(0,R1,R8)
361 STXVD2X(0,R1,R8)
367 LXVD2X(0,R1,R8)
/linux-4.4.14/arch/ia64/include/uapi/asm/
H A Dia64regs.h25 #define _IA64_REG_GP 1025 /* R1 */
/linux-4.4.14/arch/arm/vfp/
H A Dvfp.h40 "movcc %0, %R1\n\t" vfp_hi64to32jamming()
41 "orrcs %0, %R1, #1" vfp_hi64to32jamming()
52 "adc %R1, %R3, %R5" add128()
65 "sbc %R1, %R3, %R5\n\t" sub128()
/linux-4.4.14/arch/arm/boot/dts/
H A Dst-pincfg.h47 * R0, R1, R0D, R1D modes
/linux-4.4.14/drivers/tty/serial/
H A Dip22zilog.c146 regval = read_zsreg(channel, R1); ip22zilog_clear_fifo()
167 unsigned char stat = read_zsreg(channel, R1); __load_zsregs()
180 write_zsreg(channel, R1, __load_zsregs()
181 regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB)); __load_zsregs()
226 /* Rewrite R1, this time without IRQ enabled masked. */ __load_zsregs()
227 write_zsreg(channel, R1, regs[R1]); __load_zsregs()
264 r1 = read_zsreg(channel, R1); ip22zilog_receive_chars()
635 up->curregs[R1] &= ~RxINT_MASK; ip22zilog_stop_rx()
696 unsigned char stat = read_zsreg(channel, R1); __ip22zilog_reset()
731 up->curregs[R1] |= EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB; __ip22zilog_startup()
792 up->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK); ip22zilog_shutdown()
1140 up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB; ip22zilog_prepare()
H A Dsunzilog.c163 regval = read_zsreg(channel, R1); sunzilog_clear_fifo()
186 unsigned char stat = read_zsreg(channel, R1); __load_zsregs()
199 write_zsreg(channel, R1, __load_zsregs()
200 regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB)); __load_zsregs()
259 /* Rewrite R1, this time without IRQ enabled masked. */ __load_zsregs()
260 write_zsreg(channel, R1, regs[R1]); __load_zsregs()
338 r1 = read_zsreg(channel, R1); sunzilog_receive_chars()
349 * with the other bits we care about in R1. sunzilog_receive_chars()
735 up->curregs[R1] &= ~RxINT_MASK; sunzilog_stop_rx()
796 up->curregs[R1] |= EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB; __sunzilog_startup()
857 up->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK); sunzilog_shutdown()
1013 r1 = read_zsreg(channel, R1); sunzilog_get_poll_char()
1024 * with the other bits we care about in R1. sunzilog_get_poll_char()
1350 up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB; sunzilog_init_hw()
1366 up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB; sunzilog_init_hw()
H A Dzs.c258 while (!(read_zsreg(zport, R1) & ALL_SNT) && --loops) { zs_line_drain()
276 write_zsreg(zport, R1, regs[1]); load_zsregs()
315 status = read_zsreg(zport, R1); zs_tx_empty()
471 write_zsreg(zport_a, R1, zport_a->regs[1]); zs_stop_rx()
484 write_zsreg(zport, R1, zport->regs[1]); zs_stop_rx()
512 write_zsreg(zport_a, R1, zport_a->regs[1]); zs_enable_ms()
556 status = read_zsreg(zport, R1) & (Rx_OVR | FRM_ERR | PAR_ERR); zs_receive_chars()
792 write_zsreg(zport, R1, zport->regs[1]); zs_startup()
1163 write_zsreg(zport, R1, zport->regs[1]); zs_console_write()
1183 write_zsreg(zport, R1, zport->regs[1]); zs_console_write()
H A Dpmac_zilog.c135 unsigned char stat = read_zsreg(uap, R1); pmz_load_zsregs()
148 write_zsreg(uap, R1, pmz_load_zsregs()
149 regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB)); pmz_load_zsregs()
193 /* Rewrite R1, this time without IRQ enabled masked. */ pmz_load_zsregs()
194 write_zsreg(uap, R1, regs[R1]); pmz_load_zsregs()
229 write_zsreg(uap, R1, uap->curregs[1]); pmz_interrupt_control()
250 r1 = read_zsreg(uap, R1); pmz_receive_chars()
405 * a closed channel. The interrupt mask in R1 is clear, but pmz_transmit_chars()
409 * R3 interrup status bits are masked by R1 interrupt enable pmz_transmit_chars()
683 uap->curregs[R1] &= ~RxINT_MASK; pmz_stop_rx()
868 write_zsreg(uap, R1, 0); __pmz_startup()
1164 || (read_zsreg(uap, R1) & ALL_SNT) == 0) { pmz_irda_setup()
1979 write_zsreg(uap, R1, uap->curregs[1] & ~TxINT_ENAB); pmz_console_write()
1985 write_zsreg(uap, R1, uap->curregs[1]); pmz_console_write()
H A Dip22zilog.h39 #define R1 1 macro
H A Dsunzilog.h31 #define R1 1 macro
H A Dzs.h60 #define R1 1 macro
H A Dpmac_zilog.h127 #define R1 1 macro
/linux-4.4.14/arch/arm/mach-iop13xx/
H A Dirq.c43 /* INTCTL1 CP6 R1 Page 4
89 /* INTSTR1 CP6 R1 Page 5
/linux-4.4.14/arch/m68k/include/asm/
H A Duaccess_mm.h172 "2: "MOVES".l (%2),%R1\n" \
178 " sub.l %R1,%R1\n" \
/linux-4.4.14/arch/arm/include/asm/
H A Ddiv64.h174 "adcs %R0, %R0, %R1\n\t" \
181 asm ( "umlal %R0, %Q0, %R1, %Q2\n\t" \
184 "umlal %Q0, %R0, %R1, %R2" \
/linux-4.4.14/arch/arm/mach-iop13xx/include/mach/
H A Dirqs.h16 /* INTPND1 CP6 R1 Page 3
/linux-4.4.14/drivers/mmc/host/
H A Dmmc_spi.c253 case MMC_RSP_SPI_R1: return "R1"; maptype()
287 /* Data block reads (R1 response types) may need more data... */ mmc_spi_response_get()
339 /* Status byte: the entire seven-bit R1 response. */ mmc_spi_response_get()
356 /* SPI R1B == R1 + busy; STOP_TRANSMISSION (for multiblock reads) mmc_spi_response_get()
367 /* SPI R2 == R1 + second status byte; SEND_STATUS mmc_spi_response_get()
368 * SPI R5 == R1 + data byte; IO_RW_DIRECT mmc_spi_response_get()
388 /* SPI R3, R4, or R7 == R1 + 4 bytes */ mmc_spi_response_get()
412 /* SPI R1 == just one status byte */ mmc_spi_response_get()
478 * + nothing, for R1 or R1B responses mmc_spi_command_send()
511 /* R1 */ mmc_spi_command_send()
520 /* else: R1 (most commands) */ mmc_spi_command_send()
H A Dtoshsd.c248 /* R1, R1B, R3, R6, R7 */ toshsd_cmd_irq()
H A Ddavinci_mmc.c293 s = ", R1/R5/R6/R7 response"; mmc_davinci_start_command()
H A Drtsx_usb_sdmmc.c315 * R1, R5, R6, R7 sd_send_cmd_get_rsp()
H A Dtmio_mmc_pio.c309 * types. Note that R1 and R6 are the same in this scheme. */
H A Dmtk-sd.c593 /* Actually, R1, R5, R6, R7 are the same */ msdc_cmd_find_resp()
H A Ds3cmci.c183 dbg(host, dbg_debug, "%s R0:[%08x] R1:[%08x]" dbg_dumpregs()
H A Dsh_mmcif.c75 #define CMD_SET_RTYP_6B ((0 << 23) | (1 << 22)) /* R1/R1b/R3/R4/R5 */
/linux-4.4.14/drivers/net/hamradio/
H A Ddmascc.c527 write_scc(priv, R1, EXT_INT_ENAB); setup_adapter()
543 write_scc(priv, R1, 0); setup_adapter()
759 write_scc(priv, R1, EXT_INT_ENAB | WT_FN_RDYFN); scc_open()
996 write_scc(priv, R1, tx_on()
1008 write_scc(priv, R1, tx_on()
1042 write_scc(priv, R1, EXT_INT_ENAB | INT_ERR_Rx | rx_on()
1048 write_scc(priv, R1, EXT_INT_ENAB | INT_ALL_Rx | WT_RDY_RT | rx_on()
1064 write_scc(priv, R1, EXT_INT_ENAB | WT_FN_RDYFN); rx_off()
1166 special_condition(priv, read_scc(priv, R1)); rx_isr()
1173 rc = read_scc(priv, R1); rx_isr()
1344 write_scc(priv, R1, EXT_INT_ENAB | WT_FN_RDYFN); es_isr()
H A Dscc.c570 status = InReg(scc->ctrl,R1); /* read receiver status */ scc_spint()
800 wr(scc,R1,0); /* no W/REQ operation */ init_channel()
876 or(scc,R1,INT_ALL_Rx|TxINT_ENAB|EXT_INT_ENAB); /* enable interrupts */ init_channel()
914 or(scc, R1, TxINT_ENAB); /* t_maxkeyup may have reset these */ scc_key_trx()
1249 cl(scc, R1, TxINT_ENAB); /* force an ABORT, but don't */ t_maxkeyup()
1605 wr(scc,R1,0); /* disable interrupts */ scc_net_close()
2065 seq_printf(seq, "\tR %2.2x %2.2x XX ", InReg(scc->ctrl,R0), InReg(scc->ctrl,R1)); scc_net_seq_show()
H A Dz8530.h7 #define R1 1 macro
/linux-4.4.14/drivers/media/i2c/
H A Dwm8739.c48 R0 = 0, R1, enumerator in enum:__anon5966
128 wm8739_write(sd, R1, (vol_r & 0x1f) | mute); wm8739_s_ctrl()
/linux-4.4.14/arch/mips/include/asm/
H A Dpgtable-bits.h189 * 64-bit, R1 or earlier: CCC D V G [S H] M A W R P
190 * 32-bit, R1 or earler: CCC D V G M A W R P
H A Dhazards.h80 * These are slightly complicated by the fact that we guarantee R1 kernels to
/linux-4.4.14/arch/s390/include/asm/
H A Dkvm_para.h14 * s390 ABI, so we use R2-R6 for parameters 1-5. In addition we use R1
18 * the instruction encoded number, but specify the number in R1 and
H A Dprocessor.h235 " stg %0,%O1+8(%R1)\n" __load_psw_mask()
/linux-4.4.14/arch/parisc/kernel/
H A Dunaligned.c119 #define R1(i) (((i)>>21)&0x1f) macro
452 unsigned long newbase = R1(regs->iir)?regs->gr[R1(regs->iir)]:0; handle_unaligned()
669 if (ret == 0 && modify && R1(regs->iir)) handle_unaligned()
670 regs->gr[R1(regs->iir)] = newbase; handle_unaligned()
/linux-4.4.14/arch/sh/kernel/
H A Dptrace_64.c161 /* R1 -> R63 */ genregs_get()
194 /* R1 -> R63 */ genregs_set()
348 * R1 --> R63,
H A Dprocess_32.c48 printk("R0 : %08lx R1 : %08lx R2 : %08lx R3 : %08lx\n", show_regs()
H A Dentry-common.S270 * Arguments #4 to #6: R0, R1, R2
H A Dprocess_64.c73 printk("R0 : %08Lx%08Lx R1 : %08Lx%08Lx R2 : %08Lx%08Lx\n", show_regs()
/linux-4.4.14/arch/m32r/kernel/
H A Dentry.S89 #define R1(reg) @(0x14,reg) define
134 ld r1, R1(r8)
253 ld r1, R1(sp)
H A Dprocess.c82 printk("R0 [%08lx]:R1 [%08lx]:R2 [%08lx]:R3 [%08lx]\n", \ show_regs()
H A Dhead.S86 ldi r1, #0 ; clear R1 for longwords store
/linux-4.4.14/include/linux/
H A Dhp_sdc.h246 HIL MLC R0,R1 i8042 HIL watchdog */
250 #define HP_SDC_HIL_CMD 0x50 /* Data from HIL MLC R1/8042 */
251 #define HP_SDC_HIL_R1MASK 0x0f /* Contents of HIL MLC R1 0:3 */
/linux-4.4.14/kernel/bpf/
H A Dhelpers.c31 /* verifier checked that R1 contains a valid pointer to bpf_map bpf_map_lookup_elem()
H A Dverifier.c40 * copied to R1.
44 * R1-R5 argument passing registers
48 * At the start of BPF program the register R1 contains a pointer to bpf_context
54 * 1st insn copies R10 (which has FRAME_PTR) type into R1
57 * So after 2nd insn, the register R1 has type PTR_TO_STACK
105 * BPF_LD_MAP_FD(BPF_REG_1, map_fd), // after this insn R1 type is CONST_PTR_TO_MAP
108 * .arg1_type == ARG_CONST_MAP_PTR and R1->type == CONST_PTR_TO_MAP, which is ok,
109 * Now verifier knows that this map has key of R1->map_ptr->key_size bytes
124 * After the call R0 is set to return type of the function and registers R1-R5
1079 /* case: R1 = R2 check_alu_op()
1336 * - since they are wrappers of function calls, they scratch R1-R5 registers,
/linux-4.4.14/arch/m32r/boot/compressed/
H A Dhead.S105 ldi r1, #0 ; clear R1 for longwords store
/linux-4.4.14/arch/arm/probes/uprobes/
H A Dactions-arm.c45 * pick LR instead of R1. uprobes_substitute_pc()
/linux-4.4.14/arch/arm/mach-omap2/
H A Dsleep24xx.S46 * R1 : SDRC_DLLA_CTRL
/linux-4.4.14/arch/arm/mach-pxa/
H A Dcsb726.c39 * XXX: 33 CS_5 for LAN9215 on R1
/linux-4.4.14/drivers/hwmon/
H A Dds1621.c70 * |Done|THF |TLF |NVB | R1 | R0 |POL |1SHOT|
74 * |Done| X | X | U | R1 | R0 |POL |1SHOT|
H A Dds620.c38 * |Done|NVB |THF |TLF |R1 |R0 |AUTOC|1SHOT|
H A Dw83793.c240 * byte 1: Temp R1,R2 mode, each has 1 bit
/linux-4.4.14/drivers/net/wireless/iwlegacy/
H A D4965.c1581 s32 R1, R2, R3; il4965_hw_get_temperature() local
1587 R1 = (s32) le32_to_cpu(il->card_alive_init.therm_r1[1]); il4965_hw_get_temperature()
1593 R1 = (s32) le32_to_cpu(il->card_alive_init.therm_r1[0]); il4965_hw_get_temperature()
1613 D_TEMP("Calib values R[1-3]: %d %d %d R4: %d\n", R1, R2, R3, vt); il4965_hw_get_temperature()
1615 if (R3 == R1) { il4965_hw_get_temperature()
1616 IL_ERR("Calibration conflict R1 == R3\n"); il4965_hw_get_temperature()
1623 temperature /= (R3 - R1); il4965_hw_get_temperature()
H A D4965.h239 * calculation uses 4 measurements, 3 of which (R1, R2, R3) are calibration
254 * degrees Kelvin = ((97 * 259 * (R4 - R2) / (R3 - R1)) / 100) + 8
256 * NOTE: The basic formula is 259 * (R4-R2) / (R3-R1). The 97/100 is
/linux-4.4.14/drivers/media/dvb-frontends/
H A Ddrxd_hard.c93 u16 R1; member in struct:SCfgAgc
876 R1 ReadIFAgc()
884 u32 R1 = state->if_agc_cfg.R1; ReadIFAgc() local
890 if (R2 == 0 && (R1 == 0 || R3 == 0)) ReadIFAgc()
893 Vmax = (3300 * R2) / (R1 + R2); ReadIFAgc()
895 Vmin = (3300 * Rpar) / (R1 + Rpar); ReadIFAgc()
2514 state->if_agc_cfg.R1 = (u16) (ulIfAgcR1); CDRXD()
2518 state->rf_agc_cfg.R1 = (u16) (ulRfAgcR1); CDRXD()
H A Ddvb-pll.c513 /* byte 4 : 1 * * AGD R3 R2 R1 R0
515 * AGD = 1, R3 R2 R1 R0 = 0 1 0 1 => byte 4 = 1**10101 = 0x95
H A Dzl10036.c173 * 5[0x00]: P0 | C1 | C0 | R4 | R3 | R2 | R1 | R0
/linux-4.4.14/drivers/mmc/core/
H A Dmmc_ops.c308 * not R1 plus a data block. mmc_send_cxd_data()
499 * to a R1 response instead of a R1B. __mmc_switch()
703 * not R1 plus a data block. mmc_send_bus_test()
H A Dcore.c306 * When the urgent BKOPS bit is set in a R1 command response
601 * Check BKOPS urgency for each R1 response mmc_start_req()
H A Dmmc.c1701 * from doing hw busy detection, which is done by converting to a R1 mmc_sleep()
/linux-4.4.14/arch/arc/include/asm/
H A Duaccess.h100 "4: ld %R1,[%2, 4]\n" \
148 "4: st %R1,[%2, 4]\n" \
/linux-4.4.14/arch/cris/arch-v32/kernel/
H A Dkgdb_asm.S31 move.d $r1, [$acr] ; Save R1
473 move.d [$acr], $r1 ; Restore R1
H A Dkgdb.c311 R0, R1, R2, R3, enumerator in enum:register_name
/linux-4.4.14/arch/powerpc/kernel/
H A Dtm.S400 /* Clear the MSR RI since we are about to change R1. EE is already off
462 /* R1 is restored, so we are recoverable again. EE is still off */
H A Dprocess.c646 * change and later in the trecheckpoint code, we have a userspace R1. tm_recheckpoint()
/linux-4.4.14/arch/mips/
H A DMakefile171 # as MIPS64 R1; older versions as just R1. This leaves the possibility open
/linux-4.4.14/drivers/pinctrl/mediatek/
H A Dpinctrl-mtk-common.h204 * up/down bit, R0 and R1 resistor bit, so they need special pull setting.
H A Dpinctrl-mtk-common.c295 * they have separate pull up/down bit, R0 and R1 mtk_pconf_set_pull_select()
/linux-4.4.14/arch/mips/kernel/
H A Delf.c208 /* Make sure 64-bit MIPS III/IV/64R1 will not pick FR1 */ arch_check_elf()
/linux-4.4.14/arch/sh/kernel/cpu/sh2/
H A Dentry.S109 mov.l @(4,r2),r0 ! old R1
/linux-4.4.14/arch/sh/kernel/cpu/sh2a/
H A Dentry.S92 mov.l @r8+,r1 ! old R1
/linux-4.4.14/sound/soc/intel/boards/
H A Dcht_bsw_rt5672.c118 {"DMIC R1", NULL, "Int Mic"},
H A Dcht_bsw_rt5645.c108 {"DMIC R1", NULL, "Int Mic"},
/linux-4.4.14/sound/soc/mediatek/
H A Dmt8173-rt5650-rt5676.c39 {"Sub DMIC R1", NULL, "Int Mic"},
/linux-4.4.14/sound/pci/ali5451/
H A Dali5451.c648 u8 bval, R1 = 0, R2; snd_ali_detect_spdif_rate() local
654 while ((R1 < 0x0b || R1 > 0x0e) && R1 != 0x12 && count <= 50000) { snd_ali_detect_spdif_rate()
658 R1 = bval & 0x1F; snd_ali_detect_spdif_rate()
670 if (R2 != R1) snd_ali_detect_spdif_rate()
671 R1 = R2; snd_ali_detect_spdif_rate()
/linux-4.4.14/arch/cris/arch-v10/kernel/
H A Dkgdb.c303 R0, R1, R2, R3, enumerator in enum:register_name
929 " move.d $r1,[cris_reg+0x04] ; Save R1\n"
982 " move.d [cris_reg+0x04],$r1 ; Restore R1\n"
1025 " move.d $r1,[cris_reg+0x04] ; Save R1\n"
1080 " move.d [cris_reg+0x04],$r1 ; Restore R1\n"
/linux-4.4.14/drivers/staging/rtl8188eu/hal/
H A DHal8188ERateAdaptive.c731 ("macid =%d Total =%d R0 =%d R1 =%d R2 =%d R3 =%d R4 =%d D0 =%d valid0 =%x valid1 =%x\n", ODM_RA_TxRPT2Handle_8188E()
754 ("macid =%d R0 =%d R1 =%d R2 =%d R3 =%d R4 =%d drop =%d valid0 =%x RateID =%d SGI =%d\n", ODM_RA_TxRPT2Handle_8188E()
/linux-4.4.14/arch/sh/boards/
H A Dboard-magicpanelr2.c180 * R3 A21; R2 A20; R1 A19; R0 A0; setup_port_multiplexing()
/linux-4.4.14/arch/ia64/kernel/
H A Dunwind_decoder.c167 UNW_DEC_PROLOGUE(R1, body, rlen, arg); unw_decode_r1()
H A Divt.S993 st8 [r17]=r28,PT(R1)-PT(B0) // save b0
997 st8.spill [r17]=r20,PT(R13)-PT(R1) // save original r1
H A Dentry.S778 ld8 r31=[r3],PT(R1)-PT(PR) // M0|1 load predicates
/linux-4.4.14/include/linux/mfd/wm831x/
H A Dcore.h208 * R1 (0x01) - Revision
/linux-4.4.14/drivers/tty/serial/8250/
H A Dserial_cs.c789 PCMCIA_DEVICE_CIS_PROD_ID12("Sierra Wireless", "AC850", 0xd85f6206, 0x42a2c018, "cis/SW_8xx_SER.cis"), /* Sierra Wireless AC850 3G Network Adapter R1 */
790 PCMCIA_DEVICE_CIS_PROD_ID12("Sierra Wireless", "AC860", 0xd85f6206, 0x698f93db, "cis/SW_8xx_SER.cis"), /* Sierra Wireless AC860 3G Network Adapter R1 */
791 PCMCIA_DEVICE_CIS_PROD_ID12("Sierra Wireless", "AC710/AC750", 0xd85f6206, 0x761b11e0, "cis/SW_7xx_SER.cis"), /* Sierra Wireless AC710/AC750 GPRS Network Adapter R1 */
/linux-4.4.14/drivers/input/mouse/
H A Dvsxxxaa.c328 * [0]: 1 0 1 0 R3 R2 R1 R0 vsxxxaa_handle_POR_packet()
/linux-4.4.14/drivers/mfd/
H A Dwm8350-regmap.c28 { 0x7CFF, 0x0C00, 0x0000 }, /* R1 - ID */
H A Dwm8994-regmap.c23 { 0x0001, 0x0000 }, /* R1 - Power Management (1) */
255 { 0x0001, 0x0000 }, /* R1 - Power Management (1) */
474 { 0x0001, 0x0000 }, /* R1 - Power Management (1) */
/linux-4.4.14/drivers/net/wireless/b43/
H A Dradio_2055.h61 #define B2055_PLL_LFR1 0x36 /* PLL LF R1 */
/linux-4.4.14/drivers/platform/x86/
H A Dalienware-wmi.c91 .ident = "Alienware X51 R1",
H A Dpanasonic-laptop.c174 /* R1 handles SINF_AC_CUR_BRIGHT as SINF_CUR_BRIGHT, doesn't know AC state */
/linux-4.4.14/drivers/dma/ppc4xx/
H A Dadma.c2317 /* may do RXOR R1 R2 */ ppc440spe_dma01_prep_pq()
2322 /* do RXOR R1 R2 R3 */ ppc440spe_dma01_prep_pq()
2326 /* do RXOR R1 R2 R4 */ ppc440spe_dma01_prep_pq()
2329 /* do RXOR R1 R2 R5 */ ppc440spe_dma01_prep_pq()
2333 /* do RXOR R1 R2 */ ppc440spe_dma01_prep_pq()
2338 /* do RXOR R1 R2 */ ppc440spe_dma01_prep_pq()
3134 /* setup sources region (R1-2-3, R1-2-4, ppc440spe_adma_pq_set_src()
3135 * or R1-2-5) ppc440spe_adma_pq_set_src()
/linux-4.4.14/include/linux/mfd/wm8350/
H A Dcore.h83 * R1 (0x01) - ID
/linux-4.4.14/arch/mips/pci/
H A Dops-tx4927.c287 /* PCI->GB mappings (MEM 512MB (64MB on R1.x)) */ tx4927_pcic_setup()
/linux-4.4.14/arch/hexagon/lib/
H A Dmemcpy.S152 #define ptr_in R1 /* source pointer */
/linux-4.4.14/arch/arm/probes/
H A Ddecode.h252 * instruction will be modified to "AND R0, R2, R3, ASL R1" and then placed into
/linux-4.4.14/arch/arm/kernel/
H A Dentry-header.S60 * xPSR, ReturnAddress(), LR (R14), R12, R3, R2, R1, and R0 are
/linux-4.4.14/net/bluetooth/
H A Decc.c693 /* R0 and R1 */ ecc_point_mult()
/linux-4.4.14/net/sctp/
H A Dtransport.c192 * R1) Every time a DATA chunk is sent to any address(including a sctp_transport_reset_timers()
/linux-4.4.14/arch/s390/mm/
H A Dfault.c139 pr_cont("R1:%016lx ", *table); dump_pagetable()
/linux-4.4.14/arch/arm/probes/kprobes/
H A Dactions-thumb.c519 insn |= 0x001; /* Set Rdn = R1 and Rm = R0 */ t16_decode_hiregs()
/linux-4.4.14/drivers/scsi/pcmcia/
H A Dnsp_cs.c22 "WBT", "NinjaSCSI-3", "R1.0"
1730 PCMCIA_DEVICE_PROD_ID123("WBT", "NinjaSCSI-3", "R1.0", 0xc7ba805f, 0xfdc7c97d, 0x6973710e),
/linux-4.4.14/drivers/net/wireless/rt2x00/
H A Drt2500pci.c485 * For RT2523 devices we do not need to update the R1 register. rt2500pci_config_channel()
526 * For RT2523 devices we do not need to update the R1 register. rt2500pci_config_channel()
H A Drt2400pci.h740 * R1: TX antenna control
/linux-4.4.14/arch/sh/kernel/cpu/sh5/
H A Dentry.S77 /* Save R0/R1 : PT-migrating compiler currently dishounours -ffixed-r0 and -ffixed-r1 causing
514 /* Save SSR & SPC, together with R0 & R1, as we need to use 2 regs. */
/linux-4.4.14/drivers/scsi/megaraid/
H A Dmegaraid_sas_fp.c1341 dev_dbg(&instance->pdev->dev, "LSI Debug R1 Load balance " megasas_get_best_arm_pd()
/linux-4.4.14/drivers/net/can/m_can/
H A Dm_can.c262 /* R1 */
/linux-4.4.14/include/linux/mfd/
H A Dwm8400-private.h131 * R1 (0x01) - ID
/linux-4.4.14/arch/microblaze/kernel/
H A Dentry.S782 * by PT_SIZE but we need to get correct R1 value */
/linux-4.4.14/arch/arm/net/
H A Dbpf_jit_32.c599 /* the offset is already in R1 */ build_body()
/linux-4.4.14/include/net/sctp/
H A Dstructs.h1742 * R1) One and only one ASCONF Chunk MAY be in transit and
1781 * R1) One and only one ASCONF Chunk MAY be in transit and
/linux-4.4.14/drivers/net/wireless/cw1200/
H A Dwsm.c1291 print_hex_dump_bytes("R1: ", DUMP_PREFIX_NONE, wsm_handle_exception()
/linux-4.4.14/sound/usb/
H A Dpcm.c1357 * L1 L2 0x05 R1 R2 0x05 L3 L4 0xfa R3 R4 0xfa fill_playback_urb_dsd_dop()
/linux-4.4.14/net/sunrpc/auth_gss/
H A Dauth_gss.c201 ctx->gc_seq = 1; /* NetApp 6.4R1 doesn't accept seq. no. 0 */ gss_alloc_context()

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