1* Mediatek MT65XX Pin Controller
2
3The Mediatek's Pin controller is used to control SoC pins.
4
5Required properties:
6- compatible: value should be one of the following.
7    (a) "mediatek,mt8135-pinctrl", compatible with mt8135 pinctrl.
8    (b) "mediatek,mt8173-pinctrl", compatible with mt8173 pinctrl.
9    (c) "mediatek,mt6397-pinctrl", compatible with mt6397 pinctrl.
10    (d) "mediatek,mt8127-pinctrl", compatible with mt8127 pinctrl.
11- pins-are-numbered: Specify the subnodes are using numbered pinmux to
12  specify pins.
13- gpio-controller : Marks the device node as a gpio controller.
14- #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
15  binding is used, the amount of cells must be specified as 2. See the below
16  mentioned gpio binding representation for description of particular cells.
17
18	Eg: <&pio 6 0>
19	<[phandle of the gpio controller node]
20	[line number within the gpio controller]
21	[flags]>
22
23	Values for gpio specifier:
24	- Line number: is a value between 0 to 202.
25	- Flags:  bit field of flags, as defined in <dt-bindings/gpio/gpio.h>.
26            Only the following flags are supported:
27            0 - GPIO_ACTIVE_HIGH
28            1 - GPIO_ACTIVE_LOW
29
30Optional properties:
31- mediatek,pctl-regmap: Should be a phandle of the syscfg node.
32- reg: physicall address base for EINT registers
33- interrupt-controller: Marks the device node as an interrupt controller
34- #interrupt-cells: Should be two.
35- interrupts : The interrupt outputs from the controller.
36
37Please refer to pinctrl-bindings.txt in this directory for details of the
38common pinctrl bindings used by client devices.
39
40Subnode format
41A pinctrl node should contain at least one subnodes representing the
42pinctrl groups available on the machine. Each subnode will list the
43pins it needs, and how they should be configured, with regard to muxer
44configuration, pullups, drive strength, input enable/disable and input schmitt.
45
46    node {
47	pinmux = <PIN_NUMBER_PINMUX>;
48	GENERIC_PINCONFIG;
49    };
50
51Required properties:
52- pinmux: integer array, represents gpio pin number and mux setting.
53    Supported pin number and mux varies for different SoCs, and are defined
54    as macros in boot/dts/<soc>-pinfunc.h directly.
55
56Optional properties:
57- GENERIC_PINCONFIG: is the generic pinconfig options to use, bias-disable,
58    bias-pull-down, bias-pull-up, input-enable, input-disable, output-low, output-high,
59    input-schmitt-enable, input-schmitt-disable and drive-strength are valid.
60
61    Some special pins have extra pull up strength, there are R0 and R1 pull-up
62    resistors available, but for user, it's only need to set R1R0 as 00, 01, 10 or 11.
63    So when config bias-pull-up, it support arguments for those special pins.
64    Some macros have been defined for this usage, such as MTK_PUPD_SET_R1R0_00.
65    See dt-bindings/pinctrl/mt65xx.h.
66
67    When config drive-strength, it can support some arguments, such as
68    MTK_DRIVE_4mA, MTK_DRIVE_6mA, etc. See dt-bindings/pinctrl/mt65xx.h.
69
70Examples:
71
72#include "mt8135-pinfunc.h"
73
74...
75{
76	syscfg_pctl_a: syscfg_pctl_a@10005000 {
77		compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon";
78		reg = <0 0x10005000 0 0x1000>;
79	};
80
81	syscfg_pctl_b: syscfg_pctl_b@1020C020 {
82		compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon";
83		reg = <0 0x1020C020 0 0x1000>;
84	};
85
86	pinctrl@01c20800 {
87		compatible = "mediatek,mt8135-pinctrl";
88		reg = <0 0x1000B000 0 0x1000>;
89		mediatek,pctl-regmap = <&syscfg_pctl_a &syscfg_pctl_b>;
90		pins-are-numbered;
91		gpio-controller;
92		#gpio-cells = <2>;
93		interrupt-controller;
94		#interrupt-cells = <2>;
95		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
96				<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
97				<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
98
99		i2c0_pins_a: i2c0@0 {
100			pins1 {
101				pinmux = <MT8135_PIN_100_SDA0__FUNC_SDA0>,
102					 <MT8135_PIN_101_SCL0__FUNC_SCL0>;
103				bias-disable;
104			};
105		};
106
107		i2c1_pins_a: i2c1@0 {
108			pins {
109				pinmux = <MT8135_PIN_195_SDA1__FUNC_SDA1>,
110					 <MT8135_PIN_196_SCL1__FUNC_SCL1>;
111				bias-pull-up = <55>;
112			};
113		};
114
115		i2c2_pins_a: i2c2@0 {
116			pins1 {
117				pinmux = <MT8135_PIN_193_SDA2__FUNC_SDA2>;
118				bias-pull-down;
119			};
120
121			pins2 {
122				pinmux = <MT8135_PIN_49_WATCHDOG__FUNC_GPIO49>;
123				bias-pull-up;
124			};
125		};
126
127		i2c3_pins_a: i2c3@0 {
128			pins1 {
129				pinmux = <MT8135_PIN_40_DAC_CLK__FUNC_GPIO40>,
130					 <MT8135_PIN_41_DAC_WS__FUNC_GPIO41>;
131				bias-pull-up = <55>;
132			};
133
134			pins2 {
135				pinmux = <MT8135_PIN_35_SCL3__FUNC_SCL3>,
136					 <MT8135_PIN_36_SDA3__FUNC_SDA3>;
137				output-low;
138				bias-pull-up = <55>;
139			};
140
141			pins3 {
142				pinmux = <MT8135_PIN_57_JTCK__FUNC_GPIO57>,
143					 <MT8135_PIN_60_JTDI__FUNC_JTDI>;
144				drive-strength = <32>;
145			};
146		};
147
148		...
149	}
150};
151