Searched refs:R0 (Results 1 - 183 of 183) sorted by relevance

/linux-4.4.14/arch/blackfin/lib/
H A Dumulsi3_highpart.S18 R2 = R1.H * R0.H, R3 = R1.L * R0.H (FU);
19 R0 = R1.L * R0.L, R1 = R1.H * R0.L (FU); define
20 R0 >>= 16;
23 R0 = R0 + R3; define
24 R0 = R0 + R1; define
27 R1 = PACK(R1.l,R0.h);
28 R0 = R1 + R2; define
H A Dmuldi3.S18 R1:R0 * R3:R2
19 = R1.h:R1.l:R0.h:R0.l * R3.h:R3.l:R2.h:R2.l
22 [X] + (R1.h * R2.h + R1.l * R3.l + R3.h * R0.h) * 2^64
23 [T1] + (R1.h * R2.l + R3.h * R0.l + R1.l * R2.h + R3.l * R0.h) * 2^48
24 [T2] + (R1.l * R2.l + R3.l * R0.l + R0.h * R2.h) * 2^32
25 [T3] + (R0.l * R2.h + R2.l * R0.h) * 2^16
26 [T4] + (R0.l * R2.l)
32 [E1] = R1.h * R2.l + R3.h * R0.l + R1.l * R2.h + R3.l * R0.h
33 [E2] = R1.l * R2.l + R3.l * R0.l + R0.h * R2.h
34 [E3] = R0.l * R2.h + R2.l * R0.h
35 [E4] = R0.l * R2.l
52 A0 += R3.H * R0.L, A1 += R3.L * R0.H (FU) || [SP] = R4; /* E1 */
55 A0 = R0.l * R3.l (FU); /* E2 */
58 A1 = R2.L * R0.L (FU); /* E4 */
61 A0 += R2.H * R0.H, A1 += R2.L * R0.H (FU); /* E2, E3c */
62 A1 += R0.L * R2.H (FU); /* E3c */
63 R0 = A1.w; define
69 R0 = PACK (R0.l, R3.l); define
H A Dsmulsi3_highpart.S18 R2 = R1.L * R0.L (FU);
19 R3 = R1.H * R0.L (IS,M);
20 R0 = R0.H * R1.H, R1 = R0.H * R1.L (IS,M); define
35 R0 = R0 + R1; define
H A Ddivsi3.S19 * Operand : R0 - Numerator (i)
21 * R0 - Quotient (o)
39 R3 = R0 ^ R1;
40 R0 = ABS R0; define
57 DIVS(R0, R1);
58 DIVQ(R0, R1);
59 DIVQ(R0, R1);
60 DIVQ(R0, R1);
61 DIVQ(R0, R1);
62 DIVQ(R0, R1);
63 DIVQ(R0, R1);
64 DIVQ(R0, R1);
65 DIVQ(R0, R1);
66 DIVQ(R0, R1);
67 DIVQ(R0, R1);
68 DIVQ(R0, R1);
69 DIVQ(R0, R1);
70 DIVQ(R0, R1);
71 DIVQ(R0, R1);
72 DIVQ(R0, R1);
73 DIVQ(R0, R1);
75 R0 = R0.L (Z); define
91 CC = R0 == 0; /* check for division of zero */
94 CC = R0 == R1; /* check for identical operands */
114 R2 = R0 << 1; /* R2 lsw of dividend */
115 R6 = R0 ^ R1; /* Get sign */
118 R0 = 0 ; /* Clear msw partial remainder */ define
120 R6 = R0 ^ R1; /* Get new quotient bit */
125 R0 = R0 << 1 || R5 = [SP]; define
126 R0 = R0 | R7; /* and add carry */ define
130 R0 = R0 + R5; /* do add or subtract, as indicated by AQ */ define
131 R6 = R0 ^ R1; /* Generate next quotient bit */
153 CC = R0 == R1; /* check for identical operands => 1 */
157 R2 = R0; /* assume divide by 1 => numerator */
161 R0 = R2; /* Return an identity value */ define
164 IF CC R0 = R2;
180 R2 = R0 >> 31;
187 R0 = LSHIFT R0 by R1.L; define
190 R2 = -R0; // negate result if necessary
192 IF CC R0 = R2;
196 R0 = 0; define
H A Douts.S18 P0 = R0; /* P0 = port */
23 .Llong_loop_s: R0 = [P1++];
24 .Llong_loop_e: [P0] = R0;
31 P0 = R0; /* P0 = port */
36 .Lword_loop_s: R0 = W[P1++];
37 .Lword_loop_e: W[P0] = R0;
44 P0 = R0; /* P0 = port */
49 .Lbyte_loop_s: R0 = B[P1++];
50 .Lbyte_loop_e: B[P0] = R0;
57 P0 = R0; /* P0 = port */
63 R0 = B[P1++]; define
64 R0 = R0 << 8; define
65 R0 = R0 + R1; define
66 .Lword8_loop_e: W[P0] = R0;
H A Dumodsi3.S21 CC=R0==0;
25 CC=R0==R1;
29 CC = R0<R1 (IU);
30 IF CC JUMP .LRETURN_R0; /* Return dividend (R0),IF NR<DR */
34 R7 = R0; /* Copy of R0 */
39 R0 *= R6; /* Quotient * divisor */
40 R0 = R7 - R0; /* Dividend - (quotient * divisor) */ define
45 R0 = 0; define
H A Dstrncmp.S10 * R0 = address (dest)
28 P0 = R0 ; /* s1 */
31 R0 = B[P0++] (Z); /* get *s1 */ define
33 CC = R0 == R1; /* compare a byte */
35 CC = R0; /* at end of s1? */
41 R0 = 0; /* strings are equal */ define
44 R0 = R0 - R1; /* *s1 - *s2 */ define
49 R0 = 0; define
H A Dins.S76 P0 = R0; /* P0 = port */ \
92 R0 = [P0]; \ define
93 [P1++] = R0; \
97 R0 = W[P0]; \ define
98 W[P1++] = R0; \
102 R0 = W[P0]; \ define
103 B[P1++] = R0; \
104 R0 = R0 >> 8; \ define
105 B[P1++] = R0; \
109 R0 = B[P0]; \ define
110 B[P1++] = R0; \
114 R0 = [P0]; \ define
115 W[P1++] = R0; \
116 R0 = R0 >> 16; \ define
117 W[P1++] = R0; \
H A Dstrncpy.S11 * R0 = address (dest)
14 * Returns a pointer (R0) to the destination string dest
15 * we do this by not changing R0
31 P0 = R0 ; /* dst*/
63 * R0 = address
68 I1 = R0;
69 R0 = RETS; define
70 I0 = R0;
71 R0 = P0; define
73 R0 = I0; define
74 RETS = R0;
75 R0 = I1; define
H A Dmemchr.S10 * R0 = address (s)
22 P0 = R0; /* P0 = address */
39 R0=0;
43 R0 = P0; define
44 R0 += -1;
H A Dmemcmp.S10 * R0 = First Address (s1)
23 P0 = R0; /* P0 = s1 address */
29 R1 = R1 | R0; /* OR addresses together */
42 R0 = [P0++]; define
45 MNOP || R0 = [P0++] || R1 = [I0++];
47 CC = R0 == R1;
61 R0 = B[P0++](Z); /* *s1 */ define
62 CC = R0 == R1;
68 R0 = R0 - R1; define
88 R0 = 0; define
H A Dstrcmp.S10 * R0 = address (s1)
27 P0 = R0 ; /* s1 */
31 R0 = B[P0++] (Z); /* get *s1 */ define
33 CC = R0 == R1; /* compare a byte */
35 CC = R0; /* at end of s1? */
39 R0 = R0 - R1; /* *s1 - *s2 */ define
H A Dmemset.S19 * R0 = address (leave unchanged to form result)
27 P0 = R0 ; /* P0 = address */
29 R3 = R0 + R2; /* end */
34 R2 = R0 & R2; /* addr bottom two bits */
72 CC = BITTST (R0, 0); /* odd byte */
73 R0 = 4; define
74 R0 = R0 - R2; define
75 P1 = R0;
76 R0 = P0; /* Recover return address */ define
H A Dmodsi3.S4 * Registers in: R0, R1 = Numerator/ Denominator
5 * Registers out: R0 = Remainder
25 CC=R0==0;
29 CC=R0==R1;
41 R7 = R0; /* Copy of R0 */
46 R0 *= R6; /* Quotient * divisor */
47 R0 = R7 - R0; /* Dividend - (quotient * divisor) */ define
53 R0 = 0; define
H A Dudivsi3.S20 CC = R0 < R1 (IU); /* If X < Y, always return 0 */
24 CC = R2 <= R0 (IU);
27 R2 = R0 >> 31; /* if X is a 31-bit number */
46 R0 <<= 1;
47 DIVQ(R0, R1); // 1
48 DIVQ(R0, R1); // 2
49 DIVQ(R0, R1); // 3
50 DIVQ(R0, R1); // 4
51 DIVQ(R0, R1); // 5
52 DIVQ(R0, R1); // 6
53 DIVQ(R0, R1); // 7
54 DIVQ(R0, R1); // 8
55 DIVQ(R0, R1); // 9
56 DIVQ(R0, R1); // 10
57 DIVQ(R0, R1); // 11
58 DIVQ(R0, R1); // 12
59 DIVQ(R0, R1); // 13
60 DIVQ(R0, R1); // 14
61 DIVQ(R0, R1); // 15
62 DIVQ(R0, R1); // 16
63 R0 = R0.L (Z); define
78 CC = ! BITTST(R0, 31);
90 R2 = R0 >> 16;
104 CC = R0 == 0; /* 0/Y => 0 */
106 CC = R0 == R1; /* X==Y => 1 */
125 /* If either R0 or R1 have sign set, */
136 R2 = R0 >> 1;
137 R2 = R0 >> 1;
138 CC = R0 < 0;
140 IF !CC R2 = R0; /* Shifted R0 */
173 R5 = R0 - R3; /* Z = (dividend - Q * divisor) */
180 R0 = R2; /* Store quotient */ define
184 CC = R0 < R1 (IU); /* If X < Y, always return 0 */
191 CC = R0 == R1; /* X==Y => 1 */
193 R2 = R0; /* X/1 => X */
197 R0 = R2; define
213 R2 = R0 >> 31;
220 R0 = LSHIFT R0 by R1.L; define
233 R2 = R0;
264 R2 = R0 - R2; /* E = X - M */
265 R0 = R3; /* Copy Q into result reg */ define
273 R1 = R0 - R3;
274 IF CC R0 = R1;
H A Dstrcpy.S10 * R0 = address (dest)
25 P0 = R0 ; /* dst*/
H A Dmemmove.S13 * R0 = To Address (leave unchanged to form result)
21 P0 = R0; /* P0 = To address */
27 CC = R1 < R0 (IU); /* From < To */
30 CC = R0 <= R3 (IU); /* (From+len) >= To */
36 R3 = R1 | R0; /* OR addresses together */
H A Dmemcpy.S16 * R0 = To Address (dest) (leave unchanged to form result)
35 P0 = R0 ; /* dst*/
40 CC = R1 < R0; /* src < dst */
43 CC = R0 < R3; /* and dst < src+len */
49 R3 = R1 | R0;
/linux-4.4.14/arch/hexagon/kernel/
H A Dvm_entry.S50 memd(R0 + #_PT_R3130) = R31:30; \
51 { memw(R0 + #_PT_R2928) = R28; \
52 R31 = memw(R0 + #_PT_ER_VMPSP); }\
53 { memw(R0 + #(_PT_R2928 + 4)) = R31; \
55 { memd(R0 + #_PT_R2726) = R27:26; \
57 memd(R0 + #_PT_R2524) = R25:24; \
58 memd(R0 + #_PT_R2322) = R23:22; \
59 memd(R0 + #_PT_R2120) = R21:20; \
60 memd(R0 + #_PT_R1918) = R19:18; \
61 memd(R0 + #_PT_R1716) = R17:16; \
62 memd(R0 + #_PT_R1514) = R15:14; \
63 memd(R0 + #_PT_R1312) = R13:12; \
64 { memd(R0 + #_PT_R1110) = R11:10; \
66 { memd(R0 + #_PT_R0908) = R9:8; \
68 { memd(R0 + #_PT_R0706) = R7:6; \
70 { memd(R0 + #_PT_R0504) = R5:4; \
72 { memd(R0 + #_PT_GPUGP) = R31:30; \
75 { memd(R0 + #_PT_LC0SA0) = R15:14; \
78 { memd(R0 + #_PT_LC1SA1) = R13:12; \
81 { memd(R0 + #_PT_M1M0) = R11:10; \
83 R2 = and(R0,R2); } \
84 { memd(R0 + #_PT_PREDSUSR) = R15:14; \
87 memw(THREADINFO_REG + #_THREAD_INFO_PT_REGS) = R0; \
89 { memw(R0 + #_PT_SYSCALL_NR) = R2; \
95 { memd(R0 + #_PT_R3130) = R31:30; \
96 R30 = memw(R0 + #_PT_ER_VMPSP); }\
97 { memw(R0 + #_PT_R2928) = R28; \
98 memw(R0 + #(_PT_R2928 + 4)) = R30; }\
100 memd(R0 + #_PT_R2726) = R27:26; \
101 memd(R0 + #_PT_R2524) = R25:24; }\
102 { memd(R0 + #_PT_R2322) = R23:22; \
103 memd(R0 + #_PT_R2120) = R21:20; }\
104 { memd(R0 + #_PT_R1918) = R19:18; \
105 memd(R0 + #_PT_R1716) = R17:16; }\
106 { memd(R0 + #_PT_R1514) = R15:14; \
107 memd(R0 + #_PT_R1312) = R13:12; \
109 { memd(R0 + #_PT_R1110) = R11:10; \
110 memd(R0 + #_PT_R0908) = R9:8; \
112 { memd(R0 + #_PT_R0706) = R7:6; \
113 memd(R0 + #_PT_R0504) = R5:4; \
115 { memd(R0 + #_PT_GPUGP) = R31:30; \
116 memd(R0 + #_PT_LC0SA0) = R15:14; \
118 { THREADINFO_REG = and(R0, # ## #-_THREAD_SIZE); \
119 memd(R0 + #_PT_LC1SA1) = R13:12; \
121 { memd(R0 + #_PT_M1M0) = R11:10; \
122 memw(R0 + #_PT_PREDSUSR + 4) = R15; }\
124 memw(THREADINFO_REG + #_THREAD_INFO_PT_REGS) = R0; \
126 { memw(R0 + #_PT_SYSCALL_NR) = R2; \
127 memd(R0 + #_PT_CS1CS0) = R17:16; \
140 R15:14 = memd(R0 + #_PT_PREDSUSR); } \
141 { R11:10 = memd(R0 + #_PT_M1M0); \
143 { R13:12 = memd(R0 + #_PT_LC1SA1); \
145 { R15:14 = memd(R0 + #_PT_LC0SA0); \
147 { R3:2 = memd(R0 + #_PT_R0302); \
149 { R5:4 = memd(R0 + #_PT_R0504); \
151 { R7:6 = memd(R0 + #_PT_R0706); \
153 { R9:8 = memd(R0 + #_PT_R0908); \
155 { R11:10 = memd(R0 + #_PT_R1110); \
157 { R13:12 = memd(R0 + #_PT_R1312); \
158 R15:14 = memd(R0 + #_PT_R1514); } \
159 { R17:16 = memd(R0 + #_PT_R1716); \
160 R19:18 = memd(R0 + #_PT_R1918); } \
161 { R21:20 = memd(R0 + #_PT_R2120); \
162 R23:22 = memd(R0 + #_PT_R2322); } \
163 { R25:24 = memd(R0 + #_PT_R2524); \
164 R27:26 = memd(R0 + #_PT_R2726); } \
165 R31:30 = memd(R0 + #_PT_GPUGP); \
166 { R28 = memw(R0 + #_PT_R2928); \
168 { R31:30 = memd(R0 + #_PT_R3130); \
174 R15:14 = memd(R0 + #_PT_PREDSUSR); } \
175 { R11:10 = memd(R0 + #_PT_M1M0); \
176 R13:12 = memd(R0 + #_PT_LC1SA1); \
178 { R15:14 = memd(R0 + #_PT_LC0SA0); \
179 R3:2 = memd(R0 + #_PT_R0302); \
181 { R5:4 = memd(R0 + #_PT_R0504); \
182 R7:6 = memd(R0 + #_PT_R0706); \
184 { R9:8 = memd(R0 + #_PT_R0908); \
185 R11:10 = memd(R0 + #_PT_R1110); \
187 { R13:12 = memd(R0 + #_PT_R1312); \
188 R15:14 = memd(R0 + #_PT_R1514); \
190 { R17:16 = memd(R0 + #_PT_R1716); \
191 R19:18 = memd(R0 + #_PT_R1918); } \
192 { R21:20 = memd(R0 + #_PT_R2120); \
193 R23:22 = memd(R0 + #_PT_R2322); } \
194 { R25:24 = memd(R0 + #_PT_R2524); \
195 R27:26 = memd(R0 + #_PT_R2726); } \
196 R31:30 = memd(R0 + #_PT_CS1CS0); \
198 R31:30 = memd(R0 + #_PT_GPUGP) ; \
199 R28 = memw(R0 + #_PT_R2928); }\
201 R31:30 = memd(R0 + #_PT_R3130); }
206 * of pt_regs in HVM mode. Save R0/R1, set handler's address in R1.
207 * R0 is the address of pt_regs and is the parameter to save_pt_regs.
213 * Need to save off R0, R1, R2, R3 immediately.
228 R0 = R29; \ define
245 R0 = usr; \ define
248 memw(R29 + #_PT_PREDSUSR) = R0; \
249 R0 = setbit(R0, #16); \ define
251 usr = R0; \
259 R0 = R29; \ define
287 R0 = #VM_INT_DISABLE define
293 R0 = memw(R29 + #_PT_ER_VMEST); define
297 P0 = tstbit(R0, #HVM_VMEST_UM_SFT);
300 R0 = #VM_INT_DISABLE; define
307 * R26 needs to have do_work_pending, and R0 should have VM_INT_DISABLE
314 R0 = R29; /* regs should still be at top of stack */ define
320 P0 = cmp.eq(R0, #0); if (!P0.new) jump:nt check_work_pending;
321 R0 = #VM_INT_DISABLE; define
327 * R0 gets preloaded with #VM_INT_DISABLE before we get here.
344 R0 = R29 define
383 R0 = #VM_INT_DISABLE; define
387 R0 = R25; define
392 R0 = #VM_INT_DISABLE; define
H A Dvm_switch.S47 * in the new R0's pointer. Technically it should be R2, but they should
49 * R0, let it go back out unmolested.
68 memw(R0+#_TASK_THREAD_INFO) = THREADINFO_REG;
69 memw(R0 +#(_TASK_STRUCT_THREAD + _THREAD_STRUCT_SWITCH_SP)) = R29;
H A Dhead.S167 memw(R1 ++ #4) = R0
H A Dtraps.c388 * GPR R0 carries the first parameter, and is also used do_trap0()
/linux-4.4.14/arch/blackfin/kernel/
H A Dfixed_code.S37 * Output: R0: old contents of the memory address, zero extended.
40 R0 = [P0]; define
53 * Output: R0: old contents of the memory address.
56 R0 = [P0]; define
57 CC = R0 == R1;
68 * R0: value to add
69 * Outputs: R0: new contents of the memory address.
74 R0 = R1 + R0; define
75 [P0] = R0;
83 * R0: value to subtract
84 * Outputs: R0: new contents of the memory address.
89 R0 = R1 - R0; define
90 [P0] = R0;
98 * R0: value to ior
99 * Outputs: R0: new contents of the memory address.
104 R0 = R1 | R0; define
105 [P0] = R0;
113 * R0: value to and
114 * Outputs: R0: new contents of the memory address.
119 R0 = R1 & R0; define
120 [P0] = R0;
128 * R0: value to xor
129 * Outputs: R0: new contents of the memory address.
134 R0 = R1 ^ R0; define
135 [P0] = R0;
H A Dftrace-entry.S27 * save/restore the registers used for argument passing (R0-R2) in case
H A Dpseudodbg.c13 "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7",
H A Dtrace.c959 pr_notice(" R0 : %08lx R1 : %08lx R2 : %08lx R3 : %08lx\n", show_regs()
/linux-4.4.14/lib/
H A Dtest_bpf.c45 #define R0 BPF_REG_0 macro
281 insn[1] = BPF_ALU32_IMM(BPF_MOV, R0, 0xcbababab); bpf_fill_maxinsns9()
285 insn[i] = BPF_ALU32_IMM(BPF_MOV, R0, 0xfefefefe); bpf_fill_maxinsns9()
312 insn[hlen] = BPF_ALU32_IMM(BPF_MOV, R0, 0xabababac); bpf_fill_maxinsns10()
402 insn[i] = BPF_JMP_IMM(BPF_JNE, R0, 0x34, len - i - 2); bpf_fill_ld_abs_vlan_push_pop()
409 insn[i] = BPF_JMP_IMM(BPF_JNE, R0, 0, len - i - 2); bpf_fill_ld_abs_vlan_push_pop()
415 insn[i] = BPF_JMP_IMM(BPF_JNE, R0, 0x34, len - i - 2); bpf_fill_ld_abs_vlan_push_pop()
420 insn[i] = BPF_JMP_IMM(BPF_JNE, R0, 0, len - i - 2); bpf_fill_ld_abs_vlan_push_pop()
427 insn[i] = BPF_ALU32_IMM(BPF_MOV, R0, 0xbef); bpf_fill_ld_abs_vlan_push_pop()
1062 BPF_ALU64_REG(BPF_MOV, R0, R1),
1072 BPF_ALU64_IMM(BPF_MOV, R0, -1),
1078 BPF_ALU64_IMM(BPF_MOV, R0, 1),
1088 BPF_ALU32_IMM(BPF_MOV, R0, -1),
1095 BPF_ALU32_IMM(BPF_MOV, R0, 1),
1105 BPF_ALU32_IMM(BPF_MOV, R0, -1),
1112 BPF_ALU32_IMM(BPF_MOV, R0, 1),
1126 BPF_ALU64_IMM(BPF_MOV, R0, 0),
1136 BPF_ALU64_IMM(BPF_ADD, R0, 20),
1146 BPF_ALU64_IMM(BPF_SUB, R0, 10),
1156 BPF_ALU64_REG(BPF_ADD, R0, R0),
1157 BPF_ALU64_REG(BPF_ADD, R0, R1),
1158 BPF_ALU64_REG(BPF_ADD, R0, R2),
1159 BPF_ALU64_REG(BPF_ADD, R0, R3),
1160 BPF_ALU64_REG(BPF_ADD, R0, R4),
1161 BPF_ALU64_REG(BPF_ADD, R0, R5),
1162 BPF_ALU64_REG(BPF_ADD, R0, R6),
1163 BPF_ALU64_REG(BPF_ADD, R0, R7),
1164 BPF_ALU64_REG(BPF_ADD, R0, R8),
1165 BPF_ALU64_REG(BPF_ADD, R0, R9), /* R0 == 155 */
1166 BPF_JMP_IMM(BPF_JEQ, R0, 155, 1),
1168 BPF_ALU64_REG(BPF_ADD, R1, R0),
1180 BPF_ALU64_REG(BPF_ADD, R2, R0),
1192 BPF_ALU64_REG(BPF_ADD, R3, R0),
1204 BPF_ALU64_REG(BPF_ADD, R4, R0),
1216 BPF_ALU64_REG(BPF_ADD, R5, R0),
1228 BPF_ALU64_REG(BPF_ADD, R6, R0),
1240 BPF_ALU64_REG(BPF_ADD, R7, R0),
1252 BPF_ALU64_REG(BPF_ADD, R8, R0),
1264 BPF_ALU64_REG(BPF_ADD, R9, R0),
1274 BPF_ALU64_REG(BPF_MOV, R0, R9),
1284 BPF_ALU32_IMM(BPF_MOV, R0, 20),
1303 BPF_ALU32_REG(BPF_ADD, R0, R1),
1304 BPF_ALU32_REG(BPF_ADD, R0, R2),
1305 BPF_ALU32_REG(BPF_ADD, R0, R3),
1306 BPF_ALU32_REG(BPF_ADD, R0, R4),
1307 BPF_ALU32_REG(BPF_ADD, R0, R5),
1308 BPF_ALU32_REG(BPF_ADD, R0, R6),
1309 BPF_ALU32_REG(BPF_ADD, R0, R7),
1310 BPF_ALU32_REG(BPF_ADD, R0, R8),
1311 BPF_ALU32_REG(BPF_ADD, R0, R9), /* R0 == 155 */
1312 BPF_JMP_IMM(BPF_JEQ, R0, 155, 1),
1314 BPF_ALU32_REG(BPF_ADD, R1, R0),
1326 BPF_ALU32_REG(BPF_ADD, R2, R0),
1338 BPF_ALU32_REG(BPF_ADD, R3, R0),
1350 BPF_ALU32_REG(BPF_ADD, R4, R0),
1362 BPF_ALU32_REG(BPF_ADD, R5, R0),
1374 BPF_ALU32_REG(BPF_ADD, R6, R0),
1386 BPF_ALU32_REG(BPF_ADD, R7, R0),
1398 BPF_ALU32_REG(BPF_ADD, R8, R0),
1410 BPF_ALU32_REG(BPF_ADD, R9, R0),
1420 BPF_ALU32_REG(BPF_MOV, R0, R9),
1430 BPF_ALU64_IMM(BPF_MOV, R0, 0),
1440 BPF_ALU64_REG(BPF_SUB, R0, R0),
1441 BPF_ALU64_REG(BPF_SUB, R0, R1),
1442 BPF_ALU64_REG(BPF_SUB, R0, R2),
1443 BPF_ALU64_REG(BPF_SUB, R0, R3),
1444 BPF_ALU64_REG(BPF_SUB, R0, R4),
1445 BPF_ALU64_REG(BPF_SUB, R0, R5),
1446 BPF_ALU64_REG(BPF_SUB, R0, R6),
1447 BPF_ALU64_REG(BPF_SUB, R0, R7),
1448 BPF_ALU64_REG(BPF_SUB, R0, R8),
1449 BPF_ALU64_REG(BPF_SUB, R0, R9),
1450 BPF_ALU64_IMM(BPF_SUB, R0, 10),
1451 BPF_JMP_IMM(BPF_JEQ, R0, -55, 1),
1453 BPF_ALU64_REG(BPF_SUB, R1, R0),
1463 BPF_ALU64_REG(BPF_SUB, R2, R0),
1473 BPF_ALU64_REG(BPF_SUB, R3, R0),
1483 BPF_ALU64_REG(BPF_SUB, R4, R0),
1493 BPF_ALU64_REG(BPF_SUB, R5, R0),
1503 BPF_ALU64_REG(BPF_SUB, R6, R0),
1513 BPF_ALU64_REG(BPF_SUB, R7, R0),
1523 BPF_ALU64_REG(BPF_SUB, R8, R0),
1533 BPF_ALU64_REG(BPF_SUB, R9, R0),
1543 BPF_ALU64_IMM(BPF_SUB, R0, 10),
1544 BPF_ALU64_IMM(BPF_NEG, R0, 0),
1545 BPF_ALU64_REG(BPF_SUB, R0, R1),
1546 BPF_ALU64_REG(BPF_SUB, R0, R2),
1547 BPF_ALU64_REG(BPF_SUB, R0, R3),
1548 BPF_ALU64_REG(BPF_SUB, R0, R4),
1549 BPF_ALU64_REG(BPF_SUB, R0, R5),
1550 BPF_ALU64_REG(BPF_SUB, R0, R6),
1551 BPF_ALU64_REG(BPF_SUB, R0, R7),
1552 BPF_ALU64_REG(BPF_SUB, R0, R8),
1553 BPF_ALU64_REG(BPF_SUB, R0, R9),
1563 BPF_ALU64_REG(BPF_SUB, R0, R0),
1565 BPF_JMP_REG(BPF_JEQ, R0, R1, 1),
1567 BPF_ALU64_IMM(BPF_MOV, R0, 10),
1575 BPF_ALU64_IMM(BPF_MOV, R0, 10),
1611 BPF_ALU64_REG(BPF_XOR, R0, R0),
1612 BPF_JMP_REG(BPF_JEQ, R9, R0, 1),
1615 BPF_ALU64_REG(BPF_XOR, R0, R0),
1616 BPF_JMP_REG(BPF_JEQ, R9, R0, 2),
1617 BPF_ALU64_IMM(BPF_MOV, R0, 0),
1619 BPF_ALU64_IMM(BPF_MOV, R0, 1),
1629 BPF_ALU64_IMM(BPF_MOV, R0, 11),
1639 BPF_ALU64_REG(BPF_MUL, R0, R0),
1640 BPF_ALU64_REG(BPF_MUL, R0, R1),
1641 BPF_ALU64_REG(BPF_MUL, R0, R2),
1642 BPF_ALU64_REG(BPF_MUL, R0, R3),
1643 BPF_ALU64_REG(BPF_MUL, R0, R4),
1644 BPF_ALU64_REG(BPF_MUL, R0, R5),
1645 BPF_ALU64_REG(BPF_MUL, R0, R6),
1646 BPF_ALU64_REG(BPF_MUL, R0, R7),
1647 BPF_ALU64_REG(BPF_MUL, R0, R8),
1648 BPF_ALU64_REG(BPF_MUL, R0, R9),
1649 BPF_ALU64_IMM(BPF_MUL, R0, 10),
1650 BPF_JMP_IMM(BPF_JEQ, R0, 439084800, 1),
1652 BPF_ALU64_REG(BPF_MUL, R1, R0),
1670 BPF_ALU64_REG(BPF_MUL, R2, R0),
1681 BPF_ALU64_REG(BPF_MOV, R0, R2),
1691 BPF_ALU64_IMM(BPF_MOV, R0, 11),
1692 BPF_ALU64_IMM(BPF_ADD, R0, -1),
1695 BPF_ALU64_REG(BPF_DIV, R0, R2),
1696 BPF_JMP_IMM(BPF_JEQ, R0, 10, 1),
1698 BPF_ALU64_IMM(BPF_MOD, R0, 3),
1699 BPF_JMP_IMM(BPF_JEQ, R0, 1, 1),
1701 BPF_ALU64_IMM(BPF_MOV, R0, -1),
1711 BPF_MOV64_IMM(R0, -1234),
1713 BPF_ALU32_REG(BPF_RSH, R0, R1),
1714 BPF_JMP_IMM(BPF_JEQ, R0, 0x7ffffd97, 1),
1717 BPF_ALU64_REG(BPF_LSH, R0, R2),
1719 BPF_JMP_REG(BPF_JEQ, R0, R4, 1),
1722 BPF_ALU64_REG(BPF_LSH, R0, R4), /* R0 <= 46 */
1724 BPF_ALU64_REG(BPF_ARSH, R0, R3),
1725 BPF_JMP_IMM(BPF_JEQ, R0, -617, 1),
1739 BPF_MOV64_IMM(R0, -1),
1752 BPF_ALU32_REG(BPF_DIV, R0, R2),
1753 BPF_ALU64_REG(BPF_MOV, R8, R0),
1755 BPF_ALU64_REG(BPF_ADD, R8, R0),
1769 BPF_ALU32_REG(BPF_DIV, R0, R7),
2111 BPF_ALU64_IMM(BPF_MOV, R0, 0),
2116 BPF_LD_IMM64(R0, 0x1ffffffffLL),
2117 BPF_ALU64_IMM(BPF_RSH, R0, 32), /* R0 = 1 */
2129 BPF_JMP_IMM(BPF_JNE, R0, 0x806, 28),
2131 BPF_JMP_IMM(BPF_JNE, R0, 0x806, 26),
2132 BPF_MOV32_IMM(R0, 18),
2133 BPF_STX_MEM(BPF_W, R10, R0, -64),
2136 BPF_STX_MEM(BPF_W, R10, R0, -60),
2137 BPF_MOV32_IMM(R0, 280971478),
2138 BPF_STX_MEM(BPF_W, R10, R0, -56),
2140 BPF_LDX_MEM(BPF_W, R0, R10, -60),
2141 BPF_ALU32_REG(BPF_SUB, R0, R7),
2142 BPF_JMP_IMM(BPF_JNE, R0, 0, 15),
2144 BPF_JMP_IMM(BPF_JNE, R0, 0x806, 13),
2145 BPF_MOV32_IMM(R0, 22),
2146 BPF_STX_MEM(BPF_W, R10, R0, -56),
2149 BPF_STX_MEM(BPF_W, R10, R0, -52),
2150 BPF_MOV32_IMM(R0, 17366),
2151 BPF_STX_MEM(BPF_W, R10, R0, -48),
2153 BPF_LDX_MEM(BPF_W, R0, R10, -52),
2154 BPF_ALU32_REG(BPF_SUB, R0, R7),
2155 BPF_JMP_IMM(BPF_JNE, R0, 0, 2),
2156 BPF_MOV32_IMM(R0, 256),
2158 BPF_MOV32_IMM(R0, 0),
2172 BPF_ALU32_REG(BPF_MOV, R0, R1),
2183 BPF_ALU32_REG(BPF_MOV, R0, R1),
2194 BPF_ALU64_REG(BPF_MOV, R0, R1),
2205 BPF_ALU64_REG(BPF_MOV, R0, R1),
2216 BPF_ALU32_IMM(BPF_MOV, R0, 2),
2226 BPF_ALU32_IMM(BPF_MOV, R0, 4294967295U),
2240 BPF_MOV32_IMM(R0, 2),
2242 BPF_MOV32_IMM(R0, 1),
2252 BPF_ALU64_IMM(BPF_MOV, R0, 2),
2262 BPF_ALU64_IMM(BPF_MOV, R0, 2147483647),
2276 BPF_MOV32_IMM(R0, 2),
2278 BPF_MOV32_IMM(R0, 1),
2292 BPF_MOV32_IMM(R0, 2),
2294 BPF_MOV32_IMM(R0, 1),
2305 BPF_LD_IMM64(R0, 1),
2307 BPF_ALU32_REG(BPF_ADD, R0, R1),
2317 BPF_LD_IMM64(R0, 1),
2319 BPF_ALU32_REG(BPF_ADD, R0, R1),
2329 BPF_LD_IMM64(R0, 1),
2331 BPF_ALU64_REG(BPF_ADD, R0, R1),
2341 BPF_LD_IMM64(R0, 1),
2343 BPF_ALU64_REG(BPF_ADD, R0, R1),
2354 BPF_LD_IMM64(R0, 1),
2355 BPF_ALU32_IMM(BPF_ADD, R0, 2),
2365 BPF_LD_IMM64(R0, 3),
2366 BPF_ALU32_IMM(BPF_ADD, R0, 0),
2376 BPF_LD_IMM64(R0, 1),
2377 BPF_ALU32_IMM(BPF_ADD, R0, 4294967294U),
2391 BPF_MOV32_IMM(R0, 2),
2393 BPF_MOV32_IMM(R0, 1),
2403 BPF_LD_IMM64(R0, 1),
2404 BPF_ALU64_IMM(BPF_ADD, R0, 2),
2414 BPF_LD_IMM64(R0, 3),
2415 BPF_ALU64_IMM(BPF_ADD, R0, 0),
2425 BPF_LD_IMM64(R0, 1),
2426 BPF_ALU64_IMM(BPF_ADD, R0, 2147483646),
2436 BPF_LD_IMM64(R0, 2147483646),
2437 BPF_ALU64_IMM(BPF_ADD, R0, -2147483647),
2451 BPF_MOV32_IMM(R0, 2),
2453 BPF_MOV32_IMM(R0, 1),
2467 BPF_MOV32_IMM(R0, 2),
2469 BPF_MOV32_IMM(R0, 1),
2480 BPF_LD_IMM64(R0, 3),
2482 BPF_ALU32_REG(BPF_SUB, R0, R1),
2492 BPF_LD_IMM64(R0, 4294967295U),
2494 BPF_ALU32_REG(BPF_SUB, R0, R1),
2504 BPF_LD_IMM64(R0, 3),
2506 BPF_ALU64_REG(BPF_SUB, R0, R1),
2516 BPF_LD_IMM64(R0, 4294967295U),
2518 BPF_ALU64_REG(BPF_SUB, R0, R1),
2529 BPF_LD_IMM64(R0, 3),
2530 BPF_ALU32_IMM(BPF_SUB, R0, 1),
2540 BPF_LD_IMM64(R0, 3),
2541 BPF_ALU32_IMM(BPF_SUB, R0, 0),
2551 BPF_LD_IMM64(R0, 4294967295U),
2552 BPF_ALU32_IMM(BPF_SUB, R0, 4294967294U),
2562 BPF_LD_IMM64(R0, 3),
2563 BPF_ALU64_IMM(BPF_SUB, R0, 1),
2573 BPF_LD_IMM64(R0, 3),
2574 BPF_ALU64_IMM(BPF_SUB, R0, 0),
2584 BPF_LD_IMM64(R0, 4294967294U),
2585 BPF_ALU64_IMM(BPF_SUB, R0, 4294967295U),
2595 BPF_LD_IMM64(R0, 2147483646),
2596 BPF_ALU64_IMM(BPF_SUB, R0, 2147483647),
2607 BPF_LD_IMM64(R0, 2),
2609 BPF_ALU32_REG(BPF_MUL, R0, R1),
2619 BPF_LD_IMM64(R0, 2),
2621 BPF_ALU32_REG(BPF_MUL, R0, R1),
2631 BPF_LD_IMM64(R0, -1),
2633 BPF_ALU32_REG(BPF_MUL, R0, R1),
2643 BPF_LD_IMM64(R0, 2),
2645 BPF_ALU64_REG(BPF_MUL, R0, R1),
2655 BPF_LD_IMM64(R0, 1),
2657 BPF_ALU64_REG(BPF_MUL, R0, R1),
2668 BPF_LD_IMM64(R0, 2),
2669 BPF_ALU32_IMM(BPF_MUL, R0, 3),
2679 BPF_LD_IMM64(R0, 3),
2680 BPF_ALU32_IMM(BPF_MUL, R0, 1),
2690 BPF_LD_IMM64(R0, 2),
2691 BPF_ALU32_IMM(BPF_MUL, R0, 0x7FFFFFF8),
2705 BPF_MOV32_IMM(R0, 2),
2707 BPF_MOV32_IMM(R0, 1),
2717 BPF_LD_IMM64(R0, 2),
2718 BPF_ALU64_IMM(BPF_MUL, R0, 3),
2728 BPF_LD_IMM64(R0, 3),
2729 BPF_ALU64_IMM(BPF_MUL, R0, 1),
2739 BPF_LD_IMM64(R0, 1),
2740 BPF_ALU64_IMM(BPF_MUL, R0, 2147483647),
2750 BPF_LD_IMM64(R0, 1),
2751 BPF_ALU64_IMM(BPF_MUL, R0, -2147483647),
2765 BPF_MOV32_IMM(R0, 2),
2767 BPF_MOV32_IMM(R0, 1),
2778 BPF_LD_IMM64(R0, 6),
2780 BPF_ALU32_REG(BPF_DIV, R0, R1),
2790 BPF_LD_IMM64(R0, 4294967295U),
2792 BPF_ALU32_REG(BPF_DIV, R0, R1),
2802 BPF_LD_IMM64(R0, 6),
2804 BPF_ALU64_REG(BPF_DIV, R0, R1),
2814 BPF_LD_IMM64(R0, 2147483647),
2816 BPF_ALU64_REG(BPF_DIV, R0, R1),
2831 BPF_MOV32_IMM(R0, 2),
2833 BPF_MOV32_IMM(R0, 1),
2844 BPF_LD_IMM64(R0, 6),
2845 BPF_ALU32_IMM(BPF_DIV, R0, 2),
2855 BPF_LD_IMM64(R0, 3),
2856 BPF_ALU32_IMM(BPF_DIV, R0, 1),
2866 BPF_LD_IMM64(R0, 4294967295U),
2867 BPF_ALU32_IMM(BPF_DIV, R0, 4294967295U),
2881 BPF_MOV32_IMM(R0, 2),
2883 BPF_MOV32_IMM(R0, 1),
2893 BPF_LD_IMM64(R0, 6),
2894 BPF_ALU64_IMM(BPF_DIV, R0, 2),
2904 BPF_LD_IMM64(R0, 3),
2905 BPF_ALU64_IMM(BPF_DIV, R0, 1),
2915 BPF_LD_IMM64(R0, 2147483647),
2916 BPF_ALU64_IMM(BPF_DIV, R0, 2147483647),
2930 BPF_MOV32_IMM(R0, 2),
2932 BPF_MOV32_IMM(R0, 1),
2943 BPF_LD_IMM64(R0, 3),
2945 BPF_ALU32_REG(BPF_MOD, R0, R1),
2955 BPF_LD_IMM64(R0, 4294967295U),
2957 BPF_ALU32_REG(BPF_MOD, R0, R1),
2967 BPF_LD_IMM64(R0, 3),
2969 BPF_ALU64_REG(BPF_MOD, R0, R1),
2979 BPF_LD_IMM64(R0, 2147483647),
2981 BPF_ALU64_REG(BPF_MOD, R0, R1),
2992 BPF_LD_IMM64(R0, 3),
2993 BPF_ALU32_IMM(BPF_MOD, R0, 2),
3003 BPF_LD_IMM64(R0, 3),
3004 BPF_ALU32_IMM(BPF_MOD, R0, 1),
3014 BPF_LD_IMM64(R0, 4294967295U),
3015 BPF_ALU32_IMM(BPF_MOD, R0, 4294967293U),
3025 BPF_LD_IMM64(R0, 3),
3026 BPF_ALU64_IMM(BPF_MOD, R0, 2),
3036 BPF_LD_IMM64(R0, 3),
3037 BPF_ALU64_IMM(BPF_MOD, R0, 1),
3047 BPF_LD_IMM64(R0, 2147483647),
3048 BPF_ALU64_IMM(BPF_MOD, R0, 2147483645),
3059 BPF_LD_IMM64(R0, 3),
3061 BPF_ALU32_REG(BPF_AND, R0, R1),
3071 BPF_LD_IMM64(R0, 0xffffffff),
3073 BPF_ALU32_REG(BPF_AND, R0, R1),
3083 BPF_LD_IMM64(R0, 3),
3085 BPF_ALU64_REG(BPF_AND, R0, R1),
3095 BPF_LD_IMM64(R0, 0xffffffff),
3097 BPF_ALU64_REG(BPF_AND, R0, R1),
3108 BPF_LD_IMM64(R0, 3),
3109 BPF_ALU32_IMM(BPF_AND, R0, 2),
3119 BPF_LD_IMM64(R0, 0xffffffff),
3120 BPF_ALU32_IMM(BPF_AND, R0, 0xffffffff),
3130 BPF_LD_IMM64(R0, 3),
3131 BPF_ALU64_IMM(BPF_AND, R0, 2),
3141 BPF_LD_IMM64(R0, 0xffffffff),
3142 BPF_ALU64_IMM(BPF_AND, R0, 0xffffffff),
3156 BPF_MOV32_IMM(R0, 2),
3158 BPF_MOV32_IMM(R0, 1),
3172 BPF_MOV32_IMM(R0, 2),
3174 BPF_MOV32_IMM(R0, 1),
3188 BPF_MOV32_IMM(R0, 2),
3190 BPF_MOV32_IMM(R0, 1),
3201 BPF_LD_IMM64(R0, 1),
3203 BPF_ALU32_REG(BPF_OR, R0, R1),
3213 BPF_LD_IMM64(R0, 0),
3215 BPF_ALU32_REG(BPF_OR, R0, R1),
3225 BPF_LD_IMM64(R0, 1),
3227 BPF_ALU64_REG(BPF_OR, R0, R1),
3237 BPF_LD_IMM64(R0, 0),
3239 BPF_ALU64_REG(BPF_OR, R0, R1),
3250 BPF_LD_IMM64(R0, 1),
3251 BPF_ALU32_IMM(BPF_OR, R0, 2),
3261 BPF_LD_IMM64(R0, 0),
3262 BPF_ALU32_IMM(BPF_OR, R0, 0xffffffff),
3272 BPF_LD_IMM64(R0, 1),
3273 BPF_ALU64_IMM(BPF_OR, R0, 2),
3283 BPF_LD_IMM64(R0, 0),
3284 BPF_ALU64_IMM(BPF_OR, R0, 0xffffffff),
3298 BPF_MOV32_IMM(R0, 2),
3300 BPF_MOV32_IMM(R0, 1),
3314 BPF_MOV32_IMM(R0, 2),
3316 BPF_MOV32_IMM(R0, 1),
3330 BPF_MOV32_IMM(R0, 2),
3332 BPF_MOV32_IMM(R0, 1),
3343 BPF_LD_IMM64(R0, 5),
3345 BPF_ALU32_REG(BPF_XOR, R0, R1),
3355 BPF_LD_IMM64(R0, 1),
3357 BPF_ALU32_REG(BPF_XOR, R0, R1),
3367 BPF_LD_IMM64(R0, 5),
3369 BPF_ALU64_REG(BPF_XOR, R0, R1),
3379 BPF_LD_IMM64(R0, 1),
3381 BPF_ALU64_REG(BPF_XOR, R0, R1),
3392 BPF_LD_IMM64(R0, 5),
3393 BPF_ALU32_IMM(BPF_XOR, R0, 6),
3403 BPF_LD_IMM64(R0, 1),
3404 BPF_ALU32_IMM(BPF_XOR, R0, 0xffffffff),
3414 BPF_LD_IMM64(R0, 5),
3415 BPF_ALU64_IMM(BPF_XOR, R0, 6),
3425 BPF_LD_IMM64(R0, 1),
3426 BPF_ALU64_IMM(BPF_XOR, R0, 0xffffffff),
3440 BPF_MOV32_IMM(R0, 2),
3442 BPF_MOV32_IMM(R0, 1),
3456 BPF_MOV32_IMM(R0, 2),
3458 BPF_MOV32_IMM(R0, 1),
3472 BPF_MOV32_IMM(R0, 2),
3474 BPF_MOV32_IMM(R0, 1),
3485 BPF_LD_IMM64(R0, 1),
3487 BPF_ALU32_REG(BPF_LSH, R0, R1),
3497 BPF_LD_IMM64(R0, 1),
3499 BPF_ALU32_REG(BPF_LSH, R0, R1),
3509 BPF_LD_IMM64(R0, 1),
3511 BPF_ALU64_REG(BPF_LSH, R0, R1),
3521 BPF_LD_IMM64(R0, 1),
3523 BPF_ALU64_REG(BPF_LSH, R0, R1),
3534 BPF_LD_IMM64(R0, 1),
3535 BPF_ALU32_IMM(BPF_LSH, R0, 1),
3545 BPF_LD_IMM64(R0, 1),
3546 BPF_ALU32_IMM(BPF_LSH, R0, 31),
3556 BPF_LD_IMM64(R0, 1),
3557 BPF_ALU64_IMM(BPF_LSH, R0, 1),
3567 BPF_LD_IMM64(R0, 1),
3568 BPF_ALU64_IMM(BPF_LSH, R0, 31),
3579 BPF_LD_IMM64(R0, 2),
3581 BPF_ALU32_REG(BPF_RSH, R0, R1),
3591 BPF_LD_IMM64(R0, 0x80000000),
3593 BPF_ALU32_REG(BPF_RSH, R0, R1),
3603 BPF_LD_IMM64(R0, 2),
3605 BPF_ALU64_REG(BPF_RSH, R0, R1),
3615 BPF_LD_IMM64(R0, 0x80000000),
3617 BPF_ALU64_REG(BPF_RSH, R0, R1),
3628 BPF_LD_IMM64(R0, 2),
3629 BPF_ALU32_IMM(BPF_RSH, R0, 1),
3639 BPF_LD_IMM64(R0, 0x80000000),
3640 BPF_ALU32_IMM(BPF_RSH, R0, 31),
3650 BPF_LD_IMM64(R0, 2),
3651 BPF_ALU64_IMM(BPF_RSH, R0, 1),
3661 BPF_LD_IMM64(R0, 0x80000000),
3662 BPF_ALU64_IMM(BPF_RSH, R0, 31),
3673 BPF_LD_IMM64(R0, 0xff00ff0000000000LL),
3675 BPF_ALU64_REG(BPF_ARSH, R0, R1),
3686 BPF_LD_IMM64(R0, 0xff00ff0000000000LL),
3687 BPF_ALU64_IMM(BPF_ARSH, R0, 40),
3698 BPF_ALU32_IMM(BPF_MOV, R0, 3),
3699 BPF_ALU32_IMM(BPF_NEG, R0, 0),
3709 BPF_ALU32_IMM(BPF_MOV, R0, -3),
3710 BPF_ALU32_IMM(BPF_NEG, R0, 0),
3720 BPF_LD_IMM64(R0, 3),
3721 BPF_ALU64_IMM(BPF_NEG, R0, 0),
3731 BPF_LD_IMM64(R0, -3),
3732 BPF_ALU64_IMM(BPF_NEG, R0, 0),
3743 BPF_LD_IMM64(R0, 0x0123456789abcdefLL),
3744 BPF_ENDIAN(BPF_FROM_BE, R0, 16),
3754 BPF_LD_IMM64(R0, 0x0123456789abcdefLL),
3755 BPF_ENDIAN(BPF_FROM_BE, R0, 32),
3756 BPF_ALU64_REG(BPF_MOV, R1, R0),
3758 BPF_ALU32_REG(BPF_ADD, R0, R1), /* R1 = 0 */
3768 BPF_LD_IMM64(R0, 0x0123456789abcdefLL),
3769 BPF_ENDIAN(BPF_FROM_BE, R0, 64),
3780 BPF_LD_IMM64(R0, 0x0123456789abcdefLL),
3781 BPF_ENDIAN(BPF_FROM_LE, R0, 16),
3791 BPF_LD_IMM64(R0, 0x0123456789abcdefLL),
3792 BPF_ENDIAN(BPF_FROM_LE, R0, 32),
3793 BPF_ALU64_REG(BPF_MOV, R1, R0),
3795 BPF_ALU32_REG(BPF_ADD, R0, R1), /* R1 = 0 */
3805 BPF_LD_IMM64(R0, 0x0123456789abcdefLL),
3806 BPF_ENDIAN(BPF_FROM_LE, R0, 64),
3817 BPF_ALU32_IMM(BPF_MOV, R0, 1),
3819 BPF_LDX_MEM(BPF_B, R0, R10, -40),
3829 BPF_ALU32_IMM(BPF_MOV, R0, 1),
3831 BPF_LDX_MEM(BPF_H, R0, R10, -40),
3841 BPF_LD_IMM64(R0, 0),
3844 BPF_LDX_MEM(BPF_B, R0, R10, -40),
3854 BPF_ALU32_IMM(BPF_MOV, R0, 1),
3856 BPF_LDX_MEM(BPF_H, R0, R10, -40),
3866 BPF_ALU32_IMM(BPF_MOV, R0, 1),
3868 BPF_LDX_MEM(BPF_H, R0, R10, -40),
3878 BPF_LD_IMM64(R0, 0),
3881 BPF_LDX_MEM(BPF_H, R0, R10, -40),
3891 BPF_ALU32_IMM(BPF_MOV, R0, 1),
3893 BPF_LDX_MEM(BPF_W, R0, R10, -40),
3903 BPF_ALU32_IMM(BPF_MOV, R0, 1),
3905 BPF_LDX_MEM(BPF_W, R0, R10, -40),
3915 BPF_LD_IMM64(R0, 0),
3918 BPF_LDX_MEM(BPF_W, R0, R10, -40),
3928 BPF_ALU32_IMM(BPF_MOV, R0, 1),
3930 BPF_LDX_MEM(BPF_DW, R0, R10, -40),
3945 BPF_MOV32_IMM(R0, 2),
3947 BPF_MOV32_IMM(R0, 1),
3957 BPF_ALU32_IMM(BPF_MOV, R0, 1),
3959 BPF_LDX_MEM(BPF_DW, R0, R10, -40),
3969 BPF_LD_IMM64(R0, 0),
3972 BPF_LDX_MEM(BPF_W, R0, R10, -40),
3983 BPF_ALU32_IMM(BPF_MOV, R0, 0x12),
3985 BPF_STX_XADD(BPF_W, R10, R0, -40),
3986 BPF_LDX_MEM(BPF_W, R0, R10, -40),
3996 BPF_ALU32_IMM(BPF_MOV, R0, 0x12),
3998 BPF_STX_XADD(BPF_DW, R10, R0, -40),
3999 BPF_LDX_MEM(BPF_DW, R0, R10, -40),
4010 BPF_ALU32_IMM(BPF_MOV, R0, 0x4711),
4012 BPF_ALU32_IMM(BPF_MOV, R0, 0x4712),
4022 BPF_ALU32_IMM(BPF_MOV, R0, 0),
4025 BPF_ALU32_IMM(BPF_MOV, R0, 1),
4036 BPF_ALU32_IMM(BPF_MOV, R0, 0),
4040 BPF_ALU32_IMM(BPF_MOV, R0, 1),
4050 BPF_ALU32_IMM(BPF_MOV, R0, 1),
4054 BPF_ALU32_IMM(BPF_MOV, R0, 0),
4065 BPF_ALU32_IMM(BPF_MOV, R0, 0),
4069 BPF_ALU32_IMM(BPF_MOV, R0, 1),
4079 BPF_ALU32_IMM(BPF_MOV, R0, 0),
4083 BPF_ALU32_IMM(BPF_MOV, R0, 1),
4094 BPF_ALU32_IMM(BPF_MOV, R0, 0),
4098 BPF_ALU32_IMM(BPF_MOV, R0, 1),
4109 BPF_ALU32_IMM(BPF_MOV, R0, 0),
4113 BPF_ALU32_IMM(BPF_MOV, R0, 1),
4125 BPF_ALU32_IMM(BPF_MOV, R0, 1), /* out: */
4127 BPF_ALU32_IMM(BPF_MOV, R0, 0), /* start: */
4139 BPF_ALU32_IMM(BPF_MOV, R0, 0),
4143 BPF_ALU32_IMM(BPF_MOV, R0, 1),
4154 BPF_ALU32_IMM(BPF_MOV, R0, 0),
4158 BPF_ALU32_IMM(BPF_MOV, R0, 1),
4169 BPF_ALU32_IMM(BPF_MOV, R0, 0),
4173 BPF_ALU32_IMM(BPF_MOV, R0, 1),
4184 BPF_ALU32_IMM(BPF_MOV, R0, 0),
4188 BPF_ALU32_IMM(BPF_MOV, R0, 1),
4198 BPF_ALU32_IMM(BPF_MOV, R0, 0),
4202 BPF_ALU32_IMM(BPF_MOV, R0, 1),
4213 BPF_ALU32_IMM(BPF_MOV, R0, 0),
4218 BPF_ALU32_IMM(BPF_MOV, R0, 1),
4228 BPF_ALU32_IMM(BPF_MOV, R0, 1),
4233 BPF_ALU32_IMM(BPF_MOV, R0, 0),
4244 BPF_ALU32_IMM(BPF_MOV, R0, 0),
4249 BPF_ALU32_IMM(BPF_MOV, R0, 1),
4259 BPF_ALU32_IMM(BPF_MOV, R0, 0),
4264 BPF_ALU32_IMM(BPF_MOV, R0, 1),
4275 BPF_ALU32_IMM(BPF_MOV, R0, 0),
4280 BPF_ALU32_IMM(BPF_MOV, R0, 1),
4291 BPF_ALU32_IMM(BPF_MOV, R0, 0),
4296 BPF_ALU32_IMM(BPF_MOV, R0, 1),
4306 BPF_ALU32_IMM(BPF_MOV, R0, 0),
4311 BPF_ALU32_IMM(BPF_MOV, R0, 1),
4322 BPF_ALU32_IMM(BPF_MOV, R0, 0),
4327 BPF_ALU32_IMM(BPF_MOV, R0, 1),
4338 BPF_ALU32_IMM(BPF_MOV, R0, 0),
4343 BPF_ALU32_IMM(BPF_MOV, R0, 1),
4354 BPF_ALU32_IMM(BPF_MOV, R0, 0),
4359 BPF_ALU32_IMM(BPF_MOV, R0, 1),
4369 BPF_ALU32_IMM(BPF_MOV, R0, 0),
4374 BPF_ALU32_IMM(BPF_MOV, R0, 1),
/linux-4.4.14/arch/x86/crypto/
H A Dtwofish-x86_64-asm_64.S42 #define R0 %rax define
239 encrypt_round(R0,R1,R2,R3,0);
240 encrypt_round(R2,R3,R0,R1,8);
241 encrypt_round(R0,R1,R2,R3,2*8);
242 encrypt_round(R2,R3,R0,R1,3*8);
243 encrypt_round(R0,R1,R2,R3,4*8);
244 encrypt_round(R2,R3,R0,R1,5*8);
245 encrypt_round(R0,R1,R2,R3,6*8);
246 encrypt_round(R2,R3,R0,R1,7*8);
247 encrypt_round(R0,R1,R2,R3,8*8);
248 encrypt_round(R2,R3,R0,R1,9*8);
249 encrypt_round(R0,R1,R2,R3,10*8);
250 encrypt_round(R2,R3,R0,R1,11*8);
251 encrypt_round(R0,R1,R2,R3,12*8);
252 encrypt_round(R2,R3,R0,R1,13*8);
253 encrypt_round(R0,R1,R2,R3,14*8);
254 encrypt_last_round(R2,R3,R0,R1,15*8);
261 xor R0, R1
292 decrypt_round(R0,R1,R2,R3,15*8);
293 decrypt_round(R2,R3,R0,R1,14*8);
294 decrypt_round(R0,R1,R2,R3,13*8);
295 decrypt_round(R2,R3,R0,R1,12*8);
296 decrypt_round(R0,R1,R2,R3,11*8);
297 decrypt_round(R2,R3,R0,R1,10*8);
298 decrypt_round(R0,R1,R2,R3,9*8);
299 decrypt_round(R2,R3,R0,R1,8*8);
300 decrypt_round(R0,R1,R2,R3,7*8);
301 decrypt_round(R2,R3,R0,R1,6*8);
302 decrypt_round(R0,R1,R2,R3,5*8);
303 decrypt_round(R2,R3,R0,R1,4*8);
304 decrypt_round(R0,R1,R2,R3,3*8);
305 decrypt_round(R2,R3,R0,R1,2*8);
306 decrypt_round(R0,R1,R2,R3,1*8);
307 decrypt_last_round(R2,R3,R0,R1,0);
313 xor R0, R1
H A Dtwofish-i586-asm_32.S244 encrypt_round(R0,R1,R2,R3,0);
245 encrypt_round(R2,R3,R0,R1,8);
246 encrypt_round(R0,R1,R2,R3,2*8);
247 encrypt_round(R2,R3,R0,R1,3*8);
248 encrypt_round(R0,R1,R2,R3,4*8);
249 encrypt_round(R2,R3,R0,R1,5*8);
250 encrypt_round(R0,R1,R2,R3,6*8);
251 encrypt_round(R2,R3,R0,R1,7*8);
252 encrypt_round(R0,R1,R2,R3,8*8);
253 encrypt_round(R2,R3,R0,R1,9*8);
254 encrypt_round(R0,R1,R2,R3,10*8);
255 encrypt_round(R2,R3,R0,R1,11*8);
256 encrypt_round(R0,R1,R2,R3,12*8);
257 encrypt_round(R2,R3,R0,R1,13*8);
258 encrypt_round(R0,R1,R2,R3,14*8);
259 encrypt_last_round(R2,R3,R0,R1,15*8);
301 decrypt_round(R0,R1,R2,R3,15*8);
302 decrypt_round(R2,R3,R0,R1,14*8);
303 decrypt_round(R0,R1,R2,R3,13*8);
304 decrypt_round(R2,R3,R0,R1,12*8);
305 decrypt_round(R0,R1,R2,R3,11*8);
306 decrypt_round(R2,R3,R0,R1,10*8);
307 decrypt_round(R0,R1,R2,R3,9*8);
308 decrypt_round(R2,R3,R0,R1,8*8);
309 decrypt_round(R0,R1,R2,R3,7*8);
310 decrypt_round(R2,R3,R0,R1,6*8);
311 decrypt_round(R0,R1,R2,R3,5*8);
312 decrypt_round(R2,R3,R0,R1,4*8);
313 decrypt_round(R0,R1,R2,R3,3*8);
314 decrypt_round(R2,R3,R0,R1,2*8);
315 decrypt_round(R0,R1,R2,R3,1*8);
316 decrypt_last_round(R2,R3,R0,R1,0);
/linux-4.4.14/arch/blackfin/include/asm/
H A Dentry.h60 [--sp] = R0; /*orig_r0*/ \
62 R0 = (N); \
69 [--sp] = R0; /*orig_r0*/ \
74 R0 = (N); \
85 [--sp] = R0; /*orig_r0*/ \
90 R0 = (N); \
111 [--sp] = R0; /*orig_r0*/ \
120 R0 = [P0]; \
121 CC = BITTST(R0, EVT_IVHW_P); \
127 R0 = (N); \
141 [--sp] = R0; /*orig_r0*/ \
150 R0 = [P0]; \
151 CC = BITTST(R0, EVT_IVHW_P); \
157 R0 = (N); \
H A Dcontext.S21 [--sp] = R0; /*orig_r0*/
94 [--sp] = R0; /*orig_r0*/
153 [--sp] = R0; /* orig_r0 */
H A Ddpmc.h20 #define PM_REG7 R0
121 M3 = R0;
620 R0 = 0x1;
621 [FP - 0xC] = R0;
/linux-4.4.14/arch/blackfin/mach-common/
H A Ddpmc_modes.S32 R0 = IWR_ENABLE(0); define
66 R4 = R0;
71 R0 = IWR_DISABLE_ALL; define
95 P3 = R0;
99 R0 = IWR_ENABLE(0); define
109 R0.L = 0xF;
110 W[P0] = R0.l; /* Set Max VCO to SCLK divider */
115 R0.L = (CONFIG_MIN_VCO_HZ/CONFIG_CLKIN_HZ) << 9;
116 W[P0] = R0.l; /* Set Min CLKIN to VCO multiplier */
139 R0 = P3; define
146 R0 = W[P0](z); define
147 BITSET (R0, 3);
148 W[P0] = R0.L; /* Turn CCLK OFF */
154 R0 = IWR_ENABLE(0); define
261 [P0 + (SIC_IWR0 - SYSMMR_BASE)] = R0;
269 [P0] = R0;
280 R0 = W[P0] (Z); define
281 CC = BITTST(R0,5);
293 R0 = M3; define
H A Dcache.S26 * R0 = start address
34 R0 = R0 & R2; define
42 R2 = R1 - R0;
49 P0 = R0;
H A Dhead.S32 /* R0: argument of command line string, passed from uboot, save it */
33 R7 = R0;
37 R0 = SYSCFG_SNEN; define
39 R0 = SYSCFG_SNEN | SYSCFG_CCEN; define
41 SYSCFG = R0;
45 * offset syntax. R0 = [P5 + <constant>];
220 R0 = R7; define
H A Dinterrupt.S35 * R0 contains the interrupt number, while R1 may contain the value of IPEND,
164 R0 = 0; define
175 R0 += 1;
190 R0 = R0 | R1; define
191 [sp + PT_SEQSTAT] = R0;
H A Dentry.S94 R0 = SEQSTAT; define
102 CC = R0 == 0;
/linux-4.4.14/arch/arm/include/asm/
H A Ddiv64.h159 asm ( "umull %Q0, %R0, %Q1, %Q2\n\t" \
166 asm ( "umlal %Q0, %R0, %Q1, %Q2\n\t" \
172 asm ( "umull %Q0, %R0, %Q1, %Q2\n\t" \
174 "adcs %R0, %R0, %R1\n\t" \
181 asm ( "umlal %R0, %Q0, %R1, %Q2\n\t" \
182 "umlal %R0, %Q0, %Q1, %R2\n\t" \
183 "mov %R0, #0\n\t" \
184 "umlal %Q0, %R0, %R1, %R2" \
189 asm ( "umlal %R0, %Q0, %R2, %Q3\n\t" \
190 "umlal %R0, %1, %Q2, %R3\n\t" \
191 "mov %R0, #0\n\t" \
193 "adc %R0, %R0, #0\n\t" \
194 "umlal %Q0, %R0, %R2, %R3" \
H A Datomic.h288 " " #op2 " %R0, %R0, %R4\n" \
309 " " #op2 " %R0, %R0, %R4\n" \
396 " sbc %R0, %R0, #0\n" atomic64_dec_if_positive()
397 " teq %R0, #0\n" atomic64_dec_if_positive()
428 " adc %R0, %R0, %R6\n" atomic64_add_unless()
H A Darch_timer.h86 asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (cval)); arch_counter_get_cntpct()
95 asm volatile("mrrc p15, 1, %Q0, %R0, c14" : "=r" (cval)); arch_counter_get_cntvct()
H A Dmemory.h185 "1: mov %R0, %1\n" \
195 " adc %R0, %R0, #0\n" \
H A Dproc-fns.h123 __asm__("mrrc p15, " #nr ", %Q0, %R0, c2" \
H A Darch_gicv3.h27 #define __ACCESS_CP15_64(Op1, CRm) p15, Op1, %Q0, %R0, CRm
/linux-4.4.14/arch/sh/kernel/cpu/sh3/
H A Dswsusp.S62 ! BL=0: R7->R0 is bank0
68 ! BL=1: R7->R0 is bank1
83 ! BL=0: R7->R0 is bank0
108 ! BL=0: R7->R0 is bank0
115 ! BL=1: R7->R0 is bank1
122 ! BL=0: R7->R0 is bank0
/linux-4.4.14/arch/blackfin/mach-bf561/
H A Dsecondary.S28 R0 = SYSCFG_SNEN; define
30 R0 = SYSCFG_SNEN | SYSCFG_CCEN; define
32 SYSCFG = R0;
36 * offset syntax. R0 = [P5 + <constant>];
145 R0 = IWR_DISABLE_ALL; define
148 [P0 + (SICB_IWR0 - SYSMMR_BASE)] = R0;
149 [P0 + (SICB_IWR1 - SYSMMR_BASE)] = R0;
/linux-4.4.14/sound/pci/oxygen/
H A Dwm8785.h9 /* R0 */
/linux-4.4.14/tools/perf/arch/arm/util/
H A Dunwind-libdw.c17 dwarf_regs[0] = REG(R0); libdw__arch_set_initial_registers()
/linux-4.4.14/tools/perf/arch/arm/tests/
H A Dregs_load.S3 #define R0 0x00 define
40 str r0, [r0, #R0]
/linux-4.4.14/drivers/misc/echo/
H A Dfir.h129 "R0.L = W[I0++] || R1.L = W[I1++];\n\t" dot_asm()
132 "A0 += R0.L * R1.L (IS) || R0.L = W[I0++] || R1.L = W[I1++];\n\t" dot_asm()
134 "A0 += R0.L*R1.L (IS);\n\t" dot_asm()
135 "R0 = A0;\n\t" dot_asm()
136 "%0 = R0;\n\t" dot_asm()
139 : "I0", "I1", "A1", "A0", "R0", "R1" dot_asm()
H A Decho.c153 R0 = W [P0++] (X); lms_adapt_bg()
154 R0 *= R2; lms_adapt_bg()
155 R0 = R0 + R3 (NS) || lms_adapt_bg()
158 R0 >>>= 15; lms_adapt_bg()
159 R0 = R0 + R1; lms_adapt_bg()
160 W [P1++] = R0; lms_adapt_bg()
/linux-4.4.14/arch/hexagon/mm/
H A Dstrnlen_user.S115 R0 = sub(start,isrc); define
121 R0 = add(max,#1); define
129 R0 = #0; define
/linux-4.4.14/drivers/media/usb/dvb-usb/
H A Ddigitv.h23 * <cmdbyte> VV <len> R0 R1 R2 R3
/linux-4.4.14/net/ax25/
H A Dax25_ds_subr.c47 * DB0ACH->DL1BKE <RR C P R0> [DAMA] ax25_ds_enquiry_response()
50 * DL1BKE->DB0ACH <RR R F R0> ax25_ds_enquiry_response()
55 * DB0ACH->DL1BKE <RR C P R0> [DAMA] ax25_ds_enquiry_response()
56 * DL1BKE->DB0ACH <RR R F R0> ax25_ds_enquiry_response()
/linux-4.4.14/arch/openrisc/include/uapi/asm/
H A Dptrace.h27 /* GPR R0-R31... */
/linux-4.4.14/arch/blackfin/mach-bf609/
H A Ddpm.S48 R0 = [P0]; define
54 [P1] = R0;
/linux-4.4.14/arch/arm/mach-iop13xx/
H A Dirq.c30 /* INTCTL0 CP6 R0 Page 4
82 /* INTSTR0 CP6 R0 Page 5
110 /* INTBASE CP6 R0 Page 2
/linux-4.4.14/arch/tile/include/asm/
H A Dkgdb.h27 * 56 GPRs(R0 - R52, TP, SP, LR), 8 special GPRs(networks and ZERO),
H A Dsyscall.h67 /* R0 is the passed-in negative error, R1 is positive. */ syscall_set_return_value()
/linux-4.4.14/arch/arm/boot/dts/
H A Dst-pincfg.h47 * R0, R1, R0D, R1D modes
/linux-4.4.14/arch/sh/math-emu/
H A Dmath.c50 #define R0 (regs->regs[0]) macro
160 READ(FRn, Rm + R0 + 4); fmov_idx_reg()
162 READ(FRn, Rm + R0); fmov_idx_reg()
164 READ(FRn, Rm + R0); fmov_idx_reg()
210 WRITE(FRm, Rn + R0 + 4); fmov_reg_idx()
212 WRITE(FRm, Rn + R0); fmov_reg_idx()
214 WRITE(FRm, Rn + R0); fmov_reg_idx()
/linux-4.4.14/drivers/net/hamradio/
H A Ddmascc.c504 if (read_scc(priv, R0) & Tx_BUF_EMP) { setup_adapter()
526 write_scc(priv, R0, RES_EXT_INT); setup_adapter()
545 write_scc(priv, R0, RES_EXT_INT); setup_adapter()
851 priv->rr0 = read_scc(priv, R0); scc_open()
1014 write_scc(priv, R0, RES_EOM_L); tx_on()
1023 while (read_scc(priv, R0) & Rx_CH_AV) rx_on()
1051 write_scc(priv, R0, ERR_RES); rx_on()
1112 write_scc(&info->priv[0], R0, RES_H_IUS); z8530_isr()
1167 write_scc(priv, R0, ERR_RES); rx_isr()
1172 while (read_scc(priv, R0) & Rx_CH_AV) { rx_isr()
1199 write_scc(priv, R0, ERR_RES); special_condition()
1298 write_scc(priv, R0, RES_Tx_P); tx_isr()
1303 while ((read_scc(priv, R0) & Tx_BUF_EMP) && p < priv->tx_len[i]) { tx_isr()
1309 write_scc(priv, R0, RES_EOM_L); tx_isr()
1321 rr0 = read_scc(priv, R0); es_isr()
1322 write_scc(priv, R0, RES_EXT_INT); es_isr()
1350 write_scc(priv, R0, RES_EXT_INT); es_isr()
1351 write_scc(priv, R0, RES_EXT_INT); es_isr()
1419 priv->rr0 = read_scc(priv, R0); tm_isr()
1446 priv->rr0 = read_scc(priv, R0); tm_isr()
H A Dscc.c399 OutReg(scc->ctrl, R0, RES_Tx_CRC); scc_txint()
436 status = InReg(scc->ctrl,R0); scc_exint()
652 OutReg(scc->ctrl,R0,RES_H_IUS); /* Reset Highest IUS */ scc_isr()
701 OutReg(scc->ctrl,R0,RES_H_IUS); scc_isr()
863 if(scc->kiss.softdcd || (InReg(scc->ctrl,R0) & DCD)) init_channel()
878 scc->status = InReg(scc->ctrl,R0); /* read initial status */ init_channel()
1251 OutReg(scc->ctrl, R0, RES_Tx_P); t_maxkeyup()
2065 seq_printf(seq, "\tR %2.2x %2.2x XX ", InReg(scc->ctrl,R0), InReg(scc->ctrl,R1)); scc_net_seq_show()
H A Dz8530.h6 #define R0 0 /* Register selects */ macro
/linux-4.4.14/drivers/tty/serial/
H A Dzs.c235 while ((read_zsreg(zport, R0) & Rx_CH_AV) && --loops) zs_receive_drain()
245 while (!(read_zsreg(zport, R0) & Tx_BUF_EMP) && --loops) { zs_transmit_drain()
327 status_a = read_zsreg(zport_a, R0); zs_raw_get_ab_mctrl()
328 status_b = read_zsreg(zport_b, R0); zs_raw_get_ab_mctrl()
424 write_zsreg(zport, R0, RES_Tx_P); zs_raw_stop_tx()
501 write_zsreg(zport_a, R0, RES_EXT_INT); zs_enable_ms()
550 avail = read_zsreg(zport, R0) & Rx_CH_AV; zs_receive_chars()
575 write_zsreg(zport, R0, ERR_RES); zs_receive_chars()
659 status = read_zsreg(zport, R0); zs_status_handle()
696 write_zsreg(zport, R0, RES_EXT_INT); zs_status_handle()
781 write_zsreg(zport, R0, ERR_RES); zs_startup()
782 write_zsreg(zport, R0, RES_Tx_P); zs_startup()
785 write_zsreg(zport, R0, RES_EXT_INT); zs_startup()
799 zport->brk = read_zsreg(zport, R0) & BRK_ABRT; zs_startup()
839 read_zsreg(zport, R0); zs_reset()
H A Dpmac_zilog.c186 write_zsreg(uap, R0, RES_EXT_INT); pmz_load_zsregs()
187 write_zsreg(uap, R0, RES_EXT_INT); pmz_load_zsregs()
254 write_zsreg(uap, R0, ERR_RES); pmz_receive_chars()
328 ch = read_zsreg(uap, R0); pmz_receive_chars()
344 status = read_zsreg(uap, R0); pmz_status_handle()
345 write_zsreg(uap, R0, RES_EXT_INT); pmz_status_handle()
378 unsigned char status = read_zsreg(uap, R0); pmz_transmit_chars()
447 write_zsreg(uap, R0, RES_Tx_P); pmz_transmit_chars()
477 write_zsreg(uap_a, R0, RES_H_IUS); pmz_interrupt()
502 write_zsreg(uap_b, R0, RES_H_IUS); pmz_interrupt()
530 status = read_zsreg(uap, R0); pmz_peek_status()
602 status = read_zsreg(uap, R0); pmz_get_mctrl()
639 status = read_zsreg(uap, R0); pmz_start_tx()
869 write_zsreg(uap, R0, ERR_RES); __pmz_startup()
870 write_zsreg(uap, R0, ERR_RES); __pmz_startup()
871 write_zsreg(uap, R0, RES_H_IUS); __pmz_startup()
872 write_zsreg(uap, R0, RES_H_IUS); __pmz_startup()
897 uap->prev_status = read_zsreg(uap, R0); __pmz_startup()
1163 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0 pmz_irda_setup()
1178 while (read_zsreg(uap, R0) & Rx_CH_AV) { pmz_irda_setup()
1201 while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) { pmz_irda_setup()
1218 while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) { pmz_irda_setup()
1360 if ((read_zsreg(uap, R0) & Rx_CH_AV) != 0) pmz_poll_get_char()
1375 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0) pmz_poll_put_char()
1962 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0) pmz_console_putchar()
H A Dip22zilog.c219 write_zsreg(channel, R0, RES_EXT_INT); __load_zsregs()
220 write_zsreg(channel, R0, RES_EXT_INT); __load_zsregs()
489 /* A convenient way to quickly get R0 status. The caller must _not_ hold the
708 (void) read_zsreg(channel, R0); __ip22zilog_reset()
H A Dip22zilog.h38 #define R0 0 /* Register selects */ macro
H A Dsunzilog.c252 write_zsreg(channel, R0, RES_EXT_INT); /* First Latch */ __load_zsregs()
253 write_zsreg(channel, R0, RES_EXT_INT); /* Second Latch */ __load_zsregs()
589 /* A convenient way to quickly get R0 status. The caller must _not_ hold the
1345 (void) read_zsreg(channel, R0); sunzilog_init_hw()
H A Dsunzilog.h30 #define R0 0 /* Register selects */ macro
H A Dzs.h59 #define R0 0 /* Register selects */ macro
H A Dpmac_zilog.h126 #define R0 0 /* Register selects */ macro
/linux-4.4.14/arch/m32r/kernel/
H A Dentry.S88 #define R0(reg) @(0x10,reg) define
133 ld r0, R0(r8)
210 st r0, R0(sp) ; save the return value
250 st r4, R0(sp)
280 st r4, R0(sp)
286 st r4, R0(sp)
H A Dprocess.c82 printk("R0 [%08lx]:R1 [%08lx]:R2 [%08lx]:R3 [%08lx]\n", \ show_regs()
/linux-4.4.14/arch/cris/arch-v32/drivers/
H A Diop_fw_load.c151 /* put start address in R0 */ iop_fw_load_mpu()
153 /* write to memory by executing 'SWX i, 4, R0' for each word */ iop_fw_load_mpu()
/linux-4.4.14/arch/sh/lib/
H A Dmemcpy.S38 mov r0,r3 ! Save the value on R0 to R3
43 mov r3,r0 ! and back to R0
H A Dmemmove.S48 mov r0,r3 ! Save the value on R0 to R3
53 mov r3,r0 ! and back to R0
/linux-4.4.14/tools/include/linux/
H A Dfilter.h131 /* Direct packet access, R0 = *(uint *) (skb->data + imm32) */
141 /* Indirect packet access, R0 = *(uint *) (skb->data + src_reg + imm32) */
/linux-4.4.14/samples/bpf/
H A Dsock_example.c45 BPF_LD_ABS(BPF_B, ETH_HLEN + offsetof(struct iphdr, protocol) /* R0 = ip->proto */), test_sock()
H A Dtest_verifier.c214 "program doesn't init R0 before exit",
219 .errstr = "R0 !read_ok",
223 "program doesn't init R0 before exit in all branches",
230 .errstr = "R0 !read_ok",
302 /* should be able to access R0 = *(R2 + 8) */
307 .errstr_unpriv = "R0 leaks addr",
320 /* fill back into R0 should fail */
454 .errstr = "R0 invalid mem access 'map_value_or_null'",
488 .errstr = "R0 invalid mem access",
489 .errstr_unpriv = "R0 leaks addr",
927 .errstr_unpriv = "R0 leaks addr",
1093 .errstr_unpriv = "R0 leaks addr",
H A Dlibbpf.h115 /* Direct packet access, R0 = *(uint *) (skb->data + imm32) */
/linux-4.4.14/arch/sh/include/asm/
H A Dsyscall_32.h61 /* Argument pattern is: R4, R5, R6, R7, R0, R1 */ syscall_get_arguments()
/linux-4.4.14/drivers/media/pci/cx88/
H A Dcx88-reg.h108 #define MO_DMA21_PTR1 0x300080 // {24}R0* DMA Current Ptr : Ch#21
109 #define MO_DMA22_PTR1 0x300084 // {24}R0* DMA Current Ptr : Ch#22
110 #define MO_DMA23_PTR1 0x300088 // {24}R0* DMA Current Ptr : Ch#23
111 #define MO_DMA24_PTR1 0x30008C // {24}R0* DMA Current Ptr : Ch#24
112 #define MO_DMA25_PTR1 0x300090 // {24}R0* DMA Current Ptr : Ch#25
113 #define MO_DMA26_PTR1 0x300094 // {24}R0* DMA Current Ptr : Ch#26
114 #define MO_DMA27_PTR1 0x300098 // {24}R0* DMA Current Ptr : Ch#27
115 #define MO_DMA28_PTR1 0x30009C // {24}R0* DMA Current Ptr : Ch#28
116 #define MO_DMA29_PTR1 0x3000A0 // {24}R0* DMA Current Ptr : Ch#29
117 #define MO_DMA30_PTR1 0x3000A4 // {24}R0* DMA Current Ptr : Ch#30
118 #define MO_DMA31_PTR1 0x3000A8 // {24}R0* DMA Current Ptr : Ch#31
119 #define MO_DMA32_PTR1 0x3000AC // {24}R0* DMA Current Ptr : Ch#32
/linux-4.4.14/arch/powerpc/mm/
H A Dtlb_nohash_low.S262 PPC_TLBILX_ALL(0,R0)
275 PPC_TLBILX_PID(0,R0)
327 PPC_TLBILX_PID(0,R0)
339 PPC_TLBILX_PID(0,R0)
346 PPC_TLBILX_ALL(0,R0)
/linux-4.4.14/drivers/net/wan/
H A Dz85230.c342 if(!(read_zsreg(c, R0)&1)) z8530_rx()
413 if(!(read_zsreg(c, R0)&4)) z8530_tx()
454 status = read_zsreg(chan, R0); z8530_status()
566 status=read_zsreg(chan, R0); z8530_dma_status()
674 u8 status=read_zsreg(chan, R0); z8530_status_clear()
838 chk=read_zsreg(c,R0); z8530_sync_close()
1031 chk=read_zsreg(c,R0); z8530_sync_dma_close()
1195 chk=read_zsreg(c,R0); z8530_sync_txdma_close()
1283 if(read_zsreg(&dev->chanA, R0)&Tx_BUF_EMP) do_z8530_init()
1406 c->status=read_zsreg(c, R0); z8530_channel_load()
1503 while(c->txcount && (read_zsreg(c,R0)&Tx_BUF_EMP)) z8530_tx_begin()
1622 write_zsreg(c, R0, RES_Rx_CRC); z8530_rx_done()
H A Dz85230.h25 #define R0 0 /* Register selects */ macro
/linux-4.4.14/arch/sh/kernel/
H A Dentry-common.S193 ! Reload R0-R4 from kernel stack, where the
195 ! ptrace(POKEUSR). (Note that R0-R2 are
270 * Arguments #4 to #6: R0, R1, R2
H A Dprocess_32.c48 printk("R0 : %08lx R1 : %08lx R2 : %08lx R3 : %08lx\n", show_regs()
H A Dtraps_32.c193 case 0x81: /* mov.w R0,@(disp,Rn) */ handle_unaligned_ins()
206 case 0x85: /* mov.w @(disp,Rm),R0 */ handle_unaligned_ins()
396 case 0x0100: /* mov.w R0,@(disp,Rm) */ handle_unaligned_access()
398 case 0x0500: /* mov.w @(disp,Rm),R0 */ handle_unaligned_access()
H A Dptrace_32.c322 * R0 --> R15
H A Dprocess_64.c73 printk("R0 : %08Lx%08Lx R1 : %08Lx%08Lx R2 : %08Lx%08Lx\n", show_regs()
/linux-4.4.14/arch/cris/arch-v32/kernel/
H A Dentry.S257 movem [$sp+], $r13 ; Registers R0-R13.
276 ;; R0 contains current at this point and irq's are disabled.
402 subq 14*4, $sp ; Make room for R0-R13.
403 movem $r13, [$sp] ; Push R0-R13.
460 subq 14*4, $sp ; Make room for R0-R13.
461 movem $r13, [$sp] ; Push R0-R13.
523 nop ; Empty delay-slot (cannot pop R0 here).
525 move.d [$sp+], $r0 ; Restore R0 in delay slot.
530 move.d [$sp+], $r0 ; Restore R0 in delay slot.
H A Dkgdb_asm.S29 move.d $r0, [$acr] ; Save R0 (start of register struct)
471 move.d [$acr], $r0 ; Restore R0
H A Dkgdb.c311 R0, R1, R2, R3, enumerator in enum:register_name
542 if (regno >= R0 && regno <= ACR) { write_register()
544 if (hex2bin((unsigned char *)&reg.r0 + (regno - R0) * sizeof(unsigned int), write_register()
595 if (regno >= R0 && regno <= ACR) { read_register()
597 *valptr = *(unsigned int *)((char *)&reg.r0 + (regno - R0) * sizeof(unsigned int)); read_register()
1496 Restart the target system. R0 handle_exception()
/linux-4.4.14/include/linux/
H A Dscc.h66 unsigned char status; /* Copy of R0 at last external interrupt */
H A Dfilter.h172 /* Direct packet access, R0 = *(uint *) (skb->data + imm32) */
182 /* Indirect packet access, R0 = *(uint *) (skb->data + src_reg + imm32) */
H A Dhp_sdc.h246 HIL MLC R0,R1 i8042 HIL watchdog */
258 #define HP_SDC_HIL_DAT 0x60 /* Data from HIL MLC R0 */
/linux-4.4.14/arch/arm/probes/kprobes/
H A Dactions-common.c137 /* Instruction only uses registers in the range R0..R12 */ kprobe_decode_ldmstm()
H A Dactions-thumb.c519 insn |= 0x001; /* Set Rdn = R1 and Rm = R0 */ t16_decode_hiregs()
H A Dtest-core.c165 * CPU register context. This should now have R0 holding the same value as
/linux-4.4.14/arch/blackfin/include/uapi/asm/
H A Dptrace.h13 * 0 - 7 are data registers R0-R7
/linux-4.4.14/arch/arm/mach-iop13xx/include/mach/
H A Dirqs.h7 /* INTPND0 CP6 R0 Page 3
H A Diop13xx.h19 /* CPUID CP6 R0 Page 0 */ iop13xx_cpu_id()
/linux-4.4.14/sound/soc/codecs/
H A Dwm8523.h39 * R0 (0x00) - DEVICE_ID
H A Dwm8741.h41 * R0 (0x00) - DACLLSB_ATTENUATION
H A Dsta529.c98 { 0, 0x35 }, /* R0 - FFX Configuration reg 0 */
H A Dwm8737.h44 * R0 (0x00) - Left PGA volume
H A Dwm8737.c50 { 0, 0x00C3 }, /* R0 - Left PGA volume */
H A Dwm8741.c52 { 0, 0x0000 }, /* R0 - DACLLSB Attenuation */
H A Dwm8961.c36 { 0, 0x009F }, /* R0 - Left Input volume */
H A Dwm8961.h97 * R0 (0x00) - Left Input volume
H A Dwm8990.h90 * R0 (0x00) - Reset
H A Dwm8991.h88 * R0 (0x00) - Reset
H A Dwm9081.h91 * R0 (0x00) - Software Reset
H A Dwm9090.h78 * R0 (0x00) - Software Reset
H A Dwm8903.h116 * R0 (0x00) - SW Reset and ID
H A Dwm8983.h82 * R0 (0x00) - Software Reset
H A Dwm8985.h80 * R0 (0x00) - Software Reset
H A Dwm8993.c761 SOC_ENUM("DRC R0", drc_r0),
H A Dwm8904.h139 * R0 (0x00) - SW Reset and ID
H A Dwm8903.c663 SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0),
H A Dwm8993.h134 * R0 (0x00) - Software Reset
H A Dwm5100-tables.c819 { 0x0000, 0x0000 }, /* R0 - software reset */
H A Dwm8962.c117 { 0, 0x009F }, /* R0 - Left Input volume */
H A Dwm2200.h533 * R0 (0x00) - software reset
H A Dwm8962.h1181 * R0 (0x00) - Left Input volume
H A Dwm8995.h756 * R0 (0x00) - Software Reset
H A Dwm8996.h748 * R0 (0x00) - Software Reset
H A Dwm5100.h895 * R0 (0x00) - software reset
/linux-4.4.14/arch/cris/arch-v10/kernel/
H A Dkgdb.c188 There are 16 general 32-bit registers, R0-R15, where R14 is the stack
296 There are 16 general 32-bit registers, R0-R15, where R14 is the stack
303 R0, R1, R2, R3, enumerator in enum:register_name
582 if (regno >= R0 && regno <= PC) { write_register()
621 if (regno >= R0 && regno <= PC) { read_register()
681 for (regno = R0; regno <= USP; regno++) { stub_is_stopped()
891 Restart the target system. R0 handle_exception()
928 " move.d $r0,[cris_reg] ; Save R0\n"
981 " move.d [cris_reg],$r0 ; Restore R0\n"
1024 " move.d $r0,[cris_reg] ; Save R0\n"
1079 " move.d [cris_reg],$r0 ; Restore R0\n"
/linux-4.4.14/drivers/media/i2c/
H A Dwm8739.c48 R0 = 0, R1, enumerator in enum:__anon5966
127 wm8739_write(sd, R0, (vol_l & 0x1f) | mute); wm8739_s_ctrl()
/linux-4.4.14/drivers/gpu/drm/msm/hdmi/
H A Dhdmi_hdcp.c814 /* read R0' from sink and pass it to HDCP engine */ hdmi_hdcp_auth_part1_recv_r0()
823 * Wait here at least 100ms before reading R0' hdmi_hdcp_auth_part1_recv_r0()
829 /* Read R0' at offset 0x08 */ hdmi_hdcp_auth_part1_recv_r0()
832 pr_err("%s:R0' read failed\n", __func__); hdmi_hdcp_auth_part1_recv_r0()
835 DBG("R0'=%02x%02x", buf[1], buf[0]); hdmi_hdcp_auth_part1_recv_r0()
837 /* Write R0' to HDCP registers and check to see if it is a match */ hdmi_hdcp_auth_part1_recv_r0()
844 /* Wait for authenticating result: R0/R0' are matched or not */ hdmi_hdcp_auth_part1_verify_r0()
/linux-4.4.14/arch/powerpc/lib/
H A Dldstfp.S335 2: LXVD2X(0,R0,R4)
364 2: STXVD2X(0,R0,R4)
/linux-4.4.14/arch/arm/vfp/
H A Dvfp.h50 "adcs %R0, %R2, %R4\n\t" add128()
63 "sbcs %R0, %R2, %R4\n\t" sub128()
/linux-4.4.14/arch/arm/mach-pxa/
H A Dpxa27x.c135 asm volatile("mra %Q0, %R0, acc0" : "=r" (acc0)); pxa27x_cpu_pm_enter()
154 asm volatile("mar acc0, %Q0, %R0" : "=r" (acc0)); pxa27x_cpu_pm_enter()
H A Dpxa3xx.c106 asm volatile("mra %Q0, %R0, acc0" : "=r" (acc0)); pxa3xx_cpu_pm_suspend()
136 asm volatile("mar acc0, %Q0, %R0" : "=r" (acc0)); pxa3xx_cpu_pm_suspend()
/linux-4.4.14/drivers/media/dvb-frontends/
H A Dtda826x.c90 /* with R0 = 0.35 and some transformations: */ tda826x_set_params()
H A Ddvb-pll.c513 /* byte 4 : 1 * * AGD R3 R2 R1 R0
515 * AGD = 1, R3 R2 R1 R0 = 0 1 0 1 => byte 4 = 1**10101 = 0x95
H A Dzl10036.c173 * 5[0x00]: P0 | C1 | C0 | R4 | R3 | R2 | R1 | R0
H A Ddrxk_hard.c189 u32 R0 = 0; Frac28a() local
191 R0 = (a % c) << 4; /* 32-28 == 4 shifts possible at max */ Frac28a()
199 Q1 = (Q1 << 4) | (R0 / c); Frac28a()
200 R0 = (R0 % c) << 4; Frac28a()
203 if ((R0 >> 3) >= c) Frac28a()
/linux-4.4.14/arch/hexagon/include/uapi/asm/
H A Dregisters.h26 long restart_r0; /* R0 checkpoint for syscall restart */
/linux-4.4.14/arch/arm/mach-omap2/
H A Dsleep24xx.S45 * R0 : DLL ctrl value pre-Sleep
/linux-4.4.14/drivers/hwmon/
H A Dds1621.c70 * |Done|THF |TLF |NVB | R1 | R0 |POL |1SHOT|
74 * |Done| X | X | U | R1 | R0 |POL |1SHOT|
H A Dds620.c38 * |Done|NVB |THF |TLF |R1 |R0 |AUTOC|1SHOT|
/linux-4.4.14/arch/powerpc/kernel/
H A Dmisc_64.S364 LBZCIX(R3,R0,R3)
379 STBCIX(R3,R0,R4)
513 PPC_TLBILX_ALL(0,R0)
H A Dexceptions-64e.S178 PPC_TLBILX_ALL(0,R0)
1257 PPC_TLBILX_ALL(0,R0)
1476 PPC_TLBILX(0,0,R0)
/linux-4.4.14/kernel/bpf/
H A Dverifier.c43 * R0 - return register
116 * R0->type = PTR_TO_MAP_VALUE_OR_NULL which means bpf_map_lookup_elem() function
124 * After the call R0 is set to return type of the function and registers R1-R5
1337 * preserve R6-R9, and store return value into R0
1347 * R0 - 8/16/32-bit skb data converted to cpu endianness
1392 /* mark destination R0 register as readable, since it contains check_ld_abs()
1913 /* eBPF calling convetion is such that R0 is used do_check()
1924 verbose("R0 leaks addr as return value\n"); do_check()
/linux-4.4.14/arch/arm/kernel/
H A Dentry-header.S27 * The SWI code relies on the fact that R0 is at the bottom of the stack
60 * xPSR, ReturnAddress(), LR (R14), R12, R3, R2, R1, and R0 are
H A Dunwind.c303 /* pop R0-R3 according to mask */ unwind_exec_pop_subset_r0_to_r3()
/linux-4.4.14/drivers/pinctrl/mediatek/
H A Dpinctrl-mtk-common.h204 * up/down bit, R0 and R1 resistor bit, so they need special pull setting.
H A Dpinctrl-mtk-common.c295 * they have separate pull up/down bit, R0 and R1 mtk_pconf_set_pull_select()
/linux-4.4.14/arch/sh/kernel/cpu/sh2/
H A Dentry.S111 mov.l @r2,r0 ! old R0
/linux-4.4.14/arch/sh/kernel/cpu/sh2a/
H A Dentry.S91 mov.l @r8+,r0 ! old R0
/linux-4.4.14/drivers/staging/rtl8188eu/hal/
H A DHal8188ERateAdaptive.c731 ("macid =%d Total =%d R0 =%d R1 =%d R2 =%d R3 =%d R4 =%d D0 =%d valid0 =%x valid1 =%x\n", ODM_RA_TxRPT2Handle_8188E()
754 ("macid =%d R0 =%d R1 =%d R2 =%d R3 =%d R4 =%d drop =%d valid0 =%x RateID =%d SGI =%d\n", ODM_RA_TxRPT2Handle_8188E()
/linux-4.4.14/crypto/
H A Dcast5_generic.c323 /* (L0,R0) <-- (m1...m64). (Split the plaintext into left and __cast5_encrypt()
324 * right 32-bit halves L0 = m1...m32 and R0 = m33...m64.) __cast5_encrypt()
/linux-4.4.14/arch/powerpc/include/asm/
H A Dppc_asm.h565 * case R0-R31 as they provide more error checking in the assembler.
566 * Use R0-31 only when really nessesary.
/linux-4.4.14/arch/powerpc/kvm/
H A Dbooke_interrupts.S218 stw r0, VCPU_GPR(R0)(r4)
427 lwz r0, VCPU_GPR(R0)(r4)
H A Dbookehv_interrupts.S386 PPC_STL r0, VCPU_GPR(R0)(r4)
649 PPC_LL r0, VCPU_GPR(R0)(r4)
H A Dbook3s_hv_rmhandlers.S1059 ld r0, VCPU_GPR(R0)(r4)
1126 std r0, VCPU_GPR(R0)(r9)
1765 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
1841 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
/linux-4.4.14/arch/arm64/net/
H A Dbpf_jit_comp.c641 /* R0 = ntohx(*(size *)(((struct sk_buff *)R6)->data + imm)) */ build_insn()
645 /* R0 = ntohx(*(size *)(((struct sk_buff *)R6)->data + src + imm)) */ build_insn()
/linux-4.4.14/drivers/media/radio/
H A Dradio-gemtek.c113 #define BU2614_STDF_BITS 3 /* R0..R2, Standard frequency data */
/linux-4.4.14/arch/sh/boards/
H A Dboard-magicpanelr2.c180 * R3 A21; R2 A20; R1 A19; R0 A0; setup_port_multiplexing()
/linux-4.4.14/include/linux/mfd/wm831x/
H A Dcore.h201 * R0 (0x00) - Reset ID
/linux-4.4.14/drivers/input/mouse/
H A Dvsxxxaa.c328 * [0]: 1 0 1 0 R3 R2 R1 R0 vsxxxaa_handle_POR_packet()
/linux-4.4.14/drivers/mfd/
H A Dwm8350-regmap.c27 { 0xFFFF, 0xFFFF, 0x0000 }, /* R0 - Reset/ID */
/linux-4.4.14/include/linux/mfd/wm8350/
H A Dcore.h78 * R0 (0x00) - Reset/ID
/linux-4.4.14/arch/hexagon/lib/
H A Dmemcpy.S151 #define ptr_out R0 /* destination pounter */
/linux-4.4.14/arch/arm/probes/
H A Ddecode.h252 * instruction will be modified to "AND R0, R2, R3, ASL R1" and then placed into
/linux-4.4.14/drivers/net/can/m_can/
H A Dm_can.c258 /* R0 */
268 /* R0 */
/linux-4.4.14/kernel/debug/
H A Dgdbstub.c678 /* For now, only honor R0 */ gdb_cmd_reboot()
679 if (strcmp(remcom_in_buffer, "R0") == 0) { gdb_cmd_reboot()
/linux-4.4.14/arch/unicore32/kernel/
H A Dentry.S31 * The SWI code relies on the fact that R0 is at the bottom of the stack
/linux-4.4.14/net/bluetooth/
H A Decc.c693 /* R0 and R1 */ ecc_point_mult()
/linux-4.4.14/arch/powerpc/net/
H A Dbpf_jit_comp.c39 EMIT(PPC_INST_MFLR | __PPC_RT(R0)); bpf_jit_build_prologue()
/linux-4.4.14/arch/arm/mach-tegra/
H A Dsleep-tegra30.S153 * and powergates it -- flags (in R0) indicate the request type.
/linux-4.4.14/drivers/mmc/host/
H A Ds3cmci.c183 dbg(host, dbg_debug, "%s R0:[%08x] R1:[%08x]" dbg_dumpregs()
216 dbg(host, dbglvl, "CMD[OK] %s R0:0x%08x\n", dbg_dumpcmd()
H A Drtsx_usb_sdmmc.c314 * R0 sd_send_cmd_get_rsp()
/linux-4.4.14/arch/sh/kernel/cpu/sh5/
H A Dentry.S77 /* Save R0/R1 : PT-migrating compiler currently dishounours -ffixed-r0 and -ffixed-r1 causing
514 /* Save SSR & SPC, together with R0 & R1, as we need to use 2 regs. */
/linux-4.4.14/lib/mpi/
H A Dlonglong.h880 __asm__ ("movw %1,%R0\n" \
/linux-4.4.14/include/linux/mfd/
H A Dwm8400-private.h124 * R0 (0x00) - Reset/ID
/linux-4.4.14/arch/microblaze/kernel/
H A Dentry.S770 swi r0, r1, PT_R0; /* R0 must be saved too */
/linux-4.4.14/drivers/media/dvb-frontends/drx39xyj/
H A Ddrxj.c1071 u32 R0 = 0; frac28() local
1073 R0 = (N % D) << 4; /* 32-28 == 4 shifts possible at max */ frac28()
1079 Q1 = (Q1 << 4) | R0 / D; frac28()
1080 R0 = (R0 % D) << 4; frac28()
1083 if ((R0 >> 3) >= D) frac28()
/linux-4.4.14/drivers/s390/block/
H A Ddasd_eckd.c2241 /* grant subsystem permission to format R0 */ dasd_eckd_build_format()
2250 /* grant subsystem permission to format R0 */ dasd_eckd_build_format()
/linux-4.4.14/include/linux/mfd/wm8994/
H A Dregisters.h911 * R0 (0x00) - Software Reset
/linux-4.4.14/include/linux/mfd/arizona/
H A Dregisters.h1211 * R0 (0x00) - software reset

Completed in 5140 milliseconds