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Searched refs:R0 (Results 1 – 88 of 88) sorted by relevance

/linux-4.4.14/arch/hexagon/kernel/
Dvm_entry.S50 memd(R0 + #_PT_R3130) = R31:30; \
51 { memw(R0 + #_PT_R2928) = R28; \
52 R31 = memw(R0 + #_PT_ER_VMPSP); }\
53 { memw(R0 + #(_PT_R2928 + 4)) = R31; \
55 { memd(R0 + #_PT_R2726) = R27:26; \
57 memd(R0 + #_PT_R2524) = R25:24; \
58 memd(R0 + #_PT_R2322) = R23:22; \
59 memd(R0 + #_PT_R2120) = R21:20; \
60 memd(R0 + #_PT_R1918) = R19:18; \
61 memd(R0 + #_PT_R1716) = R17:16; \
[all …]
Dvm_switch.S68 memw(R0+#_TASK_THREAD_INFO) = THREADINFO_REG;
69 memw(R0 +#(_TASK_STRUCT_THREAD + _THREAD_STRUCT_SWITCH_SP)) = R29;
Dhead.S167 memw(R1 ++ #4) = R0
/linux-4.4.14/arch/blackfin/lib/
Ddivsi3.S39 R3 = R0 ^ R1;
40 R0 = ABS R0; define
57 DIVS(R0, R1);
58 DIVQ(R0, R1);
59 DIVQ(R0, R1);
60 DIVQ(R0, R1);
61 DIVQ(R0, R1);
62 DIVQ(R0, R1);
63 DIVQ(R0, R1);
64 DIVQ(R0, R1);
[all …]
Dudivsi3.S20 CC = R0 < R1 (IU); /* If X < Y, always return 0 */
24 CC = R2 <= R0 (IU);
27 R2 = R0 >> 31; /* if X is a 31-bit number */
46 R0 <<= 1;
47 DIVQ(R0, R1); // 1
48 DIVQ(R0, R1); // 2
49 DIVQ(R0, R1); // 3
50 DIVQ(R0, R1); // 4
51 DIVQ(R0, R1); // 5
52 DIVQ(R0, R1); // 6
[all …]
Dins.S76 P0 = R0; /* P0 = port */ \
92 R0 = [P0]; \
93 [P1++] = R0; \
97 R0 = W[P0]; \
98 W[P1++] = R0; \
102 R0 = W[P0]; \
103 B[P1++] = R0; \
104 R0 = R0 >> 8; \
105 B[P1++] = R0; \
109 R0 = B[P0]; \
[all …]
Douts.S18 P0 = R0; /* P0 = port */
23 .Llong_loop_s: R0 = [P1++];
24 .Llong_loop_e: [P0] = R0;
31 P0 = R0; /* P0 = port */
36 .Lword_loop_s: R0 = W[P1++];
37 .Lword_loop_e: W[P0] = R0;
44 P0 = R0; /* P0 = port */
49 .Lbyte_loop_s: R0 = B[P1++];
50 .Lbyte_loop_e: B[P0] = R0;
57 P0 = R0; /* P0 = port */
[all …]
Dumulsi3_highpart.S18 R2 = R1.H * R0.H, R3 = R1.L * R0.H (FU);
19 R0 = R1.L * R0.L, R1 = R1.H * R0.L (FU); define
20 R0 >>= 16;
23 R0 = R0 + R3; define
24 R0 = R0 + R1; define
27 R1 = PACK(R1.l,R0.h);
28 R0 = R1 + R2; define
Dmemcmp.S23 P0 = R0; /* P0 = s1 address */
29 R1 = R1 | R0; /* OR addresses together */
42 R0 = [P0++]; define
45 MNOP || R0 = [P0++] || R1 = [I0++];
47 CC = R0 == R1;
61 R0 = B[P0++](Z); /* *s1 */ define
62 CC = R0 == R1;
68 R0 = R0 - R1; define
88 R0 = 0; define
Dmuldi3.S52 A0 += R3.H * R0.L, A1 += R3.L * R0.H (FU) || [SP] = R4; /* E1 */
55 A0 = R0.l * R3.l (FU); /* E2 */
58 A1 = R2.L * R0.L (FU); /* E4 */
61 A0 += R2.H * R0.H, A1 += R2.L * R0.H (FU); /* E2, E3c */
62 A1 += R0.L * R2.H (FU); /* E3c */
63 R0 = A1.w; define
69 R0 = PACK (R0.l, R3.l); define
Dstrncmp.S28 P0 = R0 ; /* s1 */
31 R0 = B[P0++] (Z); /* get *s1 */ define
33 CC = R0 == R1; /* compare a byte */
35 CC = R0; /* at end of s1? */
41 R0 = 0; /* strings are equal */ define
44 R0 = R0 - R1; /* *s1 - *s2 */ define
49 R0 = 0; define
Dumodsi3.S21 CC=R0==0;
25 CC=R0==R1;
29 CC = R0<R1 (IU);
34 R7 = R0; /* Copy of R0 */
39 R0 *= R6; /* Quotient * divisor */
40 R0 = R7 - R0; /* Dividend - (quotient * divisor) */ define
45 R0 = 0; define
Dstrncpy.S31 P0 = R0 ; /* dst*/
68 I1 = R0;
69 R0 = RETS; define
70 I0 = R0;
71 R0 = P0; define
73 R0 = I0; define
74 RETS = R0;
75 R0 = I1; define
Dmemset.S27 P0 = R0 ; /* P0 = address */
29 R3 = R0 + R2; /* end */
34 R2 = R0 & R2; /* addr bottom two bits */
72 CC = BITTST (R0, 0); /* odd byte */
73 R0 = 4; define
74 R0 = R0 - R2; define
75 P1 = R0;
76 R0 = P0; /* Recover return address */ define
Dmodsi3.S25 CC=R0==0;
29 CC=R0==R1;
41 R7 = R0; /* Copy of R0 */
46 R0 *= R6; /* Quotient * divisor */
47 R0 = R7 - R0; /* Dividend - (quotient * divisor) */ define
53 R0 = 0; define
Dsmulsi3_highpart.S18 R2 = R1.L * R0.L (FU);
19 R3 = R1.H * R0.L (IS,M);
20 R0 = R0.H * R1.H, R1 = R0.H * R1.L (IS,M); define
35 R0 = R0 + R1; define
Dstrcmp.S27 P0 = R0 ; /* s1 */
31 R0 = B[P0++] (Z); /* get *s1 */ define
33 CC = R0 == R1; /* compare a byte */
35 CC = R0; /* at end of s1? */
39 R0 = R0 - R1; /* *s1 - *s2 */ define
Dmemchr.S22 P0 = R0; /* P0 = address */
39 R0=0;
43 R0 = P0; define
44 R0 += -1;
Dmemcpy.S35 P0 = R0 ; /* dst*/
40 CC = R1 < R0; /* src < dst */
43 CC = R0 < R3; /* and dst < src+len */
49 R3 = R1 | R0;
Dmemmove.S21 P0 = R0; /* P0 = To address */
27 CC = R1 < R0 (IU); /* From < To */
30 CC = R0 <= R3 (IU); /* (From+len) >= To */
36 R3 = R1 | R0; /* OR addresses together */
Dstrcpy.S25 P0 = R0 ; /* dst*/
/linux-4.4.14/lib/
Dtest_bpf.c45 #define R0 BPF_REG_0 macro
281 insn[1] = BPF_ALU32_IMM(BPF_MOV, R0, 0xcbababab); in bpf_fill_maxinsns9()
285 insn[i] = BPF_ALU32_IMM(BPF_MOV, R0, 0xfefefefe); in bpf_fill_maxinsns9()
312 insn[hlen] = BPF_ALU32_IMM(BPF_MOV, R0, 0xabababac); in bpf_fill_maxinsns10()
402 insn[i] = BPF_JMP_IMM(BPF_JNE, R0, 0x34, len - i - 2); in bpf_fill_ld_abs_vlan_push_pop()
409 insn[i] = BPF_JMP_IMM(BPF_JNE, R0, 0, len - i - 2); in bpf_fill_ld_abs_vlan_push_pop()
415 insn[i] = BPF_JMP_IMM(BPF_JNE, R0, 0x34, len - i - 2); in bpf_fill_ld_abs_vlan_push_pop()
420 insn[i] = BPF_JMP_IMM(BPF_JNE, R0, 0, len - i - 2); in bpf_fill_ld_abs_vlan_push_pop()
427 insn[i] = BPF_ALU32_IMM(BPF_MOV, R0, 0xbef); in bpf_fill_ld_abs_vlan_push_pop()
1062 BPF_ALU64_REG(BPF_MOV, R0, R1),
[all …]
/linux-4.4.14/arch/blackfin/kernel/
Dfixed_code.S40 R0 = [P0]; define
56 R0 = [P0]; define
57 CC = R0 == R1;
74 R0 = R1 + R0; define
75 [P0] = R0;
89 R0 = R1 - R0; define
90 [P0] = R0;
104 R0 = R1 | R0; define
105 [P0] = R0;
119 R0 = R1 & R0; define
[all …]
/linux-4.4.14/arch/x86/crypto/
Dtwofish-x86_64-asm_64.S42 #define R0 %rax macro
239 encrypt_round(R0,R1,R2,R3,0);
240 encrypt_round(R2,R3,R0,R1,8);
241 encrypt_round(R0,R1,R2,R3,2*8);
242 encrypt_round(R2,R3,R0,R1,3*8);
243 encrypt_round(R0,R1,R2,R3,4*8);
244 encrypt_round(R2,R3,R0,R1,5*8);
245 encrypt_round(R0,R1,R2,R3,6*8);
246 encrypt_round(R2,R3,R0,R1,7*8);
247 encrypt_round(R0,R1,R2,R3,8*8);
[all …]
Dtwofish-i586-asm_32.S244 encrypt_round(R0,R1,R2,R3,0);
245 encrypt_round(R2,R3,R0,R1,8);
246 encrypt_round(R0,R1,R2,R3,2*8);
247 encrypt_round(R2,R3,R0,R1,3*8);
248 encrypt_round(R0,R1,R2,R3,4*8);
249 encrypt_round(R2,R3,R0,R1,5*8);
250 encrypt_round(R0,R1,R2,R3,6*8);
251 encrypt_round(R2,R3,R0,R1,7*8);
252 encrypt_round(R0,R1,R2,R3,8*8);
253 encrypt_round(R2,R3,R0,R1,9*8);
[all …]
/linux-4.4.14/arch/blackfin/include/asm/
Dentry.h60 [--sp] = R0; /*orig_r0*/ \
62 R0 = (N); \
69 [--sp] = R0; /*orig_r0*/ \
74 R0 = (N); \
85 [--sp] = R0; /*orig_r0*/ \
90 R0 = (N); \
111 [--sp] = R0; /*orig_r0*/ \
120 R0 = [P0]; \
121 CC = BITTST(R0, EVT_IVHW_P); \
127 R0 = (N); \
[all …]
Dcontext.S21 [--sp] = R0; /*orig_r0*/
94 [--sp] = R0; /*orig_r0*/
153 [--sp] = R0; /* orig_r0 */
Ddpmc.h20 #define PM_REG7 R0
121 M3 = R0;
620 R0 = 0x1;
621 [FP - 0xC] = R0;
/linux-4.4.14/arch/blackfin/mach-common/
Ddpmc_modes.S32 R0 = IWR_ENABLE(0); define
66 R4 = R0;
71 R0 = IWR_DISABLE_ALL; define
95 P3 = R0;
99 R0 = IWR_ENABLE(0); define
109 R0.L = 0xF;
110 W[P0] = R0.l; /* Set Max VCO to SCLK divider */
115 R0.L = (CONFIG_MIN_VCO_HZ/CONFIG_CLKIN_HZ) << 9;
116 W[P0] = R0.l; /* Set Min CLKIN to VCO multiplier */
139 R0 = P3; define
[all …]
Dcache.S34 R0 = R0 & R2; define
42 R2 = R1 - R0;
49 P0 = R0;
Dhead.S33 R7 = R0;
37 R0 = SYSCFG_SNEN; define
39 R0 = SYSCFG_SNEN | SYSCFG_CCEN; define
41 SYSCFG = R0;
220 R0 = R7; define
Dinterrupt.S164 R0 = 0; define
175 R0 += 1;
190 R0 = R0 | R1; define
191 [sp + PT_SEQSTAT] = R0;
Dentry.S94 R0 = SEQSTAT; define
102 CC = R0 == 0;
/linux-4.4.14/arch/blackfin/mach-bf561/
Dsecondary.S28 R0 = SYSCFG_SNEN; define
30 R0 = SYSCFG_SNEN | SYSCFG_CCEN; define
32 SYSCFG = R0;
145 R0 = IWR_DISABLE_ALL; define
148 [P0 + (SICB_IWR0 - SYSMMR_BASE)] = R0;
149 [P0 + (SICB_IWR1 - SYSMMR_BASE)] = R0;
/linux-4.4.14/arch/sh/kernel/cpu/sh3/
Dswsusp.S62 ! BL=0: R7->R0 is bank0
68 ! BL=1: R7->R0 is bank1
83 ! BL=0: R7->R0 is bank0
108 ! BL=0: R7->R0 is bank0
115 ! BL=1: R7->R0 is bank1
122 ! BL=0: R7->R0 is bank0
/linux-4.4.14/drivers/tty/serial/
Dpmac_zilog.c186 write_zsreg(uap, R0, RES_EXT_INT); in pmz_load_zsregs()
187 write_zsreg(uap, R0, RES_EXT_INT); in pmz_load_zsregs()
254 write_zsreg(uap, R0, ERR_RES); in pmz_receive_chars()
328 ch = read_zsreg(uap, R0); in pmz_receive_chars()
344 status = read_zsreg(uap, R0); in pmz_status_handle()
345 write_zsreg(uap, R0, RES_EXT_INT); in pmz_status_handle()
378 unsigned char status = read_zsreg(uap, R0); in pmz_transmit_chars()
447 write_zsreg(uap, R0, RES_Tx_P); in pmz_transmit_chars()
477 write_zsreg(uap_a, R0, RES_H_IUS); in pmz_interrupt()
502 write_zsreg(uap_b, R0, RES_H_IUS); in pmz_interrupt()
[all …]
Dzs.c235 while ((read_zsreg(zport, R0) & Rx_CH_AV) && --loops) in zs_receive_drain()
245 while (!(read_zsreg(zport, R0) & Tx_BUF_EMP) && --loops) { in zs_transmit_drain()
327 status_a = read_zsreg(zport_a, R0); in zs_raw_get_ab_mctrl()
328 status_b = read_zsreg(zport_b, R0); in zs_raw_get_ab_mctrl()
424 write_zsreg(zport, R0, RES_Tx_P); in zs_raw_stop_tx()
501 write_zsreg(zport_a, R0, RES_EXT_INT); in zs_enable_ms()
550 avail = read_zsreg(zport, R0) & Rx_CH_AV; in zs_receive_chars()
575 write_zsreg(zport, R0, ERR_RES); in zs_receive_chars()
659 status = read_zsreg(zport, R0); in zs_status_handle()
696 write_zsreg(zport, R0, RES_EXT_INT); in zs_status_handle()
[all …]
Dzs.h59 #define R0 0 /* Register selects */ macro
Dip22zilog.h38 #define R0 0 /* Register selects */ macro
Dsunzilog.h30 #define R0 0 /* Register selects */ macro
Dpmac_zilog.h126 #define R0 0 /* Register selects */ macro
Dip22zilog.c219 write_zsreg(channel, R0, RES_EXT_INT); in __load_zsregs()
220 write_zsreg(channel, R0, RES_EXT_INT); in __load_zsregs()
708 (void) read_zsreg(channel, R0); in __ip22zilog_reset()
Dsunzilog.c252 write_zsreg(channel, R0, RES_EXT_INT); /* First Latch */ in __load_zsregs()
253 write_zsreg(channel, R0, RES_EXT_INT); /* Second Latch */ in __load_zsregs()
1345 (void) read_zsreg(channel, R0); in sunzilog_init_hw()
/linux-4.4.14/arch/hexagon/mm/
Dstrnlen_user.S115 R0 = sub(start,isrc); define
121 R0 = add(max,#1); define
129 R0 = #0; define
/linux-4.4.14/drivers/net/hamradio/
Ddmascc.c504 if (read_scc(priv, R0) & Tx_BUF_EMP) { in setup_adapter()
526 write_scc(priv, R0, RES_EXT_INT); in setup_adapter()
545 write_scc(priv, R0, RES_EXT_INT); in setup_adapter()
851 priv->rr0 = read_scc(priv, R0); in scc_open()
1014 write_scc(priv, R0, RES_EOM_L); in tx_on()
1023 while (read_scc(priv, R0) & Rx_CH_AV) in rx_on()
1051 write_scc(priv, R0, ERR_RES); in rx_on()
1112 write_scc(&info->priv[0], R0, RES_H_IUS); in z8530_isr()
1167 write_scc(priv, R0, ERR_RES); in rx_isr()
1172 while (read_scc(priv, R0) & Rx_CH_AV) { in rx_isr()
[all …]
Dz8530.h6 #define R0 0 /* Register selects */ macro
Dscc.c399 OutReg(scc->ctrl, R0, RES_Tx_CRC); in scc_txint()
436 status = InReg(scc->ctrl,R0); in scc_exint()
652 OutReg(scc->ctrl,R0,RES_H_IUS); /* Reset Highest IUS */ in scc_isr()
701 OutReg(scc->ctrl,R0,RES_H_IUS); in scc_isr()
863 if(scc->kiss.softdcd || (InReg(scc->ctrl,R0) & DCD)) in init_channel()
878 scc->status = InReg(scc->ctrl,R0); /* read initial status */ in init_channel()
1251 OutReg(scc->ctrl, R0, RES_Tx_P); in t_maxkeyup()
2065 seq_printf(seq, "\tR %2.2x %2.2x XX ", InReg(scc->ctrl,R0), InReg(scc->ctrl,R1)); in scc_net_seq_show()
/linux-4.4.14/tools/perf/arch/arm/tests/
Dregs_load.S3 #define R0 0x00 macro
40 str r0, [r0, #R0]
/linux-4.4.14/drivers/net/wan/
Dz85230.c342 if(!(read_zsreg(c, R0)&1)) in z8530_rx()
413 if(!(read_zsreg(c, R0)&4)) in z8530_tx()
454 status = read_zsreg(chan, R0); in z8530_status()
566 status=read_zsreg(chan, R0); in z8530_dma_status()
674 u8 status=read_zsreg(chan, R0); in z8530_status_clear()
838 chk=read_zsreg(c,R0); in z8530_sync_close()
1031 chk=read_zsreg(c,R0); in z8530_sync_dma_close()
1195 chk=read_zsreg(c,R0); in z8530_sync_txdma_close()
1283 if(read_zsreg(&dev->chanA, R0)&Tx_BUF_EMP) in do_z8530_init()
1406 c->status=read_zsreg(c, R0); in z8530_channel_load()
[all …]
Dz85230.h25 #define R0 0 /* Register selects */ macro
/linux-4.4.14/arch/sh/math-emu/
Dmath.c50 #define R0 (regs->regs[0]) macro
160 READ(FRn, Rm + R0 + 4); in fmov_idx_reg()
162 READ(FRn, Rm + R0); in fmov_idx_reg()
164 READ(FRn, Rm + R0); in fmov_idx_reg()
210 WRITE(FRm, Rn + R0 + 4); in fmov_reg_idx()
212 WRITE(FRm, Rn + R0); in fmov_reg_idx()
214 WRITE(FRm, Rn + R0); in fmov_reg_idx()
/linux-4.4.14/arch/powerpc/mm/
Dtlb_nohash_low.S262 PPC_TLBILX_ALL(0,R0)
275 PPC_TLBILX_PID(0,R0)
327 PPC_TLBILX_PID(0,R0)
339 PPC_TLBILX_PID(0,R0)
346 PPC_TLBILX_ALL(0,R0)
/linux-4.4.14/arch/cris/arch-v10/kernel/
Dkgdb.c303 R0, R1, R2, R3, enumerator
582 if (regno >= R0 && regno <= PC) { in write_register()
621 if (regno >= R0 && regno <= PC) { in read_register()
681 for (regno = R0; regno <= USP; regno++) { in stub_is_stopped()
/linux-4.4.14/arch/cris/arch-v32/kernel/
Dentry.S257 movem [$sp+], $r13 ; Registers R0-R13.
276 ;; R0 contains current at this point and irq's are disabled.
402 subq 14*4, $sp ; Make room for R0-R13.
403 movem $r13, [$sp] ; Push R0-R13.
523 nop ; Empty delay-slot (cannot pop R0 here).
525 move.d [$sp+], $r0 ; Restore R0 in delay slot.
530 move.d [$sp+], $r0 ; Restore R0 in delay slot.
Dkgdb.c311 R0, R1, R2, R3, enumerator
542 if (regno >= R0 && regno <= ACR) { in write_register()
544 if (hex2bin((unsigned char *)&reg.r0 + (regno - R0) * sizeof(unsigned int), in write_register()
595 if (regno >= R0 && regno <= ACR) { in read_register()
597 *valptr = *(unsigned int *)((char *)&reg.r0 + (regno - R0) * sizeof(unsigned int)); in read_register()
Dkgdb_asm.S471 move.d [$acr], $r0 ; Restore R0
/linux-4.4.14/arch/blackfin/mach-bf609/
Ddpm.S48 R0 = [P0]; define
54 [P1] = R0;
/linux-4.4.14/arch/m32r/kernel/
Dentry.S88 #define R0(reg) @(0x10,reg) macro
133 ld r0, R0(r8)
/linux-4.4.14/Documentation/networking/
Dfilter.txt618 * R0 - return value from in-kernel function, and exit value for eBPF program
630 R0 - R5 are scratch registers and eBPF program needs spill/fill them if
674 After an in-kernel function call, R1 - R5 are reset to unreadable and R0 has
716 R0 - rax
739 bpf_mov R7, R0 /* save foo() return value */
746 bpf_add R0, R7
784 registers and place their return value into '%rax' which is R0 in eBPF.
786 interpreter. R0-R5 are scratch registers, so eBPF program needs to preserve
793 bpf_mov R0, R1
928 value into register R0 before doing a BPF_EXIT. Class 6 in eBPF is currently
[all …]
/linux-4.4.14/drivers/media/i2c/
Dwm8739.c48 R0 = 0, R1, enumerator
127 wm8739_write(sd, R0, (vol_l & 0x1f) | mute); in wm8739_s_ctrl()
/linux-4.4.14/tools/perf/arch/arm/util/
Dunwind-libdw.c17 dwarf_regs[0] = REG(R0); in libdw__arch_set_initial_registers()
/linux-4.4.14/arch/powerpc/kernel/
Dmisc_64.S364 LBZCIX(R3,R0,R3)
379 STBCIX(R3,R0,R4)
513 PPC_TLBILX_ALL(0,R0)
Dexceptions-64e.S178 PPC_TLBILX_ALL(0,R0)
1257 PPC_TLBILX_ALL(0,R0)
1476 PPC_TLBILX(0,0,R0)
/linux-4.4.14/arch/arm/include/asm/
Darch_gicv3.h27 #define __ACCESS_CP15_64(Op1, CRm) p15, Op1, %Q0, %R0, CRm
/linux-4.4.14/Documentation/hwmon/
Dds1621116 support, which is achieved via the R0 and R1 config register bits, where:
118 R0..R1
/linux-4.4.14/arch/powerpc/lib/
Dldstfp.S335 2: LXVD2X(0,R0,R4)
364 2: STXVD2X(0,R0,R4)
/linux-4.4.14/Documentation/devicetree/bindings/display/
Darm,pl11x.txt49 as R0 (first bit of the red component), second value
/linux-4.4.14/arch/m32r/platforms/oaks32r/
Ddot.gdbinit.nommu78 printf " R0[0x%08lX] R1[0x%08lX] R2[0x%08lX] R3[0x%08lX]\n",$r0,$r1,$r2,$r3
/linux-4.4.14/Documentation/devicetree/bindings/pinctrl/
Dpinctrl-mt65xx.txt61 Some special pins have extra pull up strength, there are R0 and R1 pull-up
/linux-4.4.14/arch/powerpc/kvm/
Dbooke_interrupts.S218 stw r0, VCPU_GPR(R0)(r4)
427 lwz r0, VCPU_GPR(R0)(r4)
Dbookehv_interrupts.S386 PPC_STL r0, VCPU_GPR(R0)(r4)
649 PPC_LL r0, VCPU_GPR(R0)(r4)
Dbook3s_hv_rmhandlers.S1059 ld r0, VCPU_GPR(R0)(r4)
1126 std r0, VCPU_GPR(R0)(r9)
1765 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
1841 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
/linux-4.4.14/arch/m32r/platforms/mappi3/
Ddot.gdbinit136 printf " R0[0x%08lX] R1[0x%08lX] R2[0x%08lX] R3[0x%08lX]\n",$r0,$r1,$r2,$r3
/linux-4.4.14/arch/m32r/platforms/mappi2/
Ddot.gdbinit.vdec2147 printf " R0[0x%08lX] R1[0x%08lX] R2[0x%08lX] R3[0x%08lX]\n",$r0,$r1,$r2,$r3
/linux-4.4.14/arch/sh/kernel/cpu/sh2a/
Dentry.S91 mov.l @r8+,r0 ! old R0
/linux-4.4.14/arch/m32r/platforms/m32700ut/
Ddot.gdbinit_400MHz_32MB148 printf " R0[0x%08lX] R1[0x%08lX] R2[0x%08lX] R3[0x%08lX]\n",$r0,$r1,$r2,$r3
Ddot.gdbinit_200MHz_16MB148 printf " R0[0x%08lX] R1[0x%08lX] R2[0x%08lX] R3[0x%08lX]\n",$r0,$r1,$r2,$r3
Ddot.gdbinit_300MHz_32MB148 printf " R0[0x%08lX] R1[0x%08lX] R2[0x%08lX] R3[0x%08lX]\n",$r0,$r1,$r2,$r3
/linux-4.4.14/arch/m32r/platforms/mappi/
Ddot.gdbinit164 printf " R0[0x%08lX] R1[0x%08lX] R2[0x%08lX] R3[0x%08lX]\n",$r0,$r1,$r2,$r3
Ddot.gdbinit.nommu164 printf " R0[0x%08lX] R1[0x%08lX] R2[0x%08lX] R3[0x%08lX]\n",$r0,$r1,$r2,$r3
Ddot.gdbinit.smp232 printf " R0[0x%08lX] R1[0x%08lX] R2[0x%08lX] R3[0x%08lX]\n",$r0,$r1,$r2,$r3
/linux-4.4.14/arch/hexagon/lib/
Dmemcpy.S151 #define ptr_out R0 /* destination pounter */
/linux-4.4.14/Documentation/devicetree/bindings/arm/
Darm,scpi.txt88 R0 and Juno R1 refer to [3].
/linux-4.4.14/arch/m32r/platforms/opsput/
Ddot.gdbinit173 printf " R0[%08lx] R1[%08lx] R2[%08lx] R3[%08lx]\n",$r0,$r1,$r2,$r3
/linux-4.4.14/arch/sh/kernel/cpu/sh2/
Dentry.S111 mov.l @r2,r0 ! old R0
/linux-4.4.14/arch/powerpc/net/
Dbpf_jit_comp.c39 EMIT(PPC_INST_MFLR | __PPC_RT(R0)); in bpf_jit_build_prologue()
/linux-4.4.14/drivers/media/dvb-frontends/
Ddrxk_hard.c189 u32 R0 = 0; in Frac28a() local
191 R0 = (a % c) << 4; /* 32-28 == 4 shifts possible at max */ in Frac28a()
199 Q1 = (Q1 << 4) | (R0 / c); in Frac28a()
200 R0 = (R0 % c) << 4; in Frac28a()
203 if ((R0 >> 3) >= c) in Frac28a()
/linux-4.4.14/drivers/media/dvb-frontends/drx39xyj/
Ddrxj.c1071 u32 R0 = 0; in frac28() local
1073 R0 = (N % D) << 4; /* 32-28 == 4 shifts possible at max */ in frac28()
1079 Q1 = (Q1 << 4) | R0 / D; in frac28()
1080 R0 = (R0 % D) << 4; in frac28()
1083 if ((R0 >> 3) >= D) in frac28()