32 	R0 = IWR_ENABLE(0);  define
66 	R4 = R0;
71 	R0 = IWR_DISABLE_ALL;  define
95 	P3 = R0;
99 	R0 = IWR_ENABLE(0);  define
109 	R0.L = 0xF;
110 	W[P0] = R0.l;		/* Set Max VCO to SCLK divider */
115 	R0.L = (CONFIG_MIN_VCO_HZ/CONFIG_CLKIN_HZ) << 9;
116 	W[P0] = R0.l;		/* Set Min CLKIN to VCO multiplier */
139 	R0 = P3;  define
146 	R0 = W[P0](z);  define
147 	BITSET (R0, 3);
148 	W[P0] = R0.L;		/* Turn CCLK OFF */
154 	R0 = IWR_ENABLE(0);  define
261 	[P0 + (SIC_IWR0 - SYSMMR_BASE)] = R0;
269 	[P0] = R0;
280 	R0 = W[P0] (Z);  define
281 	CC = BITTST(R0,5);
293 	R0 = M3;  define