Lines Matching refs:R0
50 memd(R0 + #_PT_R3130) = R31:30; \
51 { memw(R0 + #_PT_R2928) = R28; \
52 R31 = memw(R0 + #_PT_ER_VMPSP); }\
53 { memw(R0 + #(_PT_R2928 + 4)) = R31; \
55 { memd(R0 + #_PT_R2726) = R27:26; \
57 memd(R0 + #_PT_R2524) = R25:24; \
58 memd(R0 + #_PT_R2322) = R23:22; \
59 memd(R0 + #_PT_R2120) = R21:20; \
60 memd(R0 + #_PT_R1918) = R19:18; \
61 memd(R0 + #_PT_R1716) = R17:16; \
62 memd(R0 + #_PT_R1514) = R15:14; \
63 memd(R0 + #_PT_R1312) = R13:12; \
64 { memd(R0 + #_PT_R1110) = R11:10; \
66 { memd(R0 + #_PT_R0908) = R9:8; \
68 { memd(R0 + #_PT_R0706) = R7:6; \
70 { memd(R0 + #_PT_R0504) = R5:4; \
72 { memd(R0 + #_PT_GPUGP) = R31:30; \
75 { memd(R0 + #_PT_LC0SA0) = R15:14; \
78 { memd(R0 + #_PT_LC1SA1) = R13:12; \
81 { memd(R0 + #_PT_M1M0) = R11:10; \
83 R2 = and(R0,R2); } \
84 { memd(R0 + #_PT_PREDSUSR) = R15:14; \
87 memw(THREADINFO_REG + #_THREAD_INFO_PT_REGS) = R0; \
89 { memw(R0 + #_PT_SYSCALL_NR) = R2; \
95 { memd(R0 + #_PT_R3130) = R31:30; \
96 R30 = memw(R0 + #_PT_ER_VMPSP); }\
97 { memw(R0 + #_PT_R2928) = R28; \
98 memw(R0 + #(_PT_R2928 + 4)) = R30; }\
100 memd(R0 + #_PT_R2726) = R27:26; \
101 memd(R0 + #_PT_R2524) = R25:24; }\
102 { memd(R0 + #_PT_R2322) = R23:22; \
103 memd(R0 + #_PT_R2120) = R21:20; }\
104 { memd(R0 + #_PT_R1918) = R19:18; \
105 memd(R0 + #_PT_R1716) = R17:16; }\
106 { memd(R0 + #_PT_R1514) = R15:14; \
107 memd(R0 + #_PT_R1312) = R13:12; \
109 { memd(R0 + #_PT_R1110) = R11:10; \
110 memd(R0 + #_PT_R0908) = R9:8; \
112 { memd(R0 + #_PT_R0706) = R7:6; \
113 memd(R0 + #_PT_R0504) = R5:4; \
115 { memd(R0 + #_PT_GPUGP) = R31:30; \
116 memd(R0 + #_PT_LC0SA0) = R15:14; \
118 { THREADINFO_REG = and(R0, # ## #-_THREAD_SIZE); \
119 memd(R0 + #_PT_LC1SA1) = R13:12; \
121 { memd(R0 + #_PT_M1M0) = R11:10; \
122 memw(R0 + #_PT_PREDSUSR + 4) = R15; }\
124 memw(THREADINFO_REG + #_THREAD_INFO_PT_REGS) = R0; \
126 { memw(R0 + #_PT_SYSCALL_NR) = R2; \
127 memd(R0 + #_PT_CS1CS0) = R17:16; \
140 R15:14 = memd(R0 + #_PT_PREDSUSR); } \
141 { R11:10 = memd(R0 + #_PT_M1M0); \
143 { R13:12 = memd(R0 + #_PT_LC1SA1); \
145 { R15:14 = memd(R0 + #_PT_LC0SA0); \
147 { R3:2 = memd(R0 + #_PT_R0302); \
149 { R5:4 = memd(R0 + #_PT_R0504); \
151 { R7:6 = memd(R0 + #_PT_R0706); \
153 { R9:8 = memd(R0 + #_PT_R0908); \
155 { R11:10 = memd(R0 + #_PT_R1110); \
157 { R13:12 = memd(R0 + #_PT_R1312); \
158 R15:14 = memd(R0 + #_PT_R1514); } \
159 { R17:16 = memd(R0 + #_PT_R1716); \
160 R19:18 = memd(R0 + #_PT_R1918); } \
161 { R21:20 = memd(R0 + #_PT_R2120); \
162 R23:22 = memd(R0 + #_PT_R2322); } \
163 { R25:24 = memd(R0 + #_PT_R2524); \
164 R27:26 = memd(R0 + #_PT_R2726); } \
165 R31:30 = memd(R0 + #_PT_GPUGP); \
166 { R28 = memw(R0 + #_PT_R2928); \
168 { R31:30 = memd(R0 + #_PT_R3130); \
174 R15:14 = memd(R0 + #_PT_PREDSUSR); } \
175 { R11:10 = memd(R0 + #_PT_M1M0); \
176 R13:12 = memd(R0 + #_PT_LC1SA1); \
178 { R15:14 = memd(R0 + #_PT_LC0SA0); \
179 R3:2 = memd(R0 + #_PT_R0302); \
181 { R5:4 = memd(R0 + #_PT_R0504); \
182 R7:6 = memd(R0 + #_PT_R0706); \
184 { R9:8 = memd(R0 + #_PT_R0908); \
185 R11:10 = memd(R0 + #_PT_R1110); \
187 { R13:12 = memd(R0 + #_PT_R1312); \
188 R15:14 = memd(R0 + #_PT_R1514); \
190 { R17:16 = memd(R0 + #_PT_R1716); \
191 R19:18 = memd(R0 + #_PT_R1918); } \
192 { R21:20 = memd(R0 + #_PT_R2120); \
193 R23:22 = memd(R0 + #_PT_R2322); } \
194 { R25:24 = memd(R0 + #_PT_R2524); \
195 R27:26 = memd(R0 + #_PT_R2726); } \
196 R31:30 = memd(R0 + #_PT_CS1CS0); \
198 R31:30 = memd(R0 + #_PT_GPUGP) ; \
199 R28 = memw(R0 + #_PT_R2928); }\
201 R31:30 = memd(R0 + #_PT_R3130); }
228 R0 = R29; \
245 R0 = usr; \
248 memw(R29 + #_PT_PREDSUSR) = R0; \
249 R0 = setbit(R0, #16); \
251 usr = R0; \
259 R0 = R29; \
287 R0 = #VM_INT_DISABLE define
293 R0 = memw(R29 + #_PT_ER_VMEST); define
297 P0 = tstbit(R0, #HVM_VMEST_UM_SFT);
300 R0 = #VM_INT_DISABLE; define
314 R0 = R29; /* regs should still be at top of stack */ define
320 P0 = cmp.eq(R0, #0); if (!P0.new) jump:nt check_work_pending;
321 R0 = #VM_INT_DISABLE; define
344 R0 = R29 define
383 R0 = #VM_INT_DISABLE; define
387 R0 = R25; define
392 R0 = #VM_INT_DISABLE; define