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Searched refs:I915_WRITE (Results 1 – 39 of 39) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/i915/
Di915_suspend.c71 I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB); in i915_restore_display()
77 I915_WRITE(PCH_LVDS, dev_priv->regfile.saveLVDS & mask); in i915_restore_display()
79 I915_WRITE(LVDS, dev_priv->regfile.saveLVDS & mask); in i915_restore_display()
83 I915_WRITE(PCH_PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS); in i915_restore_display()
84 I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS); in i915_restore_display()
85 I915_WRITE(PCH_PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR); in i915_restore_display()
86 I915_WRITE(PCH_PP_CONTROL, dev_priv->regfile.savePP_CONTROL); in i915_restore_display()
88 I915_WRITE(PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS); in i915_restore_display()
89 I915_WRITE(PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS); in i915_restore_display()
90 I915_WRITE(PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR); in i915_restore_display()
[all …]
Dintel_sprite.c231 I915_WRITE(PLANE_KEYVAL(pipe, plane), key->min_value); in skl_update_plane()
232 I915_WRITE(PLANE_KEYMAX(pipe, plane), key->max_value); in skl_update_plane()
233 I915_WRITE(PLANE_KEYMSK(pipe, plane), key->channel_mask); in skl_update_plane()
259 I915_WRITE(PLANE_OFFSET(pipe, plane), plane_offset); in skl_update_plane()
260 I915_WRITE(PLANE_STRIDE(pipe, plane), stride); in skl_update_plane()
261 I915_WRITE(PLANE_SIZE(pipe, plane), plane_size); in skl_update_plane()
271 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); in skl_update_plane()
272 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); in skl_update_plane()
273 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y); in skl_update_plane()
274 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), in skl_update_plane()
[all …]
Dintel_guc_loader.c91 I915_WRITE(RING_MODE_GEN7(ring), irqs); in direct_interrupts_to_host()
94 I915_WRITE(GUC_BCS_RCS_IER, 0); in direct_interrupts_to_host()
95 I915_WRITE(GUC_VCS2_VCS1_IER, 0); in direct_interrupts_to_host()
96 I915_WRITE(GUC_WD_VECS_IER, 0); in direct_interrupts_to_host()
108 I915_WRITE(RING_MODE_GEN7(ring), irqs); in direct_interrupts_to_guc()
114 I915_WRITE(GUC_BCS_RCS_IER, ~irqs); in direct_interrupts_to_guc()
115 I915_WRITE(GUC_VCS2_VCS1_IER, ~irqs); in direct_interrupts_to_guc()
116 I915_WRITE(GUC_WD_VECS_IER, ~irqs); in direct_interrupts_to_guc()
183 I915_WRITE(SOFT_SCRATCH(0), 0); in set_guc_init_params()
186 I915_WRITE(SOFT_SCRATCH(1 + i), params[i]); in set_guc_init_params()
[all …]
Dintel_pm.c60 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | in bxt_init_clock_gating()
67 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | in bxt_init_clock_gating()
287 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0); in intel_set_memory_cxsr()
291 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0); in intel_set_memory_cxsr()
296 I915_WRITE(DSPFW3, val); in intel_set_memory_cxsr()
301 I915_WRITE(FW_BLC_SELF, val); in intel_set_memory_cxsr()
306 I915_WRITE(INSTPM, val); in intel_set_memory_cxsr()
643 I915_WRITE(DSPFW1, reg); in pineview_update_wm()
653 I915_WRITE(DSPFW3, reg); in pineview_update_wm()
662 I915_WRITE(DSPFW3, reg); in pineview_update_wm()
[all …]
Dintel_dsi.c74 I915_WRITE(reg, val); in write_data()
133 I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL); in intel_dsi_host_transfer()
140 I915_WRITE(ctrl_reg, header[2] << 16 | header[1] << 8 | header[0]); in intel_dsi_host_transfer()
226 I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT); in dpi_send_cmd()
232 I915_WRITE(MIPI_DPI_CONTROL(port), cmd); in dpi_send_cmd()
299 I915_WRITE(BXT_MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD); in bxt_dsi_device_ready()
306 I915_WRITE(MIPI_DEVICE_READY(port), val); in bxt_dsi_device_ready()
313 I915_WRITE(MIPI_DEVICE_READY(port), val); in bxt_dsi_device_ready()
320 I915_WRITE(MIPI_DEVICE_READY(port), val); in bxt_dsi_device_ready()
344 I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER); in vlv_dsi_device_ready()
[all …]
Di915_drv.c1229 I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark); in vlv_restore_gunit_s0ix_state()
1230 I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl); in vlv_restore_gunit_s0ix_state()
1231 I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16)); in vlv_restore_gunit_s0ix_state()
1232 I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0); in vlv_restore_gunit_s0ix_state()
1233 I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1); in vlv_restore_gunit_s0ix_state()
1236 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]); in vlv_restore_gunit_s0ix_state()
1238 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count); in vlv_restore_gunit_s0ix_state()
1239 I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count); in vlv_restore_gunit_s0ix_state()
1241 I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp); in vlv_restore_gunit_s0ix_state()
1242 I915_WRITE(GAM_ECOCHK, s->ecochk); in vlv_restore_gunit_s0ix_state()
[all …]
Di915_irq.c120 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
122 I915_WRITE(GEN8_##type##_IER(which), 0); \
123 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
125 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
130 I915_WRITE(type##IMR, 0xffffffff); \
132 I915_WRITE(type##IER, 0); \
133 I915_WRITE(type##IIR, 0xffffffff); \
135 I915_WRITE(type##IIR, 0xffffffff); \
151 I915_WRITE(reg, 0xffffffff); in gen5_assert_iir_is_zero()
153 I915_WRITE(reg, 0xffffffff); in gen5_assert_iir_is_zero()
[all …]
Dintel_tv.c862 I915_WRITE(TV_CTL, I915_READ(TV_CTL) | TV_ENC_ENABLE); in intel_enable_tv()
871 I915_WRITE(TV_CTL, I915_READ(TV_CTL) & ~TV_ENC_ENABLE); in intel_disable_tv()
989 I915_WRITE(TV_H_CTL_1, hctl1); in set_tv_mode_timings()
990 I915_WRITE(TV_H_CTL_2, hctl2); in set_tv_mode_timings()
991 I915_WRITE(TV_H_CTL_3, hctl3); in set_tv_mode_timings()
992 I915_WRITE(TV_V_CTL_1, vctl1); in set_tv_mode_timings()
993 I915_WRITE(TV_V_CTL_2, vctl2); in set_tv_mode_timings()
994 I915_WRITE(TV_V_CTL_3, vctl3); in set_tv_mode_timings()
995 I915_WRITE(TV_V_CTL_4, vctl4); in set_tv_mode_timings()
996 I915_WRITE(TV_V_CTL_5, vctl5); in set_tv_mode_timings()
[all …]
Dintel_audio.c181 I915_WRITE(reg_elda, tmp); in intel_eld_uptodate()
206 I915_WRITE(G4X_AUD_CNTL_ST, tmp); in g4x_audio_codec_disable()
236 I915_WRITE(G4X_AUD_CNTL_ST, tmp); in g4x_audio_codec_enable()
241 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); in g4x_audio_codec_enable()
245 I915_WRITE(G4X_AUD_CNTL_ST, tmp); in g4x_audio_codec_enable()
267 I915_WRITE(HSW_AUD_CFG(pipe), tmp); in hsw_audio_codec_disable()
273 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); in hsw_audio_codec_disable()
303 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); in hsw_audio_codec_enable()
315 I915_WRITE(HSW_AUD_DIP_ELD_CTRL(pipe), tmp); in hsw_audio_codec_enable()
320 I915_WRITE(HSW_AUD_EDID_DATA(pipe), *((uint32_t *)eld + i)); in hsw_audio_codec_enable()
[all …]
Dintel_ddi.c532 I915_WRITE(DDI_BUF_TRANS_LO(port, i), in intel_prepare_ddi_buffers()
534 I915_WRITE(DDI_BUF_TRANS_HI(port, i), in intel_prepare_ddi_buffers()
547 I915_WRITE(DDI_BUF_TRANS_LO(port, i), in intel_prepare_ddi_buffers()
549 I915_WRITE(DDI_BUF_TRANS_HI(port, i), in intel_prepare_ddi_buffers()
621 I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) | in hsw_fdi_link_train()
629 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); in hsw_fdi_link_train()
635 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); in hsw_fdi_link_train()
638 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel); in hsw_fdi_link_train()
645 I915_WRITE(DP_TP_CTL(PORT_E), in hsw_fdi_link_train()
655 I915_WRITE(DDI_BUF_CTL(PORT_E), in hsw_fdi_link_train()
[all …]
Dintel_i2c.c117 I915_WRITE(GMBUS0, 0); in intel_i2c_reset()
118 I915_WRITE(GMBUS4, 0); in intel_i2c_reset()
134 I915_WRITE(DSPCLK_GATE_D, val); in intel_i2c_quirk_set()
273 I915_WRITE(GMBUS4, gmbus4_irq_en); in gmbus_wait_hw_status()
287 I915_WRITE(GMBUS4, 0); in gmbus_wait_hw_status()
307 I915_WRITE(GMBUS4, GMBUS_IDLE_EN); in gmbus_wait_idle()
312 I915_WRITE(GMBUS4, 0); in gmbus_wait_idle()
326 I915_WRITE(GMBUS1, in gmbus_xfer_read_chunk()
388 I915_WRITE(GMBUS3, val); in gmbus_xfer_write_chunk()
389 I915_WRITE(GMBUS1, in gmbus_xfer_write_chunk()
[all …]
Dintel_fbc.c74 I915_WRITE(FBC_CONTROL, fbc_ctl); in i8xx_fbc_disable()
109 I915_WRITE(FBC_TAG(i), 0); in i8xx_fbc_enable()
117 I915_WRITE(FBC_CONTROL2, fbc_ctl2); in i8xx_fbc_enable()
118 I915_WRITE(FBC_FENCE_OFF, get_crtc_fence_y_offset(crtc)); in i8xx_fbc_enable()
129 I915_WRITE(FBC_CONTROL, fbc_ctl); in i8xx_fbc_enable()
156 I915_WRITE(DPFC_FENCE_YOFF, get_crtc_fence_y_offset(crtc)); in g4x_fbc_enable()
159 I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); in g4x_fbc_enable()
174 I915_WRITE(DPFC_CONTROL, dpfc_ctl); in g4x_fbc_disable()
187 I915_WRITE(MSG_FBC_REND_STATE, FBC_REND_NUKE); in intel_fbc_nuke()
223 I915_WRITE(ILK_DPFC_FENCE_YOFF, y_offset); in ilk_fbc_enable()
[all …]
Dintel_psr.c90 I915_WRITE(ctl_reg, 0); in intel_psr_write_vsc()
94 I915_WRITE(HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, in intel_psr_write_vsc()
99 I915_WRITE(HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, in intel_psr_write_vsc()
102 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW); in intel_psr_write_vsc()
119 I915_WRITE(VLV_VSCSDP(pipe), val); in vlv_psr_setup_vsc()
191 I915_WRITE(aux_data_reg + i, in hsw_psr_enable_sink()
206 I915_WRITE(aux_ctl_reg, val); in hsw_psr_enable_sink()
208 I915_WRITE(aux_ctl_reg, in hsw_psr_enable_sink()
227 I915_WRITE(VLV_PSRCTL(pipe), in vlv_psr_enable_source()
246 I915_WRITE(VLV_PSRCTL(pipe), I915_READ(VLV_PSRCTL(pipe)) | in vlv_psr_activate()
[all …]
Dintel_sideband.c60 I915_WRITE(VLV_IOSF_ADDR, addr); in vlv_sideband_rw()
62 I915_WRITE(VLV_IOSF_DATA, *val); in vlv_sideband_rw()
63 I915_WRITE(VLV_IOSF_DOORBELL_REQ, cmd); in vlv_sideband_rw()
73 I915_WRITE(VLV_IOSF_DATA, 0); in vlv_sideband_rw()
224 I915_WRITE(SBI_ADDR, (reg << 16)); in intel_sbi_read()
230 I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY); in intel_sbi_read()
254 I915_WRITE(SBI_ADDR, (reg << 16)); in intel_sbi_write()
255 I915_WRITE(SBI_DATA, value); in intel_sbi_write()
261 I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp); in intel_sbi_write()
Dintel_hdmi.c151 I915_WRITE(VIDEO_DIP_CTL, val); in g4x_write_infoframe()
155 I915_WRITE(VIDEO_DIP_DATA, *data); in g4x_write_infoframe()
160 I915_WRITE(VIDEO_DIP_DATA, 0); in g4x_write_infoframe()
167 I915_WRITE(VIDEO_DIP_CTL, val); in g4x_write_infoframe()
206 I915_WRITE(reg, val); in ibx_write_infoframe()
210 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); in ibx_write_infoframe()
215 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); in ibx_write_infoframe()
222 I915_WRITE(reg, val); in ibx_write_infoframe()
267 I915_WRITE(reg, val); in cpt_write_infoframe()
271 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); in cpt_write_infoframe()
[all …]
Dintel_panel.c579 I915_WRITE(BLC_PWM_PCH_CTL2, val | level); in lpt_set_backlight()
589 I915_WRITE(BLC_PWM_CPU_CTL, tmp | level); in pch_set_backlight()
617 I915_WRITE(BLC_PWM_CTL, tmp | level); in i9xx_set_backlight()
631 I915_WRITE(VLV_BLC_PWM_CTL(pipe), tmp | level); in vlv_set_backlight()
640 I915_WRITE(BXT_BLC_PWM_DUTY(panel->backlight.controller), level); in bxt_set_backlight()
746 I915_WRITE(BLC_PWM_CPU_CTL2, tmp & ~BLM_PWM_ENABLE); in lpt_disable_backlight()
750 I915_WRITE(BLC_PWM_PCH_CTL1, tmp & ~BLM_PCH_PWM_ENABLE); in lpt_disable_backlight()
762 I915_WRITE(BLC_PWM_CPU_CTL2, tmp & ~BLM_PWM_ENABLE); in pch_disable_backlight()
765 I915_WRITE(BLC_PWM_PCH_CTL1, tmp & ~BLM_PCH_PWM_ENABLE); in pch_disable_backlight()
782 I915_WRITE(BLC_PWM_CTL2, tmp & ~BLM_PWM_ENABLE); in i965_disable_backlight()
[all …]
Dintel_crt.c173 I915_WRITE(BCLRPAT(crtc->pipe), 0); in intel_crt_set_dpms()
190 I915_WRITE(crt->adpa_reg, adpa); in intel_crt_set_dpms()
295 I915_WRITE(crt->adpa_reg, adpa); in intel_ironlake_crt_detect_hotplug()
302 I915_WRITE(crt->adpa_reg, save_adpa); in intel_ironlake_crt_detect_hotplug()
332 I915_WRITE(crt->adpa_reg, adpa); in valleyview_crt_detect_hotplug()
337 I915_WRITE(crt->adpa_reg, save_adpa); in valleyview_crt_detect_hotplug()
401 I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS); in intel_crt_detect_hotplug()
518 I915_WRITE(bclrpat_reg, 0x500050); in intel_crt_load_detect()
522 I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER); in intel_crt_load_detect()
532 I915_WRITE(pipeconf_reg, pipeconf); in intel_crt_load_detect()
[all …]
Dintel_display.c1615 I915_WRITE(reg, dpll); in vlv_enable_pll()
1622 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md); in vlv_enable_pll()
1626 I915_WRITE(reg, dpll); in vlv_enable_pll()
1629 I915_WRITE(reg, dpll); in vlv_enable_pll()
1632 I915_WRITE(reg, dpll); in vlv_enable_pll()
1665 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); in chv_enable_pll()
1672 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); in chv_enable_pll()
1713 I915_WRITE(DPLL(!crtc->pipe), in i9xx_enable_pll()
1722 I915_WRITE(reg, 0); in i9xx_enable_pll()
1724 I915_WRITE(reg, dpll); in i9xx_enable_pll()
[all …]
Dintel_fifo_underrun.c112 I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS); in i9xx_check_fifo_underruns()
132 I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS); in i9xx_set_fifo_underrun_reporting()
159 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe)); in ivybridge_set_fifo_underrun_reporting()
187 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); in broadwell_set_fifo_underrun_reporting()
212 I915_WRITE(SERR_INT, in cpt_set_fifo_underrun_reporting()
Dintel_ringbuffer.h35 #define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val)
38 #define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val)
41 #define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val)
44 #define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)
47 #define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)
50 #define I915_WRITE_MODE(ring, val) I915_WRITE(RING_MI_MODE((ring)->mmio_base), val)
Dintel_dsi_pll.c305 I915_WRITE(BXT_DSI_PLL_ENABLE, val); in bxt_disable_dsi_pll()
430 I915_WRITE(MIPI_CTRL(port), temp | in vlv_dsi_reset_clocks()
468 I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp); in bxt_dsi_program_clocks()
513 I915_WRITE(BXT_DSI_PLL_CTL, val); in bxt_configure_dsi_pll()
533 I915_WRITE(BXT_DSI_PLL_ENABLE, val); in bxt_enable_dsi_pll()
549 I915_WRITE(BXT_DSI_PLL_ENABLE, val); in bxt_enable_dsi_pll()
592 I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp); in bxt_dsi_reset_clocks()
593 I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP); in bxt_dsi_reset_clocks()
Dintel_runtime_pm.c267 I915_WRITE(HSW_PWR_WELL_DRIVER, in hsw_set_power_well()
280 I915_WRITE(HSW_PWR_WELL_DRIVER, 0); in hsw_set_power_well()
430 I915_WRITE(DC_STATE_EN, val); in bxt_enable_dc9()
444 I915_WRITE(DC_STATE_EN, val); in bxt_disable_dc9()
457 I915_WRITE(DC_STATE_DEBUG, val); in gen9_set_dc_state_debugmask_memory_up()
509 I915_WRITE(DC_STATE_EN, val); in gen9_enable_dc5()
523 I915_WRITE(DC_STATE_EN, val); in gen9_disable_dc5()
568 I915_WRITE(DC_STATE_EN, val); in skl_enable_dc6()
582 I915_WRITE(DC_STATE_EN, val); in skl_disable_dc6()
648 I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask); in skl_set_power_well()
[all …]
Dintel_dvo.c178 I915_WRITE(dvo_reg, temp & ~DVO_ENABLE); in intel_disable_dvo()
194 I915_WRITE(dvo_reg, temp | DVO_ENABLE); in intel_enable_dvo()
290 I915_WRITE(dvo_srcdim_reg, in intel_dvo_pre_enable()
294 I915_WRITE(dvo_reg, dvo_val); in intel_dvo_pre_enable()
489 I915_WRITE(DPLL(pipe), dpll[pipe] | DPLL_DVO_2X_MODE); in intel_dvo_init()
496 I915_WRITE(DPLL(pipe), dpll[pipe]); in intel_dvo_init()
Di915_gem_fence.c84 I915_WRITE(fence_reg_lo, 0); in i965_write_fence_reg()
106 I915_WRITE(fence_reg_hi, val >> 32); in i965_write_fence_reg()
109 I915_WRITE(fence_reg_lo, val); in i965_write_fence_reg()
112 I915_WRITE(fence_reg_hi, 0); in i965_write_fence_reg()
152 I915_WRITE(FENCE_REG(reg), val); in i915_write_fence_reg()
184 I915_WRITE(FENCE_REG(reg), val); in i830_write_fence_reg()
Dintel_lvds.c200 I915_WRITE(lvds_encoder->reg, temp); in intel_pre_enable_lvds()
223 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN); in intel_enable_lvds()
225 I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON); in intel_enable_lvds()
248 I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON); in intel_disable_lvds()
252 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN); in intel_disable_lvds()
952 I915_WRITE(PCH_PP_CONTROL, in intel_lvds_init()
955 I915_WRITE(PP_CONTROL, in intel_lvds_init()
994 I915_WRITE(PP_ON_DELAYS, 0x019007d0); in intel_lvds_init()
997 I915_WRITE(PP_OFF_DELAYS, 0x015e07d0); in intel_lvds_init()
Dintel_ringbuffer.c479 I915_WRITE(HWS_PGA, addr); in ring_setup_phys_status_page()
518 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr); in intel_ring_setup_status_page()
534 I915_WRITE(reg, in intel_ring_setup_status_page()
914 I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) | in gen9_init_workarounds()
918 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | in gen9_init_workarounds()
1045 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | in skl_init_workarounds()
1049 I915_WRITE(FF_SLICE_CS_CHICKEN2, in skl_init_workarounds()
1058 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) | in skl_init_workarounds()
1063 I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) | in skl_init_workarounds()
1113 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF); in bxt_init_workarounds()
[all …]
Di915_gem_gtt.c913 I915_WRITE(offset, lower_32_bits(daddr)); in gen8_ppgtt_notify_vgt()
914 I915_WRITE(offset + 4, upper_32_bits(daddr)); in gen8_ppgtt_notify_vgt()
922 I915_WRITE(offset, lower_32_bits(daddr)); in gen8_ppgtt_notify_vgt()
923 I915_WRITE(offset + 4, upper_32_bits(daddr)); in gen8_ppgtt_notify_vgt()
932 I915_WRITE(vgtif_reg(g2v_notify), msg); in gen8_ppgtt_notify_vgt()
1681 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); in vgpu_mm_switch()
1682 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); in vgpu_mm_switch()
1727 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); in gen6_mm_switch()
1728 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); in gen6_mm_switch()
1743 I915_WRITE(RING_MODE_GEN7(ring), in gen8_ppgtt_enable()
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Dintel_dp.c353 I915_WRITE(intel_dp->output_reg, DP); in vlv_power_sequencer_kick()
356 I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN); in vlv_power_sequencer_kick()
359 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); in vlv_power_sequencer_kick()
594 I915_WRITE(pp_div_reg, pp_div | 0x1F); in edp_notify_handler()
595 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); in edp_notify_handler()
857 I915_WRITE(ch_data + i, in intel_dp_aux_ch()
862 I915_WRITE(ch_ctl, send_ctl); in intel_dp_aux_ch()
867 I915_WRITE(ch_ctl, in intel_dp_aux_ch()
1567 I915_WRITE(DP_A, dpa_ctl); in ironlake_set_pll_cpu_edp()
1643 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp); in intel_dp_prepare()
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Di915_guc_submission.c95 I915_WRITE(SOFT_SCRATCH(i), data[i]); in host2guc_action()
99 I915_WRITE(HOST2GUC_INTERRUPT, HOST2GUC_TRIGGER); in host2guc_action()
271 I915_WRITE(drbreg, I915_READ(drbreg) & ~GEN8_DRB_VALID); in guc_disable_doorbell()
276 I915_WRITE(GEN8_DRBREGU(client->doorbell_id), 0); in guc_disable_doorbell()
277 I915_WRITE(drbreg, 0); in guc_disable_doorbell()
673 I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE); in gem_allocate_guc_obj()
Dintel_uncore.c1413 I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE); in g4x_do_reset()
1423 I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE); in g4x_do_reset()
1436 I915_WRITE(ILK_GDSR, in ironlake_do_reset()
1443 I915_WRITE(ILK_GDSR, in ironlake_do_reset()
1450 I915_WRITE(ILK_GDSR, 0); in ironlake_do_reset()
1492 I915_WRITE(RING_RESET_CTL(engine->mmio_base), in gen8_do_reset()
1509 I915_WRITE(RING_RESET_CTL(engine->mmio_base), in gen8_do_reset()
Dintel_csr.c281 I915_WRITE(CSR_PROGRAM(i), payload[i]); in intel_csr_load_program()
284 I915_WRITE(dev_priv->csr.mmioaddr[i], in intel_csr_load_program()
Dintel_overlay.c1353 I915_WRITE(OGAMC0, attrs->gamma0); in intel_overlay_attrs()
1354 I915_WRITE(OGAMC1, attrs->gamma1); in intel_overlay_attrs()
1355 I915_WRITE(OGAMC2, attrs->gamma2); in intel_overlay_attrs()
1356 I915_WRITE(OGAMC3, attrs->gamma3); in intel_overlay_attrs()
1357 I915_WRITE(OGAMC4, attrs->gamma4); in intel_overlay_attrs()
1358 I915_WRITE(OGAMC5, attrs->gamma5); in intel_overlay_attrs()
Dintel_lrc.c557 I915_WRITE(RING_CONTEXT_STATUS_PTR(ring), in intel_lrc_irq_handler()
1032 I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE); in intel_lr_context_do_pin()
1473 I915_WRITE(RING_HWSTAM(ring->mmio_base), 0xffffffff); in gen8_init_common_ring()
1476 I915_WRITE(RING_HWS_PGA(ring->mmio_base), in gen8_init_common_ring()
1481 I915_WRITE(RING_MODE_GEN7(ring), in gen8_init_common_ring()
1531 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); in gen8_init_render_ring()
1533 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); in gen8_init_render_ring()
2437 I915_WRITE(RING_HWS_PGA(ring->mmio_base), in lrc_setup_hardware_status_page()
Di915_gem.c4671 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | in i915_gem_init_swizzling()
4677 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); in i915_gem_init_swizzling()
4679 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); in i915_gem_init_swizzling()
4681 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); in i915_gem_init_swizzling()
4683 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); in i915_gem_init_swizzling()
4692 I915_WRITE(RING_CTL(base), 0); in init_unused_ring()
4693 I915_WRITE(RING_HEAD(base), 0); in init_unused_ring()
4694 I915_WRITE(RING_TAIL(base), 0); in init_unused_ring()
4695 I915_WRITE(RING_START(base), 0); in init_unused_ring()
4776 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); in i915_gem_init_hw()
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Dintel_dp_mst.c182 I915_WRITE(PORT_CLK_SEL(port), in intel_mst_pre_enable_dp()
205 I915_WRITE(DP_TP_STATUS(port), temp); in intel_mst_pre_enable_dp()
Di915_debugfs.c1683 I915_WRITE(ILK_DPFC_CONTROL, val ? in i915_fbc_fc_set()
3651 I915_WRITE(PORT_DFT2_G4X, tmp); in vlv_pipe_crc_ctl_reg()
3719 I915_WRITE(PORT_DFT_I9XX, in i9xx_pipe_crc_ctl_reg()
3727 I915_WRITE(PORT_DFT2_G4X, tmp); in i9xx_pipe_crc_ctl_reg()
3754 I915_WRITE(PORT_DFT2_G4X, tmp); in vlv_undo_pipe_scramble_reset()
3768 I915_WRITE(PORT_DFT2_G4X, tmp); in g4x_undo_pipe_scramble_reset()
3771 I915_WRITE(PORT_DFT_I9XX, in g4x_undo_pipe_scramble_reset()
3936 I915_WRITE(PIPE_CRC_CTL(pipe), val); in pipe_crc_set_source()
4940 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); in i915_cache_sharing_set()
Dintel_sdvo.c249 I915_WRITE(intel_sdvo->sdvo_reg, val); in intel_sdvo_write_sdvox()
256 I915_WRITE(intel_sdvo->sdvo_reg, val); in intel_sdvo_write_sdvox()
274 I915_WRITE(GEN3_SDVOB, bval); in intel_sdvo_write_sdvox()
276 I915_WRITE(GEN3_SDVOC, cval); in intel_sdvo_write_sdvox()
Di915_dma.c1075 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY); in i915_driver_load()
Di915_drv.h3425 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true) macro