913 		I915_WRITE(offset, lower_32_bits(daddr));  in gen8_ppgtt_notify_vgt()
914 		I915_WRITE(offset + 4, upper_32_bits(daddr));  in gen8_ppgtt_notify_vgt()
922 			I915_WRITE(offset, lower_32_bits(daddr));  in gen8_ppgtt_notify_vgt()
923 			I915_WRITE(offset + 4, upper_32_bits(daddr));  in gen8_ppgtt_notify_vgt()
932 	I915_WRITE(vgtif_reg(g2v_notify), msg);  in gen8_ppgtt_notify_vgt()
1681 	I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);  in vgpu_mm_switch()
1682 	I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));  in vgpu_mm_switch()
1727 	I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);  in gen6_mm_switch()
1728 	I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));  in gen6_mm_switch()
1743 		I915_WRITE(RING_MODE_GEN7(ring),  in gen8_ppgtt_enable()
1756 	I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);  in gen7_ppgtt_enable()
1765 	I915_WRITE(GAM_ECOCHK, ecochk);  in gen7_ppgtt_enable()
1769 		I915_WRITE(RING_MODE_GEN7(ring),  in gen7_ppgtt_enable()
1780 	I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |  in gen6_ppgtt_enable()
1784 	I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);  in gen6_ppgtt_enable()
1787 	I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);  in gen6_ppgtt_enable()
1789 	I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));  in gen6_ppgtt_enable()
2286 			I915_WRITE(RING_FAULT_REG(ring),  in i915_check_and_clear_faults()
2298 		I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);  in i915_ggtt_flush()
2379 	I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);  in gen8_ggtt_insert_entries()
2423 	I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);  in gen6_ggtt_insert_entries()
2915 	I915_WRITE(GEN8_PRIVATE_PAT_LO, pat);  in bdw_setup_private_ppat()
2916 	I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32);  in bdw_setup_private_ppat()
2950 	I915_WRITE(GEN8_PRIVATE_PAT_LO, pat);  in chv_setup_private_ppat()
2951 	I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32);  in chv_setup_private_ppat()