Searched refs:GIC (Results 1 – 30 of 30) sorted by relevance
1 MIPS Global Interrupt Controller (GIC)3 The MIPS GIC routes external interrupts to individual VPEs and IRQ pins.5 interrupts which can be used as IPIs. The GIC also includes a free-running15 - The second cell is the GIC interrupt number.21 - reg : Base address and length of the GIC registers. If not present,24 to which the GIC may not route interrupts. Valid values are 2 - 7.29 - interrupts : Interrupt for the GIC local timer.32 - clocks : GIC timer operating clock.33 - clock-frequency : Clock frequency at which the GIC timers operate.
3 ARM SMP cores are often associated with a GIC, providing per processor7 Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.42 the 8 possible cpus attached to the GIC. A bit set to '1' indicated49 - reg : Specifies base physical address(s) and size of the GIC registers. The50 first region is the GIC distributor register base and size. The 2nd region is51 the GIC cpu interface register base and size.55 secondary GICs, or VGIC maintenance interrupt on primary GIC (see59 regions, used when the GIC doesn't have banked registers. The offset is64 - clock-names : List of names for the GIC clock input(s). Valid clock names65 depend on the GIC variant:[all …]
4 is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based24 2nd level interrupt line Outputs for the parent controller (e.g: ARM GIC)26 0 -----[ MUX ] ------------|==========> GIC interrupt 7529 1 -----[ MUX ] --------)---|==========> GIC interrupt 7632 2 -----[ MUX ] --------)---|==========> GIC interrupt 7738 7 ---------------------|---|===========> GIC interrupt 6644 |===========> GIC interrupt 64
4 routes interrupts to the GIC, and also serves as a wakeup source. It15 - interrupt-parent : a phandle to the GIC these interrupts are routed20 - Because this HW ultimately routes interrupts to the GIC, the21 interrupt specifier must be that of the GIC.
4 interrupts to the GIC, and also serves as a wakeup source. It is also22 - interrupt-parent : a phandle to the GIC these interrupts are routed27 - Because this HW ultimately routes interrupts to the GIC, the28 interrupt specifier must be that of the GIC.
31 - reg : Specifies base physical address(s) and size of the GIC33 - GIC Distributor interface (GICD)34 - GIC Redistributors (GICR), one range per redistributor region35 - GIC CPU interface (GICC)36 - GIC Hypervisor interface (GICH)37 - GIC Virtual CPU interface (GICV)65 The main GIC node must contain the appropriate #address-cells,
3 Mediatek SOCs sysirq support controllable irq inverter for each GIC SPI18 - #interrupt-cells : Use the same format as specified by GIC in21 use the same interrupt-cells format as GIC.
24 connected as a slave to the Cortex-A9 GIC. The provided interrupt25 indicate to which GIC interrupt the MPIC output is connected.
6 interrupt controller, such as GIC in case of Exynos4210.
198 gic = ravb_read(ndev, GIC); in ravb_ptp_extts()203 ravb_write(ndev, gic, GIC); in ravb_ptp_extts()251 gic = ravb_read(ndev, GIC); in ravb_ptp_perout()253 ravb_write(ndev, gic, GIC); in ravb_ptp_perout()262 gic = ravb_read(ndev, GIC); in ravb_ptp_perout()264 ravb_write(ndev, gic, GIC); in ravb_ptp_perout()304 gis &= ravb_read(ndev, GIC); in ravb_ptp_interrupt()355 ravb_write(ndev, 0, GIC); in ravb_ptp_stop()
167 GIC = 0x03AC, enumerator
19 Flags get passed only when using GIC as parent. Flags20 encoding as documented by the GIC bindings.23 is either the node of the GIC or NVIC controller.
86 interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */88 reg = <0x0 0x78090000 0x0 0x10000>, /* GIC Dist */89 <0x0 0x780A0000 0x0 0x20000>, /* GIC CPU */90 <0x0 0x780C0000 0x0 0x10000>, /* GIC VCPU Control */91 <0x0 0x780E0000 0x0 0x20000>; /* GIC VCPU */
84 reg = <0x0 0x78010000 0x0 0x1000>, /* GIC Dist */85 <0x0 0x78020000 0x0 0x1000>, /* GIC CPU */86 <0x0 0x78040000 0x0 0x2000>, /* GIC VCPU Control */87 <0x0 0x78060000 0x0 0x2000>; /* GIC VCPU */88 interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */
21 Base address in the guest physical address space of the GIC distributor26 Base address in the guest physical address space of the GIC virtual cpu102 this GIC instance, ranging from 64 to 1024, in increments of 32.106 -EBUSY: Value has already be set, or GIC has already been initialized
21 interrupts: GIC interrupt lines connected to PCI MSI interrupt lines41 interrupts: GIC interrupt lines connected to PCI Legacy interrupt lines
23 interrupts to the GIC interrupts.
5 Interrupt Controller's (GIC's) hardware support for virtualization by32 Registers (LRs) on the GIC before running a VCPU. The LR is programmed74 configures the physical GIC with EOIMode=1, which causes EOI operations to75 perform a priority drop allowing the GIC to receive other interrupts of the84 Level-triggered interrupts will keep the interrupt line to the GIC92 must be set when entering the guest, preventing the GIC from forwarding
7 The per-core architected timer is attached to a GIC to deliver its8 per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
16 A GIC node is also required.
7 The TWD is usually attached to a GIC to deliver its two per-processor
223 /* Active high IRQ 0 is connected to GIC's SPI0 */
5 The MPU contain CPUs, GIC, L2 cache and a local PRCM.
181 /* Primary DevChip GIC synthesized with the CPU */363 /* This GIC on the board is cascaded off the DevChip GIC */
95 * In order, these are GIC interrupts 17, 18, 19, 20.
25 fed into the ARM GIC. The PMC is not involved in the detection or
166 This MSI driver supports Altera MSI to GIC controller IP.
164 Required for arm64. Only the GIC interrupt controller structures413 interrupt model available is GIC.
137 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
630 On ARM/arm64, a GICv2 is created. Any other GIC versions require the usage of667 in-kernel irqchip (GIC), and for in-kernel irqchip can tell the GIC to675 - irq_type[0]: out-of-kernel GIC: irq_id 0 is IRQ, irq_id 1 is FIQ676 - irq_type[1]: in-kernel GIC: SPI, irq_id between 32 and 1019 (incl.)678 - irq_type[2]: in-kernel GIC: PPI, irq_id between 16 and 31 (incl.)680 (The irq_id field thus corresponds nicely to the IRQ ID in the ARM GIC specs)2337 Peripheral Interrupt (SPI) index, such that the GIC interrupt ID is2650 ARM/arm64 currently only require this when using the in-kernel GIC