Lines Matching refs:GIC

3 ARM SMP cores are often associated with a GIC, providing per processor
7 Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
42 	the 8 possible cpus attached to the GIC.  A bit set to '1' indicated
49 - reg : Specifies base physical address(s) and size of the GIC registers. The
50   first region is the GIC distributor register base and size. The 2nd region is
51   the GIC cpu interface register base and size.
55   secondary GICs, or VGIC maintenance interrupt on primary GIC (see
59   regions, used when the GIC doesn't have banked registers. The offset is
64 - clock-names   : List of names for the GIC clock input(s). Valid clock names
65   depend on the GIC variant:
73 		  the power controller specified by phandle, used when the GIC
89 * GIC virtualization extensions (VGIC)
92 properties must be described (they only exist if the GIC is the
98   size of the VGIC registers. The first additional region is the GIC
100   region is the GIC virtual cpu interface register base and size.
120 Certain revisions of GIC-400 supports MSI/MSI-x via V2M register frame(s).