1* ARM Generic Interrupt Controller, version 3 2 3AArch64 SMP cores are often associated with a GICv3, providing Private 4Peripheral Interrupts (PPI), Shared Peripheral Interrupts (SPI), 5Software Generated Interrupts (SGI), and Locality-specific Peripheral 6Interrupts (LPI). 7 8Main node required properties: 9 10- compatible : should at least contain "arm,gic-v3". 11- interrupt-controller : Identifies the node as an interrupt controller 12- #interrupt-cells : Specifies the number of cells needed to encode an 13 interrupt source. Must be a single cell with a value of at least 3. 14 15 The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI 16 interrupts. Other values are reserved for future use. 17 18 The 2nd cell contains the interrupt number for the interrupt type. 19 SPI interrupts are in the range [0-987]. PPI interrupts are in the 20 range [0-15]. 21 22 The 3rd cell is the flags, encoded as follows: 23 bits[3:0] trigger type and level flags. 24 1 = edge triggered 25 4 = level triggered 26 27 Cells 4 and beyond are reserved for future use. When the 1st cell 28 has a value of 0 or 1, cells 4 and beyond act as padding, and may be 29 ignored. It is recommended that padding cells have a value of 0. 30 31- reg : Specifies base physical address(s) and size of the GIC 32 registers, in the following order: 33 - GIC Distributor interface (GICD) 34 - GIC Redistributors (GICR), one range per redistributor region 35 - GIC CPU interface (GICC) 36 - GIC Hypervisor interface (GICH) 37 - GIC Virtual CPU interface (GICV) 38 39 GICC, GICH and GICV are optional. 40 41- interrupts : Interrupt source of the VGIC maintenance interrupt. 42 43Optional 44 45- redistributor-stride : If using padding pages, specifies the stride 46 of consecutive redistributors. Must be a multiple of 64kB. 47 48- #redistributor-regions: The number of independent contiguous regions 49 occupied by the redistributors. Required if more than one such 50 region is present. 51 52Sub-nodes: 53 54GICv3 has one or more Interrupt Translation Services (ITS) that are 55used to route Message Signalled Interrupts (MSI) to the CPUs. 56 57These nodes must have the following properties: 58- compatible : Should at least contain "arm,gic-v3-its". 59- msi-controller : Boolean property. Identifies the node as an MSI controller 60- #msi-cells: Must be <1>. The single msi-cell is the DeviceID of the device 61 which will generate the MSI. 62- reg: Specifies the base physical address and size of the ITS 63 registers. 64 65The main GIC node must contain the appropriate #address-cells, 66#size-cells and ranges properties for the reg property of all ITS 67nodes. 68 69Examples: 70 71 gic: interrupt-controller@2cf00000 { 72 compatible = "arm,gic-v3"; 73 #interrupt-cells = <3>; 74 #address-cells = <2>; 75 #size-cells = <2>; 76 ranges; 77 interrupt-controller; 78 reg = <0x0 0x2f000000 0 0x10000>, // GICD 79 <0x0 0x2f100000 0 0x200000>, // GICR 80 <0x0 0x2c000000 0 0x2000>, // GICC 81 <0x0 0x2c010000 0 0x2000>, // GICH 82 <0x0 0x2c020000 0 0x2000>; // GICV 83 interrupts = <1 9 4>; 84 85 gic-its@2c200000 { 86 compatible = "arm,gic-v3-its"; 87 msi-controller; 88 #msi-cells = <1>; 89 reg = <0x0 0x2c200000 0 0x200000>; 90 }; 91 }; 92 93 gic: interrupt-controller@2c010000 { 94 compatible = "arm,gic-v3"; 95 #interrupt-cells = <3>; 96 #address-cells = <2>; 97 #size-cells = <2>; 98 ranges; 99 interrupt-controller; 100 redistributor-stride = <0x0 0x40000>; // 256kB stride 101 #redistributor-regions = <2>; 102 reg = <0x0 0x2c010000 0 0x10000>, // GICD 103 <0x0 0x2d000000 0 0x800000>, // GICR 1: CPUs 0-31 104 <0x0 0x2e000000 0 0x800000>; // GICR 2: CPUs 32-63 105 <0x0 0x2c040000 0 0x2000>, // GICC 106 <0x0 0x2c060000 0 0x2000>, // GICH 107 <0x0 0x2c080000 0 0x2000>; // GICV 108 interrupts = <1 9 4>; 109 110 gic-its@2c200000 { 111 compatible = "arm,gic-v3-its"; 112 msi-controller; 113 #msi-cells = <1>; 114 reg = <0x0 0x2c200000 0 0x200000>; 115 }; 116 117 gic-its@2c400000 { 118 compatible = "arm,gic-v3-its"; 119 msi-controller; 120 #msi-cells = <1>; 121 reg = <0x0 0x2c400000 0 0x200000>; 122 }; 123 }; 124