1* ARM architected timer
2
3ARM cores may have a per-core architected timer, which provides per-cpu timers,
4or a memory mapped architected timer, which provides up to 8 frames with a
5physical and optional virtual timer per frame.
6
7The per-core architected timer is attached to a GIC to deliver its
8per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
9to deliver its interrupts via SPIs.
10
11** CP15 Timer node properties:
12
13- compatible : Should at least contain one of
14	"arm,armv7-timer"
15	"arm,armv8-timer"
16
17- interrupts : Interrupt list for secure, non-secure, virtual and
18  hypervisor timers, in that order.
19
20- clock-frequency : The frequency of the main counter, in Hz. Should be present
21  only where necessary to work around broken firmware which does not configure
22  CNTFRQ on all CPUs to a uniform correct value. Use of this property is
23  strongly discouraged; fix your firmware unless absolutely impossible.
24
25- always-on : a boolean property. If present, the timer is powered through an
26  always-on power domain, therefore it never loses context.
27
28** Optional properties:
29
30- arm,cpu-registers-not-fw-configured : Firmware does not initialize
31  any of the generic timer CPU registers, which contain their
32  architecturally-defined reset values. Only supported for 32-bit
33  systems which follow the ARMv7 architected reset values.
34
35
36Example:
37
38	timer {
39		compatible = "arm,cortex-a15-timer",
40			     "arm,armv7-timer";
41		interrupts = <1 13 0xf08>,
42			     <1 14 0xf08>,
43			     <1 11 0xf08>,
44			     <1 10 0xf08>;
45		clock-frequency = <100000000>;
46	};
47
48** Memory mapped timer node properties:
49
50- compatible : Should at least contain "arm,armv7-timer-mem".
51
52- clock-frequency : The frequency of the main counter, in Hz. Should be present
53  only when firmware has not configured the MMIO CNTFRQ registers.
54
55- reg : The control frame base address.
56
57Note that #address-cells, #size-cells, and ranges shall be present to ensure
58the CPU can address a frame's registers.
59
60A timer node has up to 8 frame sub-nodes, each with the following properties:
61
62- frame-number: 0 to 7.
63
64- interrupts : Interrupt list for physical and virtual timers in that order.
65  The virtual timer interrupt is optional.
66
67- reg : The first and second view base addresses in that order. The second view
68  base address is optional.
69
70- status : "disabled" indicates the frame is not available for use. Optional.
71
72Example:
73
74	timer@f0000000 {
75		compatible = "arm,armv7-timer-mem";
76		#address-cells = <1>;
77		#size-cells = <1>;
78		ranges;
79		reg = <0xf0000000 0x1000>;
80		clock-frequency = <50000000>;
81
82		frame@f0001000 {
83			frame-number = <0>
84			interrupts = <0 13 0x8>,
85				     <0 14 0x8>;
86			reg = <0xf0001000 0x1000>,
87			      <0xf0002000 0x1000>;
88		};
89
90		frame@f0003000 {
91			frame-number = <1>
92			interrupts = <0 15 0x8>;
93			reg = <0xf0003000 0x1000>;
94			status = "disabled";
95		};
96	};
97