Searched refs:val (Results 1 - 200 of 6569) sorted by relevance

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/linux-4.1.27/lib/
H A Dbcd.c4 unsigned _bcd2bin(unsigned char val) _bcd2bin() argument
6 return (val & 0x0f) + (val >> 4) * 10; _bcd2bin()
10 unsigned char _bin2bcd(unsigned val) _bin2bcd() argument
12 return ((val / 10) << 4) + val % 10; _bin2bcd()
H A Dclz_ctz.c19 int __weak __ctzsi2(int val); __ctzsi2()
20 int __weak __ctzsi2(int val) __ctzsi2() argument
22 return __ffs(val); __ctzsi2()
26 int __weak __clzsi2(int val); __clzsi2()
27 int __weak __clzsi2(int val) __clzsi2() argument
29 return 32 - fls(val); __clzsi2()
33 int __weak __clzdi2(long val);
34 int __weak __ctzdi2(long val);
37 int __weak __clzdi2(long val) __clzdi2() argument
39 return 32 - fls((int)val); __clzdi2()
43 int __weak __ctzdi2(long val) __ctzdi2() argument
45 return __ffs((u32)val); __ctzdi2()
51 int __weak __clzdi2(long val) __clzdi2() argument
53 return 64 - fls64((u64)val); __clzdi2()
57 int __weak __ctzdi2(long val) __ctzdi2() argument
59 return __ffs64((u64)val); __ctzdi2()
H A Datomic64.c53 long long val; atomic64_read() local
56 val = v->counter; atomic64_read()
58 return val; atomic64_read()
90 long long val; \
93 val = (v->counter c_op a); \
95 return val; \
114 long long val; atomic64_dec_if_positive() local
117 val = v->counter - 1; atomic64_dec_if_positive()
118 if (val >= 0) atomic64_dec_if_positive()
119 v->counter = val; atomic64_dec_if_positive()
121 return val; atomic64_dec_if_positive()
129 long long val; atomic64_cmpxchg() local
132 val = v->counter; atomic64_cmpxchg()
133 if (val == o) atomic64_cmpxchg()
136 return val; atomic64_cmpxchg()
144 long long val; atomic64_xchg() local
147 val = v->counter; atomic64_xchg()
150 return val; atomic64_xchg()
/linux-4.1.27/arch/blackfin/mach-bf561/include/mach/
H A DcdefBF561.h17 #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val)
20 #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val)
22 #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val)
27 #define bfin_write_SWRST(val) bfin_write16(SWRST,val)
29 #define bfin_write_SYSCR(val) bfin_write16(SYSCR,val)
31 #define bfin_write_SIC_RVECT(val) bfin_write16(SIC_RVECT,val)
33 #define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0,val)
35 #define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1,val)
37 #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val)
39 #define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1,val)
41 #define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2,val)
43 #define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3,val)
45 #define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4,val)
47 #define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5,val)
49 #define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6,val)
51 #define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7,val)
53 #define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0,val)
55 #define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1,val)
57 #define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0,val)
59 #define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1,val)
63 #define bfin_write_SICB_SWRST(val) bfin_write16(SICB_SWRST,val)
65 #define bfin_write_SICB_SYSCR(val) bfin_write16(SICB_SYSCR,val)
67 #define bfin_write_SICB_RVECT(val) bfin_write16(SICB_RVECT,val)
69 #define bfin_write_SICB_IMASK0(val) bfin_write32(SICB_IMASK0,val)
71 #define bfin_write_SICB_IMASK1(val) bfin_write32(SICB_IMASK1,val)
73 #define bfin_write_SICB_IAR0(val) bfin_write32(SICB_IAR0,val)
75 #define bfin_write_SICB_IAR1(val) bfin_write32(SICB_IAR1,val)
77 #define bfin_write_SICB_IAR2(val) bfin_write32(SICB_IAR2,val)
79 #define bfin_write_SICB_IAR3(val) bfin_write32(SICB_IAR3,val)
81 #define bfin_write_SICB_IAR4(val) bfin_write32(SICB_IAR4,val)
83 #define bfin_write_SICB_IAR5(val) bfin_write32(SICB_IAR5,val)
85 #define bfin_write_SICB_IAR6(val) bfin_write32(SICB_IAR6,val)
87 #define bfin_write_SICB_IAR7(val) bfin_write32(SICB_IAR7,val)
89 #define bfin_write_SICB_ISR0(val) bfin_write32(SICB_ISR0,val)
91 #define bfin_write_SICB_ISR1(val) bfin_write32(SICB_ISR1,val)
93 #define bfin_write_SICB_IWR0(val) bfin_write32(SICB_IWR0,val)
95 #define bfin_write_SICB_IWR1(val) bfin_write32(SICB_IWR1,val)
98 #define bfin_write_WDOGA_CTL(val) bfin_write16(WDOGA_CTL,val)
100 #define bfin_write_WDOGA_CNT(val) bfin_write32(WDOGA_CNT,val)
102 #define bfin_write_WDOGA_STAT(val) bfin_write32(WDOGA_STAT,val)
106 #define bfin_write_WDOGB_CTL(val) bfin_write16(WDOGB_CTL,val)
108 #define bfin_write_WDOGB_CNT(val) bfin_write32(WDOGB_CNT,val)
110 #define bfin_write_WDOGB_STAT(val) bfin_write32(WDOGB_STAT,val)
114 #define bfin_write_UART_THR(val) bfin_write16(UART_THR,val)
116 #define bfin_write_UART_RBR(val) bfin_write16(UART_RBR,val)
118 #define bfin_write_UART_DLL(val) bfin_write16(UART_DLL,val)
120 #define bfin_write_UART_IER(val) bfin_write16(UART_IER,val)
122 #define bfin_write_UART_DLH(val) bfin_write16(UART_DLH,val)
124 #define bfin_write_UART_IIR(val) bfin_write16(UART_IIR,val)
126 #define bfin_write_UART_LCR(val) bfin_write16(UART_LCR,val)
128 #define bfin_write_UART_MCR(val) bfin_write16(UART_MCR,val)
130 #define bfin_write_UART_LSR(val) bfin_write16(UART_LSR,val)
132 #define bfin_write_UART_MSR(val) bfin_write16(UART_MSR,val)
134 #define bfin_write_UART_SCR(val) bfin_write16(UART_SCR,val)
136 #define bfin_write_UART_GCTL(val) bfin_write16(UART_GCTL,val)
140 #define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL,val)
142 #define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG,val)
144 #define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT,val)
146 #define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR,val)
148 #define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR,val)
150 #define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD,val)
152 #define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW,val)
156 #define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG,val)
158 #define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER,val)
160 #define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD,val)
162 #define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH,val)
164 #define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG,val)
166 #define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER,val)
168 #define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD,val)
170 #define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH,val)
172 #define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG,val)
174 #define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER,val)
176 #define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD,val)
178 #define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH,val)
180 #define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG,val)
182 #define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER,val)
184 #define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD,val)
186 #define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH,val)
188 #define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG,val)
190 #define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER,val)
192 #define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD,val)
194 #define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH,val)
196 #define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG,val)
198 #define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER,val)
200 #define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD,val)
202 #define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH,val)
204 #define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG,val)
206 #define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER,val)
208 #define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD,val)
210 #define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH,val)
212 #define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG,val)
214 #define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER,val)
216 #define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD,val)
218 #define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH,val)
222 #define bfin_write_TMRS8_ENABLE(val) bfin_write16(TMRS8_ENABLE,val)
224 #define bfin_write_TMRS8_DISABLE(val) bfin_write16(TMRS8_DISABLE,val)
226 #define bfin_write_TMRS8_STATUS(val) bfin_write32(TMRS8_STATUS,val)
228 #define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG,val)
230 #define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER,val)
232 #define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD,val)
234 #define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH,val)
236 #define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG,val)
238 #define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER,val)
240 #define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD,val)
242 #define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH,val)
244 #define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG,val)
246 #define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER,val)
248 #define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD,val)
250 #define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH,val)
252 #define bfin_write_TIMER11_CONFIG(val) bfin_write16(TIMER11_CONFIG,val)
254 #define bfin_write_TIMER11_COUNTER(val) bfin_write32(TIMER11_COUNTER,val)
256 #define bfin_write_TIMER11_PERIOD(val) bfin_write32(TIMER11_PERIOD,val)
258 #define bfin_write_TIMER11_WIDTH(val) bfin_write32(TIMER11_WIDTH,val)
260 #define bfin_write_TMRS4_ENABLE(val) bfin_write16(TMRS4_ENABLE,val)
262 #define bfin_write_TMRS4_DISABLE(val) bfin_write16(TMRS4_DISABLE,val)
264 #define bfin_write_TMRS4_STATUS(val) bfin_write32(TMRS4_STATUS,val)
268 #define bfin_write_FIO0_FLAG_D(val) bfin_write16(FIO0_FLAG_D,val)
270 #define bfin_write_FIO0_FLAG_C(val) bfin_write16(FIO0_FLAG_C,val)
272 #define bfin_write_FIO0_FLAG_S(val) bfin_write16(FIO0_FLAG_S,val)
274 #define bfin_write_FIO0_FLAG_T(val) bfin_write16(FIO0_FLAG_T,val)
276 #define bfin_write_FIO0_MASKA_D(val) bfin_write16(FIO0_MASKA_D,val)
278 #define bfin_write_FIO0_MASKA_C(val) bfin_write16(FIO0_MASKA_C,val)
280 #define bfin_write_FIO0_MASKA_S(val) bfin_write16(FIO0_MASKA_S,val)
282 #define bfin_write_FIO0_MASKA_T(val) bfin_write16(FIO0_MASKA_T,val)
284 #define bfin_write_FIO0_MASKB_D(val) bfin_write16(FIO0_MASKB_D,val)
286 #define bfin_write_FIO0_MASKB_C(val) bfin_write16(FIO0_MASKB_C,val)
288 #define bfin_write_FIO0_MASKB_S(val) bfin_write16(FIO0_MASKB_S,val)
290 #define bfin_write_FIO0_MASKB_T(val) bfin_write16(FIO0_MASKB_T,val)
292 #define bfin_write_FIO0_DIR(val) bfin_write16(FIO0_DIR,val)
294 #define bfin_write_FIO0_POLAR(val) bfin_write16(FIO0_POLAR,val)
296 #define bfin_write_FIO0_EDGE(val) bfin_write16(FIO0_EDGE,val)
298 #define bfin_write_FIO0_BOTH(val) bfin_write16(FIO0_BOTH,val)
300 #define bfin_write_FIO0_INEN(val) bfin_write16(FIO0_INEN,val)
303 #define bfin_write_FIO1_FLAG_D(val) bfin_write16(FIO1_FLAG_D,val)
305 #define bfin_write_FIO1_FLAG_C(val) bfin_write16(FIO1_FLAG_C,val)
307 #define bfin_write_FIO1_FLAG_S(val) bfin_write16(FIO1_FLAG_S,val)
309 #define bfin_write_FIO1_FLAG_T(val) bfin_write16(FIO1_FLAG_T,val)
311 #define bfin_write_FIO1_MASKA_D(val) bfin_write16(FIO1_MASKA_D,val)
313 #define bfin_write_FIO1_MASKA_C(val) bfin_write16(FIO1_MASKA_C,val)
315 #define bfin_write_FIO1_MASKA_S(val) bfin_write16(FIO1_MASKA_S,val)
317 #define bfin_write_FIO1_MASKA_T(val) bfin_write16(FIO1_MASKA_T,val)
319 #define bfin_write_FIO1_MASKB_D(val) bfin_write16(FIO1_MASKB_D,val)
321 #define bfin_write_FIO1_MASKB_C(val) bfin_write16(FIO1_MASKB_C,val)
323 #define bfin_write_FIO1_MASKB_S(val) bfin_write16(FIO1_MASKB_S,val)
325 #define bfin_write_FIO1_MASKB_T(val) bfin_write16(FIO1_MASKB_T,val)
327 #define bfin_write_FIO1_DIR(val) bfin_write16(FIO1_DIR,val)
329 #define bfin_write_FIO1_POLAR(val) bfin_write16(FIO1_POLAR,val)
331 #define bfin_write_FIO1_EDGE(val) bfin_write16(FIO1_EDGE,val)
333 #define bfin_write_FIO1_BOTH(val) bfin_write16(FIO1_BOTH,val)
335 #define bfin_write_FIO1_INEN(val) bfin_write16(FIO1_INEN,val)
338 #define bfin_write_FIO2_FLAG_D(val) bfin_write16(FIO2_FLAG_D,val)
340 #define bfin_write_FIO2_FLAG_C(val) bfin_write16(FIO2_FLAG_C,val)
342 #define bfin_write_FIO2_FLAG_S(val) bfin_write16(FIO2_FLAG_S,val)
344 #define bfin_write_FIO2_FLAG_T(val) bfin_write16(FIO2_FLAG_T,val)
346 #define bfin_write_FIO2_MASKA_D(val) bfin_write16(FIO2_MASKA_D,val)
348 #define bfin_write_FIO2_MASKA_C(val) bfin_write16(FIO2_MASKA_C,val)
350 #define bfin_write_FIO2_MASKA_S(val) bfin_write16(FIO2_MASKA_S,val)
352 #define bfin_write_FIO2_MASKA_T(val) bfin_write16(FIO2_MASKA_T,val)
354 #define bfin_write_FIO2_MASKB_D(val) bfin_write16(FIO2_MASKB_D,val)
356 #define bfin_write_FIO2_MASKB_C(val) bfin_write16(FIO2_MASKB_C,val)
358 #define bfin_write_FIO2_MASKB_S(val) bfin_write16(FIO2_MASKB_S,val)
360 #define bfin_write_FIO2_MASKB_T(val) bfin_write16(FIO2_MASKB_T,val)
362 #define bfin_write_FIO2_DIR(val) bfin_write16(FIO2_DIR,val)
364 #define bfin_write_FIO2_POLAR(val) bfin_write16(FIO2_POLAR,val)
366 #define bfin_write_FIO2_EDGE(val) bfin_write16(FIO2_EDGE,val)
368 #define bfin_write_FIO2_BOTH(val) bfin_write16(FIO2_BOTH,val)
370 #define bfin_write_FIO2_INEN(val) bfin_write16(FIO2_INEN,val)
373 #define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1,val)
375 #define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2,val)
377 #define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV,val)
379 #define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV,val)
381 #define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX,val)
383 #define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX,val)
385 #define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX,val)
387 #define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX,val)
389 #define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX,val)
391 #define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX,val)
393 #define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1,val)
395 #define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2,val)
397 #define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV,val)
399 #define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV,val)
401 #define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT,val)
403 #define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL,val)
405 #define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1,val)
407 #define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2,val)
409 #define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0,val)
411 #define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1,val)
413 #define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2,val)
415 #define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3,val)
417 #define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0,val)
419 #define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1,val)
421 #define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2,val)
423 #define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3,val)
426 #define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1,val)
428 #define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2,val)
430 #define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV,val)
432 #define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV,val)
434 #define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX,val)
436 #define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX,val)
438 #define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX,val)
440 #define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX,val)
442 #define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX,val)
444 #define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX,val)
446 #define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1,val)
448 #define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2,val)
450 #define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV,val)
452 #define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV,val)
454 #define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT,val)
456 #define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL,val)
458 #define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1,val)
460 #define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2,val)
462 #define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0,val)
464 #define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1,val)
466 #define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2,val)
468 #define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3,val)
470 #define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0,val)
472 #define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1,val)
474 #define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2,val)
476 #define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3,val)
479 #define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL,val)
481 #define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0,val)
483 #define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1,val)
486 #define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL,val)
488 #define bfin_write_EBIU_SDBCTL(val) bfin_write32(EBIU_SDBCTL,val)
490 #define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC,val)
492 #define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT,val)
495 #define bfin_write_PPI0_CONTROL(val) bfin_write16(PPI0_CONTROL,val)
497 #define bfin_write_PPI0_STATUS(val) bfin_write16(PPI0_STATUS,val)
500 #define bfin_write_PPI0_COUNT(val) bfin_write16(PPI0_COUNT,val)
502 #define bfin_write_PPI0_DELAY(val) bfin_write16(PPI0_DELAY,val)
504 #define bfin_write_PPI0_FRAME(val) bfin_write16(PPI0_FRAME,val)
507 #define bfin_write_PPI1_CONTROL(val) bfin_write16(PPI1_CONTROL,val)
509 #define bfin_write_PPI1_STATUS(val) bfin_write16(PPI1_STATUS,val)
512 #define bfin_write_PPI1_COUNT(val) bfin_write16(PPI1_COUNT,val)
514 #define bfin_write_PPI1_DELAY(val) bfin_write16(PPI1_DELAY,val)
516 #define bfin_write_PPI1_FRAME(val) bfin_write16(PPI1_FRAME,val)
519 #define bfin_write_DMAC0_TC_PER(val) bfin_write16(DMAC0_TC_PER,val)
521 #define bfin_write_DMAC0_TC_CNT(val) bfin_write16(DMAC0_TC_CNT,val)
523 #define bfin_write_DMAC1_TC_PER(val) bfin_write16(DMAC1_TC_PER,val)
525 #define bfin_write_DMAC1_TC_CNT(val) bfin_write16(DMAC1_TC_CNT,val)
528 #define bfin_write_DMA1_0_CONFIG(val) bfin_write16(DMA1_0_CONFIG,val)
530 #define bfin_write_DMA1_0_NEXT_DESC_PTR(val) bfin_write32(DMA1_0_NEXT_DESC_PTR,val)
532 #define bfin_write_DMA1_0_START_ADDR(val) bfin_write32(DMA1_0_START_ADDR,val)
534 #define bfin_write_DMA1_0_X_COUNT(val) bfin_write16(DMA1_0_X_COUNT,val)
536 #define bfin_write_DMA1_0_Y_COUNT(val) bfin_write16(DMA1_0_Y_COUNT,val)
538 #define bfin_write_DMA1_0_X_MODIFY(val) bfin_write16(DMA1_0_X_MODIFY,val)
540 #define bfin_write_DMA1_0_Y_MODIFY(val) bfin_write16(DMA1_0_Y_MODIFY,val)
542 #define bfin_write_DMA1_0_CURR_DESC_PTR(val) bfin_write32(DMA1_0_CURR_DESC_PTR,val)
544 #define bfin_write_DMA1_0_CURR_ADDR(val) bfin_write32(DMA1_0_CURR_ADDR,val)
546 #define bfin_write_DMA1_0_CURR_X_COUNT(val) bfin_write16(DMA1_0_CURR_X_COUNT,val)
548 #define bfin_write_DMA1_0_CURR_Y_COUNT(val) bfin_write16(DMA1_0_CURR_Y_COUNT,val)
550 #define bfin_write_DMA1_0_IRQ_STATUS(val) bfin_write16(DMA1_0_IRQ_STATUS,val)
552 #define bfin_write_DMA1_0_PERIPHERAL_MAP(val) bfin_write16(DMA1_0_PERIPHERAL_MAP,val)
554 #define bfin_write_DMA1_1_CONFIG(val) bfin_write16(DMA1_1_CONFIG,val)
556 #define bfin_write_DMA1_1_NEXT_DESC_PTR(val) bfin_write32(DMA1_1_NEXT_DESC_PTR,val)
558 #define bfin_write_DMA1_1_START_ADDR(val) bfin_write32(DMA1_1_START_ADDR,val)
560 #define bfin_write_DMA1_1_X_COUNT(val) bfin_write16(DMA1_1_X_COUNT,val)
562 #define bfin_write_DMA1_1_Y_COUNT(val) bfin_write16(DMA1_1_Y_COUNT,val)
564 #define bfin_write_DMA1_1_X_MODIFY(val) bfin_write16(DMA1_1_X_MODIFY,val)
566 #define bfin_write_DMA1_1_Y_MODIFY(val) bfin_write16(DMA1_1_Y_MODIFY,val)
568 #define bfin_write_DMA1_1_CURR_DESC_PTR(val) bfin_write32(DMA1_1_CURR_DESC_PTR,val)
570 #define bfin_write_DMA1_1_CURR_ADDR(val) bfin_write32(DMA1_1_CURR_ADDR,val)
572 #define bfin_write_DMA1_1_CURR_X_COUNT(val) bfin_write16(DMA1_1_CURR_X_COUNT,val)
574 #define bfin_write_DMA1_1_CURR_Y_COUNT(val) bfin_write16(DMA1_1_CURR_Y_COUNT,val)
576 #define bfin_write_DMA1_1_IRQ_STATUS(val) bfin_write16(DMA1_1_IRQ_STATUS,val)
578 #define bfin_write_DMA1_1_PERIPHERAL_MAP(val) bfin_write16(DMA1_1_PERIPHERAL_MAP,val)
580 #define bfin_write_DMA1_2_CONFIG(val) bfin_write16(DMA1_2_CONFIG,val)
582 #define bfin_write_DMA1_2_NEXT_DESC_PTR(val) bfin_write32(DMA1_2_NEXT_DESC_PTR,val)
584 #define bfin_write_DMA1_2_START_ADDR(val) bfin_write32(DMA1_2_START_ADDR,val)
586 #define bfin_write_DMA1_2_X_COUNT(val) bfin_write16(DMA1_2_X_COUNT,val)
588 #define bfin_write_DMA1_2_Y_COUNT(val) bfin_write16(DMA1_2_Y_COUNT,val)
590 #define bfin_write_DMA1_2_X_MODIFY(val) bfin_write16(DMA1_2_X_MODIFY,val)
592 #define bfin_write_DMA1_2_Y_MODIFY(val) bfin_write16(DMA1_2_Y_MODIFY,val)
594 #define bfin_write_DMA1_2_CURR_DESC_PTR(val) bfin_write32(DMA1_2_CURR_DESC_PTR,val)
596 #define bfin_write_DMA1_2_CURR_ADDR(val) bfin_write32(DMA1_2_CURR_ADDR,val)
598 #define bfin_write_DMA1_2_CURR_X_COUNT(val) bfin_write16(DMA1_2_CURR_X_COUNT,val)
600 #define bfin_write_DMA1_2_CURR_Y_COUNT(val) bfin_write16(DMA1_2_CURR_Y_COUNT,val)
602 #define bfin_write_DMA1_2_IRQ_STATUS(val) bfin_write16(DMA1_2_IRQ_STATUS,val)
604 #define bfin_write_DMA1_2_PERIPHERAL_MAP(val) bfin_write16(DMA1_2_PERIPHERAL_MAP,val)
606 #define bfin_write_DMA1_3_CONFIG(val) bfin_write16(DMA1_3_CONFIG,val)
608 #define bfin_write_DMA1_3_NEXT_DESC_PTR(val) bfin_write32(DMA1_3_NEXT_DESC_PTR,val)
610 #define bfin_write_DMA1_3_START_ADDR(val) bfin_write32(DMA1_3_START_ADDR,val)
612 #define bfin_write_DMA1_3_X_COUNT(val) bfin_write16(DMA1_3_X_COUNT,val)
614 #define bfin_write_DMA1_3_Y_COUNT(val) bfin_write16(DMA1_3_Y_COUNT,val)
616 #define bfin_write_DMA1_3_X_MODIFY(val) bfin_write16(DMA1_3_X_MODIFY,val)
618 #define bfin_write_DMA1_3_Y_MODIFY(val) bfin_write16(DMA1_3_Y_MODIFY,val)
620 #define bfin_write_DMA1_3_CURR_DESC_PTR(val) bfin_write32(DMA1_3_CURR_DESC_PTR,val)
622 #define bfin_write_DMA1_3_CURR_ADDR(val) bfin_write32(DMA1_3_CURR_ADDR,val)
624 #define bfin_write_DMA1_3_CURR_X_COUNT(val) bfin_write16(DMA1_3_CURR_X_COUNT,val)
626 #define bfin_write_DMA1_3_CURR_Y_COUNT(val) bfin_write16(DMA1_3_CURR_Y_COUNT,val)
628 #define bfin_write_DMA1_3_IRQ_STATUS(val) bfin_write16(DMA1_3_IRQ_STATUS,val)
630 #define bfin_write_DMA1_3_PERIPHERAL_MAP(val) bfin_write16(DMA1_3_PERIPHERAL_MAP,val)
632 #define bfin_write_DMA1_4_CONFIG(val) bfin_write16(DMA1_4_CONFIG,val)
634 #define bfin_write_DMA1_4_NEXT_DESC_PTR(val) bfin_write32(DMA1_4_NEXT_DESC_PTR,val)
636 #define bfin_write_DMA1_4_START_ADDR(val) bfin_write32(DMA1_4_START_ADDR,val)
638 #define bfin_write_DMA1_4_X_COUNT(val) bfin_write16(DMA1_4_X_COUNT,val)
640 #define bfin_write_DMA1_4_Y_COUNT(val) bfin_write16(DMA1_4_Y_COUNT,val)
642 #define bfin_write_DMA1_4_X_MODIFY(val) bfin_write16(DMA1_4_X_MODIFY,val)
644 #define bfin_write_DMA1_4_Y_MODIFY(val) bfin_write16(DMA1_4_Y_MODIFY,val)
646 #define bfin_write_DMA1_4_CURR_DESC_PTR(val) bfin_write32(DMA1_4_CURR_DESC_PTR,val)
648 #define bfin_write_DMA1_4_CURR_ADDR(val) bfin_write32(DMA1_4_CURR_ADDR,val)
650 #define bfin_write_DMA1_4_CURR_X_COUNT(val) bfin_write16(DMA1_4_CURR_X_COUNT,val)
652 #define bfin_write_DMA1_4_CURR_Y_COUNT(val) bfin_write16(DMA1_4_CURR_Y_COUNT,val)
654 #define bfin_write_DMA1_4_IRQ_STATUS(val) bfin_write16(DMA1_4_IRQ_STATUS,val)
656 #define bfin_write_DMA1_4_PERIPHERAL_MAP(val) bfin_write16(DMA1_4_PERIPHERAL_MAP,val)
658 #define bfin_write_DMA1_5_CONFIG(val) bfin_write16(DMA1_5_CONFIG,val)
660 #define bfin_write_DMA1_5_NEXT_DESC_PTR(val) bfin_write32(DMA1_5_NEXT_DESC_PTR,val)
662 #define bfin_write_DMA1_5_START_ADDR(val) bfin_write32(DMA1_5_START_ADDR,val)
664 #define bfin_write_DMA1_5_X_COUNT(val) bfin_write16(DMA1_5_X_COUNT,val)
666 #define bfin_write_DMA1_5_Y_COUNT(val) bfin_write16(DMA1_5_Y_COUNT,val)
668 #define bfin_write_DMA1_5_X_MODIFY(val) bfin_write16(DMA1_5_X_MODIFY,val)
670 #define bfin_write_DMA1_5_Y_MODIFY(val) bfin_write16(DMA1_5_Y_MODIFY,val)
672 #define bfin_write_DMA1_5_CURR_DESC_PTR(val) bfin_write32(DMA1_5_CURR_DESC_PTR,val)
674 #define bfin_write_DMA1_5_CURR_ADDR(val) bfin_write32(DMA1_5_CURR_ADDR,val)
676 #define bfin_write_DMA1_5_CURR_X_COUNT(val) bfin_write16(DMA1_5_CURR_X_COUNT,val)
678 #define bfin_write_DMA1_5_CURR_Y_COUNT(val) bfin_write16(DMA1_5_CURR_Y_COUNT,val)
680 #define bfin_write_DMA1_5_IRQ_STATUS(val) bfin_write16(DMA1_5_IRQ_STATUS,val)
682 #define bfin_write_DMA1_5_PERIPHERAL_MAP(val) bfin_write16(DMA1_5_PERIPHERAL_MAP,val)
684 #define bfin_write_DMA1_6_CONFIG(val) bfin_write16(DMA1_6_CONFIG,val)
686 #define bfin_write_DMA1_6_NEXT_DESC_PTR(val) bfin_write32(DMA1_6_NEXT_DESC_PTR,val)
688 #define bfin_write_DMA1_6_START_ADDR(val) bfin_write32(DMA1_6_START_ADDR,val)
690 #define bfin_write_DMA1_6_X_COUNT(val) bfin_write16(DMA1_6_X_COUNT,val)
692 #define bfin_write_DMA1_6_Y_COUNT(val) bfin_write16(DMA1_6_Y_COUNT,val)
694 #define bfin_write_DMA1_6_X_MODIFY(val) bfin_write16(DMA1_6_X_MODIFY,val)
696 #define bfin_write_DMA1_6_Y_MODIFY(val) bfin_write16(DMA1_6_Y_MODIFY,val)
698 #define bfin_write_DMA1_6_CURR_DESC_PTR(val) bfin_write32(DMA1_6_CURR_DESC_PTR,val)
700 #define bfin_write_DMA1_6_CURR_ADDR(val) bfin_write32(DMA1_6_CURR_ADDR,val)
702 #define bfin_write_DMA1_6_CURR_X_COUNT(val) bfin_write16(DMA1_6_CURR_X_COUNT,val)
704 #define bfin_write_DMA1_6_CURR_Y_COUNT(val) bfin_write16(DMA1_6_CURR_Y_COUNT,val)
706 #define bfin_write_DMA1_6_IRQ_STATUS(val) bfin_write16(DMA1_6_IRQ_STATUS,val)
708 #define bfin_write_DMA1_6_PERIPHERAL_MAP(val) bfin_write16(DMA1_6_PERIPHERAL_MAP,val)
710 #define bfin_write_DMA1_7_CONFIG(val) bfin_write16(DMA1_7_CONFIG,val)
712 #define bfin_write_DMA1_7_NEXT_DESC_PTR(val) bfin_write32(DMA1_7_NEXT_DESC_PTR,val)
714 #define bfin_write_DMA1_7_START_ADDR(val) bfin_write32(DMA1_7_START_ADDR,val)
716 #define bfin_write_DMA1_7_X_COUNT(val) bfin_write16(DMA1_7_X_COUNT,val)
718 #define bfin_write_DMA1_7_Y_COUNT(val) bfin_write16(DMA1_7_Y_COUNT,val)
720 #define bfin_write_DMA1_7_X_MODIFY(val) bfin_write16(DMA1_7_X_MODIFY,val)
722 #define bfin_write_DMA1_7_Y_MODIFY(val) bfin_write16(DMA1_7_Y_MODIFY,val)
724 #define bfin_write_DMA1_7_CURR_DESC_PTR(val) bfin_write32(DMA1_7_CURR_DESC_PTR,val)
726 #define bfin_write_DMA1_7_CURR_ADDR(val) bfin_write32(DMA1_7_CURR_ADDR,val)
728 #define bfin_write_DMA1_7_CURR_X_COUNT(val) bfin_write16(DMA1_7_CURR_X_COUNT,val)
730 #define bfin_write_DMA1_7_CURR_Y_COUNT(val) bfin_write16(DMA1_7_CURR_Y_COUNT,val)
732 #define bfin_write_DMA1_7_IRQ_STATUS(val) bfin_write16(DMA1_7_IRQ_STATUS,val)
734 #define bfin_write_DMA1_7_PERIPHERAL_MAP(val) bfin_write16(DMA1_7_PERIPHERAL_MAP,val)
736 #define bfin_write_DMA1_8_CONFIG(val) bfin_write16(DMA1_8_CONFIG,val)
738 #define bfin_write_DMA1_8_NEXT_DESC_PTR(val) bfin_write32(DMA1_8_NEXT_DESC_PTR,val)
740 #define bfin_write_DMA1_8_START_ADDR(val) bfin_write32(DMA1_8_START_ADDR,val)
742 #define bfin_write_DMA1_8_X_COUNT(val) bfin_write16(DMA1_8_X_COUNT,val)
744 #define bfin_write_DMA1_8_Y_COUNT(val) bfin_write16(DMA1_8_Y_COUNT,val)
746 #define bfin_write_DMA1_8_X_MODIFY(val) bfin_write16(DMA1_8_X_MODIFY,val)
748 #define bfin_write_DMA1_8_Y_MODIFY(val) bfin_write16(DMA1_8_Y_MODIFY,val)
750 #define bfin_write_DMA1_8_CURR_DESC_PTR(val) bfin_write32(DMA1_8_CURR_DESC_PTR,val)
752 #define bfin_write_DMA1_8_CURR_ADDR(val) bfin_write32(DMA1_8_CURR_ADDR,val)
754 #define bfin_write_DMA1_8_CURR_X_COUNT(val) bfin_write16(DMA1_8_CURR_X_COUNT,val)
756 #define bfin_write_DMA1_8_CURR_Y_COUNT(val) bfin_write16(DMA1_8_CURR_Y_COUNT,val)
758 #define bfin_write_DMA1_8_IRQ_STATUS(val) bfin_write16(DMA1_8_IRQ_STATUS,val)
760 #define bfin_write_DMA1_8_PERIPHERAL_MAP(val) bfin_write16(DMA1_8_PERIPHERAL_MAP,val)
762 #define bfin_write_DMA1_9_CONFIG(val) bfin_write16(DMA1_9_CONFIG,val)
764 #define bfin_write_DMA1_9_NEXT_DESC_PTR(val) bfin_write32(DMA1_9_NEXT_DESC_PTR,val)
766 #define bfin_write_DMA1_9_START_ADDR(val) bfin_write32(DMA1_9_START_ADDR,val)
768 #define bfin_write_DMA1_9_X_COUNT(val) bfin_write16(DMA1_9_X_COUNT,val)
770 #define bfin_write_DMA1_9_Y_COUNT(val) bfin_write16(DMA1_9_Y_COUNT,val)
772 #define bfin_write_DMA1_9_X_MODIFY(val) bfin_write16(DMA1_9_X_MODIFY,val)
774 #define bfin_write_DMA1_9_Y_MODIFY(val) bfin_write16(DMA1_9_Y_MODIFY,val)
776 #define bfin_write_DMA1_9_CURR_DESC_PTR(val) bfin_write32(DMA1_9_CURR_DESC_PTR,val)
778 #define bfin_write_DMA1_9_CURR_ADDR(val) bfin_write32(DMA1_9_CURR_ADDR,val)
780 #define bfin_write_DMA1_9_CURR_X_COUNT(val) bfin_write16(DMA1_9_CURR_X_COUNT,val)
782 #define bfin_write_DMA1_9_CURR_Y_COUNT(val) bfin_write16(DMA1_9_CURR_Y_COUNT,val)
784 #define bfin_write_DMA1_9_IRQ_STATUS(val) bfin_write16(DMA1_9_IRQ_STATUS,val)
786 #define bfin_write_DMA1_9_PERIPHERAL_MAP(val) bfin_write16(DMA1_9_PERIPHERAL_MAP,val)
788 #define bfin_write_DMA1_10_CONFIG(val) bfin_write16(DMA1_10_CONFIG,val)
790 #define bfin_write_DMA1_10_NEXT_DESC_PTR(val) bfin_write32(DMA1_10_NEXT_DESC_PTR,val)
792 #define bfin_write_DMA1_10_START_ADDR(val) bfin_write32(DMA1_10_START_ADDR,val)
794 #define bfin_write_DMA1_10_X_COUNT(val) bfin_write16(DMA1_10_X_COUNT,val)
796 #define bfin_write_DMA1_10_Y_COUNT(val) bfin_write16(DMA1_10_Y_COUNT,val)
798 #define bfin_write_DMA1_10_X_MODIFY(val) bfin_write16(DMA1_10_X_MODIFY,val)
800 #define bfin_write_DMA1_10_Y_MODIFY(val) bfin_write16(DMA1_10_Y_MODIFY,val)
802 #define bfin_write_DMA1_10_CURR_DESC_PTR(val) bfin_write32(DMA1_10_CURR_DESC_PTR,val)
804 #define bfin_write_DMA1_10_CURR_ADDR(val) bfin_write32(DMA1_10_CURR_ADDR,val)
806 #define bfin_write_DMA1_10_CURR_X_COUNT(val) bfin_write16(DMA1_10_CURR_X_COUNT,val)
808 #define bfin_write_DMA1_10_CURR_Y_COUNT(val) bfin_write16(DMA1_10_CURR_Y_COUNT,val)
810 #define bfin_write_DMA1_10_IRQ_STATUS(val) bfin_write16(DMA1_10_IRQ_STATUS,val)
812 #define bfin_write_DMA1_10_PERIPHERAL_MAP(val) bfin_write16(DMA1_10_PERIPHERAL_MAP,val)
814 #define bfin_write_DMA1_11_CONFIG(val) bfin_write16(DMA1_11_CONFIG,val)
816 #define bfin_write_DMA1_11_NEXT_DESC_PTR(val) bfin_write32(DMA1_11_NEXT_DESC_PTR,val)
818 #define bfin_write_DMA1_11_START_ADDR(val) bfin_write32(DMA1_11_START_ADDR,val)
820 #define bfin_write_DMA1_11_X_COUNT(val) bfin_write16(DMA1_11_X_COUNT,val)
822 #define bfin_write_DMA1_11_Y_COUNT(val) bfin_write16(DMA1_11_Y_COUNT,val)
824 #define bfin_write_DMA1_11_X_MODIFY(val) bfin_write16(DMA1_11_X_MODIFY,val)
826 #define bfin_write_DMA1_11_Y_MODIFY(val) bfin_write16(DMA1_11_Y_MODIFY,val)
828 #define bfin_write_DMA1_11_CURR_DESC_PTR(val) bfin_write32(DMA1_11_CURR_DESC_PTR,val)
830 #define bfin_write_DMA1_11_CURR_ADDR(val) bfin_write32(DMA1_11_CURR_ADDR,val)
832 #define bfin_write_DMA1_11_CURR_X_COUNT(val) bfin_write16(DMA1_11_CURR_X_COUNT,val)
834 #define bfin_write_DMA1_11_CURR_Y_COUNT(val) bfin_write16(DMA1_11_CURR_Y_COUNT,val)
836 #define bfin_write_DMA1_11_IRQ_STATUS(val) bfin_write16(DMA1_11_IRQ_STATUS,val)
838 #define bfin_write_DMA1_11_PERIPHERAL_MAP(val) bfin_write16(DMA1_11_PERIPHERAL_MAP,val)
841 #define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG,val)
843 #define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_write32(MDMA_D2_NEXT_DESC_PTR,val)
845 #define bfin_write_MDMA_D2_START_ADDR(val) bfin_write32(MDMA_D2_START_ADDR,val)
847 #define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT,val)
849 #define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT,val)
851 #define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY,val)
853 #define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY,val)
855 #define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_write32(MDMA_D2_CURR_DESC_PTR,val)
857 #define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_write32(MDMA_D2_CURR_ADDR,val)
859 #define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT,val)
861 #define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT,val)
863 #define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS,val)
865 #define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP,val)
867 #define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG,val)
869 #define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_write32(MDMA_S2_NEXT_DESC_PTR,val)
871 #define bfin_write_MDMA_S2_START_ADDR(val) bfin_write32(MDMA_S2_START_ADDR,val)
873 #define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT,val)
875 #define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT,val)
877 #define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY,val)
879 #define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY,val)
881 #define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_write32(MDMA_S2_CURR_DESC_PTR,val)
883 #define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_write32(MDMA_S2_CURR_ADDR,val)
885 #define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT,val)
887 #define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT,val)
889 #define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS,val)
891 #define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP,val)
893 #define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG,val)
895 #define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_write32(MDMA_D3_NEXT_DESC_PTR,val)
897 #define bfin_write_MDMA_D3_START_ADDR(val) bfin_write32(MDMA_D3_START_ADDR,val)
899 #define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT,val)
901 #define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT,val)
903 #define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY,val)
905 #define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY,val)
907 #define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_write32(MDMA_D3_CURR_DESC_PTR,val)
909 #define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_write32(MDMA_D3_CURR_ADDR,val)
911 #define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT,val)
913 #define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT,val)
915 #define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS,val)
917 #define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP,val)
919 #define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG,val)
921 #define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_write32(MDMA_S3_NEXT_DESC_PTR,val)
923 #define bfin_write_MDMA_S3_START_ADDR(val) bfin_write32(MDMA_S3_START_ADDR,val)
925 #define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT,val)
927 #define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT,val)
929 #define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY,val)
931 #define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY,val)
933 #define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_write32(MDMA_S3_CURR_DESC_PTR,val)
935 #define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_write32(MDMA_S3_CURR_ADDR,val)
937 #define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT,val)
939 #define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT,val)
941 #define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS,val)
943 #define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP,val)
946 #define bfin_write_DMA2_0_CONFIG(val) bfin_write16(DMA2_0_CONFIG,val)
948 #define bfin_write_DMA2_0_NEXT_DESC_PTR(val) bfin_write32(DMA2_0_NEXT_DESC_PTR,val)
950 #define bfin_write_DMA2_0_START_ADDR(val) bfin_write32(DMA2_0_START_ADDR,val)
952 #define bfin_write_DMA2_0_X_COUNT(val) bfin_write16(DMA2_0_X_COUNT,val)
954 #define bfin_write_DMA2_0_Y_COUNT(val) bfin_write16(DMA2_0_Y_COUNT,val)
956 #define bfin_write_DMA2_0_X_MODIFY(val) bfin_write16(DMA2_0_X_MODIFY,val)
958 #define bfin_write_DMA2_0_Y_MODIFY(val) bfin_write16(DMA2_0_Y_MODIFY,val)
960 #define bfin_write_DMA2_0_CURR_DESC_PTR(val) bfin_write32(DMA2_0_CURR_DESC_PTR,val)
962 #define bfin_write_DMA2_0_CURR_ADDR(val) bfin_write32(DMA2_0_CURR_ADDR,val)
964 #define bfin_write_DMA2_0_CURR_X_COUNT(val) bfin_write16(DMA2_0_CURR_X_COUNT,val)
966 #define bfin_write_DMA2_0_CURR_Y_COUNT(val) bfin_write16(DMA2_0_CURR_Y_COUNT,val)
968 #define bfin_write_DMA2_0_IRQ_STATUS(val) bfin_write16(DMA2_0_IRQ_STATUS,val)
970 #define bfin_write_DMA2_0_PERIPHERAL_MAP(val) bfin_write16(DMA2_0_PERIPHERAL_MAP,val)
972 #define bfin_write_DMA2_1_CONFIG(val) bfin_write16(DMA2_1_CONFIG,val)
974 #define bfin_write_DMA2_1_NEXT_DESC_PTR(val) bfin_write32(DMA2_1_NEXT_DESC_PTR,val)
976 #define bfin_write_DMA2_1_START_ADDR(val) bfin_write32(DMA2_1_START_ADDR,val)
978 #define bfin_write_DMA2_1_X_COUNT(val) bfin_write16(DMA2_1_X_COUNT,val)
980 #define bfin_write_DMA2_1_Y_COUNT(val) bfin_write16(DMA2_1_Y_COUNT,val)
982 #define bfin_write_DMA2_1_X_MODIFY(val) bfin_write16(DMA2_1_X_MODIFY,val)
984 #define bfin_write_DMA2_1_Y_MODIFY(val) bfin_write16(DMA2_1_Y_MODIFY,val)
986 #define bfin_write_DMA2_1_CURR_DESC_PTR(val) bfin_write32(DMA2_1_CURR_DESC_PTR,val)
988 #define bfin_write_DMA2_1_CURR_ADDR(val) bfin_write32(DMA2_1_CURR_ADDR,val)
990 #define bfin_write_DMA2_1_CURR_X_COUNT(val) bfin_write16(DMA2_1_CURR_X_COUNT,val)
992 #define bfin_write_DMA2_1_CURR_Y_COUNT(val) bfin_write16(DMA2_1_CURR_Y_COUNT,val)
994 #define bfin_write_DMA2_1_IRQ_STATUS(val) bfin_write16(DMA2_1_IRQ_STATUS,val)
996 #define bfin_write_DMA2_1_PERIPHERAL_MAP(val) bfin_write16(DMA2_1_PERIPHERAL_MAP,val)
998 #define bfin_write_DMA2_2_CONFIG(val) bfin_write16(DMA2_2_CONFIG,val)
1000 #define bfin_write_DMA2_2_NEXT_DESC_PTR(val) bfin_write32(DMA2_2_NEXT_DESC_PTR,val)
1002 #define bfin_write_DMA2_2_START_ADDR(val) bfin_write32(DMA2_2_START_ADDR,val)
1004 #define bfin_write_DMA2_2_X_COUNT(val) bfin_write16(DMA2_2_X_COUNT,val)
1006 #define bfin_write_DMA2_2_Y_COUNT(val) bfin_write16(DMA2_2_Y_COUNT,val)
1008 #define bfin_write_DMA2_2_X_MODIFY(val) bfin_write16(DMA2_2_X_MODIFY,val)
1010 #define bfin_write_DMA2_2_Y_MODIFY(val) bfin_write16(DMA2_2_Y_MODIFY,val)
1012 #define bfin_write_DMA2_2_CURR_DESC_PTR(val) bfin_write32(DMA2_2_CURR_DESC_PTR,val)
1014 #define bfin_write_DMA2_2_CURR_ADDR(val) bfin_write32(DMA2_2_CURR_ADDR,val)
1016 #define bfin_write_DMA2_2_CURR_X_COUNT(val) bfin_write16(DMA2_2_CURR_X_COUNT,val)
1018 #define bfin_write_DMA2_2_CURR_Y_COUNT(val) bfin_write16(DMA2_2_CURR_Y_COUNT,val)
1020 #define bfin_write_DMA2_2_IRQ_STATUS(val) bfin_write16(DMA2_2_IRQ_STATUS,val)
1022 #define bfin_write_DMA2_2_PERIPHERAL_MAP(val) bfin_write16(DMA2_2_PERIPHERAL_MAP,val)
1024 #define bfin_write_DMA2_3_CONFIG(val) bfin_write16(DMA2_3_CONFIG,val)
1026 #define bfin_write_DMA2_3_NEXT_DESC_PTR(val) bfin_write32(DMA2_3_NEXT_DESC_PTR,val)
1028 #define bfin_write_DMA2_3_START_ADDR(val) bfin_write32(DMA2_3_START_ADDR,val)
1030 #define bfin_write_DMA2_3_X_COUNT(val) bfin_write16(DMA2_3_X_COUNT,val)
1032 #define bfin_write_DMA2_3_Y_COUNT(val) bfin_write16(DMA2_3_Y_COUNT,val)
1034 #define bfin_write_DMA2_3_X_MODIFY(val) bfin_write16(DMA2_3_X_MODIFY,val)
1036 #define bfin_write_DMA2_3_Y_MODIFY(val) bfin_write16(DMA2_3_Y_MODIFY,val)
1038 #define bfin_write_DMA2_3_CURR_DESC_PTR(val) bfin_write32(DMA2_3_CURR_DESC_PTR,val)
1040 #define bfin_write_DMA2_3_CURR_ADDR(val) bfin_write32(DMA2_3_CURR_ADDR,val)
1042 #define bfin_write_DMA2_3_CURR_X_COUNT(val) bfin_write16(DMA2_3_CURR_X_COUNT,val)
1044 #define bfin_write_DMA2_3_CURR_Y_COUNT(val) bfin_write16(DMA2_3_CURR_Y_COUNT,val)
1046 #define bfin_write_DMA2_3_IRQ_STATUS(val) bfin_write16(DMA2_3_IRQ_STATUS,val)
1048 #define bfin_write_DMA2_3_PERIPHERAL_MAP(val) bfin_write16(DMA2_3_PERIPHERAL_MAP,val)
1050 #define bfin_write_DMA2_4_CONFIG(val) bfin_write16(DMA2_4_CONFIG,val)
1052 #define bfin_write_DMA2_4_NEXT_DESC_PTR(val) bfin_write32(DMA2_4_NEXT_DESC_PTR,val)
1054 #define bfin_write_DMA2_4_START_ADDR(val) bfin_write32(DMA2_4_START_ADDR,val)
1056 #define bfin_write_DMA2_4_X_COUNT(val) bfin_write16(DMA2_4_X_COUNT,val)
1058 #define bfin_write_DMA2_4_Y_COUNT(val) bfin_write16(DMA2_4_Y_COUNT,val)
1060 #define bfin_write_DMA2_4_X_MODIFY(val) bfin_write16(DMA2_4_X_MODIFY,val)
1062 #define bfin_write_DMA2_4_Y_MODIFY(val) bfin_write16(DMA2_4_Y_MODIFY,val)
1064 #define bfin_write_DMA2_4_CURR_DESC_PTR(val) bfin_write32(DMA2_4_CURR_DESC_PTR,val)
1066 #define bfin_write_DMA2_4_CURR_ADDR(val) bfin_write32(DMA2_4_CURR_ADDR,val)
1068 #define bfin_write_DMA2_4_CURR_X_COUNT(val) bfin_write16(DMA2_4_CURR_X_COUNT,val)
1070 #define bfin_write_DMA2_4_CURR_Y_COUNT(val) bfin_write16(DMA2_4_CURR_Y_COUNT,val)
1072 #define bfin_write_DMA2_4_IRQ_STATUS(val) bfin_write16(DMA2_4_IRQ_STATUS,val)
1074 #define bfin_write_DMA2_4_PERIPHERAL_MAP(val) bfin_write16(DMA2_4_PERIPHERAL_MAP,val)
1076 #define bfin_write_DMA2_5_CONFIG(val) bfin_write16(DMA2_5_CONFIG,val)
1078 #define bfin_write_DMA2_5_NEXT_DESC_PTR(val) bfin_write32(DMA2_5_NEXT_DESC_PTR,val)
1080 #define bfin_write_DMA2_5_START_ADDR(val) bfin_write32(DMA2_5_START_ADDR,val)
1082 #define bfin_write_DMA2_5_X_COUNT(val) bfin_write16(DMA2_5_X_COUNT,val)
1084 #define bfin_write_DMA2_5_Y_COUNT(val) bfin_write16(DMA2_5_Y_COUNT,val)
1086 #define bfin_write_DMA2_5_X_MODIFY(val) bfin_write16(DMA2_5_X_MODIFY,val)
1088 #define bfin_write_DMA2_5_Y_MODIFY(val) bfin_write16(DMA2_5_Y_MODIFY,val)
1090 #define bfin_write_DMA2_5_CURR_DESC_PTR(val) bfin_write32(DMA2_5_CURR_DESC_PTR,val)
1092 #define bfin_write_DMA2_5_CURR_ADDR(val) bfin_write32(DMA2_5_CURR_ADDR,val)
1094 #define bfin_write_DMA2_5_CURR_X_COUNT(val) bfin_write16(DMA2_5_CURR_X_COUNT,val)
1096 #define bfin_write_DMA2_5_CURR_Y_COUNT(val) bfin_write16(DMA2_5_CURR_Y_COUNT,val)
1098 #define bfin_write_DMA2_5_IRQ_STATUS(val) bfin_write16(DMA2_5_IRQ_STATUS,val)
1100 #define bfin_write_DMA2_5_PERIPHERAL_MAP(val) bfin_write16(DMA2_5_PERIPHERAL_MAP,val)
1102 #define bfin_write_DMA2_6_CONFIG(val) bfin_write16(DMA2_6_CONFIG,val)
1104 #define bfin_write_DMA2_6_NEXT_DESC_PTR(val) bfin_write32(DMA2_6_NEXT_DESC_PTR,val)
1106 #define bfin_write_DMA2_6_START_ADDR(val) bfin_write32(DMA2_6_START_ADDR,val)
1108 #define bfin_write_DMA2_6_X_COUNT(val) bfin_write16(DMA2_6_X_COUNT,val)
1110 #define bfin_write_DMA2_6_Y_COUNT(val) bfin_write16(DMA2_6_Y_COUNT,val)
1112 #define bfin_write_DMA2_6_X_MODIFY(val) bfin_write16(DMA2_6_X_MODIFY,val)
1114 #define bfin_write_DMA2_6_Y_MODIFY(val) bfin_write16(DMA2_6_Y_MODIFY,val)
1116 #define bfin_write_DMA2_6_CURR_DESC_PTR(val) bfin_write32(DMA2_6_CURR_DESC_PTR,val)
1118 #define bfin_write_DMA2_6_CURR_ADDR(val) bfin_write32(DMA2_6_CURR_ADDR,val)
1120 #define bfin_write_DMA2_6_CURR_X_COUNT(val) bfin_write16(DMA2_6_CURR_X_COUNT,val)
1122 #define bfin_write_DMA2_6_CURR_Y_COUNT(val) bfin_write16(DMA2_6_CURR_Y_COUNT,val)
1124 #define bfin_write_DMA2_6_IRQ_STATUS(val) bfin_write16(DMA2_6_IRQ_STATUS,val)
1126 #define bfin_write_DMA2_6_PERIPHERAL_MAP(val) bfin_write16(DMA2_6_PERIPHERAL_MAP,val)
1128 #define bfin_write_DMA2_7_CONFIG(val) bfin_write16(DMA2_7_CONFIG,val)
1130 #define bfin_write_DMA2_7_NEXT_DESC_PTR(val) bfin_write32(DMA2_7_NEXT_DESC_PTR,val)
1132 #define bfin_write_DMA2_7_START_ADDR(val) bfin_write32(DMA2_7_START_ADDR,val)
1134 #define bfin_write_DMA2_7_X_COUNT(val) bfin_write16(DMA2_7_X_COUNT,val)
1136 #define bfin_write_DMA2_7_Y_COUNT(val) bfin_write16(DMA2_7_Y_COUNT,val)
1138 #define bfin_write_DMA2_7_X_MODIFY(val) bfin_write16(DMA2_7_X_MODIFY,val)
1140 #define bfin_write_DMA2_7_Y_MODIFY(val) bfin_write16(DMA2_7_Y_MODIFY,val)
1142 #define bfin_write_DMA2_7_CURR_DESC_PTR(val) bfin_write32(DMA2_7_CURR_DESC_PTR,val)
1144 #define bfin_write_DMA2_7_CURR_ADDR(val) bfin_write32(DMA2_7_CURR_ADDR,val)
1146 #define bfin_write_DMA2_7_CURR_X_COUNT(val) bfin_write16(DMA2_7_CURR_X_COUNT,val)
1148 #define bfin_write_DMA2_7_CURR_Y_COUNT(val) bfin_write16(DMA2_7_CURR_Y_COUNT,val)
1150 #define bfin_write_DMA2_7_IRQ_STATUS(val) bfin_write16(DMA2_7_IRQ_STATUS,val)
1152 #define bfin_write_DMA2_7_PERIPHERAL_MAP(val) bfin_write16(DMA2_7_PERIPHERAL_MAP,val)
1154 #define bfin_write_DMA2_8_CONFIG(val) bfin_write16(DMA2_8_CONFIG,val)
1156 #define bfin_write_DMA2_8_NEXT_DESC_PTR(val) bfin_write32(DMA2_8_NEXT_DESC_PTR,val)
1158 #define bfin_write_DMA2_8_START_ADDR(val) bfin_write32(DMA2_8_START_ADDR,val)
1160 #define bfin_write_DMA2_8_X_COUNT(val) bfin_write16(DMA2_8_X_COUNT,val)
1162 #define bfin_write_DMA2_8_Y_COUNT(val) bfin_write16(DMA2_8_Y_COUNT,val)
1164 #define bfin_write_DMA2_8_X_MODIFY(val) bfin_write16(DMA2_8_X_MODIFY,val)
1166 #define bfin_write_DMA2_8_Y_MODIFY(val) bfin_write16(DMA2_8_Y_MODIFY,val)
1168 #define bfin_write_DMA2_8_CURR_DESC_PTR(val) bfin_write32(DMA2_8_CURR_DESC_PTR,val)
1170 #define bfin_write_DMA2_8_CURR_ADDR(val) bfin_write32(DMA2_8_CURR_ADDR,val)
1172 #define bfin_write_DMA2_8_CURR_X_COUNT(val) bfin_write16(DMA2_8_CURR_X_COUNT,val)
1174 #define bfin_write_DMA2_8_CURR_Y_COUNT(val) bfin_write16(DMA2_8_CURR_Y_COUNT,val)
1176 #define bfin_write_DMA2_8_IRQ_STATUS(val) bfin_write16(DMA2_8_IRQ_STATUS,val)
1178 #define bfin_write_DMA2_8_PERIPHERAL_MAP(val) bfin_write16(DMA2_8_PERIPHERAL_MAP,val)
1180 #define bfin_write_DMA2_9_CONFIG(val) bfin_write16(DMA2_9_CONFIG,val)
1182 #define bfin_write_DMA2_9_NEXT_DESC_PTR(val) bfin_write32(DMA2_9_NEXT_DESC_PTR,val)
1184 #define bfin_write_DMA2_9_START_ADDR(val) bfin_write32(DMA2_9_START_ADDR,val)
1186 #define bfin_write_DMA2_9_X_COUNT(val) bfin_write16(DMA2_9_X_COUNT,val)
1188 #define bfin_write_DMA2_9_Y_COUNT(val) bfin_write16(DMA2_9_Y_COUNT,val)
1190 #define bfin_write_DMA2_9_X_MODIFY(val) bfin_write16(DMA2_9_X_MODIFY,val)
1192 #define bfin_write_DMA2_9_Y_MODIFY(val) bfin_write16(DMA2_9_Y_MODIFY,val)
1194 #define bfin_write_DMA2_9_CURR_DESC_PTR(val) bfin_write32(DMA2_9_CURR_DESC_PTR,val)
1196 #define bfin_write_DMA2_9_CURR_ADDR(val) bfin_write32(DMA2_9_CURR_ADDR,val)
1198 #define bfin_write_DMA2_9_CURR_X_COUNT(val) bfin_write16(DMA2_9_CURR_X_COUNT,val)
1200 #define bfin_write_DMA2_9_CURR_Y_COUNT(val) bfin_write16(DMA2_9_CURR_Y_COUNT,val)
1202 #define bfin_write_DMA2_9_IRQ_STATUS(val) bfin_write16(DMA2_9_IRQ_STATUS,val)
1204 #define bfin_write_DMA2_9_PERIPHERAL_MAP(val) bfin_write16(DMA2_9_PERIPHERAL_MAP,val)
1206 #define bfin_write_DMA2_10_CONFIG(val) bfin_write16(DMA2_10_CONFIG,val)
1208 #define bfin_write_DMA2_10_NEXT_DESC_PTR(val) bfin_write32(DMA2_10_NEXT_DESC_PTR,val)
1210 #define bfin_write_DMA2_10_START_ADDR(val) bfin_write32(DMA2_10_START_ADDR,val)
1212 #define bfin_write_DMA2_10_X_COUNT(val) bfin_write16(DMA2_10_X_COUNT,val)
1214 #define bfin_write_DMA2_10_Y_COUNT(val) bfin_write16(DMA2_10_Y_COUNT,val)
1216 #define bfin_write_DMA2_10_X_MODIFY(val) bfin_write16(DMA2_10_X_MODIFY,val)
1218 #define bfin_write_DMA2_10_Y_MODIFY(val) bfin_write16(DMA2_10_Y_MODIFY,val)
1220 #define bfin_write_DMA2_10_CURR_DESC_PTR(val) bfin_write32(DMA2_10_CURR_DESC_PTR,val)
1222 #define bfin_write_DMA2_10_CURR_ADDR(val) bfin_write32(DMA2_10_CURR_ADDR,val)
1224 #define bfin_write_DMA2_10_CURR_X_COUNT(val) bfin_write16(DMA2_10_CURR_X_COUNT,val)
1226 #define bfin_write_DMA2_10_CURR_Y_COUNT(val) bfin_write16(DMA2_10_CURR_Y_COUNT,val)
1228 #define bfin_write_DMA2_10_IRQ_STATUS(val) bfin_write16(DMA2_10_IRQ_STATUS,val)
1230 #define bfin_write_DMA2_10_PERIPHERAL_MAP(val) bfin_write16(DMA2_10_PERIPHERAL_MAP,val)
1232 #define bfin_write_DMA2_11_CONFIG(val) bfin_write16(DMA2_11_CONFIG,val)
1234 #define bfin_write_DMA2_11_NEXT_DESC_PTR(val) bfin_write32(DMA2_11_NEXT_DESC_PTR,val)
1236 #define bfin_write_DMA2_11_START_ADDR(val) bfin_write32(DMA2_11_START_ADDR,val)
1238 #define bfin_write_DMA2_11_X_COUNT(val) bfin_write16(DMA2_11_X_COUNT,val)
1240 #define bfin_write_DMA2_11_Y_COUNT(val) bfin_write16(DMA2_11_Y_COUNT,val)
1242 #define bfin_write_DMA2_11_X_MODIFY(val) bfin_write16(DMA2_11_X_MODIFY,val)
1244 #define bfin_write_DMA2_11_Y_MODIFY(val) bfin_write16(DMA2_11_Y_MODIFY,val)
1246 #define bfin_write_DMA2_11_CURR_DESC_PTR(val) bfin_write32(DMA2_11_CURR_DESC_PTR,val)
1248 #define bfin_write_DMA2_11_CURR_ADDR(val) bfin_write32(DMA2_11_CURR_ADDR,val)
1250 #define bfin_write_DMA2_11_CURR_X_COUNT(val) bfin_write16(DMA2_11_CURR_X_COUNT,val)
1252 #define bfin_write_DMA2_11_CURR_Y_COUNT(val) bfin_write16(DMA2_11_CURR_Y_COUNT,val)
1254 #define bfin_write_DMA2_11_IRQ_STATUS(val) bfin_write16(DMA2_11_IRQ_STATUS,val)
1256 #define bfin_write_DMA2_11_PERIPHERAL_MAP(val) bfin_write16(DMA2_11_PERIPHERAL_MAP,val)
1259 #define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG,val)
1261 #define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR,val)
1263 #define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR,val)
1265 #define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT,val)
1267 #define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT,val)
1269 #define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY,val)
1271 #define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY,val)
1273 #define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR,val)
1275 #define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR,val)
1277 #define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT,val)
1279 #define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT,val)
1281 #define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS,val)
1283 #define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP,val)
1285 #define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG,val)
1287 #define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR,val)
1289 #define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR,val)
1291 #define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT,val)
1293 #define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT,val)
1295 #define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY,val)
1297 #define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY,val)
1299 #define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR,val)
1301 #define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR,val)
1303 #define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT,val)
1305 #define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT,val)
1307 #define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS,val)
1309 #define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP,val)
1311 #define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG,val)
1313 #define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR,val)
1315 #define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR,val)
1317 #define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT,val)
1319 #define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT,val)
1321 #define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY,val)
1323 #define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY,val)
1325 #define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR,val)
1327 #define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR,val)
1329 #define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT,val)
1331 #define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT,val)
1333 #define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS,val)
1335 #define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP,val)
1337 #define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG,val)
1339 #define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR,val)
1341 #define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR,val)
1343 #define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT,val)
1345 #define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT,val)
1347 #define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY,val)
1349 #define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY,val)
1351 #define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR,val)
1353 #define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR,val)
1355 #define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT,val)
1357 #define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT,val)
1359 #define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS,val)
1361 #define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP,val)
1364 #define bfin_write_IMDMA_D0_CONFIG(val) bfin_write16(IMDMA_D0_CONFIG,val)
1366 #define bfin_write_IMDMA_D0_NEXT_DESC_PTR(val) bfin_write32(IMDMA_D0_NEXT_DESC_PTR,val)
1368 #define bfin_write_IMDMA_D0_START_ADDR(val) bfin_write32(IMDMA_D0_START_ADDR,val)
1370 #define bfin_write_IMDMA_D0_X_COUNT(val) bfin_write16(IMDMA_D0_X_COUNT,val)
1372 #define bfin_write_IMDMA_D0_Y_COUNT(val) bfin_write16(IMDMA_D0_Y_COUNT,val)
1374 #define bfin_write_IMDMA_D0_X_MODIFY(val) bfin_write16(IMDMA_D0_X_MODIFY,val)
1376 #define bfin_write_IMDMA_D0_Y_MODIFY(val) bfin_write16(IMDMA_D0_Y_MODIFY,val)
1378 #define bfin_write_IMDMA_D0_CURR_DESC_PTR(val) bfin_write32(IMDMA_D0_CURR_DESC_PTR,val)
1380 #define bfin_write_IMDMA_D0_CURR_ADDR(val) bfin_write32(IMDMA_D0_CURR_ADDR,val)
1382 #define bfin_write_IMDMA_D0_CURR_X_COUNT(val) bfin_write16(IMDMA_D0_CURR_X_COUNT,val)
1384 #define bfin_write_IMDMA_D0_CURR_Y_COUNT(val) bfin_write16(IMDMA_D0_CURR_Y_COUNT,val)
1386 #define bfin_write_IMDMA_D0_IRQ_STATUS(val) bfin_write16(IMDMA_D0_IRQ_STATUS,val)
1388 #define bfin_write_IMDMA_S0_CONFIG(val) bfin_write16(IMDMA_S0_CONFIG,val)
1390 #define bfin_write_IMDMA_S0_NEXT_DESC_PTR(val) bfin_write32(IMDMA_S0_NEXT_DESC_PTR,val)
1392 #define bfin_write_IMDMA_S0_START_ADDR(val) bfin_write32(IMDMA_S0_START_ADDR,val)
1394 #define bfin_write_IMDMA_S0_X_COUNT(val) bfin_write16(IMDMA_S0_X_COUNT,val)
1396 #define bfin_write_IMDMA_S0_Y_COUNT(val) bfin_write16(IMDMA_S0_Y_COUNT,val)
1398 #define bfin_write_IMDMA_S0_X_MODIFY(val) bfin_write16(IMDMA_S0_X_MODIFY,val)
1400 #define bfin_write_IMDMA_S0_Y_MODIFY(val) bfin_write16(IMDMA_S0_Y_MODIFY,val)
1402 #define bfin_write_IMDMA_S0_CURR_DESC_PTR(val) bfin_write32(IMDMA_S0_CURR_DESC_PTR,val)
1404 #define bfin_write_IMDMA_S0_CURR_ADDR(val) bfin_write32(IMDMA_S0_CURR_ADDR,val)
1406 #define bfin_write_IMDMA_S0_CURR_X_COUNT(val) bfin_write16(IMDMA_S0_CURR_X_COUNT,val)
1408 #define bfin_write_IMDMA_S0_CURR_Y_COUNT(val) bfin_write16(IMDMA_S0_CURR_Y_COUNT,val)
1410 #define bfin_write_IMDMA_S0_IRQ_STATUS(val) bfin_write16(IMDMA_S0_IRQ_STATUS,val)
1412 #define bfin_write_IMDMA_D1_CONFIG(val) bfin_write16(IMDMA_D1_CONFIG,val)
1414 #define bfin_write_IMDMA_D1_NEXT_DESC_PTR(val) bfin_write32(IMDMA_D1_NEXT_DESC_PTR,val)
1416 #define bfin_write_IMDMA_D1_START_ADDR(val) bfin_write32(IMDMA_D1_START_ADDR,val)
1418 #define bfin_write_IMDMA_D1_X_COUNT(val) bfin_write16(IMDMA_D1_X_COUNT,val)
1420 #define bfin_write_IMDMA_D1_Y_COUNT(val) bfin_write16(IMDMA_D1_Y_COUNT,val)
1422 #define bfin_write_IMDMA_D1_X_MODIFY(val) bfin_write16(IMDMA_D1_X_MODIFY,val)
1424 #define bfin_write_IMDMA_D1_Y_MODIFY(val) bfin_write16(IMDMA_D1_Y_MODIFY,val)
1426 #define bfin_write_IMDMA_D1_CURR_DESC_PTR(val) bfin_write32(IMDMA_D1_CURR_DESC_PTR,val)
1428 #define bfin_write_IMDMA_D1_CURR_ADDR(val) bfin_write32(IMDMA_D1_CURR_ADDR,val)
1430 #define bfin_write_IMDMA_D1_CURR_X_COUNT(val) bfin_write16(IMDMA_D1_CURR_X_COUNT,val)
1432 #define bfin_write_IMDMA_D1_CURR_Y_COUNT(val) bfin_write16(IMDMA_D1_CURR_Y_COUNT,val)
1434 #define bfin_write_IMDMA_D1_IRQ_STATUS(val) bfin_write16(IMDMA_D1_IRQ_STATUS,val)
1436 #define bfin_write_IMDMA_S1_CONFIG(val) bfin_write16(IMDMA_S1_CONFIG,val)
1438 #define bfin_write_IMDMA_S1_NEXT_DESC_PTR(val) bfin_write32(IMDMA_S1_NEXT_DESC_PTR,val)
1440 #define bfin_write_IMDMA_S1_START_ADDR(val) bfin_write32(IMDMA_S1_START_ADDR,val)
1442 #define bfin_write_IMDMA_S1_X_COUNT(val) bfin_write16(IMDMA_S1_X_COUNT,val)
1444 #define bfin_write_IMDMA_S1_Y_COUNT(val) bfin_write16(IMDMA_S1_Y_COUNT,val)
1446 #define bfin_write_IMDMA_S1_X_MODIFY(val) bfin_write16(IMDMA_S1_X_MODIFY,val)
1448 #define bfin_write_IMDMA_S1_Y_MODIFY(val) bfin_write16(IMDMA_S1_Y_MODIFY,val)
1450 #define bfin_write_IMDMA_S1_CURR_DESC_PTR(val) bfin_write32(IMDMA_S1_CURR_DESC_PTR,val)
1452 #define bfin_write_IMDMA_S1_CURR_ADDR(val) bfin_write32(IMDMA_S1_CURR_ADDR,val)
1454 #define bfin_write_IMDMA_S1_CURR_X_COUNT(val) bfin_write16(IMDMA_S1_CURR_X_COUNT,val)
1456 #define bfin_write_IMDMA_S1_CURR_Y_COUNT(val) bfin_write16(IMDMA_S1_CURR_Y_COUNT,val)
1458 #define bfin_write_IMDMA_S1_IRQ_STATUS(val) bfin_write16(IMDMA_S1_IRQ_STATUS,val)
H A Dblackfin.h24 #define bfin_write_FIO_FLAG_D(val) bfin_write_FIO0_FLAG_D(val)
26 #define bfin_write_FIO_DIR(val) bfin_write_FIO0_DIR(val)
28 #define bfin_write_FIO_INEN(val) bfin_write_FIO0_INEN(val)
33 #define bfin_write_SIC_IMASK(x, val) bfin_write32(__SIC_MUX(SIC_IMASK0, x), val)
35 #define bfin_write_SICB_IMASK(x, val) bfin_write32(__SIC_MUX(SICB_IMASK0, x), val)
37 #define bfin_write_SIC_ISR(x, val) bfin_write32(__SIC_MUX(SIC_ISR0, x), val)
39 #define bfin_write_SICB_ISR(x, val) bfin_write32(__SIC_MUX(SICB_ISR0, x), val)
/linux-4.1.27/arch/blackfin/mach-bf538/include/mach/
H A DcdefBF538.h10 #define bfin_writePTR(addr, val) bfin_write32(addr, val)
14 #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
17 #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
19 #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
21 #define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
23 #define bfin_write_SWRST(val) bfin_write16(SWRST, val)
25 #define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
27 #define bfin_write_SIC_RVECT(val) bfin_writePTR(SIC_RVECT, val)
29 #define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
31 #define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
33 #define bfin_write_SIC_IMASK(x, val) bfin_write32(SIC_IMASK0 + x * (SIC_IMASK1 - SIC_IMASK0), val)
35 #define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
37 #define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
39 #define bfin_write_SIC_ISR(x, val) bfin_write32(SIC_ISR0 + x * (SIC_ISR1 - SIC_ISR0), val)
41 #define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
43 #define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val)
45 #define bfin_write_SIC_IWR(x, val) bfin_write32(SIC_IWR0 + x * (SIC_IWR1 - SIC_IWR0), val)
47 #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
49 #define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
51 #define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
53 #define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
55 #define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val)
57 #define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val)
59 #define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val)
61 #define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
63 #define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
65 #define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
67 #define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val)
69 #define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val)
71 #define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val)
73 #define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val)
75 #define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val)
77 #define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val)
79 #define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val)
81 #define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val)
83 #define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val)
85 #define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val)
87 #define bfin_write_UART0_IER(val) bfin_write16(UART0_IER, val)
89 #define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR, val)
91 #define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val)
93 #define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val)
95 #define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val)
97 #define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val)
99 #define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val)
101 #define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val)
103 #define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val)
105 #define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val)
107 #define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val)
109 #define bfin_write_UART1_IER(val) bfin_write16(UART1_IER, val)
111 #define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR, val)
113 #define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val)
115 #define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val)
117 #define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val)
119 #define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val)
121 #define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val)
123 #define bfin_write_UART2_THR(val) bfin_write16(UART2_THR, val)
125 #define bfin_write_UART2_RBR(val) bfin_write16(UART2_RBR, val)
127 #define bfin_write_UART2_DLL(val) bfin_write16(UART2_DLL, val)
129 #define bfin_write_UART2_DLH(val) bfin_write16(UART2_DLH, val)
131 #define bfin_write_UART2_IER(val) bfin_write16(UART2_IER, val)
133 #define bfin_write_UART2_IIR(val) bfin_write16(UART2_IIR, val)
135 #define bfin_write_UART2_LCR(val) bfin_write16(UART2_LCR, val)
137 #define bfin_write_UART2_MCR(val) bfin_write16(UART2_MCR, val)
139 #define bfin_write_UART2_LSR(val) bfin_write16(UART2_LSR, val)
141 #define bfin_write_UART2_SCR(val) bfin_write16(UART2_SCR, val)
143 #define bfin_write_UART2_GCTL(val) bfin_write16(UART2_GCTL, val)
145 #define bfin_write_SPI0_CTL(val) bfin_write16(SPI0_CTL, val)
147 #define bfin_write_SPI0_FLG(val) bfin_write16(SPI0_FLG, val)
149 #define bfin_write_SPI0_STAT(val) bfin_write16(SPI0_STAT, val)
151 #define bfin_write_SPI0_TDBR(val) bfin_write16(SPI0_TDBR, val)
153 #define bfin_write_SPI0_RDBR(val) bfin_write16(SPI0_RDBR, val)
155 #define bfin_write_SPI0_BAUD(val) bfin_write16(SPI0_BAUD, val)
157 #define bfin_write_SPI0_SHADOW(val) bfin_write16(SPI0_SHADOW, val)
159 #define bfin_write_SPI1_CTL(val) bfin_write16(SPI1_CTL, val)
161 #define bfin_write_SPI1_FLG(val) bfin_write16(SPI1_FLG, val)
163 #define bfin_write_SPI1_STAT(val) bfin_write16(SPI1_STAT, val)
165 #define bfin_write_SPI1_TDBR(val) bfin_write16(SPI1_TDBR, val)
167 #define bfin_write_SPI1_RDBR(val) bfin_write16(SPI1_RDBR, val)
169 #define bfin_write_SPI1_BAUD(val) bfin_write16(SPI1_BAUD, val)
171 #define bfin_write_SPI1_SHADOW(val) bfin_write16(SPI1_SHADOW, val)
173 #define bfin_write_SPI2_CTL(val) bfin_write16(SPI2_CTL, val)
175 #define bfin_write_SPI2_FLG(val) bfin_write16(SPI2_FLG, val)
177 #define bfin_write_SPI2_STAT(val) bfin_write16(SPI2_STAT, val)
179 #define bfin_write_SPI2_TDBR(val) bfin_write16(SPI2_TDBR, val)
181 #define bfin_write_SPI2_RDBR(val) bfin_write16(SPI2_RDBR, val)
183 #define bfin_write_SPI2_BAUD(val) bfin_write16(SPI2_BAUD, val)
185 #define bfin_write_SPI2_SHADOW(val) bfin_write16(SPI2_SHADOW, val)
187 #define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
189 #define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
191 #define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
193 #define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
195 #define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
197 #define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
199 #define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
201 #define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
203 #define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
205 #define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
207 #define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
209 #define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
211 #define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val)
213 #define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val)
215 #define bfin_write_TIMER_STATUS(val) bfin_write16(TIMER_STATUS, val)
217 #define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
219 #define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
221 #define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
223 #define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
225 #define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
227 #define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
229 #define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
231 #define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
233 #define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
235 #define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
237 #define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
239 #define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
241 #define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
243 #define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
245 #define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
247 #define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
249 #define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
251 #define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
253 #define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
255 #define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
257 #define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
259 #define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
261 #define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val)
263 #define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val)
265 #define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
267 #define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
269 #define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
271 #define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
273 #define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
275 #define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val)
277 #define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
279 #define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val)
281 #define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val)
283 #define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val)
285 #define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val)
287 #define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val)
289 #define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val)
291 #define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val)
293 #define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val)
295 #define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val)
297 #define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val)
299 #define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val)
301 #define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val)
303 #define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val)
305 #define bfin_write_SPORT2_TCR1(val) bfin_write16(SPORT2_TCR1, val)
307 #define bfin_write_SPORT2_TCR2(val) bfin_write16(SPORT2_TCR2, val)
309 #define bfin_write_SPORT2_TCLKDIV(val) bfin_write16(SPORT2_TCLKDIV, val)
311 #define bfin_write_SPORT2_TFSDIV(val) bfin_write16(SPORT2_TFSDIV, val)
313 #define bfin_write_SPORT2_TX(val) bfin_write32(SPORT2_TX, val)
315 #define bfin_write_SPORT2_RX(val) bfin_write32(SPORT2_RX, val)
317 #define bfin_write_SPORT2_RCR1(val) bfin_write16(SPORT2_RCR1, val)
319 #define bfin_write_SPORT2_RCR2(val) bfin_write16(SPORT2_RCR2, val)
321 #define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val)
323 #define bfin_write_SPORT2_RFSDIV(val) bfin_write16(SPORT2_RFSDIV, val)
325 #define bfin_write_SPORT2_STAT(val) bfin_write16(SPORT2_STAT, val)
327 #define bfin_write_SPORT2_CHNL(val) bfin_write16(SPORT2_CHNL, val)
329 #define bfin_write_SPORT2_MCMC1(val) bfin_write16(SPORT2_MCMC1, val)
331 #define bfin_write_SPORT2_MCMC2(val) bfin_write16(SPORT2_MCMC2, val)
333 #define bfin_write_SPORT2_MTCS0(val) bfin_write32(SPORT2_MTCS0, val)
335 #define bfin_write_SPORT2_MTCS1(val) bfin_write32(SPORT2_MTCS1, val)
337 #define bfin_write_SPORT2_MTCS2(val) bfin_write32(SPORT2_MTCS2, val)
339 #define bfin_write_SPORT2_MTCS3(val) bfin_write32(SPORT2_MTCS3, val)
341 #define bfin_write_SPORT2_MRCS0(val) bfin_write32(SPORT2_MRCS0, val)
343 #define bfin_write_SPORT2_MRCS1(val) bfin_write32(SPORT2_MRCS1, val)
345 #define bfin_write_SPORT2_MRCS2(val) bfin_write32(SPORT2_MRCS2, val)
347 #define bfin_write_SPORT2_MRCS3(val) bfin_write32(SPORT2_MRCS3, val)
349 #define bfin_write_SPORT3_TCR1(val) bfin_write16(SPORT3_TCR1, val)
351 #define bfin_write_SPORT3_TCR2(val) bfin_write16(SPORT3_TCR2, val)
353 #define bfin_write_SPORT3_TCLKDIV(val) bfin_write16(SPORT3_TCLKDIV, val)
355 #define bfin_write_SPORT3_TFSDIV(val) bfin_write16(SPORT3_TFSDIV, val)
357 #define bfin_write_SPORT3_TX(val) bfin_write32(SPORT3_TX, val)
359 #define bfin_write_SPORT3_RX(val) bfin_write32(SPORT3_RX, val)
361 #define bfin_write_SPORT3_RCR1(val) bfin_write16(SPORT3_RCR1, val)
363 #define bfin_write_SPORT3_RCR2(val) bfin_write16(SPORT3_RCR2, val)
365 #define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val)
367 #define bfin_write_SPORT3_RFSDIV(val) bfin_write16(SPORT3_RFSDIV, val)
369 #define bfin_write_SPORT3_STAT(val) bfin_write16(SPORT3_STAT, val)
371 #define bfin_write_SPORT3_CHNL(val) bfin_write16(SPORT3_CHNL, val)
373 #define bfin_write_SPORT3_MCMC1(val) bfin_write16(SPORT3_MCMC1, val)
375 #define bfin_write_SPORT3_MCMC2(val) bfin_write16(SPORT3_MCMC2, val)
377 #define bfin_write_SPORT3_MTCS0(val) bfin_write32(SPORT3_MTCS0, val)
379 #define bfin_write_SPORT3_MTCS1(val) bfin_write32(SPORT3_MTCS1, val)
381 #define bfin_write_SPORT3_MTCS2(val) bfin_write32(SPORT3_MTCS2, val)
383 #define bfin_write_SPORT3_MTCS3(val) bfin_write32(SPORT3_MTCS3, val)
385 #define bfin_write_SPORT3_MRCS0(val) bfin_write32(SPORT3_MRCS0, val)
387 #define bfin_write_SPORT3_MRCS1(val) bfin_write32(SPORT3_MRCS1, val)
389 #define bfin_write_SPORT3_MRCS2(val) bfin_write32(SPORT3_MRCS2, val)
391 #define bfin_write_SPORT3_MRCS3(val) bfin_write32(SPORT3_MRCS3, val)
393 #define bfin_write_PORTFIO(val) bfin_write16(PORTFIO, val)
395 #define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR, val)
397 #define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET, val)
399 #define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val)
401 #define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA, val)
403 #define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val)
405 #define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val)
407 #define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val)
409 #define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB, val)
411 #define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val)
413 #define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val)
415 #define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val)
417 #define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR, val)
419 #define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR, val)
421 #define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE, val)
423 #define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH, val)
425 #define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN, val)
427 #define bfin_write_PORTCIO_FER(val) bfin_write16(PORTCIO_FER, val)
429 #define bfin_write_PORTCIO(val) bfin_write16(PORTCIO, val)
431 #define bfin_write_PORTCIO_CLEAR(val) bfin_write16(PORTCIO_CLEAR, val)
433 #define bfin_write_PORTCIO_SET(val) bfin_write16(PORTCIO_SET, val)
435 #define bfin_write_PORTCIO_TOGGLE(val) bfin_write16(PORTCIO_TOGGLE, val)
437 #define bfin_write_PORTCIO_DIR(val) bfin_write16(PORTCIO_DIR, val)
439 #define bfin_write_PORTCIO_INEN(val) bfin_write16(PORTCIO_INEN, val)
441 #define bfin_write_PORTDIO_FER(val) bfin_write16(PORTDIO_FER, val)
443 #define bfin_write_PORTDIO(val) bfin_write16(PORTDIO, val)
445 #define bfin_write_PORTDIO_CLEAR(val) bfin_write16(PORTDIO_CLEAR, val)
447 #define bfin_write_PORTDIO_SET(val) bfin_write16(PORTDIO_SET, val)
449 #define bfin_write_PORTDIO_TOGGLE(val) bfin_write16(PORTDIO_TOGGLE, val)
451 #define bfin_write_PORTDIO_DIR(val) bfin_write16(PORTDIO_DIR, val)
453 #define bfin_write_PORTDIO_INEN(val) bfin_write16(PORTDIO_INEN, val)
455 #define bfin_write_PORTEIO_FER(val) bfin_write16(PORTEIO_FER, val)
457 #define bfin_write_PORTEIO(val) bfin_write16(PORTEIO, val)
459 #define bfin_write_PORTEIO_CLEAR(val) bfin_write16(PORTEIO_CLEAR, val)
461 #define bfin_write_PORTEIO_SET(val) bfin_write16(PORTEIO_SET, val)
463 #define bfin_write_PORTEIO_TOGGLE(val) bfin_write16(PORTEIO_TOGGLE, val)
465 #define bfin_write_PORTEIO_DIR(val) bfin_write16(PORTEIO_DIR, val)
467 #define bfin_write_PORTEIO_INEN(val) bfin_write16(PORTEIO_INEN, val)
469 #define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val)
471 #define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
473 #define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
475 #define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val)
477 #define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val)
479 #define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val)
481 #define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val)
483 #define bfin_write_DMAC0_TC_PER(val) bfin_write16(DMAC0_TC_PER, val)
485 #define bfin_write_DMAC0_TC_CNT(val) bfin_write16(DMAC0_TC_CNT, val)
487 #define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
489 #define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
491 #define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val)
493 #define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val)
495 #define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val)
497 #define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val)
499 #define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val)
501 #define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
503 #define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
505 #define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
507 #define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
509 #define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
511 #define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
513 #define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
515 #define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
517 #define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
519 #define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val)
521 #define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val)
523 #define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val)
525 #define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val)
527 #define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
529 #define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
531 #define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
533 #define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
535 #define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
537 #define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
539 #define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
541 #define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
543 #define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val)
545 #define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val)
547 #define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val)
549 #define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val)
551 #define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val)
553 #define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
555 #define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
557 #define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
559 #define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
561 #define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
563 #define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
565 #define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
567 #define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
569 #define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
571 #define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val)
573 #define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val)
575 #define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val)
577 #define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val)
579 #define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
581 #define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
583 #define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
585 #define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
587 #define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
589 #define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
591 #define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
593 #define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
595 #define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val)
597 #define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val)
599 #define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val)
601 #define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val)
603 #define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val)
605 #define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
607 #define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
609 #define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
611 #define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
613 #define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
615 #define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
617 #define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
619 #define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
621 #define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
623 #define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val)
625 #define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val)
627 #define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
629 #define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val)
631 #define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
633 #define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
635 #define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
637 #define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
639 #define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
641 #define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
643 #define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_writePTR(DMA6_NEXT_DESC_PTR, val)
645 #define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
647 #define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val)
649 #define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val)
651 #define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val)
653 #define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val)
655 #define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val)
657 #define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
659 #define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
661 #define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
663 #define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
665 #define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
667 #define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
669 #define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
671 #define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
673 #define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val)
675 #define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val)
677 #define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val)
679 #define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val)
681 #define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val)
683 #define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
685 #define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
687 #define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
689 #define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
691 #define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
693 #define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
695 #define bfin_write_DMAC1_TC_PER(val) bfin_write16(DMAC1_TC_PER, val)
697 #define bfin_write_DMAC1_TC_CNT(val) bfin_write16(DMAC1_TC_CNT, val)
699 #define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
701 #define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
703 #define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val)
705 #define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val)
707 #define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val)
709 #define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val)
711 #define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val)
713 #define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
715 #define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
717 #define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
719 #define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
721 #define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
723 #define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
725 #define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
727 #define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
729 #define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val)
731 #define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val)
733 #define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val)
735 #define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val)
737 #define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val)
739 #define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
741 #define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
743 #define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
745 #define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
747 #define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
749 #define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
751 #define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
753 #define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
755 #define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val)
757 #define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val)
759 #define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
761 #define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val)
763 #define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
765 #define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
767 #define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
769 #define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
771 #define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
773 #define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
775 #define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
777 #define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
779 #define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
781 #define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val)
783 #define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val)
785 #define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
787 #define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val)
789 #define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
791 #define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
793 #define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
795 #define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
797 #define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
799 #define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
801 #define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
803 #define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_writePTR(DMA12_NEXT_DESC_PTR, val)
805 #define bfin_write_DMA12_START_ADDR(val) bfin_writePTR(DMA12_START_ADDR, val)
807 #define bfin_write_DMA12_CONFIG(val) bfin_write16(DMA12_CONFIG, val)
809 #define bfin_write_DMA12_X_COUNT(val) bfin_write16(DMA12_X_COUNT, val)
811 #define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val)
813 #define bfin_write_DMA12_Y_COUNT(val) bfin_write16(DMA12_Y_COUNT, val)
815 #define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val)
817 #define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_writePTR(DMA12_CURR_DESC_PTR, val)
819 #define bfin_write_DMA12_CURR_ADDR(val) bfin_writePTR(DMA12_CURR_ADDR, val)
821 #define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val)
823 #define bfin_write_DMA12_PERIPHERAL_MAP(val) bfin_write16(DMA12_PERIPHERAL_MAP, val)
825 #define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write16(DMA12_CURR_X_COUNT, val)
827 #define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write16(DMA12_CURR_Y_COUNT, val)
829 #define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_writePTR(DMA13_NEXT_DESC_PTR, val)
831 #define bfin_write_DMA13_START_ADDR(val) bfin_writePTR(DMA13_START_ADDR, val)
833 #define bfin_write_DMA13_CONFIG(val) bfin_write16(DMA13_CONFIG, val)
835 #define bfin_write_DMA13_X_COUNT(val) bfin_write16(DMA13_X_COUNT, val)
837 #define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val)
839 #define bfin_write_DMA13_Y_COUNT(val) bfin_write16(DMA13_Y_COUNT, val)
841 #define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val)
843 #define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_writePTR(DMA13_CURR_DESC_PTR, val)
845 #define bfin_write_DMA13_CURR_ADDR(val) bfin_writePTR(DMA13_CURR_ADDR, val)
847 #define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val)
849 #define bfin_write_DMA13_PERIPHERAL_MAP(val) bfin_write16(DMA13_PERIPHERAL_MAP, val)
851 #define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write16(DMA13_CURR_X_COUNT, val)
853 #define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write16(DMA13_CURR_Y_COUNT, val)
855 #define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_writePTR(DMA14_NEXT_DESC_PTR, val)
857 #define bfin_write_DMA14_START_ADDR(val) bfin_writePTR(DMA14_START_ADDR, val)
859 #define bfin_write_DMA14_CONFIG(val) bfin_write16(DMA14_CONFIG, val)
861 #define bfin_write_DMA14_X_COUNT(val) bfin_write16(DMA14_X_COUNT, val)
863 #define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val)
865 #define bfin_write_DMA14_Y_COUNT(val) bfin_write16(DMA14_Y_COUNT, val)
867 #define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val)
869 #define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_writePTR(DMA14_CURR_DESC_PTR, val)
871 #define bfin_write_DMA14_CURR_ADDR(val) bfin_writePTR(DMA14_CURR_ADDR, val)
873 #define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val)
875 #define bfin_write_DMA14_PERIPHERAL_MAP(val) bfin_write16(DMA14_PERIPHERAL_MAP, val)
877 #define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write16(DMA14_CURR_X_COUNT, val)
879 #define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write16(DMA14_CURR_Y_COUNT, val)
881 #define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_writePTR(DMA15_NEXT_DESC_PTR, val)
883 #define bfin_write_DMA15_START_ADDR(val) bfin_writePTR(DMA15_START_ADDR, val)
885 #define bfin_write_DMA15_CONFIG(val) bfin_write16(DMA15_CONFIG, val)
887 #define bfin_write_DMA15_X_COUNT(val) bfin_write16(DMA15_X_COUNT, val)
889 #define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val)
891 #define bfin_write_DMA15_Y_COUNT(val) bfin_write16(DMA15_Y_COUNT, val)
893 #define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val)
895 #define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_writePTR(DMA15_CURR_DESC_PTR, val)
897 #define bfin_write_DMA15_CURR_ADDR(val) bfin_writePTR(DMA15_CURR_ADDR, val)
899 #define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val)
901 #define bfin_write_DMA15_PERIPHERAL_MAP(val) bfin_write16(DMA15_PERIPHERAL_MAP, val)
903 #define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write16(DMA15_CURR_X_COUNT, val)
905 #define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write16(DMA15_CURR_Y_COUNT, val)
907 #define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_writePTR(DMA16_NEXT_DESC_PTR, val)
909 #define bfin_write_DMA16_START_ADDR(val) bfin_writePTR(DMA16_START_ADDR, val)
911 #define bfin_write_DMA16_CONFIG(val) bfin_write16(DMA16_CONFIG, val)
913 #define bfin_write_DMA16_X_COUNT(val) bfin_write16(DMA16_X_COUNT, val)
915 #define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val)
917 #define bfin_write_DMA16_Y_COUNT(val) bfin_write16(DMA16_Y_COUNT, val)
919 #define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val)
921 #define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_writePTR(DMA16_CURR_DESC_PTR, val)
923 #define bfin_write_DMA16_CURR_ADDR(val) bfin_writePTR(DMA16_CURR_ADDR, val)
925 #define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val)
927 #define bfin_write_DMA16_PERIPHERAL_MAP(val) bfin_write16(DMA16_PERIPHERAL_MAP, val)
929 #define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write16(DMA16_CURR_X_COUNT, val)
931 #define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write16(DMA16_CURR_Y_COUNT, val)
933 #define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_writePTR(DMA17_NEXT_DESC_PTR, val)
935 #define bfin_write_DMA17_START_ADDR(val) bfin_writePTR(DMA17_START_ADDR, val)
937 #define bfin_write_DMA17_CONFIG(val) bfin_write16(DMA17_CONFIG, val)
939 #define bfin_write_DMA17_X_COUNT(val) bfin_write16(DMA17_X_COUNT, val)
941 #define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val)
943 #define bfin_write_DMA17_Y_COUNT(val) bfin_write16(DMA17_Y_COUNT, val)
945 #define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val)
947 #define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_writePTR(DMA17_CURR_DESC_PTR, val)
949 #define bfin_write_DMA17_CURR_ADDR(val) bfin_writePTR(DMA17_CURR_ADDR, val)
951 #define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val)
953 #define bfin_write_DMA17_PERIPHERAL_MAP(val) bfin_write16(DMA17_PERIPHERAL_MAP, val)
955 #define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write16(DMA17_CURR_X_COUNT, val)
957 #define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write16(DMA17_CURR_Y_COUNT, val)
959 #define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_writePTR(DMA18_NEXT_DESC_PTR, val)
961 #define bfin_write_DMA18_START_ADDR(val) bfin_writePTR(DMA18_START_ADDR, val)
963 #define bfin_write_DMA18_CONFIG(val) bfin_write16(DMA18_CONFIG, val)
965 #define bfin_write_DMA18_X_COUNT(val) bfin_write16(DMA18_X_COUNT, val)
967 #define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val)
969 #define bfin_write_DMA18_Y_COUNT(val) bfin_write16(DMA18_Y_COUNT, val)
971 #define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val)
973 #define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_writePTR(DMA18_CURR_DESC_PTR, val)
975 #define bfin_write_DMA18_CURR_ADDR(val) bfin_writePTR(DMA18_CURR_ADDR, val)
977 #define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val)
979 #define bfin_write_DMA18_PERIPHERAL_MAP(val) bfin_write16(DMA18_PERIPHERAL_MAP, val)
981 #define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write16(DMA18_CURR_X_COUNT, val)
983 #define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write16(DMA18_CURR_Y_COUNT, val)
985 #define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_writePTR(DMA19_NEXT_DESC_PTR, val)
987 #define bfin_write_DMA19_START_ADDR(val) bfin_writePTR(DMA19_START_ADDR, val)
989 #define bfin_write_DMA19_CONFIG(val) bfin_write16(DMA19_CONFIG, val)
991 #define bfin_write_DMA19_X_COUNT(val) bfin_write16(DMA19_X_COUNT, val)
993 #define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val)
995 #define bfin_write_DMA19_Y_COUNT(val) bfin_write16(DMA19_Y_COUNT, val)
997 #define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val)
999 #define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_writePTR(DMA19_CURR_DESC_PTR, val)
1001 #define bfin_write_DMA19_CURR_ADDR(val) bfin_writePTR(DMA19_CURR_ADDR, val)
1003 #define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val)
1005 #define bfin_write_DMA19_PERIPHERAL_MAP(val) bfin_write16(DMA19_PERIPHERAL_MAP, val)
1007 #define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val)
1009 #define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val)
1011 #define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
1013 #define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
1015 #define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
1017 #define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
1019 #define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
1021 #define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
1023 #define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
1025 #define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
1027 #define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
1029 #define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
1031 #define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
1033 #define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
1035 #define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
1037 #define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
1039 #define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
1041 #define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
1043 #define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
1045 #define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
1047 #define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
1049 #define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
1051 #define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
1053 #define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
1055 #define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
1057 #define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
1059 #define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
1061 #define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
1063 #define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
1065 #define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
1067 #define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
1069 #define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
1071 #define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
1073 #define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
1075 #define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
1077 #define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
1079 #define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
1081 #define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
1083 #define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
1085 #define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
1087 #define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
1089 #define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
1091 #define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
1093 #define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
1095 #define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
1097 #define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
1099 #define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
1101 #define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
1103 #define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
1105 #define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
1107 #define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
1109 #define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
1111 #define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
1113 #define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
1115 #define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D2_NEXT_DESC_PTR, val)
1117 #define bfin_write_MDMA_D2_START_ADDR(val) bfin_writePTR(MDMA_D2_START_ADDR, val)
1119 #define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val)
1121 #define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val)
1123 #define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val)
1125 #define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val)
1127 #define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val)
1129 #define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D2_CURR_DESC_PTR, val)
1131 #define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_writePTR(MDMA_D2_CURR_ADDR, val)
1133 #define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val)
1135 #define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP, val)
1137 #define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT, val)
1139 #define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val)
1141 #define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S2_NEXT_DESC_PTR, val)
1143 #define bfin_write_MDMA_S2_START_ADDR(val) bfin_writePTR(MDMA_S2_START_ADDR, val)
1145 #define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val)
1147 #define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val)
1149 #define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val)
1151 #define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val)
1153 #define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val)
1155 #define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S2_CURR_DESC_PTR, val)
1157 #define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_writePTR(MDMA_S2_CURR_ADDR, val)
1159 #define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val)
1161 #define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP, val)
1163 #define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT, val)
1165 #define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT, val)
1167 #define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D3_NEXT_DESC_PTR, val)
1169 #define bfin_write_MDMA_D3_START_ADDR(val) bfin_writePTR(MDMA_D3_START_ADDR, val)
1171 #define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val)
1173 #define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val)
1175 #define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val)
1177 #define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val)
1179 #define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val)
1181 #define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D3_CURR_DESC_PTR, val)
1183 #define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_writePTR(MDMA_D3_CURR_ADDR, val)
1185 #define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val)
1187 #define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP, val)
1189 #define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT, val)
1191 #define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val)
1193 #define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S3_NEXT_DESC_PTR, val)
1195 #define bfin_write_MDMA_S3_START_ADDR(val) bfin_writePTR(MDMA_S3_START_ADDR, val)
1197 #define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val)
1199 #define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val)
1201 #define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val)
1203 #define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val)
1205 #define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val)
1207 #define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S3_CURR_DESC_PTR, val)
1209 #define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_writePTR(MDMA_S3_CURR_ADDR, val)
1211 #define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val)
1213 #define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP, val)
1215 #define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT, val)
1217 #define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT, val)
1219 #define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val)
1221 #define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val)
1224 #define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val)
1226 #define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val)
1228 #define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val)
1230 #define bfin_write_CAN_MC1(val) bfin_write16(CAN_MC1, val)
1232 #define bfin_write_CAN_MD1(val) bfin_write16(CAN_MD1, val)
1234 #define bfin_write_CAN_TRS1(val) bfin_write16(CAN_TRS1, val)
1236 #define bfin_write_CAN_TRR1(val) bfin_write16(CAN_TRR1, val)
1238 #define bfin_write_CAN_TA1(val) bfin_write16(CAN_TA1, val)
1240 #define bfin_write_CAN_AA1(val) bfin_write16(CAN_AA1, val)
1242 #define bfin_write_CAN_RMP1(val) bfin_write16(CAN_RMP1, val)
1244 #define bfin_write_CAN_RML1(val) bfin_write16(CAN_RML1, val)
1246 #define bfin_write_CAN_MBTIF1(val) bfin_write16(CAN_MBTIF1, val)
1248 #define bfin_write_CAN_MBRIF1(val) bfin_write16(CAN_MBRIF1, val)
1250 #define bfin_write_CAN_MBIM1(val) bfin_write16(CAN_MBIM1, val)
1252 #define bfin_write_CAN_RFH1(val) bfin_write16(CAN_RFH1, val)
1254 #define bfin_write_CAN_OPSS1(val) bfin_write16(CAN_OPSS1, val)
1256 #define bfin_write_CAN_MC2(val) bfin_write16(CAN_MC2, val)
1258 #define bfin_write_CAN_MD2(val) bfin_write16(CAN_MD2, val)
1260 #define bfin_write_CAN_TRS2(val) bfin_write16(CAN_TRS2, val)
1262 #define bfin_write_CAN_TRR2(val) bfin_write16(CAN_TRR2, val)
1264 #define bfin_write_CAN_TA2(val) bfin_write16(CAN_TA2, val)
1266 #define bfin_write_CAN_AA2(val) bfin_write16(CAN_AA2, val)
1268 #define bfin_write_CAN_RMP2(val) bfin_write16(CAN_RMP2, val)
1270 #define bfin_write_CAN_RML2(val) bfin_write16(CAN_RML2, val)
1272 #define bfin_write_CAN_MBTIF2(val) bfin_write16(CAN_MBTIF2, val)
1274 #define bfin_write_CAN_MBRIF2(val) bfin_write16(CAN_MBRIF2, val)
1276 #define bfin_write_CAN_MBIM2(val) bfin_write16(CAN_MBIM2, val)
1278 #define bfin_write_CAN_RFH2(val) bfin_write16(CAN_RFH2, val)
1280 #define bfin_write_CAN_OPSS2(val) bfin_write16(CAN_OPSS2, val)
1282 #define bfin_write_CAN_CLOCK(val) bfin_write16(CAN_CLOCK, val)
1284 #define bfin_write_CAN_TIMING(val) bfin_write16(CAN_TIMING, val)
1286 #define bfin_write_CAN_DEBUG(val) bfin_write16(CAN_DEBUG, val)
1288 #define bfin_write_CAN_STATUS(val) bfin_write16(CAN_STATUS, val)
1290 #define bfin_write_CAN_CEC(val) bfin_write16(CAN_CEC, val)
1292 #define bfin_write_CAN_GIS(val) bfin_write16(CAN_GIS, val)
1294 #define bfin_write_CAN_GIM(val) bfin_write16(CAN_GIM, val)
1296 #define bfin_write_CAN_GIF(val) bfin_write16(CAN_GIF, val)
1298 #define bfin_write_CAN_CONTROL(val) bfin_write16(CAN_CONTROL, val)
1300 #define bfin_write_CAN_INTR(val) bfin_write16(CAN_INTR, val)
1302 #define bfin_write_CAN_VERSION(val) bfin_write16(CAN_VERSION, val)
1304 #define bfin_write_CAN_MBTD(val) bfin_write16(CAN_MBTD, val)
1306 #define bfin_write_CAN_EWR(val) bfin_write16(CAN_EWR, val)
1308 #define bfin_write_CAN_ESR(val) bfin_write16(CAN_ESR, val)
1310 #define bfin_write_CAN_UCREG(val) bfin_write16(CAN_UCREG, val)
1312 #define bfin_write_CAN_UCCNT(val) bfin_write16(CAN_UCCNT, val)
1314 #define bfin_write_CAN_UCRC(val) bfin_write16(CAN_UCRC, val)
1316 #define bfin_write_CAN_UCCNF(val) bfin_write16(CAN_UCCNF, val)
1318 #define bfin_write_CAN_VERSION2(val) bfin_write16(CAN_VERSION2, val)
1320 #define bfin_write_CAN_AM00L(val) bfin_write16(CAN_AM00L, val)
1322 #define bfin_write_CAN_AM00H(val) bfin_write16(CAN_AM00H, val)
1324 #define bfin_write_CAN_AM01L(val) bfin_write16(CAN_AM01L, val)
1326 #define bfin_write_CAN_AM01H(val) bfin_write16(CAN_AM01H, val)
1328 #define bfin_write_CAN_AM02L(val) bfin_write16(CAN_AM02L, val)
1330 #define bfin_write_CAN_AM02H(val) bfin_write16(CAN_AM02H, val)
1332 #define bfin_write_CAN_AM03L(val) bfin_write16(CAN_AM03L, val)
1334 #define bfin_write_CAN_AM03H(val) bfin_write16(CAN_AM03H, val)
1336 #define bfin_write_CAN_AM04L(val) bfin_write16(CAN_AM04L, val)
1338 #define bfin_write_CAN_AM04H(val) bfin_write16(CAN_AM04H, val)
1340 #define bfin_write_CAN_AM05L(val) bfin_write16(CAN_AM05L, val)
1342 #define bfin_write_CAN_AM05H(val) bfin_write16(CAN_AM05H, val)
1344 #define bfin_write_CAN_AM06L(val) bfin_write16(CAN_AM06L, val)
1346 #define bfin_write_CAN_AM06H(val) bfin_write16(CAN_AM06H, val)
1348 #define bfin_write_CAN_AM07L(val) bfin_write16(CAN_AM07L, val)
1350 #define bfin_write_CAN_AM07H(val) bfin_write16(CAN_AM07H, val)
1352 #define bfin_write_CAN_AM08L(val) bfin_write16(CAN_AM08L, val)
1354 #define bfin_write_CAN_AM08H(val) bfin_write16(CAN_AM08H, val)
1356 #define bfin_write_CAN_AM09L(val) bfin_write16(CAN_AM09L, val)
1358 #define bfin_write_CAN_AM09H(val) bfin_write16(CAN_AM09H, val)
1360 #define bfin_write_CAN_AM10L(val) bfin_write16(CAN_AM10L, val)
1362 #define bfin_write_CAN_AM10H(val) bfin_write16(CAN_AM10H, val)
1364 #define bfin_write_CAN_AM11L(val) bfin_write16(CAN_AM11L, val)
1366 #define bfin_write_CAN_AM11H(val) bfin_write16(CAN_AM11H, val)
1368 #define bfin_write_CAN_AM12L(val) bfin_write16(CAN_AM12L, val)
1370 #define bfin_write_CAN_AM12H(val) bfin_write16(CAN_AM12H, val)
1372 #define bfin_write_CAN_AM13L(val) bfin_write16(CAN_AM13L, val)
1374 #define bfin_write_CAN_AM13H(val) bfin_write16(CAN_AM13H, val)
1376 #define bfin_write_CAN_AM14L(val) bfin_write16(CAN_AM14L, val)
1378 #define bfin_write_CAN_AM14H(val) bfin_write16(CAN_AM14H, val)
1380 #define bfin_write_CAN_AM15L(val) bfin_write16(CAN_AM15L, val)
1382 #define bfin_write_CAN_AM15H(val) bfin_write16(CAN_AM15H, val)
1384 #define bfin_write_CAN_AM16L(val) bfin_write16(CAN_AM16L, val)
1386 #define bfin_write_CAN_AM16H(val) bfin_write16(CAN_AM16H, val)
1388 #define bfin_write_CAN_AM17L(val) bfin_write16(CAN_AM17L, val)
1390 #define bfin_write_CAN_AM17H(val) bfin_write16(CAN_AM17H, val)
1392 #define bfin_write_CAN_AM18L(val) bfin_write16(CAN_AM18L, val)
1394 #define bfin_write_CAN_AM18H(val) bfin_write16(CAN_AM18H, val)
1396 #define bfin_write_CAN_AM19L(val) bfin_write16(CAN_AM19L, val)
1398 #define bfin_write_CAN_AM19H(val) bfin_write16(CAN_AM19H, val)
1400 #define bfin_write_CAN_AM20L(val) bfin_write16(CAN_AM20L, val)
1402 #define bfin_write_CAN_AM20H(val) bfin_write16(CAN_AM20H, val)
1404 #define bfin_write_CAN_AM21L(val) bfin_write16(CAN_AM21L, val)
1406 #define bfin_write_CAN_AM21H(val) bfin_write16(CAN_AM21H, val)
1408 #define bfin_write_CAN_AM22L(val) bfin_write16(CAN_AM22L, val)
1410 #define bfin_write_CAN_AM22H(val) bfin_write16(CAN_AM22H, val)
1412 #define bfin_write_CAN_AM23L(val) bfin_write16(CAN_AM23L, val)
1414 #define bfin_write_CAN_AM23H(val) bfin_write16(CAN_AM23H, val)
1416 #define bfin_write_CAN_AM24L(val) bfin_write16(CAN_AM24L, val)
1418 #define bfin_write_CAN_AM24H(val) bfin_write16(CAN_AM24H, val)
1420 #define bfin_write_CAN_AM25L(val) bfin_write16(CAN_AM25L, val)
1422 #define bfin_write_CAN_AM25H(val) bfin_write16(CAN_AM25H, val)
1424 #define bfin_write_CAN_AM26L(val) bfin_write16(CAN_AM26L, val)
1426 #define bfin_write_CAN_AM26H(val) bfin_write16(CAN_AM26H, val)
1428 #define bfin_write_CAN_AM27L(val) bfin_write16(CAN_AM27L, val)
1430 #define bfin_write_CAN_AM27H(val) bfin_write16(CAN_AM27H, val)
1432 #define bfin_write_CAN_AM28L(val) bfin_write16(CAN_AM28L, val)
1434 #define bfin_write_CAN_AM28H(val) bfin_write16(CAN_AM28H, val)
1436 #define bfin_write_CAN_AM29L(val) bfin_write16(CAN_AM29L, val)
1438 #define bfin_write_CAN_AM29H(val) bfin_write16(CAN_AM29H, val)
1440 #define bfin_write_CAN_AM30L(val) bfin_write16(CAN_AM30L, val)
1442 #define bfin_write_CAN_AM30H(val) bfin_write16(CAN_AM30H, val)
1444 #define bfin_write_CAN_AM31L(val) bfin_write16(CAN_AM31L, val)
1446 #define bfin_write_CAN_AM31H(val) bfin_write16(CAN_AM31H, val)
1448 #define bfin_write_CAN_MB00_DATA0(val) bfin_write16(CAN_MB00_DATA0, val)
1450 #define bfin_write_CAN_MB00_DATA1(val) bfin_write16(CAN_MB00_DATA1, val)
1452 #define bfin_write_CAN_MB00_DATA2(val) bfin_write16(CAN_MB00_DATA2, val)
1454 #define bfin_write_CAN_MB00_DATA3(val) bfin_write16(CAN_MB00_DATA3, val)
1456 #define bfin_write_CAN_MB00_LENGTH(val) bfin_write16(CAN_MB00_LENGTH, val)
1458 #define bfin_write_CAN_MB00_TIMESTAMP(val) bfin_write16(CAN_MB00_TIMESTAMP, val)
1460 #define bfin_write_CAN_MB00_ID0(val) bfin_write16(CAN_MB00_ID0, val)
1462 #define bfin_write_CAN_MB00_ID1(val) bfin_write16(CAN_MB00_ID1, val)
1464 #define bfin_write_CAN_MB01_DATA0(val) bfin_write16(CAN_MB01_DATA0, val)
1466 #define bfin_write_CAN_MB01_DATA1(val) bfin_write16(CAN_MB01_DATA1, val)
1468 #define bfin_write_CAN_MB01_DATA2(val) bfin_write16(CAN_MB01_DATA2, val)
1470 #define bfin_write_CAN_MB01_DATA3(val) bfin_write16(CAN_MB01_DATA3, val)
1472 #define bfin_write_CAN_MB01_LENGTH(val) bfin_write16(CAN_MB01_LENGTH, val)
1474 #define bfin_write_CAN_MB01_TIMESTAMP(val) bfin_write16(CAN_MB01_TIMESTAMP, val)
1476 #define bfin_write_CAN_MB01_ID0(val) bfin_write16(CAN_MB01_ID0, val)
1478 #define bfin_write_CAN_MB01_ID1(val) bfin_write16(CAN_MB01_ID1, val)
1480 #define bfin_write_CAN_MB02_DATA0(val) bfin_write16(CAN_MB02_DATA0, val)
1482 #define bfin_write_CAN_MB02_DATA1(val) bfin_write16(CAN_MB02_DATA1, val)
1484 #define bfin_write_CAN_MB02_DATA2(val) bfin_write16(CAN_MB02_DATA2, val)
1486 #define bfin_write_CAN_MB02_DATA3(val) bfin_write16(CAN_MB02_DATA3, val)
1488 #define bfin_write_CAN_MB02_LENGTH(val) bfin_write16(CAN_MB02_LENGTH, val)
1490 #define bfin_write_CAN_MB02_TIMESTAMP(val) bfin_write16(CAN_MB02_TIMESTAMP, val)
1492 #define bfin_write_CAN_MB02_ID0(val) bfin_write16(CAN_MB02_ID0, val)
1494 #define bfin_write_CAN_MB02_ID1(val) bfin_write16(CAN_MB02_ID1, val)
1496 #define bfin_write_CAN_MB03_DATA0(val) bfin_write16(CAN_MB03_DATA0, val)
1498 #define bfin_write_CAN_MB03_DATA1(val) bfin_write16(CAN_MB03_DATA1, val)
1500 #define bfin_write_CAN_MB03_DATA2(val) bfin_write16(CAN_MB03_DATA2, val)
1502 #define bfin_write_CAN_MB03_DATA3(val) bfin_write16(CAN_MB03_DATA3, val)
1504 #define bfin_write_CAN_MB03_LENGTH(val) bfin_write16(CAN_MB03_LENGTH, val)
1506 #define bfin_write_CAN_MB03_TIMESTAMP(val) bfin_write16(CAN_MB03_TIMESTAMP, val)
1508 #define bfin_write_CAN_MB03_ID0(val) bfin_write16(CAN_MB03_ID0, val)
1510 #define bfin_write_CAN_MB03_ID1(val) bfin_write16(CAN_MB03_ID1, val)
1512 #define bfin_write_CAN_MB04_DATA0(val) bfin_write16(CAN_MB04_DATA0, val)
1514 #define bfin_write_CAN_MB04_DATA1(val) bfin_write16(CAN_MB04_DATA1, val)
1516 #define bfin_write_CAN_MB04_DATA2(val) bfin_write16(CAN_MB04_DATA2, val)
1518 #define bfin_write_CAN_MB04_DATA3(val) bfin_write16(CAN_MB04_DATA3, val)
1520 #define bfin_write_CAN_MB04_LENGTH(val) bfin_write16(CAN_MB04_LENGTH, val)
1522 #define bfin_write_CAN_MB04_TIMESTAMP(val) bfin_write16(CAN_MB04_TIMESTAMP, val)
1524 #define bfin_write_CAN_MB04_ID0(val) bfin_write16(CAN_MB04_ID0, val)
1526 #define bfin_write_CAN_MB04_ID1(val) bfin_write16(CAN_MB04_ID1, val)
1528 #define bfin_write_CAN_MB05_DATA0(val) bfin_write16(CAN_MB05_DATA0, val)
1530 #define bfin_write_CAN_MB05_DATA1(val) bfin_write16(CAN_MB05_DATA1, val)
1532 #define bfin_write_CAN_MB05_DATA2(val) bfin_write16(CAN_MB05_DATA2, val)
1534 #define bfin_write_CAN_MB05_DATA3(val) bfin_write16(CAN_MB05_DATA3, val)
1536 #define bfin_write_CAN_MB05_LENGTH(val) bfin_write16(CAN_MB05_LENGTH, val)
1538 #define bfin_write_CAN_MB05_TIMESTAMP(val) bfin_write16(CAN_MB05_TIMESTAMP, val)
1540 #define bfin_write_CAN_MB05_ID0(val) bfin_write16(CAN_MB05_ID0, val)
1542 #define bfin_write_CAN_MB05_ID1(val) bfin_write16(CAN_MB05_ID1, val)
1544 #define bfin_write_CAN_MB06_DATA0(val) bfin_write16(CAN_MB06_DATA0, val)
1546 #define bfin_write_CAN_MB06_DATA1(val) bfin_write16(CAN_MB06_DATA1, val)
1548 #define bfin_write_CAN_MB06_DATA2(val) bfin_write16(CAN_MB06_DATA2, val)
1550 #define bfin_write_CAN_MB06_DATA3(val) bfin_write16(CAN_MB06_DATA3, val)
1552 #define bfin_write_CAN_MB06_LENGTH(val) bfin_write16(CAN_MB06_LENGTH, val)
1554 #define bfin_write_CAN_MB06_TIMESTAMP(val) bfin_write16(CAN_MB06_TIMESTAMP, val)
1556 #define bfin_write_CAN_MB06_ID0(val) bfin_write16(CAN_MB06_ID0, val)
1558 #define bfin_write_CAN_MB06_ID1(val) bfin_write16(CAN_MB06_ID1, val)
1560 #define bfin_write_CAN_MB07_DATA0(val) bfin_write16(CAN_MB07_DATA0, val)
1562 #define bfin_write_CAN_MB07_DATA1(val) bfin_write16(CAN_MB07_DATA1, val)
1564 #define bfin_write_CAN_MB07_DATA2(val) bfin_write16(CAN_MB07_DATA2, val)
1566 #define bfin_write_CAN_MB07_DATA3(val) bfin_write16(CAN_MB07_DATA3, val)
1568 #define bfin_write_CAN_MB07_LENGTH(val) bfin_write16(CAN_MB07_LENGTH, val)
1570 #define bfin_write_CAN_MB07_TIMESTAMP(val) bfin_write16(CAN_MB07_TIMESTAMP, val)
1572 #define bfin_write_CAN_MB07_ID0(val) bfin_write16(CAN_MB07_ID0, val)
1574 #define bfin_write_CAN_MB07_ID1(val) bfin_write16(CAN_MB07_ID1, val)
1576 #define bfin_write_CAN_MB08_DATA0(val) bfin_write16(CAN_MB08_DATA0, val)
1578 #define bfin_write_CAN_MB08_DATA1(val) bfin_write16(CAN_MB08_DATA1, val)
1580 #define bfin_write_CAN_MB08_DATA2(val) bfin_write16(CAN_MB08_DATA2, val)
1582 #define bfin_write_CAN_MB08_DATA3(val) bfin_write16(CAN_MB08_DATA3, val)
1584 #define bfin_write_CAN_MB08_LENGTH(val) bfin_write16(CAN_MB08_LENGTH, val)
1586 #define bfin_write_CAN_MB08_TIMESTAMP(val) bfin_write16(CAN_MB08_TIMESTAMP, val)
1588 #define bfin_write_CAN_MB08_ID0(val) bfin_write16(CAN_MB08_ID0, val)
1590 #define bfin_write_CAN_MB08_ID1(val) bfin_write16(CAN_MB08_ID1, val)
1592 #define bfin_write_CAN_MB09_DATA0(val) bfin_write16(CAN_MB09_DATA0, val)
1594 #define bfin_write_CAN_MB09_DATA1(val) bfin_write16(CAN_MB09_DATA1, val)
1596 #define bfin_write_CAN_MB09_DATA2(val) bfin_write16(CAN_MB09_DATA2, val)
1598 #define bfin_write_CAN_MB09_DATA3(val) bfin_write16(CAN_MB09_DATA3, val)
1600 #define bfin_write_CAN_MB09_LENGTH(val) bfin_write16(CAN_MB09_LENGTH, val)
1602 #define bfin_write_CAN_MB09_TIMESTAMP(val) bfin_write16(CAN_MB09_TIMESTAMP, val)
1604 #define bfin_write_CAN_MB09_ID0(val) bfin_write16(CAN_MB09_ID0, val)
1606 #define bfin_write_CAN_MB09_ID1(val) bfin_write16(CAN_MB09_ID1, val)
1608 #define bfin_write_CAN_MB10_DATA0(val) bfin_write16(CAN_MB10_DATA0, val)
1610 #define bfin_write_CAN_MB10_DATA1(val) bfin_write16(CAN_MB10_DATA1, val)
1612 #define bfin_write_CAN_MB10_DATA2(val) bfin_write16(CAN_MB10_DATA2, val)
1614 #define bfin_write_CAN_MB10_DATA3(val) bfin_write16(CAN_MB10_DATA3, val)
1616 #define bfin_write_CAN_MB10_LENGTH(val) bfin_write16(CAN_MB10_LENGTH, val)
1618 #define bfin_write_CAN_MB10_TIMESTAMP(val) bfin_write16(CAN_MB10_TIMESTAMP, val)
1620 #define bfin_write_CAN_MB10_ID0(val) bfin_write16(CAN_MB10_ID0, val)
1622 #define bfin_write_CAN_MB10_ID1(val) bfin_write16(CAN_MB10_ID1, val)
1624 #define bfin_write_CAN_MB11_DATA0(val) bfin_write16(CAN_MB11_DATA0, val)
1626 #define bfin_write_CAN_MB11_DATA1(val) bfin_write16(CAN_MB11_DATA1, val)
1628 #define bfin_write_CAN_MB11_DATA2(val) bfin_write16(CAN_MB11_DATA2, val)
1630 #define bfin_write_CAN_MB11_DATA3(val) bfin_write16(CAN_MB11_DATA3, val)
1632 #define bfin_write_CAN_MB11_LENGTH(val) bfin_write16(CAN_MB11_LENGTH, val)
1634 #define bfin_write_CAN_MB11_TIMESTAMP(val) bfin_write16(CAN_MB11_TIMESTAMP, val)
1636 #define bfin_write_CAN_MB11_ID0(val) bfin_write16(CAN_MB11_ID0, val)
1638 #define bfin_write_CAN_MB11_ID1(val) bfin_write16(CAN_MB11_ID1, val)
1640 #define bfin_write_CAN_MB12_DATA0(val) bfin_write16(CAN_MB12_DATA0, val)
1642 #define bfin_write_CAN_MB12_DATA1(val) bfin_write16(CAN_MB12_DATA1, val)
1644 #define bfin_write_CAN_MB12_DATA2(val) bfin_write16(CAN_MB12_DATA2, val)
1646 #define bfin_write_CAN_MB12_DATA3(val) bfin_write16(CAN_MB12_DATA3, val)
1648 #define bfin_write_CAN_MB12_LENGTH(val) bfin_write16(CAN_MB12_LENGTH, val)
1650 #define bfin_write_CAN_MB12_TIMESTAMP(val) bfin_write16(CAN_MB12_TIMESTAMP, val)
1652 #define bfin_write_CAN_MB12_ID0(val) bfin_write16(CAN_MB12_ID0, val)
1654 #define bfin_write_CAN_MB12_ID1(val) bfin_write16(CAN_MB12_ID1, val)
1656 #define bfin_write_CAN_MB13_DATA0(val) bfin_write16(CAN_MB13_DATA0, val)
1658 #define bfin_write_CAN_MB13_DATA1(val) bfin_write16(CAN_MB13_DATA1, val)
1660 #define bfin_write_CAN_MB13_DATA2(val) bfin_write16(CAN_MB13_DATA2, val)
1662 #define bfin_write_CAN_MB13_DATA3(val) bfin_write16(CAN_MB13_DATA3, val)
1664 #define bfin_write_CAN_MB13_LENGTH(val) bfin_write16(CAN_MB13_LENGTH, val)
1666 #define bfin_write_CAN_MB13_TIMESTAMP(val) bfin_write16(CAN_MB13_TIMESTAMP, val)
1668 #define bfin_write_CAN_MB13_ID0(val) bfin_write16(CAN_MB13_ID0, val)
1670 #define bfin_write_CAN_MB13_ID1(val) bfin_write16(CAN_MB13_ID1, val)
1672 #define bfin_write_CAN_MB14_DATA0(val) bfin_write16(CAN_MB14_DATA0, val)
1674 #define bfin_write_CAN_MB14_DATA1(val) bfin_write16(CAN_MB14_DATA1, val)
1676 #define bfin_write_CAN_MB14_DATA2(val) bfin_write16(CAN_MB14_DATA2, val)
1678 #define bfin_write_CAN_MB14_DATA3(val) bfin_write16(CAN_MB14_DATA3, val)
1680 #define bfin_write_CAN_MB14_LENGTH(val) bfin_write16(CAN_MB14_LENGTH, val)
1682 #define bfin_write_CAN_MB14_TIMESTAMP(val) bfin_write16(CAN_MB14_TIMESTAMP, val)
1684 #define bfin_write_CAN_MB14_ID0(val) bfin_write16(CAN_MB14_ID0, val)
1686 #define bfin_write_CAN_MB14_ID1(val) bfin_write16(CAN_MB14_ID1, val)
1688 #define bfin_write_CAN_MB15_DATA0(val) bfin_write16(CAN_MB15_DATA0, val)
1690 #define bfin_write_CAN_MB15_DATA1(val) bfin_write16(CAN_MB15_DATA1, val)
1692 #define bfin_write_CAN_MB15_DATA2(val) bfin_write16(CAN_MB15_DATA2, val)
1694 #define bfin_write_CAN_MB15_DATA3(val) bfin_write16(CAN_MB15_DATA3, val)
1696 #define bfin_write_CAN_MB15_LENGTH(val) bfin_write16(CAN_MB15_LENGTH, val)
1698 #define bfin_write_CAN_MB15_TIMESTAMP(val) bfin_write16(CAN_MB15_TIMESTAMP, val)
1700 #define bfin_write_CAN_MB15_ID0(val) bfin_write16(CAN_MB15_ID0, val)
1702 #define bfin_write_CAN_MB15_ID1(val) bfin_write16(CAN_MB15_ID1, val)
1704 #define bfin_write_CAN_MB16_DATA0(val) bfin_write16(CAN_MB16_DATA0, val)
1706 #define bfin_write_CAN_MB16_DATA1(val) bfin_write16(CAN_MB16_DATA1, val)
1708 #define bfin_write_CAN_MB16_DATA2(val) bfin_write16(CAN_MB16_DATA2, val)
1710 #define bfin_write_CAN_MB16_DATA3(val) bfin_write16(CAN_MB16_DATA3, val)
1712 #define bfin_write_CAN_MB16_LENGTH(val) bfin_write16(CAN_MB16_LENGTH, val)
1714 #define bfin_write_CAN_MB16_TIMESTAMP(val) bfin_write16(CAN_MB16_TIMESTAMP, val)
1716 #define bfin_write_CAN_MB16_ID0(val) bfin_write16(CAN_MB16_ID0, val)
1718 #define bfin_write_CAN_MB16_ID1(val) bfin_write16(CAN_MB16_ID1, val)
1720 #define bfin_write_CAN_MB17_DATA0(val) bfin_write16(CAN_MB17_DATA0, val)
1722 #define bfin_write_CAN_MB17_DATA1(val) bfin_write16(CAN_MB17_DATA1, val)
1724 #define bfin_write_CAN_MB17_DATA2(val) bfin_write16(CAN_MB17_DATA2, val)
1726 #define bfin_write_CAN_MB17_DATA3(val) bfin_write16(CAN_MB17_DATA3, val)
1728 #define bfin_write_CAN_MB17_LENGTH(val) bfin_write16(CAN_MB17_LENGTH, val)
1730 #define bfin_write_CAN_MB17_TIMESTAMP(val) bfin_write16(CAN_MB17_TIMESTAMP, val)
1732 #define bfin_write_CAN_MB17_ID0(val) bfin_write16(CAN_MB17_ID0, val)
1734 #define bfin_write_CAN_MB17_ID1(val) bfin_write16(CAN_MB17_ID1, val)
1736 #define bfin_write_CAN_MB18_DATA0(val) bfin_write16(CAN_MB18_DATA0, val)
1738 #define bfin_write_CAN_MB18_DATA1(val) bfin_write16(CAN_MB18_DATA1, val)
1740 #define bfin_write_CAN_MB18_DATA2(val) bfin_write16(CAN_MB18_DATA2, val)
1742 #define bfin_write_CAN_MB18_DATA3(val) bfin_write16(CAN_MB18_DATA3, val)
1744 #define bfin_write_CAN_MB18_LENGTH(val) bfin_write16(CAN_MB18_LENGTH, val)
1746 #define bfin_write_CAN_MB18_TIMESTAMP(val) bfin_write16(CAN_MB18_TIMESTAMP, val)
1748 #define bfin_write_CAN_MB18_ID0(val) bfin_write16(CAN_MB18_ID0, val)
1750 #define bfin_write_CAN_MB18_ID1(val) bfin_write16(CAN_MB18_ID1, val)
1752 #define bfin_write_CAN_MB19_DATA0(val) bfin_write16(CAN_MB19_DATA0, val)
1754 #define bfin_write_CAN_MB19_DATA1(val) bfin_write16(CAN_MB19_DATA1, val)
1756 #define bfin_write_CAN_MB19_DATA2(val) bfin_write16(CAN_MB19_DATA2, val)
1758 #define bfin_write_CAN_MB19_DATA3(val) bfin_write16(CAN_MB19_DATA3, val)
1760 #define bfin_write_CAN_MB19_LENGTH(val) bfin_write16(CAN_MB19_LENGTH, val)
1762 #define bfin_write_CAN_MB19_TIMESTAMP(val) bfin_write16(CAN_MB19_TIMESTAMP, val)
1764 #define bfin_write_CAN_MB19_ID0(val) bfin_write16(CAN_MB19_ID0, val)
1766 #define bfin_write_CAN_MB19_ID1(val) bfin_write16(CAN_MB19_ID1, val)
1768 #define bfin_write_CAN_MB20_DATA0(val) bfin_write16(CAN_MB20_DATA0, val)
1770 #define bfin_write_CAN_MB20_DATA1(val) bfin_write16(CAN_MB20_DATA1, val)
1772 #define bfin_write_CAN_MB20_DATA2(val) bfin_write16(CAN_MB20_DATA2, val)
1774 #define bfin_write_CAN_MB20_DATA3(val) bfin_write16(CAN_MB20_DATA3, val)
1776 #define bfin_write_CAN_MB20_LENGTH(val) bfin_write16(CAN_MB20_LENGTH, val)
1778 #define bfin_write_CAN_MB20_TIMESTAMP(val) bfin_write16(CAN_MB20_TIMESTAMP, val)
1780 #define bfin_write_CAN_MB20_ID0(val) bfin_write16(CAN_MB20_ID0, val)
1782 #define bfin_write_CAN_MB20_ID1(val) bfin_write16(CAN_MB20_ID1, val)
1784 #define bfin_write_CAN_MB21_DATA0(val) bfin_write16(CAN_MB21_DATA0, val)
1786 #define bfin_write_CAN_MB21_DATA1(val) bfin_write16(CAN_MB21_DATA1, val)
1788 #define bfin_write_CAN_MB21_DATA2(val) bfin_write16(CAN_MB21_DATA2, val)
1790 #define bfin_write_CAN_MB21_DATA3(val) bfin_write16(CAN_MB21_DATA3, val)
1792 #define bfin_write_CAN_MB21_LENGTH(val) bfin_write16(CAN_MB21_LENGTH, val)
1794 #define bfin_write_CAN_MB21_TIMESTAMP(val) bfin_write16(CAN_MB21_TIMESTAMP, val)
1796 #define bfin_write_CAN_MB21_ID0(val) bfin_write16(CAN_MB21_ID0, val)
1798 #define bfin_write_CAN_MB21_ID1(val) bfin_write16(CAN_MB21_ID1, val)
1800 #define bfin_write_CAN_MB22_DATA0(val) bfin_write16(CAN_MB22_DATA0, val)
1802 #define bfin_write_CAN_MB22_DATA1(val) bfin_write16(CAN_MB22_DATA1, val)
1804 #define bfin_write_CAN_MB22_DATA2(val) bfin_write16(CAN_MB22_DATA2, val)
1806 #define bfin_write_CAN_MB22_DATA3(val) bfin_write16(CAN_MB22_DATA3, val)
1808 #define bfin_write_CAN_MB22_LENGTH(val) bfin_write16(CAN_MB22_LENGTH, val)
1810 #define bfin_write_CAN_MB22_TIMESTAMP(val) bfin_write16(CAN_MB22_TIMESTAMP, val)
1812 #define bfin_write_CAN_MB22_ID0(val) bfin_write16(CAN_MB22_ID0, val)
1814 #define bfin_write_CAN_MB22_ID1(val) bfin_write16(CAN_MB22_ID1, val)
1816 #define bfin_write_CAN_MB23_DATA0(val) bfin_write16(CAN_MB23_DATA0, val)
1818 #define bfin_write_CAN_MB23_DATA1(val) bfin_write16(CAN_MB23_DATA1, val)
1820 #define bfin_write_CAN_MB23_DATA2(val) bfin_write16(CAN_MB23_DATA2, val)
1822 #define bfin_write_CAN_MB23_DATA3(val) bfin_write16(CAN_MB23_DATA3, val)
1824 #define bfin_write_CAN_MB23_LENGTH(val) bfin_write16(CAN_MB23_LENGTH, val)
1826 #define bfin_write_CAN_MB23_TIMESTAMP(val) bfin_write16(CAN_MB23_TIMESTAMP, val)
1828 #define bfin_write_CAN_MB23_ID0(val) bfin_write16(CAN_MB23_ID0, val)
1830 #define bfin_write_CAN_MB23_ID1(val) bfin_write16(CAN_MB23_ID1, val)
1832 #define bfin_write_CAN_MB24_DATA0(val) bfin_write16(CAN_MB24_DATA0, val)
1834 #define bfin_write_CAN_MB24_DATA1(val) bfin_write16(CAN_MB24_DATA1, val)
1836 #define bfin_write_CAN_MB24_DATA2(val) bfin_write16(CAN_MB24_DATA2, val)
1838 #define bfin_write_CAN_MB24_DATA3(val) bfin_write16(CAN_MB24_DATA3, val)
1840 #define bfin_write_CAN_MB24_LENGTH(val) bfin_write16(CAN_MB24_LENGTH, val)
1842 #define bfin_write_CAN_MB24_TIMESTAMP(val) bfin_write16(CAN_MB24_TIMESTAMP, val)
1844 #define bfin_write_CAN_MB24_ID0(val) bfin_write16(CAN_MB24_ID0, val)
1846 #define bfin_write_CAN_MB24_ID1(val) bfin_write16(CAN_MB24_ID1, val)
1848 #define bfin_write_CAN_MB25_DATA0(val) bfin_write16(CAN_MB25_DATA0, val)
1850 #define bfin_write_CAN_MB25_DATA1(val) bfin_write16(CAN_MB25_DATA1, val)
1852 #define bfin_write_CAN_MB25_DATA2(val) bfin_write16(CAN_MB25_DATA2, val)
1854 #define bfin_write_CAN_MB25_DATA3(val) bfin_write16(CAN_MB25_DATA3, val)
1856 #define bfin_write_CAN_MB25_LENGTH(val) bfin_write16(CAN_MB25_LENGTH, val)
1858 #define bfin_write_CAN_MB25_TIMESTAMP(val) bfin_write16(CAN_MB25_TIMESTAMP, val)
1860 #define bfin_write_CAN_MB25_ID0(val) bfin_write16(CAN_MB25_ID0, val)
1862 #define bfin_write_CAN_MB25_ID1(val) bfin_write16(CAN_MB25_ID1, val)
1864 #define bfin_write_CAN_MB26_DATA0(val) bfin_write16(CAN_MB26_DATA0, val)
1866 #define bfin_write_CAN_MB26_DATA1(val) bfin_write16(CAN_MB26_DATA1, val)
1868 #define bfin_write_CAN_MB26_DATA2(val) bfin_write16(CAN_MB26_DATA2, val)
1870 #define bfin_write_CAN_MB26_DATA3(val) bfin_write16(CAN_MB26_DATA3, val)
1872 #define bfin_write_CAN_MB26_LENGTH(val) bfin_write16(CAN_MB26_LENGTH, val)
1874 #define bfin_write_CAN_MB26_TIMESTAMP(val) bfin_write16(CAN_MB26_TIMESTAMP, val)
1876 #define bfin_write_CAN_MB26_ID0(val) bfin_write16(CAN_MB26_ID0, val)
1878 #define bfin_write_CAN_MB26_ID1(val) bfin_write16(CAN_MB26_ID1, val)
1880 #define bfin_write_CAN_MB27_DATA0(val) bfin_write16(CAN_MB27_DATA0, val)
1882 #define bfin_write_CAN_MB27_DATA1(val) bfin_write16(CAN_MB27_DATA1, val)
1884 #define bfin_write_CAN_MB27_DATA2(val) bfin_write16(CAN_MB27_DATA2, val)
1886 #define bfin_write_CAN_MB27_DATA3(val) bfin_write16(CAN_MB27_DATA3, val)
1888 #define bfin_write_CAN_MB27_LENGTH(val) bfin_write16(CAN_MB27_LENGTH, val)
1890 #define bfin_write_CAN_MB27_TIMESTAMP(val) bfin_write16(CAN_MB27_TIMESTAMP, val)
1892 #define bfin_write_CAN_MB27_ID0(val) bfin_write16(CAN_MB27_ID0, val)
1894 #define bfin_write_CAN_MB27_ID1(val) bfin_write16(CAN_MB27_ID1, val)
1896 #define bfin_write_CAN_MB28_DATA0(val) bfin_write16(CAN_MB28_DATA0, val)
1898 #define bfin_write_CAN_MB28_DATA1(val) bfin_write16(CAN_MB28_DATA1, val)
1900 #define bfin_write_CAN_MB28_DATA2(val) bfin_write16(CAN_MB28_DATA2, val)
1902 #define bfin_write_CAN_MB28_DATA3(val) bfin_write16(CAN_MB28_DATA3, val)
1904 #define bfin_write_CAN_MB28_LENGTH(val) bfin_write16(CAN_MB28_LENGTH, val)
1906 #define bfin_write_CAN_MB28_TIMESTAMP(val) bfin_write16(CAN_MB28_TIMESTAMP, val)
1908 #define bfin_write_CAN_MB28_ID0(val) bfin_write16(CAN_MB28_ID0, val)
1910 #define bfin_write_CAN_MB28_ID1(val) bfin_write16(CAN_MB28_ID1, val)
1912 #define bfin_write_CAN_MB29_DATA0(val) bfin_write16(CAN_MB29_DATA0, val)
1914 #define bfin_write_CAN_MB29_DATA1(val) bfin_write16(CAN_MB29_DATA1, val)
1916 #define bfin_write_CAN_MB29_DATA2(val) bfin_write16(CAN_MB29_DATA2, val)
1918 #define bfin_write_CAN_MB29_DATA3(val) bfin_write16(CAN_MB29_DATA3, val)
1920 #define bfin_write_CAN_MB29_LENGTH(val) bfin_write16(CAN_MB29_LENGTH, val)
1922 #define bfin_write_CAN_MB29_TIMESTAMP(val) bfin_write16(CAN_MB29_TIMESTAMP, val)
1924 #define bfin_write_CAN_MB29_ID0(val) bfin_write16(CAN_MB29_ID0, val)
1926 #define bfin_write_CAN_MB29_ID1(val) bfin_write16(CAN_MB29_ID1, val)
1928 #define bfin_write_CAN_MB30_DATA0(val) bfin_write16(CAN_MB30_DATA0, val)
1930 #define bfin_write_CAN_MB30_DATA1(val) bfin_write16(CAN_MB30_DATA1, val)
1932 #define bfin_write_CAN_MB30_DATA2(val) bfin_write16(CAN_MB30_DATA2, val)
1934 #define bfin_write_CAN_MB30_DATA3(val) bfin_write16(CAN_MB30_DATA3, val)
1936 #define bfin_write_CAN_MB30_LENGTH(val) bfin_write16(CAN_MB30_LENGTH, val)
1938 #define bfin_write_CAN_MB30_TIMESTAMP(val) bfin_write16(CAN_MB30_TIMESTAMP, val)
1940 #define bfin_write_CAN_MB30_ID0(val) bfin_write16(CAN_MB30_ID0, val)
1942 #define bfin_write_CAN_MB30_ID1(val) bfin_write16(CAN_MB30_ID1, val)
1944 #define bfin_write_CAN_MB31_DATA0(val) bfin_write16(CAN_MB31_DATA0, val)
1946 #define bfin_write_CAN_MB31_DATA1(val) bfin_write16(CAN_MB31_DATA1, val)
1948 #define bfin_write_CAN_MB31_DATA2(val) bfin_write16(CAN_MB31_DATA2, val)
1950 #define bfin_write_CAN_MB31_DATA3(val) bfin_write16(CAN_MB31_DATA3, val)
1952 #define bfin_write_CAN_MB31_LENGTH(val) bfin_write16(CAN_MB31_LENGTH, val)
1954 #define bfin_write_CAN_MB31_TIMESTAMP(val) bfin_write16(CAN_MB31_TIMESTAMP, val)
1956 #define bfin_write_CAN_MB31_ID0(val) bfin_write16(CAN_MB31_ID0, val)
1958 #define bfin_write_CAN_MB31_ID1(val) bfin_write16(CAN_MB31_ID1, val)
H A DcdefBF539.h14 #define bfin_write_MXVR_CONFIG(val) bfin_write16(MXVR_CONFIG, val)
16 #define bfin_write_MXVR_PLL_CTL_0(val) bfin_write32(MXVR_PLL_CTL_0, val)
18 #define bfin_write_MXVR_STATE_0(val) bfin_write32(MXVR_STATE_0, val)
20 #define bfin_write_MXVR_STATE_1(val) bfin_write32(MXVR_STATE_1, val)
22 #define bfin_write_MXVR_INT_STAT_0(val) bfin_write32(MXVR_INT_STAT_0, val)
24 #define bfin_write_MXVR_INT_STAT_1(val) bfin_write32(MXVR_INT_STAT_1, val)
26 #define bfin_write_MXVR_INT_EN_0(val) bfin_write32(MXVR_INT_EN_0, val)
28 #define bfin_write_MXVR_INT_EN_1(val) bfin_write32(MXVR_INT_EN_1, val)
30 #define bfin_write_MXVR_POSITION(val) bfin_write16(MXVR_POSITION, val)
32 #define bfin_write_MXVR_MAX_POSITION(val) bfin_write16(MXVR_MAX_POSITION, val)
34 #define bfin_write_MXVR_DELAY(val) bfin_write16(MXVR_DELAY, val)
36 #define bfin_write_MXVR_MAX_DELAY(val) bfin_write16(MXVR_MAX_DELAY, val)
38 #define bfin_write_MXVR_LADDR(val) bfin_write32(MXVR_LADDR, val)
40 #define bfin_write_MXVR_GADDR(val) bfin_write16(MXVR_GADDR, val)
42 #define bfin_write_MXVR_AADDR(val) bfin_write32(MXVR_AADDR, val)
44 #define bfin_write_MXVR_ALLOC_0(val) bfin_write32(MXVR_ALLOC_0, val)
46 #define bfin_write_MXVR_ALLOC_1(val) bfin_write32(MXVR_ALLOC_1, val)
48 #define bfin_write_MXVR_ALLOC_2(val) bfin_write32(MXVR_ALLOC_2, val)
50 #define bfin_write_MXVR_ALLOC_3(val) bfin_write32(MXVR_ALLOC_3, val)
52 #define bfin_write_MXVR_ALLOC_4(val) bfin_write32(MXVR_ALLOC_4, val)
54 #define bfin_write_MXVR_ALLOC_5(val) bfin_write32(MXVR_ALLOC_5, val)
56 #define bfin_write_MXVR_ALLOC_6(val) bfin_write32(MXVR_ALLOC_6, val)
58 #define bfin_write_MXVR_ALLOC_7(val) bfin_write32(MXVR_ALLOC_7, val)
60 #define bfin_write_MXVR_ALLOC_8(val) bfin_write32(MXVR_ALLOC_8, val)
62 #define bfin_write_MXVR_ALLOC_9(val) bfin_write32(MXVR_ALLOC_9, val)
64 #define bfin_write_MXVR_ALLOC_10(val) bfin_write32(MXVR_ALLOC_10, val)
66 #define bfin_write_MXVR_ALLOC_11(val) bfin_write32(MXVR_ALLOC_11, val)
68 #define bfin_write_MXVR_ALLOC_12(val) bfin_write32(MXVR_ALLOC_12, val)
70 #define bfin_write_MXVR_ALLOC_13(val) bfin_write32(MXVR_ALLOC_13, val)
72 #define bfin_write_MXVR_ALLOC_14(val) bfin_write32(MXVR_ALLOC_14, val)
74 #define bfin_write_MXVR_SYNC_LCHAN_0(val) bfin_write32(MXVR_SYNC_LCHAN_0, val)
76 #define bfin_write_MXVR_SYNC_LCHAN_1(val) bfin_write32(MXVR_SYNC_LCHAN_1, val)
78 #define bfin_write_MXVR_SYNC_LCHAN_2(val) bfin_write32(MXVR_SYNC_LCHAN_2, val)
80 #define bfin_write_MXVR_SYNC_LCHAN_3(val) bfin_write32(MXVR_SYNC_LCHAN_3, val)
82 #define bfin_write_MXVR_SYNC_LCHAN_4(val) bfin_write32(MXVR_SYNC_LCHAN_4, val)
84 #define bfin_write_MXVR_SYNC_LCHAN_5(val) bfin_write32(MXVR_SYNC_LCHAN_5, val)
86 #define bfin_write_MXVR_SYNC_LCHAN_6(val) bfin_write32(MXVR_SYNC_LCHAN_6, val)
88 #define bfin_write_MXVR_SYNC_LCHAN_7(val) bfin_write32(MXVR_SYNC_LCHAN_7, val)
90 #define bfin_write_MXVR_DMA0_CONFIG(val) bfin_write32(MXVR_DMA0_CONFIG, val)
92 #define bfin_write_MXVR_DMA0_START_ADDR(val) bfin_writePTR(MXVR_DMA0_START_ADDR, val)
94 #define bfin_write_MXVR_DMA0_COUNT(val) bfin_write16(MXVR_DMA0_COUNT, val)
96 #define bfin_write_MXVR_DMA0_CURR_ADDR(val) bfin_writePTR(MXVR_DMA0_CURR_ADDR, val)
98 #define bfin_write_MXVR_DMA0_CURR_COUNT(val) bfin_write16(MXVR_DMA0_CURR_COUNT, val)
100 #define bfin_write_MXVR_DMA1_CONFIG(val) bfin_write32(MXVR_DMA1_CONFIG, val)
102 #define bfin_write_MXVR_DMA1_START_ADDR(val) bfin_writePTR(MXVR_DMA1_START_ADDR, val)
104 #define bfin_write_MXVR_DMA1_COUNT(val) bfin_write16(MXVR_DMA1_COUNT, val)
106 #define bfin_write_MXVR_DMA1_CURR_ADDR(val) bfin_writePTR(MXVR_DMA1_CURR_ADDR, val)
108 #define bfin_write_MXVR_DMA1_CURR_COUNT(val) bfin_write16(MXVR_DMA1_CURR_COUNT, val)
110 #define bfin_write_MXVR_DMA2_CONFIG(val) bfin_write32(MXVR_DMA2_CONFIG, val)
112 #define bfin_write_MXVR_DMA2_START_ADDR(val) bfin_writePTR(MXVR_DMA2_START_ADDR, val)
114 #define bfin_write_MXVR_DMA2_COUNT(val) bfin_write16(MXVR_DMA2_COUNT, val)
116 #define bfin_write_MXVR_DMA2_CURR_ADDR(val) bfin_writePTR(MXVR_DMA2_CURR_ADDR, val)
118 #define bfin_write_MXVR_DMA2_CURR_COUNT(val) bfin_write16(MXVR_DMA2_CURR_COUNT, val)
120 #define bfin_write_MXVR_DMA3_CONFIG(val) bfin_write32(MXVR_DMA3_CONFIG, val)
122 #define bfin_write_MXVR_DMA3_START_ADDR(val) bfin_writePTR(MXVR_DMA3_START_ADDR, val)
124 #define bfin_write_MXVR_DMA3_COUNT(val) bfin_write16(MXVR_DMA3_COUNT, val)
126 #define bfin_write_MXVR_DMA3_CURR_ADDR(val) bfin_writePTR(MXVR_DMA3_CURR_ADDR, val)
128 #define bfin_write_MXVR_DMA3_CURR_COUNT(val) bfin_write16(MXVR_DMA3_CURR_COUNT, val)
130 #define bfin_write_MXVR_DMA4_CONFIG(val) bfin_write32(MXVR_DMA4_CONFIG, val)
132 #define bfin_write_MXVR_DMA4_START_ADDR(val) bfin_writePTR(MXVR_DMA4_START_ADDR, val)
134 #define bfin_write_MXVR_DMA4_COUNT(val) bfin_write16(MXVR_DMA4_COUNT, val)
136 #define bfin_write_MXVR_DMA4_CURR_ADDR(val) bfin_writePTR(MXVR_DMA4_CURR_ADDR, val)
138 #define bfin_write_MXVR_DMA4_CURR_COUNT(val) bfin_write16(MXVR_DMA4_CURR_COUNT, val)
140 #define bfin_write_MXVR_DMA5_CONFIG(val) bfin_write32(MXVR_DMA5_CONFIG, val)
142 #define bfin_write_MXVR_DMA5_START_ADDR(val) bfin_writePTR(MXVR_DMA5_START_ADDR, val)
144 #define bfin_write_MXVR_DMA5_COUNT(val) bfin_write16(MXVR_DMA5_COUNT, val)
146 #define bfin_write_MXVR_DMA5_CURR_ADDR(val) bfin_writePTR(MXVR_DMA5_CURR_ADDR, val)
148 #define bfin_write_MXVR_DMA5_CURR_COUNT(val) bfin_write16(MXVR_DMA5_CURR_COUNT, val)
150 #define bfin_write_MXVR_DMA6_CONFIG(val) bfin_write32(MXVR_DMA6_CONFIG, val)
152 #define bfin_write_MXVR_DMA6_START_ADDR(val) bfin_writePTR(MXVR_DMA6_START_ADDR, val)
154 #define bfin_write_MXVR_DMA6_COUNT(val) bfin_write16(MXVR_DMA6_COUNT, val)
156 #define bfin_write_MXVR_DMA6_CURR_ADDR(val) bfin_writePTR(MXVR_DMA6_CURR_ADDR, val)
158 #define bfin_write_MXVR_DMA6_CURR_COUNT(val) bfin_write16(MXVR_DMA6_CURR_COUNT, val)
160 #define bfin_write_MXVR_DMA7_CONFIG(val) bfin_write32(MXVR_DMA7_CONFIG, val)
162 #define bfin_write_MXVR_DMA7_START_ADDR(val) bfin_writePTR(MXVR_DMA7_START_ADDR, val)
164 #define bfin_write_MXVR_DMA7_COUNT(val) bfin_write16(MXVR_DMA7_COUNT, val)
166 #define bfin_write_MXVR_DMA7_CURR_ADDR(val) bfin_writePTR(MXVR_DMA7_CURR_ADDR, val)
168 #define bfin_write_MXVR_DMA7_CURR_COUNT(val) bfin_write16(MXVR_DMA7_CURR_COUNT, val)
170 #define bfin_write_MXVR_AP_CTL(val) bfin_write16(MXVR_AP_CTL, val)
172 #define bfin_write_MXVR_APRB_START_ADDR(val) bfin_writePTR(MXVR_APRB_START_ADDR, val)
174 #define bfin_write_MXVR_APRB_CURR_ADDR(val) bfin_writePTR(MXVR_APRB_CURR_ADDR, val)
176 #define bfin_write_MXVR_APTB_START_ADDR(val) bfin_writePTR(MXVR_APTB_START_ADDR, val)
178 #define bfin_write_MXVR_APTB_CURR_ADDR(val) bfin_writePTR(MXVR_APTB_CURR_ADDR, val)
180 #define bfin_write_MXVR_CM_CTL(val) bfin_write32(MXVR_CM_CTL, val)
182 #define bfin_write_MXVR_CMRB_START_ADDR(val) bfin_writePTR(MXVR_CMRB_START_ADDR, val)
184 #define bfin_write_MXVR_CMRB_CURR_ADDR(val) bfin_writePTR(MXVR_CMRB_CURR_ADDR, val)
186 #define bfin_write_MXVR_CMTB_START_ADDR(val) bfin_writePTR(MXVR_CMTB_START_ADDR, val)
188 #define bfin_write_MXVR_CMTB_CURR_ADDR(val) bfin_writePTR(MXVR_CMTB_CURR_ADDR, val)
190 #define bfin_write_MXVR_RRDB_START_ADDR(val) bfin_writePTR(MXVR_RRDB_START_ADDR, val)
192 #define bfin_write_MXVR_RRDB_CURR_ADDR(val) bfin_writePTR(MXVR_RRDB_CURR_ADDR, val)
194 #define bfin_write_MXVR_PAT_DATA_0(val) bfin_write32(MXVR_PAT_DATA_0, val)
196 #define bfin_write_MXVR_PAT_EN_0(val) bfin_write32(MXVR_PAT_EN_0, val)
198 #define bfin_write_MXVR_PAT_DATA_1(val) bfin_write32(MXVR_PAT_DATA_1, val)
200 #define bfin_write_MXVR_PAT_EN_1(val) bfin_write32(MXVR_PAT_EN_1, val)
202 #define bfin_write_MXVR_FRAME_CNT_0(val) bfin_write16(MXVR_FRAME_CNT_0, val)
204 #define bfin_write_MXVR_FRAME_CNT_1(val) bfin_write16(MXVR_FRAME_CNT_1, val)
206 #define bfin_write_MXVR_ROUTING_0(val) bfin_write32(MXVR_ROUTING_0, val)
208 #define bfin_write_MXVR_ROUTING_1(val) bfin_write32(MXVR_ROUTING_1, val)
210 #define bfin_write_MXVR_ROUTING_2(val) bfin_write32(MXVR_ROUTING_2, val)
212 #define bfin_write_MXVR_ROUTING_3(val) bfin_write32(MXVR_ROUTING_3, val)
214 #define bfin_write_MXVR_ROUTING_4(val) bfin_write32(MXVR_ROUTING_4, val)
216 #define bfin_write_MXVR_ROUTING_5(val) bfin_write32(MXVR_ROUTING_5, val)
218 #define bfin_write_MXVR_ROUTING_6(val) bfin_write32(MXVR_ROUTING_6, val)
220 #define bfin_write_MXVR_ROUTING_7(val) bfin_write32(MXVR_ROUTING_7, val)
222 #define bfin_write_MXVR_ROUTING_8(val) bfin_write32(MXVR_ROUTING_8, val)
224 #define bfin_write_MXVR_ROUTING_9(val) bfin_write32(MXVR_ROUTING_9, val)
226 #define bfin_write_MXVR_ROUTING_10(val) bfin_write32(MXVR_ROUTING_10, val)
228 #define bfin_write_MXVR_ROUTING_11(val) bfin_write32(MXVR_ROUTING_11, val)
230 #define bfin_write_MXVR_ROUTING_12(val) bfin_write32(MXVR_ROUTING_12, val)
232 #define bfin_write_MXVR_ROUTING_13(val) bfin_write32(MXVR_ROUTING_13, val)
234 #define bfin_write_MXVR_ROUTING_14(val) bfin_write32(MXVR_ROUTING_14, val)
236 #define bfin_write_MXVR_PLL_CTL_1(val) bfin_write32(MXVR_PLL_CTL_1, val)
238 #define bfin_write_MXVR_BLOCK_CNT(val) bfin_write16(MXVR_BLOCK_CNT, val)
/linux-4.1.27/arch/blackfin/mach-bf527/include/mach/
H A DcdefBF525.h16 #define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
18 #define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val)
20 #define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val)
22 #define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val)
24 #define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val)
26 #define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val)
28 #define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val)
30 #define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val)
32 #define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val)
34 #define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val)
36 #define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val)
38 #define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val)
40 #define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
45 #define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
47 #define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val)
49 #define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val)
51 #define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
53 #define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val)
55 #define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val)
57 #define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val)
59 #define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val)
61 #define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val)
63 #define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
65 #define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val)
67 #define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
69 #define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val)
74 #define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val)
76 #define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val)
78 #define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val)
80 #define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val)
82 #define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val)
84 #define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val)
86 #define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val)
88 #define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val)
93 #define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
95 #define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
97 #define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
102 #define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val)
104 #define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val)
106 #define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val)
108 #define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val)
110 #define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val)
115 #define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
120 #define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
123 #define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
126 #define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
128 #define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
133 #define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
135 #define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
137 #define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
139 #define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
141 #define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
143 #define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
145 #define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
147 #define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
149 #define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
151 #define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
156 #define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
158 #define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
160 #define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
162 #define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
164 #define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
166 #define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
168 #define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
170 #define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
172 #define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
174 #define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
179 #define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
181 #define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
183 #define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
185 #define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
187 #define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
189 #define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
191 #define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
193 #define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
195 #define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
197 #define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
202 #define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
204 #define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
206 #define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
208 #define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
210 #define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
212 #define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
214 #define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
216 #define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
218 #define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
220 #define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
225 #define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
227 #define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
229 #define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
231 #define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
233 #define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
235 #define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
237 #define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
239 #define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
241 #define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
243 #define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
248 #define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
250 #define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
252 #define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
254 #define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
256 #define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
258 #define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
260 #define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
262 #define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
264 #define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
266 #define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
271 #define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
273 #define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
275 #define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
277 #define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
279 #define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
281 #define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
283 #define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
285 #define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
287 #define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
289 #define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
294 #define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
296 #define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
298 #define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
300 #define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
302 #define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
304 #define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
306 #define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
308 #define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
310 #define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
312 #define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
315 #define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
320 #define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val)
322 #define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val)
324 #define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val)
326 #define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val)
328 #define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val)
333 #define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val)
335 #define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val)
337 #define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val)
339 #define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val)
341 #define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val)
346 #define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val)
348 #define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val)
350 #define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val)
352 #define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val)
354 #define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val)
359 #define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val)
361 #define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val)
363 #define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val)
365 #define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val)
367 #define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val)
372 #define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val)
374 #define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val)
376 #define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val)
378 #define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val)
380 #define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val)
385 #define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val)
387 #define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val)
389 #define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val)
391 #define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val)
393 #define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val)
398 #define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val)
400 #define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val)
402 #define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val)
404 #define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val)
406 #define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val)
411 #define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val)
413 #define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val)
415 #define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val)
417 #define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val)
419 #define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val)
H A DcdefBF522.h13 #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
16 #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
18 #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
20 #define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
25 #define bfin_write_SWRST(val) bfin_write16(SWRST, val)
27 #define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
30 #define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val)
32 #define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
34 #define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 6)), val)
37 #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
39 #define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
41 #define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
43 #define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
46 #define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
48 #define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 6)), val)
51 #define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
53 #define bfin_write_SIC_IWR(x, val) bfin_write32((SIC_IWR0 + (x << 6)), val)
58 #define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
60 #define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val)
62 #define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val)
64 #define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val)
66 #define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val)
68 #define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
70 #define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val)
74 #define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
76 #define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
78 #define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
83 #define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val)
85 #define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val)
87 #define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val)
89 #define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val)
91 #define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val)
93 #define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST, val)
95 #define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val)
100 #define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val)
102 #define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val)
104 #define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val)
106 #define bfin_write_UART0_IER(val) bfin_write16(UART0_IER, val)
108 #define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val)
110 #define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR, val)
112 #define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val)
114 #define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val)
116 #define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val)
118 #define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val)
120 #define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val)
122 #define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val)
127 #define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL, val)
129 #define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG, val)
131 #define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT, val)
133 #define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR, val)
135 #define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR, val)
137 #define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD, val)
139 #define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW, val)
144 #define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
146 #define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
148 #define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
150 #define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
153 #define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
155 #define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
157 #define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
159 #define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
162 #define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
164 #define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
166 #define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
168 #define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
171 #define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val)
173 #define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
175 #define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val)
177 #define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val)
180 #define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val)
182 #define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
184 #define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val)
186 #define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val)
189 #define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val)
191 #define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
193 #define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val)
195 #define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val)
198 #define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val)
200 #define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
202 #define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val)
204 #define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val)
207 #define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val)
209 #define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
211 #define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val)
213 #define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val)
216 #define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val)
218 #define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val)
220 #define bfin_write_TIMER_STATUS(val) bfin_write32(TIMER_STATUS, val)
225 #define bfin_write_PORTFIO(val) bfin_write16(PORTFIO, val)
227 #define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR, val)
229 #define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET, val)
231 #define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val)
233 #define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA, val)
235 #define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val)
237 #define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val)
239 #define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val)
241 #define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB, val)
243 #define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val)
245 #define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val)
247 #define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val)
249 #define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR, val)
251 #define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR, val)
253 #define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE, val)
255 #define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH, val)
257 #define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN, val)
262 #define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
264 #define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
266 #define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
268 #define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
270 #define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
272 #define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
274 #define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX, val)
276 #define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX, val)
278 #define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX, val)
280 #define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX, val)
282 #define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
284 #define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
286 #define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
288 #define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
290 #define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
292 #define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
294 #define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
296 #define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
298 #define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
300 #define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
302 #define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
304 #define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
306 #define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
308 #define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
310 #define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
312 #define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
317 #define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val)
319 #define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val)
321 #define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
323 #define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
325 #define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
327 #define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
329 #define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX, val)
331 #define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX, val)
333 #define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX, val)
335 #define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX, val)
337 #define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
339 #define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val)
341 #define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
343 #define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val)
345 #define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val)
347 #define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val)
349 #define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val)
351 #define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val)
353 #define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val)
355 #define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val)
357 #define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val)
359 #define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val)
361 #define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val)
363 #define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val)
365 #define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val)
367 #define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val)
372 #define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val)
374 #define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
376 #define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
378 #define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val)
380 #define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val)
382 #define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val)
384 #define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val)
389 #define bfin_write_DMAC_TC_PER(val) bfin_write16(DMAC_TC_PER, val)
391 #define bfin_write_DMAC_TC_CNT(val) bfin_write16(DMAC_TC_CNT, val)
395 #define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val)
397 #define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val)
399 #define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val)
401 #define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val)
403 #define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val)
405 #define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val)
407 #define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val)
409 #define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val)
411 #define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val)
413 #define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
415 #define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
417 #define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
419 #define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
422 #define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
424 #define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val)
426 #define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val)
428 #define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val)
430 #define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val)
432 #define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val)
434 #define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val)
436 #define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val)
438 #define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val)
440 #define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
442 #define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
444 #define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
446 #define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
449 #define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val)
451 #define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val)
453 #define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val)
455 #define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val)
457 #define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val)
459 #define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val)
461 #define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val)
463 #define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val)
465 #define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val)
467 #define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
469 #define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
471 #define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
473 #define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
476 #define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
478 #define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val)
480 #define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val)
482 #define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val)
484 #define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val)
486 #define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val)
488 #define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val)
490 #define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val)
492 #define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val)
494 #define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
496 #define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
498 #define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
500 #define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
503 #define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val)
505 #define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val)
507 #define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val)
509 #define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val)
511 #define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val)
513 #define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val)
515 #define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val)
517 #define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val)
519 #define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val)
521 #define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
523 #define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
525 #define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
527 #define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
530 #define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
532 #define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val)
534 #define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val)
536 #define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val)
538 #define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
540 #define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val)
542 #define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val)
544 #define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val)
546 #define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val)
548 #define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
550 #define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
552 #define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
554 #define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
557 #define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val)
559 #define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
561 #define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val)
563 #define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val)
565 #define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val)
567 #define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val)
569 #define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val)
571 #define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val)
573 #define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val)
575 #define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
577 #define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
579 #define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
581 #define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
584 #define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val)
586 #define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val)
588 #define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val)
590 #define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val)
592 #define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val)
594 #define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val)
596 #define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val)
598 #define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val)
600 #define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val)
602 #define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
604 #define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
606 #define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
608 #define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
611 #define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val)
613 #define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR, val)
615 #define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR, val)
617 #define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val)
619 #define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val)
621 #define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val)
623 #define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val)
625 #define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR, val)
627 #define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR, val)
629 #define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
631 #define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
633 #define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
635 #define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
638 #define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val)
640 #define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR, val)
642 #define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR, val)
644 #define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val)
646 #define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val)
648 #define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val)
650 #define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val)
652 #define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR, val)
654 #define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR, val)
656 #define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
658 #define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
660 #define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
662 #define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
665 #define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val)
667 #define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR, val)
669 #define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR, val)
671 #define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val)
673 #define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val)
675 #define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
677 #define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
679 #define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR, val)
681 #define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR, val)
683 #define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
685 #define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
687 #define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
689 #define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
692 #define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val)
694 #define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR, val)
696 #define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR, val)
698 #define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val)
700 #define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val)
702 #define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
704 #define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
706 #define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR, val)
708 #define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR, val)
710 #define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
712 #define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
714 #define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
716 #define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
719 #define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
721 #define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR, val)
723 #define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val)
725 #define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
727 #define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
729 #define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
731 #define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
733 #define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val)
735 #define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val)
737 #define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
739 #define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
741 #define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
743 #define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
746 #define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
748 #define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val)
750 #define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val)
752 #define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
754 #define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
756 #define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
758 #define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
760 #define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val)
762 #define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val)
764 #define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
766 #define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
768 #define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
770 #define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
773 #define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
775 #define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val)
777 #define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val)
779 #define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
781 #define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
783 #define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
785 #define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
787 #define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val)
789 #define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val)
791 #define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
793 #define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
795 #define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
797 #define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
800 #define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
802 #define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val)
804 #define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val)
806 #define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
808 #define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
810 #define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
812 #define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
814 #define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val)
816 #define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val)
818 #define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
820 #define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
822 #define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
824 #define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
829 #define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val)
831 #define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val)
834 #define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val)
836 #define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val)
838 #define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val)
845 #define bfin_write_PORTGIO(val) bfin_write16(PORTGIO, val)
847 #define bfin_write_PORTGIO_CLEAR(val) bfin_write16(PORTGIO_CLEAR, val)
849 #define bfin_write_PORTGIO_SET(val) bfin_write16(PORTGIO_SET, val)
851 #define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val)
853 #define bfin_write_PORTGIO_MASKA(val) bfin_write16(PORTGIO_MASKA, val)
855 #define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val)
857 #define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val)
859 #define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val)
861 #define bfin_write_PORTGIO_MASKB(val) bfin_write16(PORTGIO_MASKB, val)
863 #define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val)
865 #define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val)
867 #define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val)
869 #define bfin_write_PORTGIO_DIR(val) bfin_write16(PORTGIO_DIR, val)
871 #define bfin_write_PORTGIO_POLAR(val) bfin_write16(PORTGIO_POLAR, val)
873 #define bfin_write_PORTGIO_EDGE(val) bfin_write16(PORTGIO_EDGE, val)
875 #define bfin_write_PORTGIO_BOTH(val) bfin_write16(PORTGIO_BOTH, val)
877 #define bfin_write_PORTGIO_INEN(val) bfin_write16(PORTGIO_INEN, val)
882 #define bfin_write_PORTHIO(val) bfin_write16(PORTHIO, val)
884 #define bfin_write_PORTHIO_CLEAR(val) bfin_write16(PORTHIO_CLEAR, val)
886 #define bfin_write_PORTHIO_SET(val) bfin_write16(PORTHIO_SET, val)
888 #define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val)
890 #define bfin_write_PORTHIO_MASKA(val) bfin_write16(PORTHIO_MASKA, val)
892 #define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val)
894 #define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val)
896 #define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val)
898 #define bfin_write_PORTHIO_MASKB(val) bfin_write16(PORTHIO_MASKB, val)
900 #define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val)
902 #define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val)
904 #define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val)
906 #define bfin_write_PORTHIO_DIR(val) bfin_write16(PORTHIO_DIR, val)
908 #define bfin_write_PORTHIO_POLAR(val) bfin_write16(PORTHIO_POLAR, val)
910 #define bfin_write_PORTHIO_EDGE(val) bfin_write16(PORTHIO_EDGE, val)
912 #define bfin_write_PORTHIO_BOTH(val) bfin_write16(PORTHIO_BOTH, val)
914 #define bfin_write_PORTHIO_INEN(val) bfin_write16(PORTHIO_INEN, val)
919 #define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val)
921 #define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val)
923 #define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val)
925 #define bfin_write_UART1_IER(val) bfin_write16(UART1_IER, val)
927 #define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val)
929 #define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR, val)
931 #define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val)
933 #define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val)
935 #define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val)
937 #define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val)
939 #define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val)
941 #define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val)
947 #define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val)
949 #define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val)
951 #define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val)
953 #define bfin_write_PORT_MUX(val) bfin_write16(PORT_MUX, val)
958 #define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
960 #define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
962 #define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
964 #define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
966 #define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
968 #define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
970 #define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
973 #define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
975 #define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
977 #define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
979 #define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
981 #define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
983 #define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
985 #define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
992 #define bfin_write_PORTF_MUX(val) bfin_write16(PORTF_MUX, val)
994 #define bfin_write_PORTG_MUX(val) bfin_write16(PORTG_MUX, val)
996 #define bfin_write_PORTH_MUX(val) bfin_write16(PORTH_MUX, val)
999 #define bfin_write_PORTF_DRIVE(val) bfin_write16(PORTF_DRIVE, val)
1001 #define bfin_write_PORTG_DRIVE(val) bfin_write16(PORTG_DRIVE, val)
1003 #define bfin_write_PORTH_DRIVE(val) bfin_write16(PORTH_DRIVE, val)
1005 #define bfin_write_PORTF_SLEW(val) bfin_write16(PORTF_SLEW, val)
1007 #define bfin_write_PORTG_SLEW(val) bfin_write16(PORTG_SLEW, val)
1009 #define bfin_write_PORTH_SLEW(val) bfin_write16(PORTH_SLEW, val)
1011 #define bfin_write_PORTF_HYSTERESIS(val) bfin_write16(PORTF_HYSTERESIS, val)
1013 #define bfin_write_PORTG_HYSTERESIS(val) bfin_write16(PORTG_HYSTERESIS, val)
1015 #define bfin_write_PORTH_HYSTERESIS(val) bfin_write16(PORTH_HYSTERESIS, val)
1017 #define bfin_write_MISCPORT_DRIVE(val) bfin_write16(MISCPORT_DRIVE, val)
1019 #define bfin_write_MISCPORT_SLEW(val) bfin_write16(MISCPORT_SLEW, val)
1021 #define bfin_write_MISCPORT_HYSTERESIS(val) bfin_write16(MISCPORT_HYSTERESIS, val)
1026 #define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val)
1028 #define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val)
1030 #define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val)
1035 #define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val)
1037 #define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val)
1039 #define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val)
1041 #define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val)
1043 #define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val)
1045 #define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val)
1047 #define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val)
1049 #define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val)
1054 #define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val)
1056 #define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
1058 #define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val)
1063 #define bfin_write_NFC_CTL(val) bfin_write16(NFC_CTL, val)
1065 #define bfin_write_NFC_STAT(val) bfin_write16(NFC_STAT, val)
1067 #define bfin_write_NFC_IRQSTAT(val) bfin_write16(NFC_IRQSTAT, val)
1069 #define bfin_write_NFC_IRQMASK(val) bfin_write16(NFC_IRQMASK, val)
1071 #define bfin_write_NFC_ECC0(val) bfin_write16(NFC_ECC0, val)
1073 #define bfin_write_NFC_ECC1(val) bfin_write16(NFC_ECC1, val)
1075 #define bfin_write_NFC_ECC2(val) bfin_write16(NFC_ECC2, val)
1077 #define bfin_write_NFC_ECC3(val) bfin_write16(NFC_ECC3, val)
1079 #define bfin_write_NFC_COUNT(val) bfin_write16(NFC_COUNT, val)
1081 #define bfin_write_NFC_RST(val) bfin_write16(NFC_RST, val)
1083 #define bfin_write_NFC_PGCTL(val) bfin_write16(NFC_PGCTL, val)
1085 #define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val)
1087 #define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val)
1089 #define bfin_write_NFC_CMD(val) bfin_write16(NFC_CMD, val)
1091 #define bfin_write_NFC_DATA_WR(val) bfin_write16(NFC_DATA_WR, val)
1093 #define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val)
H A DcdefBF527.h16 #define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE, val)
18 #define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO, val)
20 #define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI, val)
22 #define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO, val)
24 #define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI, val)
26 #define bfin_write_EMAC_STAADD(val) bfin_write32(EMAC_STAADD, val)
28 #define bfin_write_EMAC_STADAT(val) bfin_write32(EMAC_STADAT, val)
30 #define bfin_write_EMAC_FLC(val) bfin_write32(EMAC_FLC, val)
32 #define bfin_write_EMAC_VLAN1(val) bfin_write32(EMAC_VLAN1, val)
34 #define bfin_write_EMAC_VLAN2(val) bfin_write32(EMAC_VLAN2, val)
36 #define bfin_write_EMAC_WKUP_CTL(val) bfin_write32(EMAC_WKUP_CTL, val)
38 #define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0, val)
40 #define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1, val)
42 #define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2, val)
44 #define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3, val)
46 #define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD, val)
48 #define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF, val)
50 #define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0, val)
52 #define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1, val)
55 #define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL, val)
57 #define bfin_write_EMAC_SYSTAT(val) bfin_write32(EMAC_SYSTAT, val)
59 #define bfin_write_EMAC_RX_STAT(val) bfin_write32(EMAC_RX_STAT, val)
61 #define bfin_write_EMAC_RX_STKY(val) bfin_write32(EMAC_RX_STKY, val)
63 #define bfin_write_EMAC_RX_IRQE(val) bfin_write32(EMAC_RX_IRQE, val)
65 #define bfin_write_EMAC_TX_STAT(val) bfin_write32(EMAC_TX_STAT, val)
67 #define bfin_write_EMAC_TX_STKY(val) bfin_write32(EMAC_TX_STKY, val)
69 #define bfin_write_EMAC_TX_IRQE(val) bfin_write32(EMAC_TX_IRQE, val)
72 #define bfin_write_EMAC_MMC_CTL(val) bfin_write32(EMAC_MMC_CTL, val)
74 #define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS, val)
76 #define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE, val)
78 #define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS, val)
80 #define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE, val)
83 #define bfin_write_EMAC_RXC_OK(val) bfin_write32(EMAC_RXC_OK, val)
85 #define bfin_write_EMAC_RXC_FCS(val) bfin_write32(EMAC_RXC_FCS, val)
87 #define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN, val)
89 #define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET, val)
91 #define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF, val)
93 #define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST, val)
95 #define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI, val)
97 #define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD, val)
99 #define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI, val)
101 #define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO, val)
103 #define bfin_write_EMAC_RXC_LONG(val) bfin_write32(EMAC_RXC_LONG, val)
105 #define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL, val)
107 #define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE, val)
109 #define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE, val)
111 #define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM, val)
113 #define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT, val)
115 #define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED, val)
117 #define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT, val)
119 #define bfin_write_EMAC_RXC_EQ64(val) bfin_write32(EMAC_RXC_EQ64, val)
121 #define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128, val)
123 #define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256, val)
125 #define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512, val)
127 #define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024, val)
129 #define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024, val)
132 #define bfin_write_EMAC_TXC_OK(val) bfin_write32(EMAC_TXC_OK, val)
134 #define bfin_write_EMAC_TXC_1COL(val) bfin_write32(EMAC_TXC_1COL, val)
136 #define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL, val)
138 #define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET, val)
140 #define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER, val)
142 #define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL, val)
144 #define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL, val)
146 #define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND, val)
148 #define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR, val)
150 #define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST, val)
152 #define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI, val)
154 #define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD, val)
156 #define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR, val)
158 #define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL, val)
160 #define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM, val)
162 #define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT, val)
164 #define bfin_write_EMAC_TXC_EQ64(val) bfin_write32(EMAC_TXC_EQ64, val)
166 #define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128, val)
168 #define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256, val)
170 #define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512, val)
172 #define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024, val)
174 #define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024, val)
176 #define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val)
/linux-4.1.27/arch/blackfin/mach-bf609/include/mach/
H A DcdefBF60x_base.h17 #define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
23 #define bfin_write_SEC0_CCTL(val) bfin_write32(SEC0_CCTL, val)
25 #define bfin_write_SEC0_CSID(val) bfin_write32(SEC0_CSID, val)
27 #define bfin_write_SEC_GCTL(val) bfin_write32(SEC_GCTL, val)
30 #define bfin_write_SEC_FCTL(val) bfin_write32(SEC_FCTL, val)
33 #define bfin_write_SEC_SCTL(sid, val) bfin_write32((SEC_SCTL0 + (sid) * 8), val)
36 #define bfin_write_SEC_SSTAT(sid, val) bfin_write32((SEC_SSTAT0 + (sid) * 8), val)
40 #define bfin_write_RCU0_CTL(val) bfin_write32(RCU0_CTL, val)
44 #define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
46 #define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
48 #define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
55 #define bfin_write_UART0_REVID(val) bfin_write32(UART0_REVID, val)
57 #define bfin_write_UART0_GCTL(val) bfin_write32(UART0_GCTL, val)
59 #define bfin_write_UART0_STAT(val) bfin_write32(UART0_STAT, val)
61 #define bfin_write_UART0_SCR(val) bfin_write32(UART0_SCR, val)
63 #define bfin_write_UART0_CLK(val) bfin_write32(UART0_CLK, val)
65 #define bfin_write_UART0_IER(val) bfin_write32(UART0_IER, val)
67 #define bfin_write_UART0_IER_SET(val) bfin_write32(UART0_IER_SET, val)
69 #define bfin_write_UART0_IER_CLEAR(val) bfin_write32(UART0_IER_CLEAR, val)
71 #define bfin_write_UART0_RBR(val) bfin_write32(UART0_RBR, val)
73 #define bfin_write_UART0_THR(val) bfin_write32(UART0_THR, val)
75 #define bfin_write_UART0_TAIP(val) bfin_write32(UART0_TAIP, val)
77 #define bfin_write_UART0_TSR(val) bfin_write32(UART0_TSR, val)
79 #define bfin_write_UART0_RSR(val) bfin_write32(UART0_RSR, val)
81 #define bfin_write_UART0_TXCNT(val) bfin_write32(UART0_TXCNT, val)
83 #define bfin_write_UART0_RXCNT(val) bfin_write32(UART0_RXCNT, val)
88 #define bfin_write_UART1_REVID(val) bfin_write32(UART1_REVID, val)
90 #define bfin_write_UART1_GCTL(val) bfin_write32(UART1_GCTL, val)
92 #define bfin_write_UART1_STAT(val) bfin_write32(UART1_STAT, val)
94 #define bfin_write_UART1_SCR(val) bfin_write32(UART1_SCR, val)
96 #define bfin_write_UART1_CLK(val) bfin_write32(UART1_CLK, val)
98 #define bfin_write_UART1_IER(val) bfin_write32(UART1_IER, val)
100 #define bfin_write_UART1_IER_SET(val) bfin_write32(UART1_IER_SET, val)
102 #define bfin_write_UART1_IER_CLEAR(val) bfin_write32(UART1_IER_CLEAR, val)
104 #define bfin_write_UART1_RBR(val) bfin_write32(UART1_RBR, val)
106 #define bfin_write_UART1_THR(val) bfin_write32(UART1_THR, val)
108 #define bfin_write_UART1_TAIP(val) bfin_write32(UART1_TAIP, val)
110 #define bfin_write_UART1_TSR(val) bfin_write32(UART1_TSR, val)
112 #define bfin_write_UART1_RSR(val) bfin_write32(UART1_RSR, val)
114 #define bfin_write_UART1_TXCNT(val) bfin_write32(UART1_TXCNT, val)
116 #define bfin_write_UART1_RXCNT(val) bfin_write32(UART1_RXCNT, val)
122 #define bfin_write_SPI0_CTL(val) bfin_write32(SPI0_CTL, val)
124 #define bfin_write_SPI0_RXCTL(val) bfin_write32(SPI0_RXCTL, val)
126 #define bfin_write_SPI0_TXCTL(val) bfin_write32(SPI0_TXCTL, val)
128 #define bfin_write_SPI0_CLK(val) bfin_write32(SPI0_CLK, val)
130 #define bfin_write_SPI0_DLY(val) bfin_write32(SPI0_DLY, val)
132 #define bfin_write_SPI0_SLVSEL(val) bfin_write32(SPI0_SLVSEL, val)
134 #define bfin_write_SPI0_RWC(val) bfin_write32(SPI0_RWC, val)
136 #define bfin_write_SPI0_RWCR(val) bfin_write32(SPI0_RWCR, val)
138 #define bfin_write_SPI0_TWC(val) bfin_write32(SPI0_TWC, val)
140 #define bfin_write_SPI0_TWCR(val) bfin_write32(SPI0_TWCR, val)
142 #define bfin_write_SPI0_IMSK(val) bfin_write32(SPI0_IMSK, val)
144 #define bfin_write_SPI0_IMSK_CLR(val) bfin_write32(SPI0_IMSK_CLR, val)
146 #define bfin_write_SPI0_IMSK_SET(val) bfin_write32(SPI0_IMSK_SET, val)
148 #define bfin_write_SPI0_STAT(val) bfin_write32(SPI0_STAT, val)
150 #define bfin_write_SPI0_ILAT(val) bfin_write32(SPI0_ILAT, val)
152 #define bfin_write_SPI0_ILAT_CLR(val) bfin_write32(SPI0_ILAT_CLR, val)
154 #define bfin_write_SPI0_RFIFO(val) bfin_write32(SPI0_RFIFO, val)
156 #define bfin_write_SPI0_TFIFO(val) bfin_write32(SPI0_TFIFO, val)
161 #define bfin_write_SPI1_CTL(val) bfin_write32(SPI1_CTL, val)
163 #define bfin_write_SPI1_RXCTL(val) bfin_write32(SPI1_RXCTL, val)
165 #define bfin_write_SPI1_TXCTL(val) bfin_write32(SPI1_TXCTL, val)
167 #define bfin_write_SPI1_CLK(val) bfin_write32(SPI1_CLK, val)
169 #define bfin_write_SPI1_DLY(val) bfin_write32(SPI1_DLY, val)
171 #define bfin_write_SPI1_SLVSEL(val) bfin_write32(SPI1_SLVSEL, val)
173 #define bfin_write_SPI1_RWC(val) bfin_write32(SPI1_RWC, val)
175 #define bfin_write_SPI1_RWCR(val) bfin_write32(SPI1_RWCR, val)
177 #define bfin_write_SPI1_TWC(val) bfin_write32(SPI1_TWC, val)
179 #define bfin_write_SPI1_TWCR(val) bfin_write32(SPI1_TWCR, val)
181 #define bfin_write_SPI1_IMSK(val) bfin_write32(SPI1_IMSK, val)
183 #define bfin_write_SPI1_IMSK_CLR(val) bfin_write32(SPI1_IMSK_CLR, val)
185 #define bfin_write_SPI1_IMSK_SET(val) bfin_write32(SPI1_IMSK_SET, val)
187 #define bfin_write_SPI1_STAT(val) bfin_write32(SPI1_STAT, val)
189 #define bfin_write_SPI1_ILAT(val) bfin_write32(SPI1_ILAT, val)
191 #define bfin_write_SPI1_ILAT_CLR(val) bfin_write32(SPI1_ILAT_CLR, val)
193 #define bfin_write_SPI1_RFIFO(val) bfin_write32(SPI1_RFIFO, val)
195 #define bfin_write_SPI1_TFIFO(val) bfin_write32(SPI1_TFIFO, val)
199 #define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
201 #define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
203 #define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
205 #define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
207 #define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
209 #define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
211 #define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
213 #define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
215 #define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
217 #define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
219 #define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
221 #define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
223 #define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val)
225 #define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
227 #define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val)
229 #define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val)
231 #define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val)
233 #define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
235 #define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val)
237 #define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val)
239 #define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val)
241 #define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
243 #define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val)
245 #define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val)
247 #define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val)
249 #define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
251 #define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val)
253 #define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val)
255 #define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val)
257 #define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
259 #define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val)
261 #define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val)
273 #define bfin_write_SMC_GCTL(val) bfin_write32(SMC_GCTL, val)
276 #define bfin_write_SMC_B0CTL(val) bfin_write32(SMC_B0CTL, val)
278 #define bfin_write_SMC_B0TIM(val) bfin_write32(SMC_B0TIM, val)
280 #define bfin_write_SMC_B0ETIM(val) bfin_write32(SMC_B0ETIM, val)
282 #define bfin_write_SMC_B1CTL(val) bfin_write32(SMC_B1CTL, val)
284 #define bfin_write_SMC_B1TIM(val) bfin_write32(SMC_B1TIM, val)
286 #define bfin_write_SMC_B1ETIM(val) bfin_write32(SMC_B1ETIM, val)
288 #define bfin_write_SMC_B2CTL(val) bfin_write32(SMC_B2CTL, val)
290 #define bfin_write_SMC_B2TIM(val) bfin_write32(SMC_B2TIM, val)
292 #define bfin_write_SMC_B2ETIM(val) bfin_write32(SMC_B2ETIM, val)
294 #define bfin_write_SMC_B3CTL(val) bfin_write32(SMC_B3CTL, val)
296 #define bfin_write_SMC_B3TIM(val) bfin_write32(SMC_B3TIM, val)
298 #define bfin_write_SMC_B3ETIM(val) bfin_write32(SMC_B3ETIM, val)
302 #define bfin_write_DMC0_CFG(val) bfin_write32(DMC0_CFG, val)
304 #define bfin_write_DMC0_TR0(val) bfin_write32(DMC0_TR0, val)
306 #define bfin_write_DMC0_TR1(val) bfin_write32(DMC0_TR1, val)
308 #define bfin_write_DMC0_TR2(val) bfin_write32(DMC0_TR2, val)
310 #define bfin_write_DMC0_MR(val) bfin_write32(DMC0_MR, val)
312 #define bfin_write_DMC0_EMR1(val) bfin_write32(DMC0_EMR1, val)
314 #define bfin_write_DMC0_CTL(val) bfin_write32(DMC0_CTL, val)
316 #define bfin_write_DMC0_EFFCTL(val) bfin_write32(DMC0_EFFCTL, val)
318 #define bfin_write_DMC0_STAT(val) bfin_write32(DMC0_STAT, val)
320 #define bfin_write_DMC0_DLLCTL(val) bfin_write32(DMC0_DLLCTL, val)
328 #define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val)
330 #define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val)
332 #define bfin_write_DMA0_CONFIG(val) bfin_write32(DMA0_CONFIG, val)
334 #define bfin_write_DMA0_X_COUNT(val) bfin_write32(DMA0_X_COUNT, val)
336 #define bfin_write_DMA0_X_MODIFY(val) bfin_write32(DMA0_X_MODIFY, val)
338 #define bfin_write_DMA0_Y_COUNT(val) bfin_write32(DMA0_Y_COUNT, val)
340 #define bfin_write_DMA0_Y_MODIFY(val) bfin_write32(DMA0_Y_MODIFY, val)
342 #define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val)
344 #define bfin_write_DMA0_PREV_DESC_PTR(val) bfin_write32(DMA0_PREV_DESC_PTR, val)
346 #define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val)
348 #define bfin_write_DMA0_IRQ_STATUS(val) bfin_write32(DMA0_IRQ_STATUS, val)
350 #define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write32(DMA0_CURR_X_COUNT, val)
352 #define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write32(DMA0_CURR_Y_COUNT, val)
354 #define bfin_write_DMA0_BWL_COUNT(val) bfin_write32(DMA0_BWL_COUNT, val)
356 #define bfin_write_DMA0_CURR_BWL_COUNT(val) bfin_write32(DMA0_CURR_BWL_COUNT, val)
358 #define bfin_write_DMA0_BWM_COUNT(val) bfin_write32(DMA0_BWM_COUNT, val)
360 #define bfin_write_DMA0_CURR_BWM_COUNT(val) bfin_write32(DMA0_CURR_BWM_COUNT, val)
365 #define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val)
367 #define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val)
369 #define bfin_write_DMA1_CONFIG(val) bfin_write32(DMA1_CONFIG, val)
371 #define bfin_write_DMA1_X_COUNT(val) bfin_write32(DMA1_X_COUNT, val)
373 #define bfin_write_DMA1_X_MODIFY(val) bfin_write32(DMA1_X_MODIFY, val)
375 #define bfin_write_DMA1_Y_COUNT(val) bfin_write32(DMA1_Y_COUNT, val)
377 #define bfin_write_DMA1_Y_MODIFY(val) bfin_write32(DMA1_Y_MODIFY, val)
379 #define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val)
381 #define bfin_write_DMA1_PREV_DESC_PTR(val) bfin_write32(DMA1_PREV_DESC_PTR, val)
383 #define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val)
385 #define bfin_write_DMA1_IRQ_STATUS(val) bfin_write32(DMA1_IRQ_STATUS, val)
387 #define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write32(DMA1_CURR_X_COUNT, val)
389 #define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write32(DMA1_CURR_Y_COUNT, val)
391 #define bfin_write_DMA1_BWL_COUNT(val) bfin_write32(DMA1_BWL_COUNT, val)
393 #define bfin_write_DMA1_CURR_BWL_COUNT(val) bfin_write32(DMA1_CURR_BWL_COUNT, val)
395 #define bfin_write_DMA1_BWM_COUNT(val) bfin_write32(DMA1_BWM_COUNT, val)
397 #define bfin_write_DMA1_CURR_BWM_COUNT(val) bfin_write32(DMA1_CURR_BWM_COUNT, val)
402 #define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val)
404 #define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val)
406 #define bfin_write_DMA2_CONFIG(val) bfin_write32(DMA2_CONFIG, val)
408 #define bfin_write_DMA2_X_COUNT(val) bfin_write32(DMA2_X_COUNT, val)
410 #define bfin_write_DMA2_X_MODIFY(val) bfin_write32(DMA2_X_MODIFY, val)
412 #define bfin_write_DMA2_Y_COUNT(val) bfin_write32(DMA2_Y_COUNT, val)
414 #define bfin_write_DMA2_Y_MODIFY(val) bfin_write32(DMA2_Y_MODIFY, val)
416 #define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val)
418 #define bfin_write_DMA2_PREV_DESC_PTR(val) bfin_write32(DMA2_PREV_DESC_PTR, val)
420 #define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val)
422 #define bfin_write_DMA2_IRQ_STATUS(val) bfin_write32(DMA2_IRQ_STATUS, val)
424 #define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write32(DMA2_CURR_X_COUNT, val)
426 #define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write32(DMA2_CURR_Y_COUNT, val)
428 #define bfin_write_DMA2_BWL_COUNT(val) bfin_write32(DMA2_BWL_COUNT, val)
430 #define bfin_write_DMA2_CURR_BWL_COUNT(val) bfin_write32(DMA2_CURR_BWL_COUNT, val)
432 #define bfin_write_DMA2_BWM_COUNT(val) bfin_write32(DMA2_BWM_COUNT, val)
434 #define bfin_write_DMA2_CURR_BWM_COUNT(val) bfin_write32(DMA2_CURR_BWM_COUNT, val)
439 #define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val)
441 #define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val)
443 #define bfin_write_DMA3_CONFIG(val) bfin_write32(DMA3_CONFIG, val)
445 #define bfin_write_DMA3_X_COUNT(val) bfin_write32(DMA3_X_COUNT, val)
447 #define bfin_write_DMA3_X_MODIFY(val) bfin_write32(DMA3_X_MODIFY, val)
449 #define bfin_write_DMA3_Y_COUNT(val) bfin_write32(DMA3_Y_COUNT, val)
451 #define bfin_write_DMA3_Y_MODIFY(val) bfin_write32(DMA3_Y_MODIFY, val)
453 #define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val)
455 #define bfin_write_DMA3_PREV_DESC_PTR(val) bfin_write32(DMA3_PREV_DESC_PTR, val)
457 #define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val)
459 #define bfin_write_DMA3_IRQ_STATUS(val) bfin_write32(DMA3_IRQ_STATUS, val)
461 #define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write32(DMA3_CURR_X_COUNT, val)
463 #define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write32(DMA3_CURR_Y_COUNT, val)
465 #define bfin_write_DMA3_BWL_COUNT(val) bfin_write32(DMA3_BWL_COUNT, val)
467 #define bfin_write_DMA3_CURR_BWL_COUNT(val) bfin_write32(DMA3_CURR_BWL_COUNT, val)
469 #define bfin_write_DMA3_BWM_COUNT(val) bfin_write32(DMA3_BWM_COUNT, val)
471 #define bfin_write_DMA3_CURR_BWM_COUNT(val) bfin_write32(DMA3_CURR_BWM_COUNT, val)
476 #define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val)
478 #define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val)
480 #define bfin_write_DMA4_CONFIG(val) bfin_write32(DMA4_CONFIG, val)
482 #define bfin_write_DMA4_X_COUNT(val) bfin_write32(DMA4_X_COUNT, val)
484 #define bfin_write_DMA4_X_MODIFY(val) bfin_write32(DMA4_X_MODIFY, val)
486 #define bfin_write_DMA4_Y_COUNT(val) bfin_write32(DMA4_Y_COUNT, val)
488 #define bfin_write_DMA4_Y_MODIFY(val) bfin_write32(DMA4_Y_MODIFY, val)
490 #define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val)
492 #define bfin_write_DMA4_PREV_DESC_PTR(val) bfin_write32(DMA4_PREV_DESC_PTR, val)
494 #define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val)
496 #define bfin_write_DMA4_IRQ_STATUS(val) bfin_write32(DMA4_IRQ_STATUS, val)
498 #define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write32(DMA4_CURR_X_COUNT, val)
500 #define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write32(DMA4_CURR_Y_COUNT, val)
502 #define bfin_write_DMA4_BWL_COUNT(val) bfin_write32(DMA4_BWL_COUNT, val)
504 #define bfin_write_DMA4_CURR_BWL_COUNT(val) bfin_write32(DMA4_CURR_BWL_COUNT, val)
506 #define bfin_write_DMA4_BWM_COUNT(val) bfin_write32(DMA4_BWM_COUNT, val)
508 #define bfin_write_DMA4_CURR_BWM_COUNT(val) bfin_write32(DMA4_CURR_BWM_COUNT, val)
513 #define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val)
515 #define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val)
517 #define bfin_write_DMA5_CONFIG(val) bfin_write32(DMA5_CONFIG, val)
519 #define bfin_write_DMA5_X_COUNT(val) bfin_write32(DMA5_X_COUNT, val)
521 #define bfin_write_DMA5_X_MODIFY(val) bfin_write32(DMA5_X_MODIFY, val)
523 #define bfin_write_DMA5_Y_COUNT(val) bfin_write32(DMA5_Y_COUNT, val)
525 #define bfin_write_DMA5_Y_MODIFY(val) bfin_write32(DMA5_Y_MODIFY, val)
527 #define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val)
529 #define bfin_write_DMA5_PREV_DESC_PTR(val) bfin_write32(DMA5_PREV_DESC_PTR, val)
531 #define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val)
533 #define bfin_write_DMA5_IRQ_STATUS(val) bfin_write32(DMA5_IRQ_STATUS, val)
535 #define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write32(DMA5_CURR_X_COUNT, val)
537 #define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write32(DMA5_CURR_Y_COUNT, val)
539 #define bfin_write_DMA5_BWL_COUNT(val) bfin_write32(DMA5_BWL_COUNT, val)
541 #define bfin_write_DMA5_CURR_BWL_COUNT(val) bfin_write32(DMA5_CURR_BWL_COUNT, val)
543 #define bfin_write_DMA5_BWM_COUNT(val) bfin_write32(DMA5_BWM_COUNT, val)
545 #define bfin_write_DMA5_CURR_BWM_COUNT(val) bfin_write32(DMA5_CURR_BWM_COUNT, val)
550 #define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
552 #define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val)
554 #define bfin_write_DMA6_CONFIG(val) bfin_write32(DMA6_CONFIG, val)
556 #define bfin_write_DMA6_X_COUNT(val) bfin_write32(DMA6_X_COUNT, val)
558 #define bfin_write_DMA6_X_MODIFY(val) bfin_write32(DMA6_X_MODIFY, val)
560 #define bfin_write_DMA6_Y_COUNT(val) bfin_write32(DMA6_Y_COUNT, val)
562 #define bfin_write_DMA6_Y_MODIFY(val) bfin_write32(DMA6_Y_MODIFY, val)
564 #define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val)
566 #define bfin_write_DMA6_PREV_DESC_PTR(val) bfin_write32(DMA6_PREV_DESC_PTR, val)
568 #define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val)
570 #define bfin_write_DMA6_IRQ_STATUS(val) bfin_write32(DMA6_IRQ_STATUS, val)
572 #define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write32(DMA6_CURR_X_COUNT, val)
574 #define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write32(DMA6_CURR_Y_COUNT, val)
576 #define bfin_write_DMA6_BWL_COUNT(val) bfin_write32(DMA6_BWL_COUNT, val)
578 #define bfin_write_DMA6_CURR_BWL_COUNT(val) bfin_write32(DMA6_CURR_BWL_COUNT, val)
580 #define bfin_write_DMA6_BWM_COUNT(val) bfin_write32(DMA6_BWM_COUNT, val)
582 #define bfin_write_DMA6_CURR_BWM_COUNT(val) bfin_write32(DMA6_CURR_BWM_COUNT, val)
587 #define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val)
589 #define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val)
591 #define bfin_write_DMA7_CONFIG(val) bfin_write32(DMA7_CONFIG, val)
593 #define bfin_write_DMA7_X_COUNT(val) bfin_write32(DMA7_X_COUNT, val)
595 #define bfin_write_DMA7_X_MODIFY(val) bfin_write32(DMA7_X_MODIFY, val)
597 #define bfin_write_DMA7_Y_COUNT(val) bfin_write32(DMA7_Y_COUNT, val)
599 #define bfin_write_DMA7_Y_MODIFY(val) bfin_write32(DMA7_Y_MODIFY, val)
601 #define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val)
603 #define bfin_write_DMA7_PREV_DESC_PTR(val) bfin_write32(DMA7_PREV_DESC_PTR, val)
605 #define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val)
607 #define bfin_write_DMA7_IRQ_STATUS(val) bfin_write32(DMA7_IRQ_STATUS, val)
609 #define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write32(DMA7_CURR_X_COUNT, val)
611 #define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write32(DMA7_CURR_Y_COUNT, val)
613 #define bfin_write_DMA7_BWL_COUNT(val) bfin_write32(DMA7_BWL_COUNT, val)
615 #define bfin_write_DMA7_CURR_BWL_COUNT(val) bfin_write32(DMA7_CURR_BWL_COUNT, val)
617 #define bfin_write_DMA7_BWM_COUNT(val) bfin_write32(DMA7_BWM_COUNT, val)
619 #define bfin_write_DMA7_CURR_BWM_COUNT(val) bfin_write32(DMA7_CURR_BWM_COUNT, val)
624 #define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR, val)
626 #define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR, val)
628 #define bfin_write_DMA8_CONFIG(val) bfin_write32(DMA8_CONFIG, val)
630 #define bfin_write_DMA8_X_COUNT(val) bfin_write32(DMA8_X_COUNT, val)
632 #define bfin_write_DMA8_X_MODIFY(val) bfin_write32(DMA8_X_MODIFY, val)
634 #define bfin_write_DMA8_Y_COUNT(val) bfin_write32(DMA8_Y_COUNT, val)
636 #define bfin_write_DMA8_Y_MODIFY(val) bfin_write32(DMA8_Y_MODIFY, val)
638 #define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR, val)
640 #define bfin_write_DMA8_PREV_DESC_PTR(val) bfin_write32(DMA8_PREV_DESC_PTR, val)
642 #define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR, val)
644 #define bfin_write_DMA8_IRQ_STATUS(val) bfin_write32(DMA8_IRQ_STATUS, val)
646 #define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write32(DMA8_CURR_X_COUNT, val)
648 #define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write32(DMA8_CURR_Y_COUNT, val)
650 #define bfin_write_DMA8_BWL_COUNT(val) bfin_write32(DMA8_BWL_COUNT, val)
652 #define bfin_write_DMA8_CURR_BWL_COUNT(val) bfin_write32(DMA8_CURR_BWL_COUNT, val)
654 #define bfin_write_DMA8_BWM_COUNT(val) bfin_write32(DMA8_BWM_COUNT, val)
656 #define bfin_write_DMA8_CURR_BWM_COUNT(val) bfin_write32(DMA8_CURR_BWM_COUNT, val)
661 #define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR, val)
663 #define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR, val)
665 #define bfin_write_DMA9_CONFIG(val) bfin_write32(DMA9_CONFIG, val)
667 #define bfin_write_DMA9_X_COUNT(val) bfin_write32(DMA9_X_COUNT, val)
669 #define bfin_write_DMA9_X_MODIFY(val) bfin_write32(DMA9_X_MODIFY, val)
671 #define bfin_write_DMA9_Y_COUNT(val) bfin_write32(DMA9_Y_COUNT, val)
673 #define bfin_write_DMA9_Y_MODIFY(val) bfin_write32(DMA9_Y_MODIFY, val)
675 #define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR, val)
677 #define bfin_write_DMA9_PREV_DESC_PTR(val) bfin_write32(DMA9_PREV_DESC_PTR, val)
679 #define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR, val)
681 #define bfin_write_DMA9_IRQ_STATUS(val) bfin_write32(DMA9_IRQ_STATUS, val)
683 #define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write32(DMA9_CURR_X_COUNT, val)
685 #define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write32(DMA9_CURR_Y_COUNT, val)
687 #define bfin_write_DMA9_BWL_COUNT(val) bfin_write32(DMA9_BWL_COUNT, val)
689 #define bfin_write_DMA9_CURR_BWL_COUNT(val) bfin_write32(DMA9_CURR_BWL_COUNT, val)
691 #define bfin_write_DMA9_BWM_COUNT(val) bfin_write32(DMA9_BWM_COUNT, val)
693 #define bfin_write_DMA9_CURR_BWM_COUNT(val) bfin_write32(DMA9_CURR_BWM_COUNT, val)
698 #define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR, val)
700 #define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR, val)
702 #define bfin_write_DMA10_CONFIG(val) bfin_write32(DMA10_CONFIG, val)
704 #define bfin_write_DMA10_X_COUNT(val) bfin_write32(DMA10_X_COUNT, val)
706 #define bfin_write_DMA10_X_MODIFY(val) bfin_write32(DMA10_X_MODIFY, val)
708 #define bfin_write_DMA10_Y_COUNT(val) bfin_write32(DMA10_Y_COUNT, val)
710 #define bfin_write_DMA10_Y_MODIFY(val) bfin_write32(DMA10_Y_MODIFY, val)
712 #define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR, val)
714 #define bfin_write_DMA10_PREV_DESC_PTR(val) bfin_write32(DMA10_PREV_DESC_PTR, val)
716 #define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR, val)
718 #define bfin_write_DMA10_IRQ_STATUS(val) bfin_write32(DMA10_IRQ_STATUS, val)
720 #define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write32(DMA10_CURR_X_COUNT, val)
722 #define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write32(DMA10_CURR_Y_COUNT, val)
724 #define bfin_write_DMA10_BWL_COUNT(val) bfin_write32(DMA10_BWL_COUNT, val)
726 #define bfin_write_DMA10_CURR_BWL_COUNT(val) bfin_write32(DMA10_CURR_BWL_COUNT, val)
728 #define bfin_write_DMA10_BWM_COUNT(val) bfin_write32(DMA10_BWM_COUNT, val)
730 #define bfin_write_DMA10_CURR_BWM_COUNT(val) bfin_write32(DMA10_CURR_BWM_COUNT, val)
735 #define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR, val)
737 #define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR, val)
739 #define bfin_write_DMA11_CONFIG(val) bfin_write32(DMA11_CONFIG, val)
741 #define bfin_write_DMA11_X_COUNT(val) bfin_write32(DMA11_X_COUNT, val)
743 #define bfin_write_DMA11_X_MODIFY(val) bfin_write32(DMA11_X_MODIFY, val)
745 #define bfin_write_DMA11_Y_COUNT(val) bfin_write32(DMA11_Y_COUNT, val)
747 #define bfin_write_DMA11_Y_MODIFY(val) bfin_write32(DMA11_Y_MODIFY, val)
749 #define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR, val)
751 #define bfin_write_DMA11_PREV_DESC_PTR(val) bfin_write32(DMA11_PREV_DESC_PTR, val)
753 #define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR, val)
755 #define bfin_write_DMA11_IRQ_STATUS(val) bfin_write32(DMA11_IRQ_STATUS, val)
757 #define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write32(DMA11_CURR_X_COUNT, val)
759 #define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write32(DMA11_CURR_Y_COUNT, val)
761 #define bfin_write_DMA11_BWL_COUNT(val) bfin_write32(DMA11_BWL_COUNT, val)
763 #define bfin_write_DMA11_CURR_BWL_COUNT(val) bfin_write32(DMA11_CURR_BWL_COUNT, val)
765 #define bfin_write_DMA11_BWM_COUNT(val) bfin_write32(DMA11_BWM_COUNT, val)
767 #define bfin_write_DMA11_CURR_BWM_COUNT(val) bfin_write32(DMA11_CURR_BWM_COUNT, val)
772 #define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_write32(DMA12_NEXT_DESC_PTR, val)
774 #define bfin_write_DMA12_START_ADDR(val) bfin_write32(DMA12_START_ADDR, val)
776 #define bfin_write_DMA12_CONFIG(val) bfin_write32(DMA12_CONFIG, val)
778 #define bfin_write_DMA12_X_COUNT(val) bfin_write32(DMA12_X_COUNT, val)
780 #define bfin_write_DMA12_X_MODIFY(val) bfin_write32(DMA12_X_MODIFY, val)
782 #define bfin_write_DMA12_Y_COUNT(val) bfin_write32(DMA12_Y_COUNT, val)
784 #define bfin_write_DMA12_Y_MODIFY(val) bfin_write32(DMA12_Y_MODIFY, val)
786 #define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_write32(DMA12_CURR_DESC_PTR, val)
788 #define bfin_write_DMA12_PREV_DESC_PTR(val) bfin_write32(DMA12_PREV_DESC_PTR, val)
790 #define bfin_write_DMA12_CURR_ADDR(val) bfin_write32(DMA12_CURR_ADDR, val)
792 #define bfin_write_DMA12_IRQ_STATUS(val) bfin_write32(DMA12_IRQ_STATUS, val)
794 #define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write32(DMA12_CURR_X_COUNT, val)
796 #define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write32(DMA12_CURR_Y_COUNT, val)
798 #define bfin_write_DMA12_BWL_COUNT(val) bfin_write32(DMA12_BWL_COUNT, val)
800 #define bfin_write_DMA12_CURR_BWL_COUNT(val) bfin_write32(DMA12_CURR_BWL_COUNT, val)
802 #define bfin_write_DMA12_BWM_COUNT(val) bfin_write32(DMA12_BWM_COUNT, val)
804 #define bfin_write_DMA12_CURR_BWM_COUNT(val) bfin_write32(DMA12_CURR_BWM_COUNT, val)
809 #define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_write32(DMA13_NEXT_DESC_PTR, val)
811 #define bfin_write_DMA13_START_ADDR(val) bfin_write32(DMA13_START_ADDR, val)
813 #define bfin_write_DMA13_CONFIG(val) bfin_write32(DMA13_CONFIG, val)
815 #define bfin_write_DMA13_X_COUNT(val) bfin_write32(DMA13_X_COUNT, val)
817 #define bfin_write_DMA13_X_MODIFY(val) bfin_write32(DMA13_X_MODIFY, val)
819 #define bfin_write_DMA13_Y_COUNT(val) bfin_write32(DMA13_Y_COUNT, val)
821 #define bfin_write_DMA13_Y_MODIFY(val) bfin_write32(DMA13_Y_MODIFY, val)
823 #define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_write32(DMA13_CURR_DESC_PTR, val)
825 #define bfin_write_DMA13_PREV_DESC_PTR(val) bfin_write32(DMA13_PREV_DESC_PTR, val)
827 #define bfin_write_DMA13_CURR_ADDR(val) bfin_write32(DMA13_CURR_ADDR, val)
829 #define bfin_write_DMA13_IRQ_STATUS(val) bfin_write32(DMA13_IRQ_STATUS, val)
831 #define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write32(DMA13_CURR_X_COUNT, val)
833 #define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write32(DMA13_CURR_Y_COUNT, val)
835 #define bfin_write_DMA13_BWL_COUNT(val) bfin_write32(DMA13_BWL_COUNT, val)
837 #define bfin_write_DMA13_CURR_BWL_COUNT(val) bfin_write32(DMA13_CURR_BWL_COUNT, val)
839 #define bfin_write_DMA13_BWM_COUNT(val) bfin_write32(DMA13_BWM_COUNT, val)
841 #define bfin_write_DMA13_CURR_BWM_COUNT(val) bfin_write32(DMA13_CURR_BWM_COUNT, val)
846 #define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_write32(DMA14_NEXT_DESC_PTR, val)
848 #define bfin_write_DMA14_START_ADDR(val) bfin_write32(DMA14_START_ADDR, val)
850 #define bfin_write_DMA14_CONFIG(val) bfin_write32(DMA14_CONFIG, val)
852 #define bfin_write_DMA14_X_COUNT(val) bfin_write32(DMA14_X_COUNT, val)
854 #define bfin_write_DMA14_X_MODIFY(val) bfin_write32(DMA14_X_MODIFY, val)
856 #define bfin_write_DMA14_Y_COUNT(val) bfin_write32(DMA14_Y_COUNT, val)
858 #define bfin_write_DMA14_Y_MODIFY(val) bfin_write32(DMA14_Y_MODIFY, val)
860 #define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_write32(DMA14_CURR_DESC_PTR, val)
862 #define bfin_write_DMA14_PREV_DESC_PTR(val) bfin_write32(DMA14_PREV_DESC_PTR, val)
864 #define bfin_write_DMA14_CURR_ADDR(val) bfin_write32(DMA14_CURR_ADDR, val)
866 #define bfin_write_DMA14_IRQ_STATUS(val) bfin_write32(DMA14_IRQ_STATUS, val)
868 #define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write32(DMA14_CURR_X_COUNT, val)
870 #define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write32(DMA14_CURR_Y_COUNT, val)
872 #define bfin_write_DMA14_BWL_COUNT(val) bfin_write32(DMA14_BWL_COUNT, val)
874 #define bfin_write_DMA14_CURR_BWL_COUNT(val) bfin_write32(DMA14_CURR_BWL_COUNT, val)
876 #define bfin_write_DMA14_BWM_COUNT(val) bfin_write32(DMA14_BWM_COUNT, val)
878 #define bfin_write_DMA14_CURR_BWM_COUNT(val) bfin_write32(DMA14_CURR_BWM_COUNT, val)
883 #define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_write32(DMA15_NEXT_DESC_PTR, val)
885 #define bfin_write_DMA15_START_ADDR(val) bfin_write32(DMA15_START_ADDR, val)
887 #define bfin_write_DMA15_CONFIG(val) bfin_write32(DMA15_CONFIG, val)
889 #define bfin_write_DMA15_X_COUNT(val) bfin_write32(DMA15_X_COUNT, val)
891 #define bfin_write_DMA15_X_MODIFY(val) bfin_write32(DMA15_X_MODIFY, val)
893 #define bfin_write_DMA15_Y_COUNT(val) bfin_write32(DMA15_Y_COUNT, val)
895 #define bfin_write_DMA15_Y_MODIFY(val) bfin_write32(DMA15_Y_MODIFY, val)
897 #define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_write32(DMA15_CURR_DESC_PTR, val)
899 #define bfin_write_DMA15_PREV_DESC_PTR(val) bfin_write32(DMA15_PREV_DESC_PTR, val)
901 #define bfin_write_DMA15_CURR_ADDR(val) bfin_write32(DMA15_CURR_ADDR, val)
903 #define bfin_write_DMA15_IRQ_STATUS(val) bfin_write32(DMA15_IRQ_STATUS, val)
905 #define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write32(DMA15_CURR_X_COUNT, val)
907 #define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write32(DMA15_CURR_Y_COUNT, val)
909 #define bfin_write_DMA15_BWL_COUNT(val) bfin_write32(DMA15_BWL_COUNT, val)
911 #define bfin_write_DMA15_CURR_BWL_COUNT(val) bfin_write32(DMA15_CURR_BWL_COUNT, val)
913 #define bfin_write_DMA15_BWM_COUNT(val) bfin_write32(DMA15_BWM_COUNT, val)
915 #define bfin_write_DMA15_CURR_BWM_COUNT(val) bfin_write32(DMA15_CURR_BWM_COUNT, val)
920 #define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_write32(DMA16_NEXT_DESC_PTR, val)
922 #define bfin_write_DMA16_START_ADDR(val) bfin_write32(DMA16_START_ADDR, val)
924 #define bfin_write_DMA16_CONFIG(val) bfin_write32(DMA16_CONFIG, val)
926 #define bfin_write_DMA16_X_COUNT(val) bfin_write32(DMA16_X_COUNT, val)
928 #define bfin_write_DMA16_X_MODIFY(val) bfin_write32(DMA16_X_MODIFY, val)
930 #define bfin_write_DMA16_Y_COUNT(val) bfin_write32(DMA16_Y_COUNT, val)
932 #define bfin_write_DMA16_Y_MODIFY(val) bfin_write32(DMA16_Y_MODIFY, val)
934 #define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_write32(DMA16_CURR_DESC_PTR, val)
936 #define bfin_write_DMA16_PREV_DESC_PTR(val) bfin_write32(DMA16_PREV_DESC_PTR, val)
938 #define bfin_write_DMA16_CURR_ADDR(val) bfin_write32(DMA16_CURR_ADDR, val)
940 #define bfin_write_DMA16_IRQ_STATUS(val) bfin_write32(DMA16_IRQ_STATUS, val)
942 #define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write32(DMA16_CURR_X_COUNT, val)
944 #define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write32(DMA16_CURR_Y_COUNT, val)
946 #define bfin_write_DMA16_BWL_COUNT(val) bfin_write32(DMA16_BWL_COUNT, val)
948 #define bfin_write_DMA16_CURR_BWL_COUNT(val) bfin_write32(DMA16_CURR_BWL_COUNT, val)
950 #define bfin_write_DMA16_BWM_COUNT(val) bfin_write32(DMA16_BWM_COUNT, val)
952 #define bfin_write_DMA16_CURR_BWM_COUNT(val) bfin_write32(DMA16_CURR_BWM_COUNT, val)
957 #define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_write32(DMA17_NEXT_DESC_PTR, val)
959 #define bfin_write_DMA17_START_ADDR(val) bfin_write32(DMA17_START_ADDR, val)
961 #define bfin_write_DMA17_CONFIG(val) bfin_write32(DMA17_CONFIG, val)
963 #define bfin_write_DMA17_X_COUNT(val) bfin_write32(DMA17_X_COUNT, val)
965 #define bfin_write_DMA17_X_MODIFY(val) bfin_write32(DMA17_X_MODIFY, val)
967 #define bfin_write_DMA17_Y_COUNT(val) bfin_write32(DMA17_Y_COUNT, val)
969 #define bfin_write_DMA17_Y_MODIFY(val) bfin_write32(DMA17_Y_MODIFY, val)
971 #define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_write32(DMA17_CURR_DESC_PTR, val)
973 #define bfin_write_DMA17_PREV_DESC_PTR(val) bfin_write32(DMA17_PREV_DESC_PTR, val)
975 #define bfin_write_DMA17_CURR_ADDR(val) bfin_write32(DMA17_CURR_ADDR, val)
977 #define bfin_write_DMA17_IRQ_STATUS(val) bfin_write32(DMA17_IRQ_STATUS, val)
979 #define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write32(DMA17_CURR_X_COUNT, val)
981 #define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write32(DMA17_CURR_Y_COUNT, val)
983 #define bfin_write_DMA17_BWL_COUNT(val) bfin_write32(DMA17_BWL_COUNT, val)
985 #define bfin_write_DMA17_CURR_BWL_COUNT(val) bfin_write32(DMA17_CURR_BWL_COUNT, val)
987 #define bfin_write_DMA17_BWM_COUNT(val) bfin_write32(DMA17_BWM_COUNT, val)
989 #define bfin_write_DMA17_CURR_BWM_COUNT(val) bfin_write32(DMA17_CURR_BWM_COUNT, val)
994 #define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_write32(DMA18_NEXT_DESC_PTR, val)
996 #define bfin_write_DMA18_START_ADDR(val) bfin_write32(DMA18_START_ADDR, val)
998 #define bfin_write_DMA18_CONFIG(val) bfin_write32(DMA18_CONFIG, val)
1000 #define bfin_write_DMA18_X_COUNT(val) bfin_write32(DMA18_X_COUNT, val)
1002 #define bfin_write_DMA18_X_MODIFY(val) bfin_write32(DMA18_X_MODIFY, val)
1004 #define bfin_write_DMA18_Y_COUNT(val) bfin_write32(DMA18_Y_COUNT, val)
1006 #define bfin_write_DMA18_Y_MODIFY(val) bfin_write32(DMA18_Y_MODIFY, val)
1008 #define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_write32(DMA18_CURR_DESC_PTR, val)
1010 #define bfin_write_DMA18_PREV_DESC_PTR(val) bfin_write32(DMA18_PREV_DESC_PTR, val)
1012 #define bfin_write_DMA18_CURR_ADDR(val) bfin_write32(DMA18_CURR_ADDR, val)
1014 #define bfin_write_DMA18_IRQ_STATUS(val) bfin_write32(DMA18_IRQ_STATUS, val)
1016 #define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write32(DMA18_CURR_X_COUNT, val)
1018 #define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write32(DMA18_CURR_Y_COUNT, val)
1020 #define bfin_write_DMA18_BWL_COUNT(val) bfin_write32(DMA18_BWL_COUNT, val)
1022 #define bfin_write_DMA18_CURR_BWL_COUNT(val) bfin_write32(DMA18_CURR_BWL_COUNT, val)
1024 #define bfin_write_DMA18_BWM_COUNT(val) bfin_write32(DMA18_BWM_COUNT, val)
1026 #define bfin_write_DMA18_CURR_BWM_COUNT(val) bfin_write32(DMA18_CURR_BWM_COUNT, val)
1031 #define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_write32(DMA19_NEXT_DESC_PTR, val)
1033 #define bfin_write_DMA19_START_ADDR(val) bfin_write32(DMA19_START_ADDR, val)
1035 #define bfin_write_DMA19_CONFIG(val) bfin_write32(DMA19_CONFIG, val)
1037 #define bfin_write_DMA19_X_COUNT(val) bfin_write32(DMA19_X_COUNT, val)
1039 #define bfin_write_DMA19_X_MODIFY(val) bfin_write32(DMA19_X_MODIFY, val)
1041 #define bfin_write_DMA19_Y_COUNT(val) bfin_write32(DMA19_Y_COUNT, val)
1043 #define bfin_write_DMA19_Y_MODIFY(val) bfin_write32(DMA19_Y_MODIFY, val)
1045 #define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_write32(DMA19_CURR_DESC_PTR, val)
1047 #define bfin_write_DMA19_PREV_DESC_PTR(val) bfin_write32(DMA19_PREV_DESC_PTR, val)
1049 #define bfin_write_DMA19_CURR_ADDR(val) bfin_write32(DMA19_CURR_ADDR, val)
1051 #define bfin_write_DMA19_IRQ_STATUS(val) bfin_write32(DMA19_IRQ_STATUS, val)
1053 #define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write32(DMA19_CURR_X_COUNT, val)
1055 #define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write32(DMA19_CURR_Y_COUNT, val)
1057 #define bfin_write_DMA19_BWL_COUNT(val) bfin_write32(DMA19_BWL_COUNT, val)
1059 #define bfin_write_DMA19_CURR_BWL_COUNT(val) bfin_write32(DMA19_CURR_BWL_COUNT, val)
1061 #define bfin_write_DMA19_BWM_COUNT(val) bfin_write32(DMA19_BWM_COUNT, val)
1063 #define bfin_write_DMA19_CURR_BWM_COUNT(val) bfin_write32(DMA19_CURR_BWM_COUNT, val)
1068 #define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_write32(DMA20_NEXT_DESC_PTR, val)
1070 #define bfin_write_DMA20_START_ADDR(val) bfin_write32(DMA20_START_ADDR, val)
1072 #define bfin_write_DMA20_CONFIG(val) bfin_write32(DMA20_CONFIG, val)
1074 #define bfin_write_DMA20_X_COUNT(val) bfin_write32(DMA20_X_COUNT, val)
1076 #define bfin_write_DMA20_X_MODIFY(val) bfin_write32(DMA20_X_MODIFY, val)
1078 #define bfin_write_DMA20_Y_COUNT(val) bfin_write32(DMA20_Y_COUNT, val)
1080 #define bfin_write_DMA20_Y_MODIFY(val) bfin_write32(DMA20_Y_MODIFY, val)
1082 #define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_write32(DMA20_CURR_DESC_PTR, val)
1084 #define bfin_write_DMA20_PREV_DESC_PTR(val) bfin_write32(DMA20_PREV_DESC_PTR, val)
1086 #define bfin_write_DMA20_CURR_ADDR(val) bfin_write32(DMA20_CURR_ADDR, val)
1088 #define bfin_write_DMA20_IRQ_STATUS(val) bfin_write32(DMA20_IRQ_STATUS, val)
1090 #define bfin_write_DMA20_CURR_X_COUNT(val) bfin_write32(DMA20_CURR_X_COUNT, val)
1092 #define bfin_write_DMA20_CURR_Y_COUNT(val) bfin_write32(DMA20_CURR_Y_COUNT, val)
1094 #define bfin_write_DMA20_BWL_COUNT(val) bfin_write32(DMA20_BWL_COUNT, val)
1096 #define bfin_write_DMA20_CURR_BWL_COUNT(val) bfin_write32(DMA20_CURR_BWL_COUNT, val)
1098 #define bfin_write_DMA20_BWM_COUNT(val) bfin_write32(DMA20_BWM_COUNT, val)
1100 #define bfin_write_DMA20_CURR_BWM_COUNT(val) bfin_write32(DMA20_CURR_BWM_COUNT, val)
1106 #define bfin_write_MDMA0_DEST_CRC0_NEXT_DESC_PTR(val) bfin_write32(MDMA0_DEST_CRC0_NEXT_DESC_PTR, val)
1108 #define bfin_write_MDMA0_DEST_CRC0_START_ADDR(val) bfin_write32(MDMA0_DEST_CRC0_START_ADDR, val)
1110 #define bfin_write_MDMA0_DEST_CRC0_CONFIG(val) bfin_write32(MDMA0_DEST_CRC0_CONFIG, val)
1112 #define bfin_write_MDMA0_DEST_CRC0_X_COUNT(val) bfin_write32(MDMA0_DEST_CRC0_X_COUNT, val)
1114 #define bfin_write_MDMA0_DEST_CRC0_X_MODIFY(val) bfin_write32(MDMA0_DEST_CRC0_X_MODIFY, val)
1116 #define bfin_write_MDMA0_DEST_CRC0_Y_COUNT(val) bfin_write32(MDMA0_DEST_CRC0_Y_COUNT, val)
1118 #define bfin_write_MDMA0_DEST_CRC0_Y_MODIFY(val) bfin_write32(MDMA0_DEST_CRC0_Y_MODIFY, val)
1120 #define bfin_write_MDMA0_DEST_CRC0_CURR_DESC_PTR(val) bfin_write32(MDMA0_DEST_CRC0_CURR_DESC_PTR, val)
1122 #define bfin_write_MDMA0_DEST_CRC0_PREV_DESC_PTR(val) bfin_write32(MDMA0_DEST_CRC0_PREV_DESC_PTR, val)
1124 #define bfin_write_MDMA0_DEST_CRC0_CURR_ADDR(val) bfin_write32(MDMA0_DEST_CRC0_CURR_ADDR, val)
1126 #define bfin_write_MDMA0_DEST_CRC0_IRQ_STATUS(val) bfin_write32(MDMA0_DEST_CRC0_IRQ_STATUS, val)
1128 #define bfin_write_MDMA0_DEST_CRC0_CURR_X_COUNT(val) bfin_write32(MDMA0_DEST_CRC0_CURR_X_COUNT, val)
1130 #define bfin_write_MDMA0_DEST_CRC0_CURR_Y_COUNT(val) bfin_write32(MDMA0_DEST_CRC0_CURR_Y_COUNT, val)
1132 #define bfin_write_MDMA0_SRC_CRC0_NEXT_DESC_PTR(val) bfin_write32(MDMA0_SRC_CRC0_NEXT_DESC_PTR, val)
1134 #define bfin_write_MDMA0_SRC_CRC0_START_ADDR(val) bfin_write32(MDMA0_SRC_CRC0_START_ADDR, val)
1136 #define bfin_write_MDMA0_SRC_CRC0_CONFIG(val) bfin_write32(MDMA0_SRC_CRC0_CONFIG, val)
1138 #define bfin_write_MDMA0_SRC_CRC0_X_COUNT(val) bfin_write32(MDMA0_SRC_CRC0_X_COUNT, val)
1140 #define bfin_write_MDMA0_SRC_CRC0_X_MODIFY(val) bfin_write32(MDMA0_SRC_CRC0_X_MODIFY, val)
1142 #define bfin_write_MDMA0_SRC_CRC0_Y_COUNT(val) bfin_write32(MDMA0_SRC_CRC0_Y_COUNT, val)
1144 #define bfin_write_MDMA0_SRC_CRC0_Y_MODIFY(val) bfin_write32(MDMA0_SRC_CRC0_Y_MODIFY, val)
1146 #define bfin_write_MDMA0_SRC_CRC0_CURR_DESC_PTR(val) bfin_write32(MDMA0_SRC_CRC0_CURR_DESC_PTR, val)
1148 #define bfin_write_MDMA0_SRC_CRC0_PREV_DESC_PTR(val) bfin_write32(MDMA0_SRC_CRC0_PREV_DESC_PTR, val)
1150 #define bfin_write_MDMA0_SRC_CRC0_CURR_ADDR(val) bfin_write32(MDMA0_SRC_CRC0_CURR_ADDR, val)
1152 #define bfin_write_MDMA0_SRC_CRC0_IRQ_STATUS(val) bfin_write32(MDMA0_SRC_CRC0_IRQ_STATUS, val)
1154 #define bfin_write_MDMA0_SRC_CRC0_CURR_X_COUNT(val) bfin_write32(MDMA0_SRC_CRC0_CURR_X_COUNT, val)
1156 #define bfin_write_MDMA0_SRC_CRC0_CURR_Y_COUNT(val) bfin_write32(MDMA0_SRC_CRC0_CURR_Y_COUNT, val)
1161 #define bfin_write_MDMA1_DEST_CRC1_NEXT_DESC_PTR(val) bfin_write32(MDMA1_DEST_CRC1_NEXT_DESC_PTR, val)
1163 #define bfin_write_MDMA1_DEST_CRC1_START_ADDR(val) bfin_write32(MDMA1_DEST_CRC1_START_ADDR, val)
1165 #define bfin_write_MDMA1_DEST_CRC1_CONFIG(val) bfin_write32(MDMA1_DEST_CRC1_CONFIG, val)
1167 #define bfin_write_MDMA1_DEST_CRC1_X_COUNT(val) bfin_write32(MDMA1_DEST_CRC1_X_COUNT, val)
1169 #define bfin_write_MDMA1_DEST_CRC1_X_MODIFY(val) bfin_write32(MDMA1_DEST_CRC1_X_MODIFY, val)
1171 #define bfin_write_MDMA1_DEST_CRC1_Y_COUNT(val) bfin_write32(MDMA1_DEST_CRC1_Y_COUNT, val)
1173 #define bfin_write_MDMA1_DEST_CRC1_Y_MODIFY(val) bfin_write32(MDMA1_DEST_CRC1_Y_MODIFY, val)
1175 #define bfin_write_MDMA1_DEST_CRC1_CURR_DESC_PTR(val) bfin_write32(MDMA1_DEST_CRC1_CURR_DESC_PTR, val)
1177 #define bfin_write_MDMA1_DEST_CRC1_PREV_DESC_PTR(val) bfin_write32(MDMA1_DEST_CRC1_PREV_DESC_PTR, val)
1179 #define bfin_write_MDMA1_DEST_CRC1_CURR_ADDR(val) bfin_write32(MDMA1_DEST_CRC1_CURR_ADDR, val)
1181 #define bfin_write_MDMA1_DEST_CRC1_IRQ_STATUS(val) bfin_write32(MDMA1_DEST_CRC1_IRQ_STATUS, val)
1183 #define bfin_write_MDMA1_DEST_CRC1_CURR_X_COUNT(val) bfin_write32(MDMA1_DEST_CRC1_CURR_X_COUNT, val)
1185 #define bfin_write_MDMA1_DEST_CRC1_CURR_Y_COUNT(val) bfin_write32(MDMA1_DEST_CRC1_CURR_Y_COUNT, val)
1187 #define bfin_write_MDMA1_SRC_CRC1_NEXT_DESC_PTR(val) bfin_write32(MDMA1_SRC_CRC1_NEXT_DESC_PTR, val)
1189 #define bfin_write_MDMA1_SRC_CRC1_START_ADDR(val) bfin_write32(MDMA1_SRC_CRC1_START_ADDR, val)
1191 #define bfin_write_MDMA1_SRC_CRC1_CONFIG(val) bfin_write32(MDMA1_SRC_CRC1_CONFIG, val)
1193 #define bfin_write_MDMA1_SRC_CRC1_X_COUNT(val) bfin_write32(MDMA1_SRC_CRC1_X_COUNT, val)
1195 #define bfin_write_MDMA1_SRC_CRC1_X_MODIFY(val) bfin_write32(MDMA1_SRC_CRC1_X_MODIFY, val)
1197 #define bfin_write_MDMA1_SRC_CRC1_Y_COUNT(val) bfin_write32(MDMA1_SRC_CRC1_Y_COUNT, val)
1199 #define bfin_write_MDMA1_SRC_CRC1_Y_MODIFY(val) bfin_write32(MDMA1_SRC_CRC1_Y_MODIFY, val)
1201 #define bfin_write_MDMA1_SRC_CRC1_CURR_DESC_PTR(val) bfin_write32(MDMA1_SRC_CRC1_CURR_DESC_PTR, val)
1203 #define bfin_write_MDMA1_SRC_CRC1_PREV_DESC_PTR(val) bfin_write32(MDMA1_SRC_CRC1_PREV_DESC_PTR, val)
1205 #define bfin_write_MDMA1_SRC_CRC1_CURR_ADDR(val) bfin_write32(MDMA1_SRC_CRC1_CURR_ADDR, val)
1207 #define bfin_write_MDMA1_SRC_CRC1_IRQ_STATUS(val) bfin_write32(MDMA1_SRC_CRC1_IRQ_STATUS, val)
1209 #define bfin_write_MDMA1_SRC_CRC1_CURR_X_COUNT(val) bfin_write32(MDMA1_SRC_CRC1_CURR_X_COUNT, val)
1211 #define bfin_write_MDMA1_SRC_CRC1_CURR_Y_COUNT(val) bfin_write32(MDMA1_SRC_CRC1_CURR_Y_COUNT, val)
1217 #define bfin_write_MDMA2_DEST_NEXT_DESC_PTR(val) bfin_write32(MDMA2_DEST_NEXT_DESC_PTR, val)
1219 #define bfin_write_MDMA2_DEST_START_ADDR(val) bfin_write32(MDMA2_DEST_START_ADDR, val)
1221 #define bfin_write_MDMA2_DEST_CONFIG(val) bfin_write32(MDMA2_DEST_CONFIG, val)
1223 #define bfin_write_MDMA2_DEST_X_COUNT(val) bfin_write32(MDMA2_DEST_X_COUNT, val)
1225 #define bfin_write_MDMA2_DEST_X_MODIFY(val) bfin_write32(MDMA2_DEST_X_MODIFY, val)
1227 #define bfin_write_MDMA2_DEST_Y_COUNT(val) bfin_write32(MDMA2_DEST_Y_COUNT, val)
1229 #define bfin_write_MDMA2_DEST_Y_MODIFY(val) bfin_write32(MDMA2_DEST_Y_MODIFY, val)
1231 #define bfin_write_MDMA2_DEST_CURR_DESC_PTR(val) bfin_write32(MDMA2_DEST_CURR_DESC_PTR, val)
1233 #define bfin_write_MDMA2_DEST_PREV_DESC_PTR(val) bfin_write32(MDMA2_DEST_PREV_DESC_PTR, val)
1235 #define bfin_write_MDMA2_DEST_CURR_ADDR(val) bfin_write32(MDMA2_DEST_CURR_ADDR, val)
1237 #define bfin_write_MDMA2_DEST_IRQ_STATUS(val) bfin_write32(MDMA2_DEST_IRQ_STATUS, val)
1239 #define bfin_write_MDMA2_DEST_CURR_X_COUNT(val) bfin_write32(MDMA2_DEST_CURR_X_COUNT, val)
1241 #define bfin_write_MDMA2_DEST_CURR_Y_COUNT(val) bfin_write32(MDMA2_DEST_CURR_Y_COUNT, val)
1243 #define bfin_write_MDMA2_SRC_NEXT_DESC_PTR(val) bfin_write32(MDMA2_SRC_NEXT_DESC_PTR, val)
1245 #define bfin_write_MDMA2_SRC_START_ADDR(val) bfin_write32(MDMA2_SRC_START_ADDR, val)
1247 #define bfin_write_MDMA2_SRC_CONFIG(val) bfin_write32(MDMA2_SRC_CONFIG, val)
1249 #define bfin_write_MDMA2_SRC_X_COUNT(val) bfin_write32(MDMA2_SRC_X_COUNT, val)
1251 #define bfin_write_MDMA2_SRC_X_MODIFY(val) bfin_write32(MDMA2_SRC_X_MODIFY, val)
1253 #define bfin_write_MDMA2_SRC_Y_COUNT(val) bfin_write32(MDMA2_SRC_Y_COUNT, val)
1255 #define bfin_write_MDMA2_SRC_Y_MODIFY(val) bfin_write32(MDMA2_SRC_Y_MODIFY, val)
1257 #define bfin_write_MDMA2_SRC_CURR_DESC_PTR(val) bfin_write32(MDMA2_SRC_CURR_DESC_PTR, val)
1259 #define bfin_write_MDMA2_SRC_PREV_DESC_PTR(val) bfin_write32(MDMA2_SRC_PREV_DESC_PTR, val)
1261 #define bfin_write_MDMA2_SRC_CURR_ADDR(val) bfin_write32(MDMA2_SRC_CURR_ADDR, val)
1263 #define bfin_write_MDMA2_SRC_IRQ_STATUS(val) bfin_write32(MDMA2_SRC_IRQ_STATUS, val)
1265 #define bfin_write_MDMA2_SRC_CURR_X_COUNT(val) bfin_write32(MDMA2_SRC_CURR_X_COUNT, val)
1267 #define bfin_write_MDMA2_SRC_CURR_Y_COUNT(val) bfin_write32(MDMA2_SRC_CURR_Y_COUNT, val)
1272 #define bfin_write_MDMA3_DEST_NEXT_DESC_PTR(val) bfin_write32(MDMA3_DEST_NEXT_DESC_PTR, val)
1274 #define bfin_write_MDMA3_DEST_START_ADDR(val) bfin_write32(MDMA3_DEST_START_ADDR, val)
1276 #define bfin_write_MDMA3_DEST_CONFIG(val) bfin_write32(MDMA3_DEST_CONFIG, val)
1278 #define bfin_write_MDMA3_DEST_X_COUNT(val) bfin_write32(MDMA3_DEST_X_COUNT, val)
1280 #define bfin_write_MDMA3_DEST_X_MODIFY(val) bfin_write32(MDMA3_DEST_X_MODIFY, val)
1282 #define bfin_write_MDMA3_DEST_Y_COUNT(val) bfin_write32(MDMA3_DEST_Y_COUNT, val)
1284 #define bfin_write_MDMA3_DEST_Y_MODIFY(val) bfin_write32(MDMA3_DEST_Y_MODIFY, val)
1286 #define bfin_write_MDMA3_DEST_CURR_DESC_PTR(val) bfin_write32(MDMA3_DEST_CURR_DESC_PTR, val)
1288 #define bfin_write_MDMA3_DEST_PREV_DESC_PTR(val) bfin_write32(MDMA3_DEST_PREV_DESC_PTR, val)
1290 #define bfin_write_MDMA3_DEST_CURR_ADDR(val) bfin_write32(MDMA3_DEST_CURR_ADDR, val)
1292 #define bfin_write_MDMA3_DEST_IRQ_STATUS(val) bfin_write32(MDMA3_DEST_IRQ_STATUS, val)
1294 #define bfin_write_MDMA3_DEST_CURR_X_COUNT(val) bfin_write32(MDMA3_DEST_CURR_X_COUNT, val)
1296 #define bfin_write_MDMA3_DEST_CURR_Y_COUNT(val) bfin_write32(MDMA3_DEST_CURR_Y_COUNT, val)
1298 #define bfin_write_MDMA3_SRC_NEXT_DESC_PTR(val) bfin_write32(MDMA3_SRC_NEXT_DESC_PTR, val)
1300 #define bfin_write_MDMA3_SRC_START_ADDR(val) bfin_write32(MDMA3_SRC_START_ADDR, val)
1302 #define bfin_write_MDMA3_SRC_CONFIG(val) bfin_write32(MDMA3_SRC_CONFIG, val)
1304 #define bfin_write_MDMA3_SRC_X_COUNT(val) bfin_write32(MDMA3_SRC_X_COUNT, val)
1306 #define bfin_write_MDMA3_SRC_X_MODIFY(val) bfin_write32(MDMA3_SRC_X_MODIFY, val)
1308 #define bfin_write_MDMA3_SRC_Y_COUNT(val) bfin_write32(MDMA3_SRC_Y_COUNT, val)
1310 #define bfin_write_MDMA3_SRC_Y_MODIFY(val) bfin_write32(MDMA3_SRC_Y_MODIFY, val)
1312 #define bfin_write_MDMA3_SRC_CURR_DESC_PTR(val) bfin_write32(MDMA3_SRC_CURR_DESC_PTR, val)
1314 #define bfin_write_MDMA3_SRC_PREV_DESC_PTR(val) bfin_write32(MDMA3_SRC_PREV_DESC_PTR, val)
1316 #define bfin_write_MDMA3_SRC_CURR_ADDR(val) bfin_write32(MDMA3_SRC_CURR_ADDR, val)
1318 #define bfin_write_MDMA3_SRC_IRQ_STATUS(val) bfin_write32(MDMA3_SRC_IRQ_STATUS, val)
1320 #define bfin_write_MDMA3_SRC_CURR_X_COUNT(val) bfin_write32(MDMA3_SRC_CURR_X_COUNT, val)
1322 #define bfin_write_MDMA3_SRC_CURR_Y_COUNT(val) bfin_write32(MDMA3_SRC_CURR_Y_COUNT, val)
1328 #define bfin_write_DMA29_NEXT_DESC_PTR(val) bfin_write32(DMA29_NEXT_DESC_PTR, val)
1330 #define bfin_write_DMA29_START_ADDR(val) bfin_write32(DMA29_START_ADDR, val)
1332 #define bfin_write_DMA29_CONFIG(val) bfin_write32(DMA29_CONFIG, val)
1334 #define bfin_write_DMA29_X_COUNT(val) bfin_write32(DMA29_X_COUNT, val)
1336 #define bfin_write_DMA29_X_MODIFY(val) bfin_write32(DMA29_X_MODIFY, val)
1338 #define bfin_write_DMA29_Y_COUNT(val) bfin_write32(DMA29_Y_COUNT, val)
1340 #define bfin_write_DMA29_Y_MODIFY(val) bfin_write32(DMA29_Y_MODIFY, val)
1342 #define bfin_write_DMA29_CURR_DESC_PTR(val) bfin_write32(DMA29_CURR_DESC_PTR, val)
1344 #define bfin_write_DMA29_PREV_DESC_PTR(val) bfin_write32(DMA29_PREV_DESC_PTR, val)
1346 #define bfin_write_DMA29_CURR_ADDR(val) bfin_write32(DMA29_CURR_ADDR, val)
1348 #define bfin_write_DMA29_IRQ_STATUS(val) bfin_write32(DMA29_IRQ_STATUS, val)
1350 #define bfin_write_DMA29_CURR_X_COUNT(val) bfin_write32(DMA29_CURR_X_COUNT, val)
1352 #define bfin_write_DMA29_CURR_Y_COUNT(val) bfin_write32(DMA29_CURR_Y_COUNT, val)
1354 #define bfin_write_DMA29_BWL_COUNT(val) bfin_write32(DMA29_BWL_COUNT, val)
1356 #define bfin_write_DMA29_CURR_BWL_COUNT(val) bfin_write32(DMA29_CURR_BWL_COUNT, val)
1358 #define bfin_write_DMA29_BWM_COUNT(val) bfin_write32(DMA29_BWM_COUNT, val)
1360 #define bfin_write_DMA29_CURR_BWM_COUNT(val) bfin_write32(DMA29_CURR_BWM_COUNT, val)
1365 #define bfin_write_DMA30_NEXT_DESC_PTR(val) bfin_write32(DMA30_NEXT_DESC_PTR, val)
1367 #define bfin_write_DMA30_START_ADDR(val) bfin_write32(DMA30_START_ADDR, val)
1369 #define bfin_write_DMA30_CONFIG(val) bfin_write32(DMA30_CONFIG, val)
1371 #define bfin_write_DMA30_X_COUNT(val) bfin_write32(DMA30_X_COUNT, val)
1373 #define bfin_write_DMA30_X_MODIFY(val) bfin_write32(DMA30_X_MODIFY, val)
1375 #define bfin_write_DMA30_Y_COUNT(val) bfin_write32(DMA30_Y_COUNT, val)
1377 #define bfin_write_DMA30_Y_MODIFY(val) bfin_write32(DMA30_Y_MODIFY, val)
1379 #define bfin_write_DMA30_CURR_DESC_PTR(val) bfin_write32(DMA30_CURR_DESC_PTR, val)
1381 #define bfin_write_DMA30_PREV_DESC_PTR(val) bfin_write32(DMA30_PREV_DESC_PTR, val)
1383 #define bfin_write_DMA30_CURR_ADDR(val) bfin_write32(DMA30_CURR_ADDR, val)
1385 #define bfin_write_DMA30_IRQ_STATUS(val) bfin_write32(DMA30_IRQ_STATUS, val)
1387 #define bfin_write_DMA30_CURR_X_COUNT(val) bfin_write32(DMA30_CURR_X_COUNT, val)
1389 #define bfin_write_DMA30_CURR_Y_COUNT(val) bfin_write32(DMA30_CURR_Y_COUNT, val)
1391 #define bfin_write_DMA30_BWL_COUNT(val) bfin_write32(DMA30_BWL_COUNT, val)
1393 #define bfin_write_DMA30_CURR_BWL_COUNT(val) bfin_write32(DMA30_CURR_BWL_COUNT, val)
1395 #define bfin_write_DMA30_BWM_COUNT(val) bfin_write32(DMA30_BWM_COUNT, val)
1397 #define bfin_write_DMA30_CURR_BWM_COUNT(val) bfin_write32(DMA30_CURR_BWM_COUNT, val)
1402 #define bfin_write_DMA31_NEXT_DESC_PTR(val) bfin_write32(DMA31_NEXT_DESC_PTR, val)
1404 #define bfin_write_DMA31_START_ADDR(val) bfin_write32(DMA31_START_ADDR, val)
1406 #define bfin_write_DMA31_CONFIG(val) bfin_write32(DMA31_CONFIG, val)
1408 #define bfin_write_DMA31_X_COUNT(val) bfin_write32(DMA31_X_COUNT, val)
1410 #define bfin_write_DMA31_X_MODIFY(val) bfin_write32(DMA31_X_MODIFY, val)
1412 #define bfin_write_DMA31_Y_COUNT(val) bfin_write32(DMA31_Y_COUNT, val)
1414 #define bfin_write_DMA31_Y_MODIFY(val) bfin_write32(DMA31_Y_MODIFY, val)
1416 #define bfin_write_DMA31_CURR_DESC_PTR(val) bfin_write32(DMA31_CURR_DESC_PTR, val)
1418 #define bfin_write_DMA31_PREV_DESC_PTR(val) bfin_write32(DMA31_PREV_DESC_PTR, val)
1420 #define bfin_write_DMA31_CURR_ADDR(val) bfin_write32(DMA31_CURR_ADDR, val)
1422 #define bfin_write_DMA31_IRQ_STATUS(val) bfin_write32(DMA31_IRQ_STATUS, val)
1424 #define bfin_write_DMA31_CURR_X_COUNT(val) bfin_write32(DMA31_CURR_X_COUNT, val)
1426 #define bfin_write_DMA31_CURR_Y_COUNT(val) bfin_write32(DMA31_CURR_Y_COUNT, val)
1428 #define bfin_write_DMA31_BWL_COUNT(val) bfin_write32(DMA31_BWL_COUNT, val)
1430 #define bfin_write_DMA31_CURR_BWL_COUNT(val) bfin_write32(DMA31_CURR_BWL_COUNT, val)
1432 #define bfin_write_DMA31_BWM_COUNT(val) bfin_write32(DMA31_BWM_COUNT, val)
1434 #define bfin_write_DMA31_CURR_BWM_COUNT(val) bfin_write32(DMA31_CURR_BWM_COUNT, val)
1439 #define bfin_write_DMA32_NEXT_DESC_PTR(val) bfin_write32(DMA32_NEXT_DESC_PTR, val)
1441 #define bfin_write_DMA32_START_ADDR(val) bfin_write32(DMA32_START_ADDR, val)
1443 #define bfin_write_DMA32_CONFIG(val) bfin_write32(DMA32_CONFIG, val)
1445 #define bfin_write_DMA32_X_COUNT(val) bfin_write32(DMA32_X_COUNT, val)
1447 #define bfin_write_DMA32_X_MODIFY(val) bfin_write32(DMA32_X_MODIFY, val)
1449 #define bfin_write_DMA32_Y_COUNT(val) bfin_write32(DMA32_Y_COUNT, val)
1451 #define bfin_write_DMA32_Y_MODIFY(val) bfin_write32(DMA32_Y_MODIFY, val)
1453 #define bfin_write_DMA32_CURR_DESC_PTR(val) bfin_write32(DMA32_CURR_DESC_PTR, val)
1455 #define bfin_write_DMA32_PREV_DESC_PTR(val) bfin_write32(DMA32_PREV_DESC_PTR, val)
1457 #define bfin_write_DMA32_CURR_ADDR(val) bfin_write32(DMA32_CURR_ADDR, val)
1459 #define bfin_write_DMA32_IRQ_STATUS(val) bfin_write32(DMA32_IRQ_STATUS, val)
1461 #define bfin_write_DMA32_CURR_X_COUNT(val) bfin_write32(DMA32_CURR_X_COUNT, val)
1463 #define bfin_write_DMA32_CURR_Y_COUNT(val) bfin_write32(DMA32_CURR_Y_COUNT, val)
1465 #define bfin_write_DMA32_BWL_COUNT(val) bfin_write32(DMA32_BWL_COUNT, val)
1467 #define bfin_write_DMA32_CURR_BWL_COUNT(val) bfin_write32(DMA32_CURR_BWL_COUNT, val)
1469 #define bfin_write_DMA32_BWM_COUNT(val) bfin_write32(DMA32_BWM_COUNT, val)
1471 #define bfin_write_DMA32_CURR_BWM_COUNT(val) bfin_write32(DMA32_CURR_BWM_COUNT, val)
1476 #define bfin_write_DMA33_NEXT_DESC_PTR(val) bfin_write32(DMA33_NEXT_DESC_PTR, val)
1478 #define bfin_write_DMA33_START_ADDR(val) bfin_write32(DMA33_START_ADDR, val)
1480 #define bfin_write_DMA33_CONFIG(val) bfin_write32(DMA33_CONFIG, val)
1482 #define bfin_write_DMA33_X_COUNT(val) bfin_write32(DMA33_X_COUNT, val)
1484 #define bfin_write_DMA33_X_MODIFY(val) bfin_write32(DMA33_X_MODIFY, val)
1486 #define bfin_write_DMA33_Y_COUNT(val) bfin_write32(DMA33_Y_COUNT, val)
1488 #define bfin_write_DMA33_Y_MODIFY(val) bfin_write32(DMA33_Y_MODIFY, val)
1490 #define bfin_write_DMA33_CURR_DESC_PTR(val) bfin_write32(DMA33_CURR_DESC_PTR, val)
1492 #define bfin_write_DMA33_PREV_DESC_PTR(val) bfin_write32(DMA33_PREV_DESC_PTR, val)
1494 #define bfin_write_DMA33_CURR_ADDR(val) bfin_write32(DMA33_CURR_ADDR, val)
1496 #define bfin_write_DMA33_IRQ_STATUS(val) bfin_write32(DMA33_IRQ_STATUS, val)
1498 #define bfin_write_DMA33_CURR_X_COUNT(val) bfin_write32(DMA33_CURR_X_COUNT, val)
1500 #define bfin_write_DMA33_CURR_Y_COUNT(val) bfin_write32(DMA33_CURR_Y_COUNT, val)
1502 #define bfin_write_DMA33_BWL_COUNT(val) bfin_write32(DMA33_BWL_COUNT, val)
1504 #define bfin_write_DMA33_CURR_BWL_COUNT(val) bfin_write32(DMA33_CURR_BWL_COUNT, val)
1506 #define bfin_write_DMA33_BWM_COUNT(val) bfin_write32(DMA33_BWM_COUNT, val)
1508 #define bfin_write_DMA33_CURR_BWM_COUNT(val) bfin_write32(DMA33_CURR_BWM_COUNT, val)
1513 #define bfin_write_DMA34_NEXT_DESC_PTR(val) bfin_write32(DMA34_NEXT_DESC_PTR, val)
1515 #define bfin_write_DMA34_START_ADDR(val) bfin_write32(DMA34_START_ADDR, val)
1517 #define bfin_write_DMA34_CONFIG(val) bfin_write32(DMA34_CONFIG, val)
1519 #define bfin_write_DMA34_X_COUNT(val) bfin_write32(DMA34_X_COUNT, val)
1521 #define bfin_write_DMA34_X_MODIFY(val) bfin_write32(DMA34_X_MODIFY, val)
1523 #define bfin_write_DMA34_Y_COUNT(val) bfin_write32(DMA34_Y_COUNT, val)
1525 #define bfin_write_DMA34_Y_MODIFY(val) bfin_write32(DMA34_Y_MODIFY, val)
1527 #define bfin_write_DMA34_CURR_DESC_PTR(val) bfin_write32(DMA34_CURR_DESC_PTR, val)
1529 #define bfin_write_DMA34_PREV_DESC_PTR(val) bfin_write32(DMA34_PREV_DESC_PTR, val)
1531 #define bfin_write_DMA34_CURR_ADDR(val) bfin_write32(DMA34_CURR_ADDR, val)
1533 #define bfin_write_DMA34_IRQ_STATUS(val) bfin_write32(DMA34_IRQ_STATUS, val)
1535 #define bfin_write_DMA34_CURR_X_COUNT(val) bfin_write32(DMA34_CURR_X_COUNT, val)
1537 #define bfin_write_DMA34_CURR_Y_COUNT(val) bfin_write32(DMA34_CURR_Y_COUNT, val)
1539 #define bfin_write_DMA34_BWL_COUNT(val) bfin_write32(DMA34_BWL_COUNT, val)
1541 #define bfin_write_DMA34_CURR_BWL_COUNT(val) bfin_write32(DMA34_CURR_BWL_COUNT, val)
1543 #define bfin_write_DMA34_BWM_COUNT(val) bfin_write32(DMA34_BWM_COUNT, val)
1545 #define bfin_write_DMA34_CURR_BWM_COUNT(val) bfin_write32(DMA34_CURR_BWM_COUNT, val)
1550 #define bfin_write_DMA35_NEXT_DESC_PTR(val) bfin_write32(DMA35_NEXT_DESC_PTR, val)
1552 #define bfin_write_DMA35_START_ADDR(val) bfin_write32(DMA35_START_ADDR, val)
1554 #define bfin_write_DMA35_CONFIG(val) bfin_write32(DMA35_CONFIG, val)
1556 #define bfin_write_DMA35_X_COUNT(val) bfin_write32(DMA35_X_COUNT, val)
1558 #define bfin_write_DMA35_X_MODIFY(val) bfin_write32(DMA35_X_MODIFY, val)
1560 #define bfin_write_DMA35_Y_COUNT(val) bfin_write32(DMA35_Y_COUNT, val)
1562 #define bfin_write_DMA35_Y_MODIFY(val) bfin_write32(DMA35_Y_MODIFY, val)
1564 #define bfin_write_DMA35_CURR_DESC_PTR(val) bfin_write32(DMA35_CURR_DESC_PTR, val)
1566 #define bfin_write_DMA35_PREV_DESC_PTR(val) bfin_write32(DMA35_PREV_DESC_PTR, val)
1568 #define bfin_write_DMA35_CURR_ADDR(val) bfin_write32(DMA35_CURR_ADDR, val)
1570 #define bfin_write_DMA35_IRQ_STATUS(val) bfin_write32(DMA35_IRQ_STATUS, val)
1572 #define bfin_write_DMA35_CURR_X_COUNT(val) bfin_write32(DMA35_CURR_X_COUNT, val)
1574 #define bfin_write_DMA35_CURR_Y_COUNT(val) bfin_write32(DMA35_CURR_Y_COUNT, val)
1576 #define bfin_write_DMA35_BWL_COUNT(val) bfin_write32(DMA35_BWL_COUNT, val)
1578 #define bfin_write_DMA35_CURR_BWL_COUNT(val) bfin_write32(DMA35_CURR_BWL_COUNT, val)
1580 #define bfin_write_DMA35_BWM_COUNT(val) bfin_write32(DMA35_BWM_COUNT, val)
1582 #define bfin_write_DMA35_CURR_BWM_COUNT(val) bfin_write32(DMA35_CURR_BWM_COUNT, val)
1587 #define bfin_write_DMA36_NEXT_DESC_PTR(val) bfin_write32(DMA36_NEXT_DESC_PTR, val)
1589 #define bfin_write_DMA36_START_ADDR(val) bfin_write32(DMA36_START_ADDR, val)
1591 #define bfin_write_DMA36_CONFIG(val) bfin_write32(DMA36_CONFIG, val)
1593 #define bfin_write_DMA36_X_COUNT(val) bfin_write32(DMA36_X_COUNT, val)
1595 #define bfin_write_DMA36_X_MODIFY(val) bfin_write32(DMA36_X_MODIFY, val)
1597 #define bfin_write_DMA36_Y_COUNT(val) bfin_write32(DMA36_Y_COUNT, val)
1599 #define bfin_write_DMA36_Y_MODIFY(val) bfin_write32(DMA36_Y_MODIFY, val)
1601 #define bfin_write_DMA36_CURR_DESC_PTR(val) bfin_write32(DMA36_CURR_DESC_PTR, val)
1603 #define bfin_write_DMA36_PREV_DESC_PTR(val) bfin_write32(DMA36_PREV_DESC_PTR, val)
1605 #define bfin_write_DMA36_CURR_ADDR(val) bfin_write32(DMA36_CURR_ADDR, val)
1607 #define bfin_write_DMA36_IRQ_STATUS(val) bfin_write32(DMA36_IRQ_STATUS, val)
1609 #define bfin_write_DMA36_CURR_X_COUNT(val) bfin_write32(DMA36_CURR_X_COUNT, val)
1611 #define bfin_write_DMA36_CURR_Y_COUNT(val) bfin_write32(DMA36_CURR_Y_COUNT, val)
1613 #define bfin_write_DMA36_BWL_COUNT(val) bfin_write32(DMA36_BWL_COUNT, val)
1615 #define bfin_write_DMA36_CURR_BWL_COUNT(val) bfin_write32(DMA36_CURR_BWL_COUNT, val)
1617 #define bfin_write_DMA36_BWM_COUNT(val) bfin_write32(DMA36_BWM_COUNT, val)
1619 #define bfin_write_DMA36_CURR_BWM_COUNT(val) bfin_write32(DMA36_CURR_BWM_COUNT, val)
1624 #define bfin_write_DMA37_NEXT_DESC_PTR(val) bfin_write32(DMA37_NEXT_DESC_PTR, val)
1626 #define bfin_write_DMA37_START_ADDR(val) bfin_write32(DMA37_START_ADDR, val)
1628 #define bfin_write_DMA37_CONFIG(val) bfin_write32(DMA37_CONFIG, val)
1630 #define bfin_write_DMA37_X_COUNT(val) bfin_write32(DMA37_X_COUNT, val)
1632 #define bfin_write_DMA37_X_MODIFY(val) bfin_write32(DMA37_X_MODIFY, val)
1634 #define bfin_write_DMA37_Y_COUNT(val) bfin_write32(DMA37_Y_COUNT, val)
1636 #define bfin_write_DMA37_Y_MODIFY(val) bfin_write32(DMA37_Y_MODIFY, val)
1638 #define bfin_write_DMA37_CURR_DESC_PTR(val) bfin_write32(DMA37_CURR_DESC_PTR, val)
1640 #define bfin_write_DMA37_PREV_DESC_PTR(val) bfin_write32(DMA37_PREV_DESC_PTR, val)
1642 #define bfin_write_DMA37_CURR_ADDR(val) bfin_write32(DMA37_CURR_ADDR, val)
1644 #define bfin_write_DMA37_IRQ_STATUS(val) bfin_write32(DMA37_IRQ_STATUS, val)
1646 #define bfin_write_DMA37_CURR_X_COUNT(val) bfin_write32(DMA37_CURR_X_COUNT, val)
1648 #define bfin_write_DMA37_CURR_Y_COUNT(val) bfin_write32(DMA37_CURR_Y_COUNT, val)
1650 #define bfin_write_DMA37_BWL_COUNT(val) bfin_write32(DMA37_BWL_COUNT, val)
1652 #define bfin_write_DMA37_CURR_BWL_COUNT(val) bfin_write32(DMA37_CURR_BWL_COUNT, val)
1654 #define bfin_write_DMA37_BWM_COUNT(val) bfin_write32(DMA37_BWM_COUNT, val)
1656 #define bfin_write_DMA37_CURR_BWM_COUNT(val) bfin_write32(DMA37_CURR_BWM_COUNT, val)
1661 #define bfin_write_DMA38_NEXT_DESC_PTR(val) bfin_write32(DMA38_NEXT_DESC_PTR, val)
1663 #define bfin_write_DMA38_START_ADDR(val) bfin_write32(DMA38_START_ADDR, val)
1665 #define bfin_write_DMA38_CONFIG(val) bfin_write32(DMA38_CONFIG, val)
1667 #define bfin_write_DMA38_X_COUNT(val) bfin_write32(DMA38_X_COUNT, val)
1669 #define bfin_write_DMA38_X_MODIFY(val) bfin_write32(DMA38_X_MODIFY, val)
1671 #define bfin_write_DMA38_Y_COUNT(val) bfin_write32(DMA38_Y_COUNT, val)
1673 #define bfin_write_DMA38_Y_MODIFY(val) bfin_write32(DMA38_Y_MODIFY, val)
1675 #define bfin_write_DMA38_CURR_DESC_PTR(val) bfin_write32(DMA38_CURR_DESC_PTR, val)
1677 #define bfin_write_DMA38_PREV_DESC_PTR(val) bfin_write32(DMA38_PREV_DESC_PTR, val)
1679 #define bfin_write_DMA38_CURR_ADDR(val) bfin_write32(DMA38_CURR_ADDR, val)
1681 #define bfin_write_DMA38_IRQ_STATUS(val) bfin_write32(DMA38_IRQ_STATUS, val)
1683 #define bfin_write_DMA38_CURR_X_COUNT(val) bfin_write32(DMA38_CURR_X_COUNT, val)
1685 #define bfin_write_DMA38_CURR_Y_COUNT(val) bfin_write32(DMA38_CURR_Y_COUNT, val)
1687 #define bfin_write_DMA38_BWL_COUNT(val) bfin_write32(DMA38_BWL_COUNT, val)
1689 #define bfin_write_DMA38_CURR_BWL_COUNT(val) bfin_write32(DMA38_CURR_BWL_COUNT, val)
1691 #define bfin_write_DMA38_BWM_COUNT(val) bfin_write32(DMA38_BWM_COUNT, val)
1693 #define bfin_write_DMA38_CURR_BWM_COUNT(val) bfin_write32(DMA38_CURR_BWM_COUNT, val)
1698 #define bfin_write_DMA39_NEXT_DESC_PTR(val) bfin_write32(DMA39_NEXT_DESC_PTR, val)
1700 #define bfin_write_DMA39_START_ADDR(val) bfin_write32(DMA39_START_ADDR, val)
1702 #define bfin_write_DMA39_CONFIG(val) bfin_write32(DMA39_CONFIG, val)
1704 #define bfin_write_DMA39_X_COUNT(val) bfin_write32(DMA39_X_COUNT, val)
1706 #define bfin_write_DMA39_X_MODIFY(val) bfin_write32(DMA39_X_MODIFY, val)
1708 #define bfin_write_DMA39_Y_COUNT(val) bfin_write32(DMA39_Y_COUNT, val)
1710 #define bfin_write_DMA39_Y_MODIFY(val) bfin_write32(DMA39_Y_MODIFY, val)
1712 #define bfin_write_DMA39_CURR_DESC_PTR(val) bfin_write32(DMA39_CURR_DESC_PTR, val)
1714 #define bfin_write_DMA39_PREV_DESC_PTR(val) bfin_write32(DMA39_PREV_DESC_PTR, val)
1716 #define bfin_write_DMA39_CURR_ADDR(val) bfin_write32(DMA39_CURR_ADDR, val)
1718 #define bfin_write_DMA39_IRQ_STATUS(val) bfin_write32(DMA39_IRQ_STATUS, val)
1720 #define bfin_write_DMA39_CURR_X_COUNT(val) bfin_write32(DMA39_CURR_X_COUNT, val)
1722 #define bfin_write_DMA39_CURR_Y_COUNT(val) bfin_write32(DMA39_CURR_Y_COUNT, val)
1724 #define bfin_write_DMA39_BWL_COUNT(val) bfin_write32(DMA39_BWL_COUNT, val)
1726 #define bfin_write_DMA39_CURR_BWL_COUNT(val) bfin_write32(DMA39_CURR_BWL_COUNT, val)
1728 #define bfin_write_DMA39_BWM_COUNT(val) bfin_write32(DMA39_BWM_COUNT, val)
1730 #define bfin_write_DMA39_CURR_BWM_COUNT(val) bfin_write32(DMA39_CURR_BWM_COUNT, val)
1735 #define bfin_write_DMA40_NEXT_DESC_PTR(val) bfin_write32(DMA40_NEXT_DESC_PTR, val)
1737 #define bfin_write_DMA40_START_ADDR(val) bfin_write32(DMA40_START_ADDR, val)
1739 #define bfin_write_DMA40_CONFIG(val) bfin_write32(DMA40_CONFIG, val)
1741 #define bfin_write_DMA40_X_COUNT(val) bfin_write32(DMA40_X_COUNT, val)
1743 #define bfin_write_DMA40_X_MODIFY(val) bfin_write32(DMA40_X_MODIFY, val)
1745 #define bfin_write_DMA40_Y_COUNT(val) bfin_write32(DMA40_Y_COUNT, val)
1747 #define bfin_write_DMA40_Y_MODIFY(val) bfin_write32(DMA40_Y_MODIFY, val)
1749 #define bfin_write_DMA40_CURR_DESC_PTR(val) bfin_write32(DMA40_CURR_DESC_PTR, val)
1751 #define bfin_write_DMA40_PREV_DESC_PTR(val) bfin_write32(DMA40_PREV_DESC_PTR, val)
1753 #define bfin_write_DMA40_CURR_ADDR(val) bfin_write32(DMA40_CURR_ADDR, val)
1755 #define bfin_write_DMA40_IRQ_STATUS(val) bfin_write32(DMA40_IRQ_STATUS, val)
1757 #define bfin_write_DMA40_CURR_X_COUNT(val) bfin_write32(DMA40_CURR_X_COUNT, val)
1759 #define bfin_write_DMA40_CURR_Y_COUNT(val) bfin_write32(DMA40_CURR_Y_COUNT, val)
1761 #define bfin_write_DMA40_BWL_COUNT(val) bfin_write32(DMA40_BWL_COUNT, val)
1763 #define bfin_write_DMA40_CURR_BWL_COUNT(val) bfin_write32(DMA40_CURR_BWL_COUNT, val)
1765 #define bfin_write_DMA40_BWM_COUNT(val) bfin_write32(DMA40_BWM_COUNT, val)
1767 #define bfin_write_DMA40_CURR_BWM_COUNT(val) bfin_write32(DMA40_CURR_BWM_COUNT, val)
1772 #define bfin_write_DMA41_NEXT_DESC_PTR(val) bfin_write32(DMA41_NEXT_DESC_PTR, val)
1774 #define bfin_write_DMA41_START_ADDR(val) bfin_write32(DMA41_START_ADDR, val)
1776 #define bfin_write_DMA41_CONFIG(val) bfin_write32(DMA41_CONFIG, val)
1778 #define bfin_write_DMA41_X_COUNT(val) bfin_write32(DMA41_X_COUNT, val)
1780 #define bfin_write_DMA41_X_MODIFY(val) bfin_write32(DMA41_X_MODIFY, val)
1782 #define bfin_write_DMA41_Y_COUNT(val) bfin_write32(DMA41_Y_COUNT, val)
1784 #define bfin_write_DMA41_Y_MODIFY(val) bfin_write32(DMA41_Y_MODIFY, val)
1786 #define bfin_write_DMA41_CURR_DESC_PTR(val) bfin_write32(DMA41_CURR_DESC_PTR, val)
1788 #define bfin_write_DMA41_PREV_DESC_PTR(val) bfin_write32(DMA41_PREV_DESC_PTR, val)
1790 #define bfin_write_DMA41_CURR_ADDR(val) bfin_write32(DMA41_CURR_ADDR, val)
1792 #define bfin_write_DMA41_IRQ_STATUS(val) bfin_write32(DMA41_IRQ_STATUS, val)
1794 #define bfin_write_DMA41_CURR_X_COUNT(val) bfin_write32(DMA41_CURR_X_COUNT, val)
1796 #define bfin_write_DMA41_CURR_Y_COUNT(val) bfin_write32(DMA41_CURR_Y_COUNT, val)
1798 #define bfin_write_DMA41_BWL_COUNT(val) bfin_write32(DMA41_BWL_COUNT, val)
1800 #define bfin_write_DMA41_CURR_BWL_COUNT(val) bfin_write32(DMA41_CURR_BWL_COUNT, val)
1802 #define bfin_write_DMA41_BWM_COUNT(val) bfin_write32(DMA41_BWM_COUNT, val)
1804 #define bfin_write_DMA41_CURR_BWM_COUNT(val) bfin_write32(DMA41_CURR_BWM_COUNT, val)
1809 #define bfin_write_DMA42_NEXT_DESC_PTR(val) bfin_write32(DMA42_NEXT_DESC_PTR, val)
1811 #define bfin_write_DMA42_START_ADDR(val) bfin_write32(DMA42_START_ADDR, val)
1813 #define bfin_write_DMA42_CONFIG(val) bfin_write32(DMA42_CONFIG, val)
1815 #define bfin_write_DMA42_X_COUNT(val) bfin_write32(DMA42_X_COUNT, val)
1817 #define bfin_write_DMA42_X_MODIFY(val) bfin_write32(DMA42_X_MODIFY, val)
1819 #define bfin_write_DMA42_Y_COUNT(val) bfin_write32(DMA42_Y_COUNT, val)
1821 #define bfin_write_DMA42_Y_MODIFY(val) bfin_write32(DMA42_Y_MODIFY, val)
1823 #define bfin_write_DMA42_CURR_DESC_PTR(val) bfin_write32(DMA42_CURR_DESC_PTR, val)
1825 #define bfin_write_DMA42_PREV_DESC_PTR(val) bfin_write32(DMA42_PREV_DESC_PTR, val)
1827 #define bfin_write_DMA42_CURR_ADDR(val) bfin_write32(DMA42_CURR_ADDR, val)
1829 #define bfin_write_DMA42_IRQ_STATUS(val) bfin_write32(DMA42_IRQ_STATUS, val)
1831 #define bfin_write_DMA42_CURR_X_COUNT(val) bfin_write32(DMA42_CURR_X_COUNT, val)
1833 #define bfin_write_DMA42_CURR_Y_COUNT(val) bfin_write32(DMA42_CURR_Y_COUNT, val)
1835 #define bfin_write_DMA42_BWL_COUNT(val) bfin_write32(DMA42_BWL_COUNT, val)
1837 #define bfin_write_DMA42_CURR_BWL_COUNT(val) bfin_write32(DMA42_CURR_BWL_COUNT, val)
1839 #define bfin_write_DMA42_BWM_COUNT(val) bfin_write32(DMA42_BWM_COUNT, val)
1841 #define bfin_write_DMA42_CURR_BWM_COUNT(val) bfin_write32(DMA42_CURR_BWM_COUNT, val)
1846 #define bfin_write_DMA43_NEXT_DESC_PTR(val) bfin_write32(DMA43_NEXT_DESC_PTR, val)
1848 #define bfin_write_DMA43_START_ADDR(val) bfin_write32(DMA43_START_ADDR, val)
1850 #define bfin_write_DMA43_CONFIG(val) bfin_write32(DMA43_CONFIG, val)
1852 #define bfin_write_DMA43_X_COUNT(val) bfin_write32(DMA43_X_COUNT, val)
1854 #define bfin_write_DMA43_X_MODIFY(val) bfin_write32(DMA43_X_MODIFY, val)
1856 #define bfin_write_DMA43_Y_COUNT(val) bfin_write32(DMA43_Y_COUNT, val)
1858 #define bfin_write_DMA43_Y_MODIFY(val) bfin_write32(DMA43_Y_MODIFY, val)
1860 #define bfin_write_DMA43_CURR_DESC_PTR(val) bfin_write32(DMA43_CURR_DESC_PTR, val)
1862 #define bfin_write_DMA43_PREV_DESC_PTR(val) bfin_write32(DMA43_PREV_DESC_PTR, val)
1864 #define bfin_write_DMA43_CURR_ADDR(val) bfin_write32(DMA43_CURR_ADDR, val)
1866 #define bfin_write_DMA43_IRQ_STATUS(val) bfin_write32(DMA43_IRQ_STATUS, val)
1868 #define bfin_write_DMA43_CURR_X_COUNT(val) bfin_write32(DMA43_CURR_X_COUNT, val)
1870 #define bfin_write_DMA43_CURR_Y_COUNT(val) bfin_write32(DMA43_CURR_Y_COUNT, val)
1872 #define bfin_write_DMA43_BWL_COUNT(val) bfin_write32(DMA43_BWL_COUNT, val)
1874 #define bfin_write_DMA43_CURR_BWL_COUNT(val) bfin_write32(DMA43_CURR_BWL_COUNT, val)
1876 #define bfin_write_DMA43_BWM_COUNT(val) bfin_write32(DMA43_BWM_COUNT, val)
1878 #define bfin_write_DMA43_CURR_BWM_COUNT(val) bfin_write32(DMA43_CURR_BWM_COUNT, val)
1883 #define bfin_write_DMA44_NEXT_DESC_PTR(val) bfin_write32(DMA44_NEXT_DESC_PTR, val)
1885 #define bfin_write_DMA44_START_ADDR(val) bfin_write32(DMA44_START_ADDR, val)
1887 #define bfin_write_DMA44_CONFIG(val) bfin_write32(DMA44_CONFIG, val)
1889 #define bfin_write_DMA44_X_COUNT(val) bfin_write32(DMA44_X_COUNT, val)
1891 #define bfin_write_DMA44_X_MODIFY(val) bfin_write32(DMA44_X_MODIFY, val)
1893 #define bfin_write_DMA44_Y_COUNT(val) bfin_write32(DMA44_Y_COUNT, val)
1895 #define bfin_write_DMA44_Y_MODIFY(val) bfin_write32(DMA44_Y_MODIFY, val)
1897 #define bfin_write_DMA44_CURR_DESC_PTR(val) bfin_write32(DMA44_CURR_DESC_PTR, val)
1899 #define bfin_write_DMA44_PREV_DESC_PTR(val) bfin_write32(DMA44_PREV_DESC_PTR, val)
1901 #define bfin_write_DMA44_CURR_ADDR(val) bfin_write32(DMA44_CURR_ADDR, val)
1903 #define bfin_write_DMA44_IRQ_STATUS(val) bfin_write32(DMA44_IRQ_STATUS, val)
1905 #define bfin_write_DMA44_CURR_X_COUNT(val) bfin_write32(DMA44_CURR_X_COUNT, val)
1907 #define bfin_write_DMA44_CURR_Y_COUNT(val) bfin_write32(DMA44_CURR_Y_COUNT, val)
1909 #define bfin_write_DMA44_BWL_COUNT(val) bfin_write32(DMA44_BWL_COUNT, val)
1911 #define bfin_write_DMA44_CURR_BWL_COUNT(val) bfin_write32(DMA44_CURR_BWL_COUNT, val)
1913 #define bfin_write_DMA44_BWM_COUNT(val) bfin_write32(DMA44_BWM_COUNT, val)
1915 #define bfin_write_DMA44_CURR_BWM_COUNT(val) bfin_write32(DMA44_CURR_BWM_COUNT, val)
1920 #define bfin_write_DMA45_NEXT_DESC_PTR(val) bfin_write32(DMA45_NEXT_DESC_PTR, val)
1922 #define bfin_write_DMA45_START_ADDR(val) bfin_write32(DMA45_START_ADDR, val)
1924 #define bfin_write_DMA45_CONFIG(val) bfin_write32(DMA45_CONFIG, val)
1926 #define bfin_write_DMA45_X_COUNT(val) bfin_write32(DMA45_X_COUNT, val)
1928 #define bfin_write_DMA45_X_MODIFY(val) bfin_write32(DMA45_X_MODIFY, val)
1930 #define bfin_write_DMA45_Y_COUNT(val) bfin_write32(DMA45_Y_COUNT, val)
1932 #define bfin_write_DMA45_Y_MODIFY(val) bfin_write32(DMA45_Y_MODIFY, val)
1934 #define bfin_write_DMA45_CURR_DESC_PTR(val) bfin_write32(DMA45_CURR_DESC_PTR, val)
1936 #define bfin_write_DMA45_PREV_DESC_PTR(val) bfin_write32(DMA45_PREV_DESC_PTR, val)
1938 #define bfin_write_DMA45_CURR_ADDR(val) bfin_write32(DMA45_CURR_ADDR, val)
1940 #define bfin_write_DMA45_IRQ_STATUS(val) bfin_write32(DMA45_IRQ_STATUS, val)
1942 #define bfin_write_DMA45_CURR_X_COUNT(val) bfin_write32(DMA45_CURR_X_COUNT, val)
1944 #define bfin_write_DMA45_CURR_Y_COUNT(val) bfin_write32(DMA45_CURR_Y_COUNT, val)
1946 #define bfin_write_DMA45_BWL_COUNT(val) bfin_write32(DMA45_BWL_COUNT, val)
1948 #define bfin_write_DMA45_CURR_BWL_COUNT(val) bfin_write32(DMA45_CURR_BWL_COUNT, val)
1950 #define bfin_write_DMA45_BWM_COUNT(val) bfin_write32(DMA45_BWM_COUNT, val)
1952 #define bfin_write_DMA45_CURR_BWM_COUNT(val) bfin_write32(DMA45_CURR_BWM_COUNT, val)
1957 #define bfin_write_DMA46_NEXT_DESC_PTR(val) bfin_write32(DMA46_NEXT_DESC_PTR, val)
1959 #define bfin_write_DMA46_START_ADDR(val) bfin_write32(DMA46_START_ADDR, val)
1961 #define bfin_write_DMA46_CONFIG(val) bfin_write32(DMA46_CONFIG, val)
1963 #define bfin_write_DMA46_X_COUNT(val) bfin_write32(DMA46_X_COUNT, val)
1965 #define bfin_write_DMA46_X_MODIFY(val) bfin_write32(DMA46_X_MODIFY, val)
1967 #define bfin_write_DMA46_Y_COUNT(val) bfin_write32(DMA46_Y_COUNT, val)
1969 #define bfin_write_DMA46_Y_MODIFY(val) bfin_write32(DMA46_Y_MODIFY, val)
1971 #define bfin_write_DMA46_CURR_DESC_PTR(val) bfin_write32(DMA46_CURR_DESC_PTR, val)
1973 #define bfin_write_DMA46_PREV_DESC_PTR(val) bfin_write32(DMA46_PREV_DESC_PTR, val)
1975 #define bfin_write_DMA46_CURR_ADDR(val) bfin_write32(DMA46_CURR_ADDR, val)
1977 #define bfin_write_DMA46_IRQ_STATUS(val) bfin_write32(DMA46_IRQ_STATUS, val)
1979 #define bfin_write_DMA46_CURR_X_COUNT(val) bfin_write32(DMA46_CURR_X_COUNT, val)
1981 #define bfin_write_DMA46_CURR_Y_COUNT(val) bfin_write32(DMA46_CURR_Y_COUNT, val)
1983 #define bfin_write_DMA46_BWL_COUNT(val) bfin_write32(DMA46_BWL_COUNT, val)
1985 #define bfin_write_DMA46_CURR_BWL_COUNT(val) bfin_write32(DMA46_CURR_BWL_COUNT, val)
1987 #define bfin_write_DMA46_BWM_COUNT(val) bfin_write32(DMA46_BWM_COUNT, val)
1989 #define bfin_write_DMA46_CURR_BWM_COUNT(val) bfin_write32(DMA46_CURR_BWM_COUNT, val)
1998 #define bfin_write_PINT0_MASK_SET(val) bfin_write32(PINT0_MASK_SET, val)
2000 #define bfin_write_PINT0_MASK_CLEAR(val) bfin_write32(PINT0_MASK_CLEAR, val)
2002 #define bfin_write_PINT0_REQUEST(val) bfin_write32(PINT0_REQUEST, val)
2004 #define bfin_write_PINT0_ASSIGN(val) bfin_write32(PINT0_ASSIGN, val)
2006 #define bfin_write_PINT0_EDGE_SET(val) bfin_write32(PINT0_EDGE_SET, val)
2008 #define bfin_write_PINT0_EDGE_CLEAR(val) bfin_write32(PINT0_EDGE_CLEAR, val)
2010 #define bfin_write_PINT0_INVERT_SET(val) bfin_write32(PINT0_INVERT_SET, val)
2012 #define bfin_write_PINT0_INVERT_CLEAR(val) bfin_write32(PINT0_INVERT_CLEAR, val)
2014 #define bfin_write_PINT0_PINSTATE(val) bfin_write32(PINT0_PINSTATE, val)
2016 #define bfin_write_PINT0_LATCH(val) bfin_write32(PINT0_LATCH, val)
2021 #define bfin_write_PINT1_MASK_SET(val) bfin_write32(PINT1_MASK_SET, val)
2023 #define bfin_write_PINT1_MASK_CLEAR(val) bfin_write32(PINT1_MASK_CLEAR, val)
2025 #define bfin_write_PINT1_REQUEST(val) bfin_write32(PINT1_REQUEST, val)
2027 #define bfin_write_PINT1_ASSIGN(val) bfin_write32(PINT1_ASSIGN, val)
2029 #define bfin_write_PINT1_EDGE_SET(val) bfin_write32(PINT1_EDGE_SET, val)
2031 #define bfin_write_PINT1_EDGE_CLEAR(val) bfin_write32(PINT1_EDGE_CLEAR, val)
2033 #define bfin_write_PINT1_INVERT_SET(val) bfin_write32(PINT1_INVERT_SET, val)
2035 #define bfin_write_PINT1_INVERT_CLEAR(val) bfin_write32(PINT1_INVERT_CLEAR, val)
2037 #define bfin_write_PINT1_PINSTATE(val) bfin_write32(PINT1_PINSTATE, val)
2039 #define bfin_write_PINT1_LATCH(val) bfin_write32(PINT1_LATCH, val)
2044 #define bfin_write_PINT2_MASK_SET(val) bfin_write32(PINT2_MASK_SET, val)
2046 #define bfin_write_PINT2_MASK_CLEAR(val) bfin_write32(PINT2_MASK_CLEAR, val)
2048 #define bfin_write_PINT2_REQUEST(val) bfin_write32(PINT2_REQUEST, val)
2050 #define bfin_write_PINT2_ASSIGN(val) bfin_write32(PINT2_ASSIGN, val)
2052 #define bfin_write_PINT2_EDGE_SET(val) bfin_write32(PINT2_EDGE_SET, val)
2054 #define bfin_write_PINT2_EDGE_CLEAR(val) bfin_write32(PINT2_EDGE_CLEAR, val)
2056 #define bfin_write_PINT2_INVERT_SET(val) bfin_write32(PINT2_INVERT_SET, val)
2058 #define bfin_write_PINT2_INVERT_CLEAR(val) bfin_write32(PINT2_INVERT_CLEAR, val)
2060 #define bfin_write_PINT2_PINSTATE(val) bfin_write32(PINT2_PINSTATE, val)
2062 #define bfin_write_PINT2_LATCH(val) bfin_write32(PINT2_LATCH, val)
2067 #define bfin_write_PINT3_MASK_SET(val) bfin_write32(PINT3_MASK_SET, val)
2069 #define bfin_write_PINT3_MASK_CLEAR(val) bfin_write32(PINT3_MASK_CLEAR, val)
2071 #define bfin_write_PINT3_REQUEST(val) bfin_write32(PINT3_REQUEST, val)
2073 #define bfin_write_PINT3_ASSIGN(val) bfin_write32(PINT3_ASSIGN, val)
2075 #define bfin_write_PINT3_EDGE_SET(val) bfin_write32(PINT3_EDGE_SET, val)
2077 #define bfin_write_PINT3_EDGE_CLEAR(val) bfin_write32(PINT3_EDGE_CLEAR, val)
2079 #define bfin_write_PINT3_INVERT_SET(val) bfin_write32(PINT3_INVERT_SET, val)
2081 #define bfin_write_PINT3_INVERT_CLEAR(val) bfin_write32(PINT3_INVERT_CLEAR, val)
2083 #define bfin_write_PINT3_PINSTATE(val) bfin_write32(PINT3_PINSTATE, val)
2085 #define bfin_write_PINT3_LATCH(val) bfin_write32(PINT3_LATCH, val)
2090 #define bfin_write_PINT4_MASK_SET(val) bfin_write32(PINT4_MASK_SET, val)
2092 #define bfin_write_PINT4_MASK_CLEAR(val) bfin_write32(PINT4_MASK_CLEAR, val)
2094 #define bfin_write_PINT4_REQUEST(val) bfin_write32(PINT4_REQUEST, val)
2096 #define bfin_write_PINT4_ASSIGN(val) bfin_write32(PINT4_ASSIGN, val)
2098 #define bfin_write_PINT4_EDGE_SET(val) bfin_write32(PINT4_EDGE_SET, val)
2100 #define bfin_write_PINT4_EDGE_CLEAR(val) bfin_write32(PINT4_EDGE_CLEAR, val)
2102 #define bfin_write_PINT4_INVERT_SET(val) bfin_write32(PINT4_INVERT_SET, val)
2104 #define bfin_write_PINT4_INVERT_CLEAR(val) bfin_write32(PINT4_INVERT_CLEAR, val)
2106 #define bfin_write_PINT4_PINSTATE(val) bfin_write32(PINT4_PINSTATE, val)
2108 #define bfin_write_PINT4_LATCH(val) bfin_write32(PINT4_LATCH, val)
2113 #define bfin_write_PINT5_MASK_SET(val) bfin_write32(PINT5_MASK_SET, val)
2115 #define bfin_write_PINT5_MASK_CLEAR(val) bfin_write32(PINT5_MASK_CLEAR, val)
2117 #define bfin_write_PINT5_REQUEST(val) bfin_write32(PINT5_REQUEST, val)
2119 #define bfin_write_PINT5_ASSIGN(val) bfin_write32(PINT5_ASSIGN, val)
2121 #define bfin_write_PINT5_EDGE_SET(val) bfin_write32(PINT5_EDGE_SET, val)
2123 #define bfin_write_PINT5_EDGE_CLEAR(val) bfin_write32(PINT5_EDGE_CLEAR, val)
2125 #define bfin_write_PINT5_INVERT_SET(val) bfin_write32(PINT5_INVERT_SET, val)
2127 #define bfin_write_PINT5_INVERT_CLEAR(val) bfin_write32(PINT5_INVERT_CLEAR, val)
2129 #define bfin_write_PINT5_PINSTATE(val) bfin_write32(PINT5_PINSTATE, val)
2131 #define bfin_write_PINT5_LATCH(val) bfin_write32(PINT5_LATCH, val)
2136 #define bfin_write_PORTA_FER(val) bfin_write32(PORTA_FER, val)
2138 #define bfin_write_PORTA_FER_SET(val) bfin_write32(PORTA_FER_SET, val)
2140 #define bfin_write_PORTA_FER_CLEAR(val) bfin_write32(PORTA_FER_CLEAR, val)
2142 #define bfin_write_PORTA(val) bfin_write32(PORTA, val)
2144 #define bfin_write_PORTA_SET(val) bfin_write32(PORTA_SET, val)
2146 #define bfin_write_PORTA_CLEAR(val) bfin_write32(PORTA_CLEAR, val)
2148 #define bfin_write_PORTA_DIR(val) bfin_write32(PORTA_DIR, val)
2150 #define bfin_write_PORTA_DIR_SET(val) bfin_write32(PORTA_DIR_SET, val)
2152 #define bfin_write_PORTA_DIR_CLEAR(val) bfin_write32(PORTA_DIR_CLEAR, val)
2154 #define bfin_write_PORTA_INEN(val) bfin_write32(PORTA_INEN, val)
2156 #define bfin_write_PORTA_INEN_SET(val) bfin_write32(PORTA_INEN_SET, val)
2158 #define bfin_write_PORTA_INEN_CLEAR(val) bfin_write32(PORTA_INEN_CLEAR, val)
2160 #define bfin_write_PORTA_MUX(val) bfin_write32(PORTA_MUX, val)
2162 #define bfin_write_PORTA_DATA_TGL(val) bfin_write32(PORTA_DATA_TGL, val)
2164 #define bfin_write_PORTA_POL(val) bfin_write32(PORTA_POL, val)
2166 #define bfin_write_PORTA_POL_SET(val) bfin_write32(PORTA_POL_SET, val)
2168 #define bfin_write_PORTA_POL_CLEAR(val) bfin_write32(PORTA_POL_CLEAR, val)
2170 #define bfin_write_PORTA_LOCK(val) bfin_write32(PORTA_LOCK, val)
2172 #define bfin_write_PORTA_REVID(val) bfin_write32(PORTA_REVID, val)
2178 #define bfin_write_PORTB_FER(val) bfin_write32(PORTB_FER, val)
2180 #define bfin_write_PORTB_FER_SET(val) bfin_write32(PORTB_FER_SET, val)
2182 #define bfin_write_PORTB_FER_CLEAR(val) bfin_write32(PORTB_FER_CLEAR, val)
2184 #define bfin_write_PORTB(val) bfin_write32(PORTB, val)
2186 #define bfin_write_PORTB_SET(val) bfin_write32(PORTB_SET, val)
2188 #define bfin_write_PORTB_CLEAR(val) bfin_write32(PORTB_CLEAR, val)
2190 #define bfin_write_PORTB_DIR(val) bfin_write32(PORTB_DIR, val)
2192 #define bfin_write_PORTB_DIR_SET(val) bfin_write32(PORTB_DIR_SET, val)
2194 #define bfin_write_PORTB_DIR_CLEAR(val) bfin_write32(PORTB_DIR_CLEAR, val)
2196 #define bfin_write_PORTB_INEN(val) bfin_write32(PORTB_INEN, val)
2198 #define bfin_write_PORTB_INEN_SET(val) bfin_write32(PORTB_INEN_SET, val)
2200 #define bfin_write_PORTB_INEN_CLEAR(val) bfin_write32(PORTB_INEN_CLEAR, val)
2202 #define bfin_write_PORTB_MUX(val) bfin_write32(PORTB_MUX, val)
2204 #define bfin_write_PORTB_DATA_TGL(val) bfin_write32(PORTB_DATA_TGL, val)
2206 #define bfin_write_PORTB_POL(val) bfin_write32(PORTB_POL, val)
2208 #define bfin_write_PORTB_POL_SET(val) bfin_write32(PORTB_POL_SET, val)
2210 #define bfin_write_PORTB_POL_CLEAR(val) bfin_write32(PORTB_POL_CLEAR, val)
2212 #define bfin_write_PORTB_LOCK(val) bfin_write32(PORTB_LOCK, val)
2214 #define bfin_write_PORTB_REVID(val) bfin_write32(PORTB_REVID, val)
2219 #define bfin_write_PORTC_FER(val) bfin_write32(PORTC_FER, val)
2221 #define bfin_write_PORTC_FER_SET(val) bfin_write32(PORTC_FER_SET, val)
2223 #define bfin_write_PORTC_FER_CLEAR(val) bfin_write32(PORTC_FER_CLEAR, val)
2225 #define bfin_write_PORTC(val) bfin_write32(PORTC, val)
2227 #define bfin_write_PORTC_SET(val) bfin_write32(PORTC_SET, val)
2229 #define bfin_write_PORTC_CLEAR(val) bfin_write32(PORTC_CLEAR, val)
2231 #define bfin_write_PORTC_DIR(val) bfin_write32(PORTC_DIR, val)
2233 #define bfin_write_PORTC_DIR_SET(val) bfin_write32(PORTC_DIR_SET, val)
2235 #define bfin_write_PORTC_DIR_CLEAR(val) bfin_write32(PORTC_DIR_CLEAR, val)
2237 #define bfin_write_PORTC_INEN(val) bfin_write32(PORTC_INEN, val)
2239 #define bfin_write_PORTC_INEN_SET(val) bfin_write32(PORTC_INEN_SET, val)
2241 #define bfin_write_PORTC_INEN_CLEAR(val) bfin_write32(PORTC_INEN_CLEAR, val)
2243 #define bfin_write_PORTC_MUX(val) bfin_write32(PORTC_MUX, val)
2245 #define bfin_write_PORTC_DATA_TGL(val) bfin_write32(PORTC_DATA_TGL, val)
2247 #define bfin_write_PORTC_POL(val) bfin_write32(PORTC_POL, val)
2249 #define bfin_write_PORTC_POL_SET(val) bfin_write32(PORTC_POL_SET, val)
2251 #define bfin_write_PORTC_POL_CLEAR(val) bfin_write32(PORTC_POL_CLEAR, val)
2253 #define bfin_write_PORTC_LOCK(val) bfin_write32(PORTC_LOCK, val)
2255 #define bfin_write_PORTC_REVID(val) bfin_write32(PORTC_REVID, val)
2260 #define bfin_write_PORTD_FER(val) bfin_write32(PORTD_FER, val)
2262 #define bfin_write_PORTD_FER_SET(val) bfin_write32(PORTD_FER_SET, val)
2264 #define bfin_write_PORTD_FER_CLEAR(val) bfin_write32(PORTD_FER_CLEAR, val)
2266 #define bfin_write_PORTD(val) bfin_write32(PORTD, val)
2268 #define bfin_write_PORTD_SET(val) bfin_write32(PORTD_SET, val)
2270 #define bfin_write_PORTD_CLEAR(val) bfin_write32(PORTD_CLEAR, val)
2272 #define bfin_write_PORTD_DIR(val) bfin_write32(PORTD_DIR, val)
2274 #define bfin_write_PORTD_DIR_SET(val) bfin_write32(PORTD_DIR_SET, val)
2276 #define bfin_write_PORTD_DIR_CLEAR(val) bfin_write32(PORTD_DIR_CLEAR, val)
2278 #define bfin_write_PORTD_INEN(val) bfin_write32(PORTD_INEN, val)
2280 #define bfin_write_PORTD_INEN_SET(val) bfin_write32(PORTD_INEN_SET, val)
2282 #define bfin_write_PORTD_INEN_CLEAR(val) bfin_write32(PORTD_INEN_CLEAR, val)
2284 #define bfin_write_PORTD_MUX(val) bfin_write32(PORTD_MUX, val)
2286 #define bfin_write_PORTD_DATA_TGL(val) bfin_write32(PORTD_DATA_TGL, val)
2288 #define bfin_write_PORTD_POL(val) bfin_write32(PORTD_POL, val)
2290 #define bfin_write_PORTD_POL_SET(val) bfin_write32(PORTD_POL_SET, val)
2292 #define bfin_write_PORTD_POL_CLEAR(val) bfin_write32(PORTD_POL_CLEAR, val)
2294 #define bfin_write_PORTD_LOCK(val) bfin_write32(PORTD_LOCK, val)
2296 #define bfin_write_PORTD_REVID(val) bfin_write32(PORTD_REVID, val)
2301 #define bfin_write_PORTE_FER(val) bfin_write32(PORTE_FER, val)
2303 #define bfin_write_PORTE_FER_SET(val) bfin_write32(PORTE_FER_SET, val)
2305 #define bfin_write_PORTE_FER_CLEAR(val) bfin_write32(PORTE_FER_CLEAR, val)
2307 #define bfin_write_PORTE(val) bfin_write32(PORTE, val)
2309 #define bfin_write_PORTE_SET(val) bfin_write32(PORTE_SET, val)
2311 #define bfin_write_PORTE_CLEAR(val) bfin_write32(PORTE_CLEAR, val)
2313 #define bfin_write_PORTE_DIR(val) bfin_write32(PORTE_DIR, val)
2315 #define bfin_write_PORTE_DIR_SET(val) bfin_write32(PORTE_DIR_SET, val)
2317 #define bfin_write_PORTE_DIR_CLEAR(val) bfin_write32(PORTE_DIR_CLEAR, val)
2319 #define bfin_write_PORTE_INEN(val) bfin_write32(PORTE_INEN, val)
2321 #define bfin_write_PORTE_INEN_SET(val) bfin_write32(PORTE_INEN_SET, val)
2323 #define bfin_write_PORTE_INEN_CLEAR(val) bfin_write32(PORTE_INEN_CLEAR, val)
2325 #define bfin_write_PORTE_MUX(val) bfin_write32(PORTE_MUX, val)
2327 #define bfin_write_PORTE_DATA_TGL(val) bfin_write32(PORTE_DATA_TGL, val)
2329 #define bfin_write_PORTE_POL(val) bfin_write32(PORTE_POL, val)
2331 #define bfin_write_PORTE_POL_SET(val) bfin_write32(PORTE_POL_SET, val)
2333 #define bfin_write_PORTE_POL_CLEAR(val) bfin_write32(PORTE_POL_CLEAR, val)
2335 #define bfin_write_PORTE_LOCK(val) bfin_write32(PORTE_LOCK, val)
2337 #define bfin_write_PORTE_REVID(val) bfin_write32(PORTE_REVID, val)
2342 #define bfin_write_PORTF_FER(val) bfin_write32(PORTF_FER, val)
2344 #define bfin_write_PORTF_FER_SET(val) bfin_write32(PORTF_FER_SET, val)
2346 #define bfin_write_PORTF_FER_CLEAR(val) bfin_write32(PORTF_FER_CLEAR, val)
2348 #define bfin_write_PORTF(val) bfin_write32(PORTF, val)
2350 #define bfin_write_PORTF_SET(val) bfin_write32(PORTF_SET, val)
2352 #define bfin_write_PORTF_CLEAR(val) bfin_write32(PORTF_CLEAR, val)
2354 #define bfin_write_PORTF_DIR(val) bfin_write32(PORTF_DIR, val)
2356 #define bfin_write_PORTF_DIR_SET(val) bfin_write32(PORTF_DIR_SET, val)
2358 #define bfin_write_PORTF_DIR_CLEAR(val) bfin_write32(PORTF_DIR_CLEAR, val)
2360 #define bfin_write_PORTF_INEN(val) bfin_write32(PORTF_INEN, val)
2362 #define bfin_write_PORTF_INEN_SET(val) bfin_write32(PORTF_INEN_SET, val)
2364 #define bfin_write_PORTF_INEN_CLEAR(val) bfin_write32(PORTF_INEN_CLEAR, val)
2366 #define bfin_write_PORTF_MUX(val) bfin_write32(PORTF_MUX, val)
2368 #define bfin_write_PORTF_DATA_TGL(val) bfin_write32(PORTF_DATA_TGL, val)
2370 #define bfin_write_PORTF_POL(val) bfin_write32(PORTF_POL, val)
2372 #define bfin_write_PORTF_POL_SET(val) bfin_write32(PORTF_POL_SET, val)
2374 #define bfin_write_PORTF_POL_CLEAR(val) bfin_write32(PORTF_POL_CLEAR, val)
2376 #define bfin_write_PORTF_LOCK(val) bfin_write32(PORTF_LOCK, val)
2378 #define bfin_write_PORTF_REVID(val) bfin_write32(PORTF_REVID, val)
2383 #define bfin_write_PORTG_FER(val) bfin_write32(PORTG_FER, val)
2385 #define bfin_write_PORTG_FER_SET(val) bfin_write32(PORTG_FER_SET, val)
2387 #define bfin_write_PORTG_FER_CLEAR(val) bfin_write32(PORTG_FER_CLEAR, val)
2389 #define bfin_write_PORTG(val) bfin_write32(PORTG, val)
2391 #define bfin_write_PORTG_SET(val) bfin_write32(PORTG_SET, val)
2393 #define bfin_write_PORTG_CLEAR(val) bfin_write32(PORTG_CLEAR, val)
2395 #define bfin_write_PORTG_DIR(val) bfin_write32(PORTG_DIR, val)
2397 #define bfin_write_PORTG_DIR_SET(val) bfin_write32(PORTG_DIR_SET, val)
2399 #define bfin_write_PORTG_DIR_CLEAR(val) bfin_write32(PORTG_DIR_CLEAR, val)
2401 #define bfin_write_PORTG_INEN(val) bfin_write32(PORTG_INEN, val)
2403 #define bfin_write_PORTG_INEN_SET(val) bfin_write32(PORTG_INEN_SET, val)
2405 #define bfin_write_PORTG_INEN_CLEAR(val) bfin_write32(PORTG_INEN_CLEAR, val)
2407 #define bfin_write_PORTG_MUX(val) bfin_write32(PORTG_MUX, val)
2409 #define bfin_write_PORTG_DATA_TGL(val) bfin_write32(PORTG_DATA_TGL, val)
2411 #define bfin_write_PORTG_POL(val) bfin_write32(PORTG_POL, val)
2413 #define bfin_write_PORTG_POL_SET(val) bfin_write32(PORTG_POL_SET, val)
2415 #define bfin_write_PORTG_POL_CLEAR(val) bfin_write32(PORTG_POL_CLEAR, val)
2417 #define bfin_write_PORTG_LOCK(val) bfin_write32(PORTG_LOCK, val)
2419 #define bfin_write_PORTG_REVID(val) bfin_write32(PORTG_REVID, val)
2427 #define bfin_write_CAN0_MC1(val) bfin_write16(CAN0_MC1, val)
2429 #define bfin_write_CAN0_MD1(val) bfin_write16(CAN0_MD1, val)
2431 #define bfin_write_CAN0_TRS1(val) bfin_write16(CAN0_TRS1, val)
2433 #define bfin_write_CAN0_TRR1(val) bfin_write16(CAN0_TRR1, val)
2435 #define bfin_write_CAN0_TA1(val) bfin_write16(CAN0_TA1, val)
2437 #define bfin_write_CAN0_AA1(val) bfin_write16(CAN0_AA1, val)
2439 #define bfin_write_CAN0_RMP1(val) bfin_write16(CAN0_RMP1, val)
2441 #define bfin_write_CAN0_RML1(val) bfin_write16(CAN0_RML1, val)
2443 #define bfin_write_CAN0_MBTIF1(val) bfin_write16(CAN0_MBTIF1, val)
2445 #define bfin_write_CAN0_MBRIF1(val) bfin_write16(CAN0_MBRIF1, val)
2447 #define bfin_write_CAN0_MBIM1(val) bfin_write16(CAN0_MBIM1, val)
2449 #define bfin_write_CAN0_RFH1(val) bfin_write16(CAN0_RFH1, val)
2451 #define bfin_write_CAN0_OPSS1(val) bfin_write16(CAN0_OPSS1, val)
2456 #define bfin_write_CAN0_MC2(val) bfin_write16(CAN0_MC2, val)
2458 #define bfin_write_CAN0_MD2(val) bfin_write16(CAN0_MD2, val)
2460 #define bfin_write_CAN0_TRS2(val) bfin_write16(CAN0_TRS2, val)
2462 #define bfin_write_CAN0_TRR2(val) bfin_write16(CAN0_TRR2, val)
2464 #define bfin_write_CAN0_TA2(val) bfin_write16(CAN0_TA2, val)
2466 #define bfin_write_CAN0_AA2(val) bfin_write16(CAN0_AA2, val)
2468 #define bfin_write_CAN0_RMP2(val) bfin_write16(CAN0_RMP2, val)
2470 #define bfin_write_CAN0_RML2(val) bfin_write16(CAN0_RML2, val)
2472 #define bfin_write_CAN0_MBTIF2(val) bfin_write16(CAN0_MBTIF2, val)
2474 #define bfin_write_CAN0_MBRIF2(val) bfin_write16(CAN0_MBRIF2, val)
2476 #define bfin_write_CAN0_MBIM2(val) bfin_write16(CAN0_MBIM2, val)
2478 #define bfin_write_CAN0_RFH2(val) bfin_write16(CAN0_RFH2, val)
2480 #define bfin_write_CAN0_OPSS2(val) bfin_write16(CAN0_OPSS2, val)
2485 #define bfin_write_CAN0_CLOCK(val) bfin_write16(CAN0_CLOCK, val)
2487 #define bfin_write_CAN0_TIMING(val) bfin_write16(CAN0_TIMING, val)
2489 #define bfin_write_CAN0_DEBUG(val) bfin_write16(CAN0_DEBUG, val)
2491 #define bfin_write_CAN0_STATUS(val) bfin_write16(CAN0_STATUS, val)
2493 #define bfin_write_CAN0_CEC(val) bfin_write16(CAN0_CEC, val)
2495 #define bfin_write_CAN0_GIS(val) bfin_write16(CAN0_GIS, val)
2497 #define bfin_write_CAN0_GIM(val) bfin_write16(CAN0_GIM, val)
2499 #define bfin_write_CAN0_GIF(val) bfin_write16(CAN0_GIF, val)
2501 #define bfin_write_CAN0_CONTROL(val) bfin_write16(CAN0_CONTROL, val)
2503 #define bfin_write_CAN0_INTR(val) bfin_write16(CAN0_INTR, val)
2505 #define bfin_write_CAN0_MBTD(val) bfin_write16(CAN0_MBTD, val)
2507 #define bfin_write_CAN0_EWR(val) bfin_write16(CAN0_EWR, val)
2509 #define bfin_write_CAN0_ESR(val) bfin_write16(CAN0_ESR, val)
2511 #define bfin_write_CAN0_UCCNT(val) bfin_write16(CAN0_UCCNT, val)
2513 #define bfin_write_CAN0_UCRC(val) bfin_write16(CAN0_UCRC, val)
2515 #define bfin_write_CAN0_UCCNF(val) bfin_write16(CAN0_UCCNF, val)
2520 #define bfin_write_CAN0_AM00L(val) bfin_write16(CAN0_AM00L, val)
2522 #define bfin_write_CAN0_AM00H(val) bfin_write16(CAN0_AM00H, val)
2524 #define bfin_write_CAN0_AM01L(val) bfin_write16(CAN0_AM01L, val)
2526 #define bfin_write_CAN0_AM01H(val) bfin_write16(CAN0_AM01H, val)
2528 #define bfin_write_CAN0_AM02L(val) bfin_write16(CAN0_AM02L, val)
2530 #define bfin_write_CAN0_AM02H(val) bfin_write16(CAN0_AM02H, val)
2532 #define bfin_write_CAN0_AM03L(val) bfin_write16(CAN0_AM03L, val)
2534 #define bfin_write_CAN0_AM03H(val) bfin_write16(CAN0_AM03H, val)
2536 #define bfin_write_CAN0_AM04L(val) bfin_write16(CAN0_AM04L, val)
2538 #define bfin_write_CAN0_AM04H(val) bfin_write16(CAN0_AM04H, val)
2540 #define bfin_write_CAN0_AM05L(val) bfin_write16(CAN0_AM05L, val)
2542 #define bfin_write_CAN0_AM05H(val) bfin_write16(CAN0_AM05H, val)
2544 #define bfin_write_CAN0_AM06L(val) bfin_write16(CAN0_AM06L, val)
2546 #define bfin_write_CAN0_AM06H(val) bfin_write16(CAN0_AM06H, val)
2548 #define bfin_write_CAN0_AM07L(val) bfin_write16(CAN0_AM07L, val)
2550 #define bfin_write_CAN0_AM07H(val) bfin_write16(CAN0_AM07H, val)
2552 #define bfin_write_CAN0_AM08L(val) bfin_write16(CAN0_AM08L, val)
2554 #define bfin_write_CAN0_AM08H(val) bfin_write16(CAN0_AM08H, val)
2556 #define bfin_write_CAN0_AM09L(val) bfin_write16(CAN0_AM09L, val)
2558 #define bfin_write_CAN0_AM09H(val) bfin_write16(CAN0_AM09H, val)
2560 #define bfin_write_CAN0_AM10L(val) bfin_write16(CAN0_AM10L, val)
2562 #define bfin_write_CAN0_AM10H(val) bfin_write16(CAN0_AM10H, val)
2564 #define bfin_write_CAN0_AM11L(val) bfin_write16(CAN0_AM11L, val)
2566 #define bfin_write_CAN0_AM11H(val) bfin_write16(CAN0_AM11H, val)
2568 #define bfin_write_CAN0_AM12L(val) bfin_write16(CAN0_AM12L, val)
2570 #define bfin_write_CAN0_AM12H(val) bfin_write16(CAN0_AM12H, val)
2572 #define bfin_write_CAN0_AM13L(val) bfin_write16(CAN0_AM13L, val)
2574 #define bfin_write_CAN0_AM13H(val) bfin_write16(CAN0_AM13H, val)
2576 #define bfin_write_CAN0_AM14L(val) bfin_write16(CAN0_AM14L, val)
2578 #define bfin_write_CAN0_AM14H(val) bfin_write16(CAN0_AM14H, val)
2580 #define bfin_write_CAN0_AM15L(val) bfin_write16(CAN0_AM15L, val)
2582 #define bfin_write_CAN0_AM15H(val) bfin_write16(CAN0_AM15H, val)
2587 #define bfin_write_CAN0_AM16L(val) bfin_write16(CAN0_AM16L, val)
2589 #define bfin_write_CAN0_AM16H(val) bfin_write16(CAN0_AM16H, val)
2591 #define bfin_write_CAN0_AM17L(val) bfin_write16(CAN0_AM17L, val)
2593 #define bfin_write_CAN0_AM17H(val) bfin_write16(CAN0_AM17H, val)
2595 #define bfin_write_CAN0_AM18L(val) bfin_write16(CAN0_AM18L, val)
2597 #define bfin_write_CAN0_AM18H(val) bfin_write16(CAN0_AM18H, val)
2599 #define bfin_write_CAN0_AM19L(val) bfin_write16(CAN0_AM19L, val)
2601 #define bfin_write_CAN0_AM19H(val) bfin_write16(CAN0_AM19H, val)
2603 #define bfin_write_CAN0_AM20L(val) bfin_write16(CAN0_AM20L, val)
2605 #define bfin_write_CAN0_AM20H(val) bfin_write16(CAN0_AM20H, val)
2607 #define bfin_write_CAN0_AM21L(val) bfin_write16(CAN0_AM21L, val)
2609 #define bfin_write_CAN0_AM21H(val) bfin_write16(CAN0_AM21H, val)
2611 #define bfin_write_CAN0_AM22L(val) bfin_write16(CAN0_AM22L, val)
2613 #define bfin_write_CAN0_AM22H(val) bfin_write16(CAN0_AM22H, val)
2615 #define bfin_write_CAN0_AM23L(val) bfin_write16(CAN0_AM23L, val)
2617 #define bfin_write_CAN0_AM23H(val) bfin_write16(CAN0_AM23H, val)
2619 #define bfin_write_CAN0_AM24L(val) bfin_write16(CAN0_AM24L, val)
2621 #define bfin_write_CAN0_AM24H(val) bfin_write16(CAN0_AM24H, val)
2623 #define bfin_write_CAN0_AM25L(val) bfin_write16(CAN0_AM25L, val)
2625 #define bfin_write_CAN0_AM25H(val) bfin_write16(CAN0_AM25H, val)
2627 #define bfin_write_CAN0_AM26L(val) bfin_write16(CAN0_AM26L, val)
2629 #define bfin_write_CAN0_AM26H(val) bfin_write16(CAN0_AM26H, val)
2631 #define bfin_write_CAN0_AM27L(val) bfin_write16(CAN0_AM27L, val)
2633 #define bfin_write_CAN0_AM27H(val) bfin_write16(CAN0_AM27H, val)
2635 #define bfin_write_CAN0_AM28L(val) bfin_write16(CAN0_AM28L, val)
2637 #define bfin_write_CAN0_AM28H(val) bfin_write16(CAN0_AM28H, val)
2639 #define bfin_write_CAN0_AM29L(val) bfin_write16(CAN0_AM29L, val)
2641 #define bfin_write_CAN0_AM29H(val) bfin_write16(CAN0_AM29H, val)
2643 #define bfin_write_CAN0_AM30L(val) bfin_write16(CAN0_AM30L, val)
2645 #define bfin_write_CAN0_AM30H(val) bfin_write16(CAN0_AM30H, val)
2647 #define bfin_write_CAN0_AM31L(val) bfin_write16(CAN0_AM31L, val)
2649 #define bfin_write_CAN0_AM31H(val) bfin_write16(CAN0_AM31H, val)
2654 #define bfin_write_CAN0_MB00_DATA0(val) bfin_write16(CAN0_MB00_DATA0, val)
2656 #define bfin_write_CAN0_MB00_DATA1(val) bfin_write16(CAN0_MB00_DATA1, val)
2658 #define bfin_write_CAN0_MB00_DATA2(val) bfin_write16(CAN0_MB00_DATA2, val)
2660 #define bfin_write_CAN0_MB00_DATA3(val) bfin_write16(CAN0_MB00_DATA3, val)
2662 #define bfin_write_CAN0_MB00_LENGTH(val) bfin_write16(CAN0_MB00_LENGTH, val)
2664 #define bfin_write_CAN0_MB00_TIMESTAMP(val) bfin_write16(CAN0_MB00_TIMESTAMP, val)
2666 #define bfin_write_CAN0_MB00_ID0(val) bfin_write16(CAN0_MB00_ID0, val)
2668 #define bfin_write_CAN0_MB00_ID1(val) bfin_write16(CAN0_MB00_ID1, val)
2670 #define bfin_write_CAN0_MB01_DATA0(val) bfin_write16(CAN0_MB01_DATA0, val)
2672 #define bfin_write_CAN0_MB01_DATA1(val) bfin_write16(CAN0_MB01_DATA1, val)
2674 #define bfin_write_CAN0_MB01_DATA2(val) bfin_write16(CAN0_MB01_DATA2, val)
2676 #define bfin_write_CAN0_MB01_DATA3(val) bfin_write16(CAN0_MB01_DATA3, val)
2678 #define bfin_write_CAN0_MB01_LENGTH(val) bfin_write16(CAN0_MB01_LENGTH, val)
2680 #define bfin_write_CAN0_MB01_TIMESTAMP(val) bfin_write16(CAN0_MB01_TIMESTAMP, val)
2682 #define bfin_write_CAN0_MB01_ID0(val) bfin_write16(CAN0_MB01_ID0, val)
2684 #define bfin_write_CAN0_MB01_ID1(val) bfin_write16(CAN0_MB01_ID1, val)
2686 #define bfin_write_CAN0_MB02_DATA0(val) bfin_write16(CAN0_MB02_DATA0, val)
2688 #define bfin_write_CAN0_MB02_DATA1(val) bfin_write16(CAN0_MB02_DATA1, val)
2690 #define bfin_write_CAN0_MB02_DATA2(val) bfin_write16(CAN0_MB02_DATA2, val)
2692 #define bfin_write_CAN0_MB02_DATA3(val) bfin_write16(CAN0_MB02_DATA3, val)
2694 #define bfin_write_CAN0_MB02_LENGTH(val) bfin_write16(CAN0_MB02_LENGTH, val)
2696 #define bfin_write_CAN0_MB02_TIMESTAMP(val) bfin_write16(CAN0_MB02_TIMESTAMP, val)
2698 #define bfin_write_CAN0_MB02_ID0(val) bfin_write16(CAN0_MB02_ID0, val)
2700 #define bfin_write_CAN0_MB02_ID1(val) bfin_write16(CAN0_MB02_ID1, val)
2702 #define bfin_write_CAN0_MB03_DATA0(val) bfin_write16(CAN0_MB03_DATA0, val)
2704 #define bfin_write_CAN0_MB03_DATA1(val) bfin_write16(CAN0_MB03_DATA1, val)
2706 #define bfin_write_CAN0_MB03_DATA2(val) bfin_write16(CAN0_MB03_DATA2, val)
2708 #define bfin_write_CAN0_MB03_DATA3(val) bfin_write16(CAN0_MB03_DATA3, val)
2710 #define bfin_write_CAN0_MB03_LENGTH(val) bfin_write16(CAN0_MB03_LENGTH, val)
2712 #define bfin_write_CAN0_MB03_TIMESTAMP(val) bfin_write16(CAN0_MB03_TIMESTAMP, val)
2714 #define bfin_write_CAN0_MB03_ID0(val) bfin_write16(CAN0_MB03_ID0, val)
2716 #define bfin_write_CAN0_MB03_ID1(val) bfin_write16(CAN0_MB03_ID1, val)
2718 #define bfin_write_CAN0_MB04_DATA0(val) bfin_write16(CAN0_MB04_DATA0, val)
2720 #define bfin_write_CAN0_MB04_DATA1(val) bfin_write16(CAN0_MB04_DATA1, val)
2722 #define bfin_write_CAN0_MB04_DATA2(val) bfin_write16(CAN0_MB04_DATA2, val)
2724 #define bfin_write_CAN0_MB04_DATA3(val) bfin_write16(CAN0_MB04_DATA3, val)
2726 #define bfin_write_CAN0_MB04_LENGTH(val) bfin_write16(CAN0_MB04_LENGTH, val)
2728 #define bfin_write_CAN0_MB04_TIMESTAMP(val) bfin_write16(CAN0_MB04_TIMESTAMP, val)
2730 #define bfin_write_CAN0_MB04_ID0(val) bfin_write16(CAN0_MB04_ID0, val)
2732 #define bfin_write_CAN0_MB04_ID1(val) bfin_write16(CAN0_MB04_ID1, val)
2734 #define bfin_write_CAN0_MB05_DATA0(val) bfin_write16(CAN0_MB05_DATA0, val)
2736 #define bfin_write_CAN0_MB05_DATA1(val) bfin_write16(CAN0_MB05_DATA1, val)
2738 #define bfin_write_CAN0_MB05_DATA2(val) bfin_write16(CAN0_MB05_DATA2, val)
2740 #define bfin_write_CAN0_MB05_DATA3(val) bfin_write16(CAN0_MB05_DATA3, val)
2742 #define bfin_write_CAN0_MB05_LENGTH(val) bfin_write16(CAN0_MB05_LENGTH, val)
2744 #define bfin_write_CAN0_MB05_TIMESTAMP(val) bfin_write16(CAN0_MB05_TIMESTAMP, val)
2746 #define bfin_write_CAN0_MB05_ID0(val) bfin_write16(CAN0_MB05_ID0, val)
2748 #define bfin_write_CAN0_MB05_ID1(val) bfin_write16(CAN0_MB05_ID1, val)
2750 #define bfin_write_CAN0_MB06_DATA0(val) bfin_write16(CAN0_MB06_DATA0, val)
2752 #define bfin_write_CAN0_MB06_DATA1(val) bfin_write16(CAN0_MB06_DATA1, val)
2754 #define bfin_write_CAN0_MB06_DATA2(val) bfin_write16(CAN0_MB06_DATA2, val)
2756 #define bfin_write_CAN0_MB06_DATA3(val) bfin_write16(CAN0_MB06_DATA3, val)
2758 #define bfin_write_CAN0_MB06_LENGTH(val) bfin_write16(CAN0_MB06_LENGTH, val)
2760 #define bfin_write_CAN0_MB06_TIMESTAMP(val) bfin_write16(CAN0_MB06_TIMESTAMP, val)
2762 #define bfin_write_CAN0_MB06_ID0(val) bfin_write16(CAN0_MB06_ID0, val)
2764 #define bfin_write_CAN0_MB06_ID1(val) bfin_write16(CAN0_MB06_ID1, val)
2766 #define bfin_write_CAN0_MB07_DATA0(val) bfin_write16(CAN0_MB07_DATA0, val)
2768 #define bfin_write_CAN0_MB07_DATA1(val) bfin_write16(CAN0_MB07_DATA1, val)
2770 #define bfin_write_CAN0_MB07_DATA2(val) bfin_write16(CAN0_MB07_DATA2, val)
2772 #define bfin_write_CAN0_MB07_DATA3(val) bfin_write16(CAN0_MB07_DATA3, val)
2774 #define bfin_write_CAN0_MB07_LENGTH(val) bfin_write16(CAN0_MB07_LENGTH, val)
2776 #define bfin_write_CAN0_MB07_TIMESTAMP(val) bfin_write16(CAN0_MB07_TIMESTAMP, val)
2778 #define bfin_write_CAN0_MB07_ID0(val) bfin_write16(CAN0_MB07_ID0, val)
2780 #define bfin_write_CAN0_MB07_ID1(val) bfin_write16(CAN0_MB07_ID1, val)
2782 #define bfin_write_CAN0_MB08_DATA0(val) bfin_write16(CAN0_MB08_DATA0, val)
2784 #define bfin_write_CAN0_MB08_DATA1(val) bfin_write16(CAN0_MB08_DATA1, val)
2786 #define bfin_write_CAN0_MB08_DATA2(val) bfin_write16(CAN0_MB08_DATA2, val)
2788 #define bfin_write_CAN0_MB08_DATA3(val) bfin_write16(CAN0_MB08_DATA3, val)
2790 #define bfin_write_CAN0_MB08_LENGTH(val) bfin_write16(CAN0_MB08_LENGTH, val)
2792 #define bfin_write_CAN0_MB08_TIMESTAMP(val) bfin_write16(CAN0_MB08_TIMESTAMP, val)
2794 #define bfin_write_CAN0_MB08_ID0(val) bfin_write16(CAN0_MB08_ID0, val)
2796 #define bfin_write_CAN0_MB08_ID1(val) bfin_write16(CAN0_MB08_ID1, val)
2798 #define bfin_write_CAN0_MB09_DATA0(val) bfin_write16(CAN0_MB09_DATA0, val)
2800 #define bfin_write_CAN0_MB09_DATA1(val) bfin_write16(CAN0_MB09_DATA1, val)
2802 #define bfin_write_CAN0_MB09_DATA2(val) bfin_write16(CAN0_MB09_DATA2, val)
2804 #define bfin_write_CAN0_MB09_DATA3(val) bfin_write16(CAN0_MB09_DATA3, val)
2806 #define bfin_write_CAN0_MB09_LENGTH(val) bfin_write16(CAN0_MB09_LENGTH, val)
2808 #define bfin_write_CAN0_MB09_TIMESTAMP(val) bfin_write16(CAN0_MB09_TIMESTAMP, val)
2810 #define bfin_write_CAN0_MB09_ID0(val) bfin_write16(CAN0_MB09_ID0, val)
2812 #define bfin_write_CAN0_MB09_ID1(val) bfin_write16(CAN0_MB09_ID1, val)
2814 #define bfin_write_CAN0_MB10_DATA0(val) bfin_write16(CAN0_MB10_DATA0, val)
2816 #define bfin_write_CAN0_MB10_DATA1(val) bfin_write16(CAN0_MB10_DATA1, val)
2818 #define bfin_write_CAN0_MB10_DATA2(val) bfin_write16(CAN0_MB10_DATA2, val)
2820 #define bfin_write_CAN0_MB10_DATA3(val) bfin_write16(CAN0_MB10_DATA3, val)
2822 #define bfin_write_CAN0_MB10_LENGTH(val) bfin_write16(CAN0_MB10_LENGTH, val)
2824 #define bfin_write_CAN0_MB10_TIMESTAMP(val) bfin_write16(CAN0_MB10_TIMESTAMP, val)
2826 #define bfin_write_CAN0_MB10_ID0(val) bfin_write16(CAN0_MB10_ID0, val)
2828 #define bfin_write_CAN0_MB10_ID1(val) bfin_write16(CAN0_MB10_ID1, val)
2830 #define bfin_write_CAN0_MB11_DATA0(val) bfin_write16(CAN0_MB11_DATA0, val)
2832 #define bfin_write_CAN0_MB11_DATA1(val) bfin_write16(CAN0_MB11_DATA1, val)
2834 #define bfin_write_CAN0_MB11_DATA2(val) bfin_write16(CAN0_MB11_DATA2, val)
2836 #define bfin_write_CAN0_MB11_DATA3(val) bfin_write16(CAN0_MB11_DATA3, val)
2838 #define bfin_write_CAN0_MB11_LENGTH(val) bfin_write16(CAN0_MB11_LENGTH, val)
2840 #define bfin_write_CAN0_MB11_TIMESTAMP(val) bfin_write16(CAN0_MB11_TIMESTAMP, val)
2842 #define bfin_write_CAN0_MB11_ID0(val) bfin_write16(CAN0_MB11_ID0, val)
2844 #define bfin_write_CAN0_MB11_ID1(val) bfin_write16(CAN0_MB11_ID1, val)
2846 #define bfin_write_CAN0_MB12_DATA0(val) bfin_write16(CAN0_MB12_DATA0, val)
2848 #define bfin_write_CAN0_MB12_DATA1(val) bfin_write16(CAN0_MB12_DATA1, val)
2850 #define bfin_write_CAN0_MB12_DATA2(val) bfin_write16(CAN0_MB12_DATA2, val)
2852 #define bfin_write_CAN0_MB12_DATA3(val) bfin_write16(CAN0_MB12_DATA3, val)
2854 #define bfin_write_CAN0_MB12_LENGTH(val) bfin_write16(CAN0_MB12_LENGTH, val)
2856 #define bfin_write_CAN0_MB12_TIMESTAMP(val) bfin_write16(CAN0_MB12_TIMESTAMP, val)
2858 #define bfin_write_CAN0_MB12_ID0(val) bfin_write16(CAN0_MB12_ID0, val)
2860 #define bfin_write_CAN0_MB12_ID1(val) bfin_write16(CAN0_MB12_ID1, val)
2862 #define bfin_write_CAN0_MB13_DATA0(val) bfin_write16(CAN0_MB13_DATA0, val)
2864 #define bfin_write_CAN0_MB13_DATA1(val) bfin_write16(CAN0_MB13_DATA1, val)
2866 #define bfin_write_CAN0_MB13_DATA2(val) bfin_write16(CAN0_MB13_DATA2, val)
2868 #define bfin_write_CAN0_MB13_DATA3(val) bfin_write16(CAN0_MB13_DATA3, val)
2870 #define bfin_write_CAN0_MB13_LENGTH(val) bfin_write16(CAN0_MB13_LENGTH, val)
2872 #define bfin_write_CAN0_MB13_TIMESTAMP(val) bfin_write16(CAN0_MB13_TIMESTAMP, val)
2874 #define bfin_write_CAN0_MB13_ID0(val) bfin_write16(CAN0_MB13_ID0, val)
2876 #define bfin_write_CAN0_MB13_ID1(val) bfin_write16(CAN0_MB13_ID1, val)
2878 #define bfin_write_CAN0_MB14_DATA0(val) bfin_write16(CAN0_MB14_DATA0, val)
2880 #define bfin_write_CAN0_MB14_DATA1(val) bfin_write16(CAN0_MB14_DATA1, val)
2882 #define bfin_write_CAN0_MB14_DATA2(val) bfin_write16(CAN0_MB14_DATA2, val)
2884 #define bfin_write_CAN0_MB14_DATA3(val) bfin_write16(CAN0_MB14_DATA3, val)
2886 #define bfin_write_CAN0_MB14_LENGTH(val) bfin_write16(CAN0_MB14_LENGTH, val)
2888 #define bfin_write_CAN0_MB14_TIMESTAMP(val) bfin_write16(CAN0_MB14_TIMESTAMP, val)
2890 #define bfin_write_CAN0_MB14_ID0(val) bfin_write16(CAN0_MB14_ID0, val)
2892 #define bfin_write_CAN0_MB14_ID1(val) bfin_write16(CAN0_MB14_ID1, val)
2894 #define bfin_write_CAN0_MB15_DATA0(val) bfin_write16(CAN0_MB15_DATA0, val)
2896 #define bfin_write_CAN0_MB15_DATA1(val) bfin_write16(CAN0_MB15_DATA1, val)
2898 #define bfin_write_CAN0_MB15_DATA2(val) bfin_write16(CAN0_MB15_DATA2, val)
2900 #define bfin_write_CAN0_MB15_DATA3(val) bfin_write16(CAN0_MB15_DATA3, val)
2902 #define bfin_write_CAN0_MB15_LENGTH(val) bfin_write16(CAN0_MB15_LENGTH, val)
2904 #define bfin_write_CAN0_MB15_TIMESTAMP(val) bfin_write16(CAN0_MB15_TIMESTAMP, val)
2906 #define bfin_write_CAN0_MB15_ID0(val) bfin_write16(CAN0_MB15_ID0, val)
2908 #define bfin_write_CAN0_MB15_ID1(val) bfin_write16(CAN0_MB15_ID1, val)
2913 #define bfin_write_CAN0_MB16_DATA0(val) bfin_write16(CAN0_MB16_DATA0, val)
2915 #define bfin_write_CAN0_MB16_DATA1(val) bfin_write16(CAN0_MB16_DATA1, val)
2917 #define bfin_write_CAN0_MB16_DATA2(val) bfin_write16(CAN0_MB16_DATA2, val)
2919 #define bfin_write_CAN0_MB16_DATA3(val) bfin_write16(CAN0_MB16_DATA3, val)
2921 #define bfin_write_CAN0_MB16_LENGTH(val) bfin_write16(CAN0_MB16_LENGTH, val)
2923 #define bfin_write_CAN0_MB16_TIMESTAMP(val) bfin_write16(CAN0_MB16_TIMESTAMP, val)
2925 #define bfin_write_CAN0_MB16_ID0(val) bfin_write16(CAN0_MB16_ID0, val)
2927 #define bfin_write_CAN0_MB16_ID1(val) bfin_write16(CAN0_MB16_ID1, val)
2929 #define bfin_write_CAN0_MB17_DATA0(val) bfin_write16(CAN0_MB17_DATA0, val)
2931 #define bfin_write_CAN0_MB17_DATA1(val) bfin_write16(CAN0_MB17_DATA1, val)
2933 #define bfin_write_CAN0_MB17_DATA2(val) bfin_write16(CAN0_MB17_DATA2, val)
2935 #define bfin_write_CAN0_MB17_DATA3(val) bfin_write16(CAN0_MB17_DATA3, val)
2937 #define bfin_write_CAN0_MB17_LENGTH(val) bfin_write16(CAN0_MB17_LENGTH, val)
2939 #define bfin_write_CAN0_MB17_TIMESTAMP(val) bfin_write16(CAN0_MB17_TIMESTAMP, val)
2941 #define bfin_write_CAN0_MB17_ID0(val) bfin_write16(CAN0_MB17_ID0, val)
2943 #define bfin_write_CAN0_MB17_ID1(val) bfin_write16(CAN0_MB17_ID1, val)
2945 #define bfin_write_CAN0_MB18_DATA0(val) bfin_write16(CAN0_MB18_DATA0, val)
2947 #define bfin_write_CAN0_MB18_DATA1(val) bfin_write16(CAN0_MB18_DATA1, val)
2949 #define bfin_write_CAN0_MB18_DATA2(val) bfin_write16(CAN0_MB18_DATA2, val)
2951 #define bfin_write_CAN0_MB18_DATA3(val) bfin_write16(CAN0_MB18_DATA3, val)
2953 #define bfin_write_CAN0_MB18_LENGTH(val) bfin_write16(CAN0_MB18_LENGTH, val)
2955 #define bfin_write_CAN0_MB18_TIMESTAMP(val) bfin_write16(CAN0_MB18_TIMESTAMP, val)
2957 #define bfin_write_CAN0_MB18_ID0(val) bfin_write16(CAN0_MB18_ID0, val)
2959 #define bfin_write_CAN0_MB18_ID1(val) bfin_write16(CAN0_MB18_ID1, val)
2961 #define bfin_write_CAN0_MB19_DATA0(val) bfin_write16(CAN0_MB19_DATA0, val)
2963 #define bfin_write_CAN0_MB19_DATA1(val) bfin_write16(CAN0_MB19_DATA1, val)
2965 #define bfin_write_CAN0_MB19_DATA2(val) bfin_write16(CAN0_MB19_DATA2, val)
2967 #define bfin_write_CAN0_MB19_DATA3(val) bfin_write16(CAN0_MB19_DATA3, val)
2969 #define bfin_write_CAN0_MB19_LENGTH(val) bfin_write16(CAN0_MB19_LENGTH, val)
2971 #define bfin_write_CAN0_MB19_TIMESTAMP(val) bfin_write16(CAN0_MB19_TIMESTAMP, val)
2973 #define bfin_write_CAN0_MB19_ID0(val) bfin_write16(CAN0_MB19_ID0, val)
2975 #define bfin_write_CAN0_MB19_ID1(val) bfin_write16(CAN0_MB19_ID1, val)
2977 #define bfin_write_CAN0_MB20_DATA0(val) bfin_write16(CAN0_MB20_DATA0, val)
2979 #define bfin_write_CAN0_MB20_DATA1(val) bfin_write16(CAN0_MB20_DATA1, val)
2981 #define bfin_write_CAN0_MB20_DATA2(val) bfin_write16(CAN0_MB20_DATA2, val)
2983 #define bfin_write_CAN0_MB20_DATA3(val) bfin_write16(CAN0_MB20_DATA3, val)
2985 #define bfin_write_CAN0_MB20_LENGTH(val) bfin_write16(CAN0_MB20_LENGTH, val)
2987 #define bfin_write_CAN0_MB20_TIMESTAMP(val) bfin_write16(CAN0_MB20_TIMESTAMP, val)
2989 #define bfin_write_CAN0_MB20_ID0(val) bfin_write16(CAN0_MB20_ID0, val)
2991 #define bfin_write_CAN0_MB20_ID1(val) bfin_write16(CAN0_MB20_ID1, val)
2993 #define bfin_write_CAN0_MB21_DATA0(val) bfin_write16(CAN0_MB21_DATA0, val)
2995 #define bfin_write_CAN0_MB21_DATA1(val) bfin_write16(CAN0_MB21_DATA1, val)
2997 #define bfin_write_CAN0_MB21_DATA2(val) bfin_write16(CAN0_MB21_DATA2, val)
2999 #define bfin_write_CAN0_MB21_DATA3(val) bfin_write16(CAN0_MB21_DATA3, val)
3001 #define bfin_write_CAN0_MB21_LENGTH(val) bfin_write16(CAN0_MB21_LENGTH, val)
3003 #define bfin_write_CAN0_MB21_TIMESTAMP(val) bfin_write16(CAN0_MB21_TIMESTAMP, val)
3005 #define bfin_write_CAN0_MB21_ID0(val) bfin_write16(CAN0_MB21_ID0, val)
3007 #define bfin_write_CAN0_MB21_ID1(val) bfin_write16(CAN0_MB21_ID1, val)
3009 #define bfin_write_CAN0_MB22_DATA0(val) bfin_write16(CAN0_MB22_DATA0, val)
3011 #define bfin_write_CAN0_MB22_DATA1(val) bfin_write16(CAN0_MB22_DATA1, val)
3013 #define bfin_write_CAN0_MB22_DATA2(val) bfin_write16(CAN0_MB22_DATA2, val)
3015 #define bfin_write_CAN0_MB22_DATA3(val) bfin_write16(CAN0_MB22_DATA3, val)
3017 #define bfin_write_CAN0_MB22_LENGTH(val) bfin_write16(CAN0_MB22_LENGTH, val)
3019 #define bfin_write_CAN0_MB22_TIMESTAMP(val) bfin_write16(CAN0_MB22_TIMESTAMP, val)
3021 #define bfin_write_CAN0_MB22_ID0(val) bfin_write16(CAN0_MB22_ID0, val)
3023 #define bfin_write_CAN0_MB22_ID1(val) bfin_write16(CAN0_MB22_ID1, val)
3025 #define bfin_write_CAN0_MB23_DATA0(val) bfin_write16(CAN0_MB23_DATA0, val)
3027 #define bfin_write_CAN0_MB23_DATA1(val) bfin_write16(CAN0_MB23_DATA1, val)
3029 #define bfin_write_CAN0_MB23_DATA2(val) bfin_write16(CAN0_MB23_DATA2, val)
3031 #define bfin_write_CAN0_MB23_DATA3(val) bfin_write16(CAN0_MB23_DATA3, val)
3033 #define bfin_write_CAN0_MB23_LENGTH(val) bfin_write16(CAN0_MB23_LENGTH, val)
3035 #define bfin_write_CAN0_MB23_TIMESTAMP(val) bfin_write16(CAN0_MB23_TIMESTAMP, val)
3037 #define bfin_write_CAN0_MB23_ID0(val) bfin_write16(CAN0_MB23_ID0, val)
3039 #define bfin_write_CAN0_MB23_ID1(val) bfin_write16(CAN0_MB23_ID1, val)
3041 #define bfin_write_CAN0_MB24_DATA0(val) bfin_write16(CAN0_MB24_DATA0, val)
3043 #define bfin_write_CAN0_MB24_DATA1(val) bfin_write16(CAN0_MB24_DATA1, val)
3045 #define bfin_write_CAN0_MB24_DATA2(val) bfin_write16(CAN0_MB24_DATA2, val)
3047 #define bfin_write_CAN0_MB24_DATA3(val) bfin_write16(CAN0_MB24_DATA3, val)
3049 #define bfin_write_CAN0_MB24_LENGTH(val) bfin_write16(CAN0_MB24_LENGTH, val)
3051 #define bfin_write_CAN0_MB24_TIMESTAMP(val) bfin_write16(CAN0_MB24_TIMESTAMP, val)
3053 #define bfin_write_CAN0_MB24_ID0(val) bfin_write16(CAN0_MB24_ID0, val)
3055 #define bfin_write_CAN0_MB24_ID1(val) bfin_write16(CAN0_MB24_ID1, val)
3057 #define bfin_write_CAN0_MB25_DATA0(val) bfin_write16(CAN0_MB25_DATA0, val)
3059 #define bfin_write_CAN0_MB25_DATA1(val) bfin_write16(CAN0_MB25_DATA1, val)
3061 #define bfin_write_CAN0_MB25_DATA2(val) bfin_write16(CAN0_MB25_DATA2, val)
3063 #define bfin_write_CAN0_MB25_DATA3(val) bfin_write16(CAN0_MB25_DATA3, val)
3065 #define bfin_write_CAN0_MB25_LENGTH(val) bfin_write16(CAN0_MB25_LENGTH, val)
3067 #define bfin_write_CAN0_MB25_TIMESTAMP(val) bfin_write16(CAN0_MB25_TIMESTAMP, val)
3069 #define bfin_write_CAN0_MB25_ID0(val) bfin_write16(CAN0_MB25_ID0, val)
3071 #define bfin_write_CAN0_MB25_ID1(val) bfin_write16(CAN0_MB25_ID1, val)
3073 #define bfin_write_CAN0_MB26_DATA0(val) bfin_write16(CAN0_MB26_DATA0, val)
3075 #define bfin_write_CAN0_MB26_DATA1(val) bfin_write16(CAN0_MB26_DATA1, val)
3077 #define bfin_write_CAN0_MB26_DATA2(val) bfin_write16(CAN0_MB26_DATA2, val)
3079 #define bfin_write_CAN0_MB26_DATA3(val) bfin_write16(CAN0_MB26_DATA3, val)
3081 #define bfin_write_CAN0_MB26_LENGTH(val) bfin_write16(CAN0_MB26_LENGTH, val)
3083 #define bfin_write_CAN0_MB26_TIMESTAMP(val) bfin_write16(CAN0_MB26_TIMESTAMP, val)
3085 #define bfin_write_CAN0_MB26_ID0(val) bfin_write16(CAN0_MB26_ID0, val)
3087 #define bfin_write_CAN0_MB26_ID1(val) bfin_write16(CAN0_MB26_ID1, val)
3089 #define bfin_write_CAN0_MB27_DATA0(val) bfin_write16(CAN0_MB27_DATA0, val)
3091 #define bfin_write_CAN0_MB27_DATA1(val) bfin_write16(CAN0_MB27_DATA1, val)
3093 #define bfin_write_CAN0_MB27_DATA2(val) bfin_write16(CAN0_MB27_DATA2, val)
3095 #define bfin_write_CAN0_MB27_DATA3(val) bfin_write16(CAN0_MB27_DATA3, val)
3097 #define bfin_write_CAN0_MB27_LENGTH(val) bfin_write16(CAN0_MB27_LENGTH, val)
3099 #define bfin_write_CAN0_MB27_TIMESTAMP(val) bfin_write16(CAN0_MB27_TIMESTAMP, val)
3101 #define bfin_write_CAN0_MB27_ID0(val) bfin_write16(CAN0_MB27_ID0, val)
3103 #define bfin_write_CAN0_MB27_ID1(val) bfin_write16(CAN0_MB27_ID1, val)
3105 #define bfin_write_CAN0_MB28_DATA0(val) bfin_write16(CAN0_MB28_DATA0, val)
3107 #define bfin_write_CAN0_MB28_DATA1(val) bfin_write16(CAN0_MB28_DATA1, val)
3109 #define bfin_write_CAN0_MB28_DATA2(val) bfin_write16(CAN0_MB28_DATA2, val)
3111 #define bfin_write_CAN0_MB28_DATA3(val) bfin_write16(CAN0_MB28_DATA3, val)
3113 #define bfin_write_CAN0_MB28_LENGTH(val) bfin_write16(CAN0_MB28_LENGTH, val)
3115 #define bfin_write_CAN0_MB28_TIMESTAMP(val) bfin_write16(CAN0_MB28_TIMESTAMP, val)
3117 #define bfin_write_CAN0_MB28_ID0(val) bfin_write16(CAN0_MB28_ID0, val)
3119 #define bfin_write_CAN0_MB28_ID1(val) bfin_write16(CAN0_MB28_ID1, val)
3121 #define bfin_write_CAN0_MB29_DATA0(val) bfin_write16(CAN0_MB29_DATA0, val)
3123 #define bfin_write_CAN0_MB29_DATA1(val) bfin_write16(CAN0_MB29_DATA1, val)
3125 #define bfin_write_CAN0_MB29_DATA2(val) bfin_write16(CAN0_MB29_DATA2, val)
3127 #define bfin_write_CAN0_MB29_DATA3(val) bfin_write16(CAN0_MB29_DATA3, val)
3129 #define bfin_write_CAN0_MB29_LENGTH(val) bfin_write16(CAN0_MB29_LENGTH, val)
3131 #define bfin_write_CAN0_MB29_TIMESTAMP(val) bfin_write16(CAN0_MB29_TIMESTAMP, val)
3133 #define bfin_write_CAN0_MB29_ID0(val) bfin_write16(CAN0_MB29_ID0, val)
3135 #define bfin_write_CAN0_MB29_ID1(val) bfin_write16(CAN0_MB29_ID1, val)
3137 #define bfin_write_CAN0_MB30_DATA0(val) bfin_write16(CAN0_MB30_DATA0, val)
3139 #define bfin_write_CAN0_MB30_DATA1(val) bfin_write16(CAN0_MB30_DATA1, val)
3141 #define bfin_write_CAN0_MB30_DATA2(val) bfin_write16(CAN0_MB30_DATA2, val)
3143 #define bfin_write_CAN0_MB30_DATA3(val) bfin_write16(CAN0_MB30_DATA3, val)
3145 #define bfin_write_CAN0_MB30_LENGTH(val) bfin_write16(CAN0_MB30_LENGTH, val)
3147 #define bfin_write_CAN0_MB30_TIMESTAMP(val) bfin_write16(CAN0_MB30_TIMESTAMP, val)
3149 #define bfin_write_CAN0_MB30_ID0(val) bfin_write16(CAN0_MB30_ID0, val)
3151 #define bfin_write_CAN0_MB30_ID1(val) bfin_write16(CAN0_MB30_ID1, val)
3153 #define bfin_write_CAN0_MB31_DATA0(val) bfin_write16(CAN0_MB31_DATA0, val)
3155 #define bfin_write_CAN0_MB31_DATA1(val) bfin_write16(CAN0_MB31_DATA1, val)
3157 #define bfin_write_CAN0_MB31_DATA2(val) bfin_write16(CAN0_MB31_DATA2, val)
3159 #define bfin_write_CAN0_MB31_DATA3(val) bfin_write16(CAN0_MB31_DATA3, val)
3161 #define bfin_write_CAN0_MB31_LENGTH(val) bfin_write16(CAN0_MB31_LENGTH, val)
3163 #define bfin_write_CAN0_MB31_TIMESTAMP(val) bfin_write16(CAN0_MB31_TIMESTAMP, val)
3165 #define bfin_write_CAN0_MB31_ID0(val) bfin_write16(CAN0_MB31_ID0, val)
3167 #define bfin_write_CAN0_MB31_ID1(val) bfin_write16(CAN0_MB31_ID1, val)
3172 #define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val)
3174 #define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val)
3176 #define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val)
3178 #define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val)
3180 #define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val)
3182 #define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val)
3184 #define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val)
3186 #define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val)
3190 #define bfin_write_RSI_CLK_CTL(val) bfin_write16(RSI_CLK_CONTROL, val)
3192 #define bfin_write_RSI_ARGUMENT(val) bfin_write32(RSI_ARGUMENT, val)
3194 #define bfin_write_RSI_COMMAND(val) bfin_write16(RSI_COMMAND, val)
3196 #define bfin_write_RSI_RESP_CMD(val) bfin_write16(RSI_RESP_CMD, val)
3198 #define bfin_write_RSI_RESPONSE0(val) bfin_write32(RSI_RESPONSE0, val)
3200 #define bfin_write_RSI_RESPONSE1(val) bfin_write32(RSI_RESPONSE1, val)
3202 #define bfin_write_RSI_RESPONSE2(val) bfin_write32(RSI_RESPONSE2, val)
3204 #define bfin_write_RSI_RESPONSE3(val) bfin_write32(RSI_RESPONSE3, val)
3206 #define bfin_write_RSI_DATA_TIMER(val) bfin_write32(RSI_DATA_TIMER, val)
3208 #define bfin_write_RSI_DATA_LGTH(val) bfin_write16(RSI_DATA_LGTH, val)
3210 #define bfin_write_RSI_DATA_CTL(val) bfin_write16(RSI_DATA_CONTROL, val)
3212 #define bfin_write_RSI_DATA_CNT(val) bfin_write16(RSI_DATA_CNT, val)
3214 #define bfin_write_RSI_STATUS(val) bfin_write32(RSI_STATUS, val)
3216 #define bfin_write_RSI_STATUS_CLR(val) bfin_write16(RSI_STATUSCL, val)
3218 #define bfin_write_RSI_MASK0(val) bfin_write32(RSI_MASK0, val)
3220 #define bfin_write_RSI_MASK1(val) bfin_write32(RSI_MASK1, val)
3222 #define bfin_write_RSI_FIFO_CNT(val) bfin_write16(RSI_FIFO_CNT, val)
3224 #define bfin_write_RSI_CEATA_CONTROL(val) bfin_write16(RSI_CEATA_CONTROL, val)
3226 #define bfin_write_RSI_BLKSZ(val) bfin_write16(RSI_BLKSZ, val)
3228 #define bfin_write_RSI_FIFO(val) bfin_write32(RSI_FIFO, val)
3230 #define bfin_write_RSI_E_STATUS(val) bfin_write32(RSI_ESTAT, val)
3232 #define bfin_write_RSI_E_MASK(val) bfin_write32(RSI_EMASK, val)
3234 #define bfin_write_RSI_CFG(val) bfin_write16(RSI_CONFIG, val)
3236 #define bfin_write_RSI_RD_WAIT_EN(val) bfin_write16(RSI_RD_WAIT_EN, val)
3238 #define bfin_write_RSI_PID0(val) bfin_write16(RSI_PID0, val)
3240 #define bfin_write_RSI_PID1(val) bfin_write16(RSI_PID1, val)
3242 #define bfin_write_RSI_PID2(val) bfin_write16(RSI_PID2, val)
3244 #define bfin_write_RSI_PID3(val) bfin_write16(RSI_PID3, val)
3248 #define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLL_OSC, val)
3249 #define bfin_write_USB_VBUS_CTL(val) bfin_write8(USB_VBUS_CTL, val)
3250 #define bfin_write_USB_APHY_CNTRL(val) bfin_write8(USB_PHY_CTL, val)
/linux-4.1.27/arch/blackfin/mach-bf548/include/mach/
H A DcdefBF548.h19 #define bfin_write_CAN1_MC1(val) bfin_write16(CAN1_MC1, val)
21 #define bfin_write_CAN1_MD1(val) bfin_write16(CAN1_MD1, val)
23 #define bfin_write_CAN1_TRS1(val) bfin_write16(CAN1_TRS1, val)
25 #define bfin_write_CAN1_TRR1(val) bfin_write16(CAN1_TRR1, val)
27 #define bfin_write_CAN1_TA1(val) bfin_write16(CAN1_TA1, val)
29 #define bfin_write_CAN1_AA1(val) bfin_write16(CAN1_AA1, val)
31 #define bfin_write_CAN1_RMP1(val) bfin_write16(CAN1_RMP1, val)
33 #define bfin_write_CAN1_RML1(val) bfin_write16(CAN1_RML1, val)
35 #define bfin_write_CAN1_MBTIF1(val) bfin_write16(CAN1_MBTIF1, val)
37 #define bfin_write_CAN1_MBRIF1(val) bfin_write16(CAN1_MBRIF1, val)
39 #define bfin_write_CAN1_MBIM1(val) bfin_write16(CAN1_MBIM1, val)
41 #define bfin_write_CAN1_RFH1(val) bfin_write16(CAN1_RFH1, val)
43 #define bfin_write_CAN1_OPSS1(val) bfin_write16(CAN1_OPSS1, val)
48 #define bfin_write_CAN1_MC2(val) bfin_write16(CAN1_MC2, val)
50 #define bfin_write_CAN1_MD2(val) bfin_write16(CAN1_MD2, val)
52 #define bfin_write_CAN1_TRS2(val) bfin_write16(CAN1_TRS2, val)
54 #define bfin_write_CAN1_TRR2(val) bfin_write16(CAN1_TRR2, val)
56 #define bfin_write_CAN1_TA2(val) bfin_write16(CAN1_TA2, val)
58 #define bfin_write_CAN1_AA2(val) bfin_write16(CAN1_AA2, val)
60 #define bfin_write_CAN1_RMP2(val) bfin_write16(CAN1_RMP2, val)
62 #define bfin_write_CAN1_RML2(val) bfin_write16(CAN1_RML2, val)
64 #define bfin_write_CAN1_MBTIF2(val) bfin_write16(CAN1_MBTIF2, val)
66 #define bfin_write_CAN1_MBRIF2(val) bfin_write16(CAN1_MBRIF2, val)
68 #define bfin_write_CAN1_MBIM2(val) bfin_write16(CAN1_MBIM2, val)
70 #define bfin_write_CAN1_RFH2(val) bfin_write16(CAN1_RFH2, val)
72 #define bfin_write_CAN1_OPSS2(val) bfin_write16(CAN1_OPSS2, val)
77 #define bfin_write_CAN1_CLOCK(val) bfin_write16(CAN1_CLOCK, val)
79 #define bfin_write_CAN1_TIMING(val) bfin_write16(CAN1_TIMING, val)
81 #define bfin_write_CAN1_DEBUG(val) bfin_write16(CAN1_DEBUG, val)
83 #define bfin_write_CAN1_STATUS(val) bfin_write16(CAN1_STATUS, val)
85 #define bfin_write_CAN1_CEC(val) bfin_write16(CAN1_CEC, val)
87 #define bfin_write_CAN1_GIS(val) bfin_write16(CAN1_GIS, val)
89 #define bfin_write_CAN1_GIM(val) bfin_write16(CAN1_GIM, val)
91 #define bfin_write_CAN1_GIF(val) bfin_write16(CAN1_GIF, val)
93 #define bfin_write_CAN1_CONTROL(val) bfin_write16(CAN1_CONTROL, val)
95 #define bfin_write_CAN1_INTR(val) bfin_write16(CAN1_INTR, val)
97 #define bfin_write_CAN1_MBTD(val) bfin_write16(CAN1_MBTD, val)
99 #define bfin_write_CAN1_EWR(val) bfin_write16(CAN1_EWR, val)
101 #define bfin_write_CAN1_ESR(val) bfin_write16(CAN1_ESR, val)
103 #define bfin_write_CAN1_UCCNT(val) bfin_write16(CAN1_UCCNT, val)
105 #define bfin_write_CAN1_UCRC(val) bfin_write16(CAN1_UCRC, val)
107 #define bfin_write_CAN1_UCCNF(val) bfin_write16(CAN1_UCCNF, val)
112 #define bfin_write_CAN1_AM00L(val) bfin_write16(CAN1_AM00L, val)
114 #define bfin_write_CAN1_AM00H(val) bfin_write16(CAN1_AM00H, val)
116 #define bfin_write_CAN1_AM01L(val) bfin_write16(CAN1_AM01L, val)
118 #define bfin_write_CAN1_AM01H(val) bfin_write16(CAN1_AM01H, val)
120 #define bfin_write_CAN1_AM02L(val) bfin_write16(CAN1_AM02L, val)
122 #define bfin_write_CAN1_AM02H(val) bfin_write16(CAN1_AM02H, val)
124 #define bfin_write_CAN1_AM03L(val) bfin_write16(CAN1_AM03L, val)
126 #define bfin_write_CAN1_AM03H(val) bfin_write16(CAN1_AM03H, val)
128 #define bfin_write_CAN1_AM04L(val) bfin_write16(CAN1_AM04L, val)
130 #define bfin_write_CAN1_AM04H(val) bfin_write16(CAN1_AM04H, val)
132 #define bfin_write_CAN1_AM05L(val) bfin_write16(CAN1_AM05L, val)
134 #define bfin_write_CAN1_AM05H(val) bfin_write16(CAN1_AM05H, val)
136 #define bfin_write_CAN1_AM06L(val) bfin_write16(CAN1_AM06L, val)
138 #define bfin_write_CAN1_AM06H(val) bfin_write16(CAN1_AM06H, val)
140 #define bfin_write_CAN1_AM07L(val) bfin_write16(CAN1_AM07L, val)
142 #define bfin_write_CAN1_AM07H(val) bfin_write16(CAN1_AM07H, val)
144 #define bfin_write_CAN1_AM08L(val) bfin_write16(CAN1_AM08L, val)
146 #define bfin_write_CAN1_AM08H(val) bfin_write16(CAN1_AM08H, val)
148 #define bfin_write_CAN1_AM09L(val) bfin_write16(CAN1_AM09L, val)
150 #define bfin_write_CAN1_AM09H(val) bfin_write16(CAN1_AM09H, val)
152 #define bfin_write_CAN1_AM10L(val) bfin_write16(CAN1_AM10L, val)
154 #define bfin_write_CAN1_AM10H(val) bfin_write16(CAN1_AM10H, val)
156 #define bfin_write_CAN1_AM11L(val) bfin_write16(CAN1_AM11L, val)
158 #define bfin_write_CAN1_AM11H(val) bfin_write16(CAN1_AM11H, val)
160 #define bfin_write_CAN1_AM12L(val) bfin_write16(CAN1_AM12L, val)
162 #define bfin_write_CAN1_AM12H(val) bfin_write16(CAN1_AM12H, val)
164 #define bfin_write_CAN1_AM13L(val) bfin_write16(CAN1_AM13L, val)
166 #define bfin_write_CAN1_AM13H(val) bfin_write16(CAN1_AM13H, val)
168 #define bfin_write_CAN1_AM14L(val) bfin_write16(CAN1_AM14L, val)
170 #define bfin_write_CAN1_AM14H(val) bfin_write16(CAN1_AM14H, val)
172 #define bfin_write_CAN1_AM15L(val) bfin_write16(CAN1_AM15L, val)
174 #define bfin_write_CAN1_AM15H(val) bfin_write16(CAN1_AM15H, val)
179 #define bfin_write_CAN1_AM16L(val) bfin_write16(CAN1_AM16L, val)
181 #define bfin_write_CAN1_AM16H(val) bfin_write16(CAN1_AM16H, val)
183 #define bfin_write_CAN1_AM17L(val) bfin_write16(CAN1_AM17L, val)
185 #define bfin_write_CAN1_AM17H(val) bfin_write16(CAN1_AM17H, val)
187 #define bfin_write_CAN1_AM18L(val) bfin_write16(CAN1_AM18L, val)
189 #define bfin_write_CAN1_AM18H(val) bfin_write16(CAN1_AM18H, val)
191 #define bfin_write_CAN1_AM19L(val) bfin_write16(CAN1_AM19L, val)
193 #define bfin_write_CAN1_AM19H(val) bfin_write16(CAN1_AM19H, val)
195 #define bfin_write_CAN1_AM20L(val) bfin_write16(CAN1_AM20L, val)
197 #define bfin_write_CAN1_AM20H(val) bfin_write16(CAN1_AM20H, val)
199 #define bfin_write_CAN1_AM21L(val) bfin_write16(CAN1_AM21L, val)
201 #define bfin_write_CAN1_AM21H(val) bfin_write16(CAN1_AM21H, val)
203 #define bfin_write_CAN1_AM22L(val) bfin_write16(CAN1_AM22L, val)
205 #define bfin_write_CAN1_AM22H(val) bfin_write16(CAN1_AM22H, val)
207 #define bfin_write_CAN1_AM23L(val) bfin_write16(CAN1_AM23L, val)
209 #define bfin_write_CAN1_AM23H(val) bfin_write16(CAN1_AM23H, val)
211 #define bfin_write_CAN1_AM24L(val) bfin_write16(CAN1_AM24L, val)
213 #define bfin_write_CAN1_AM24H(val) bfin_write16(CAN1_AM24H, val)
215 #define bfin_write_CAN1_AM25L(val) bfin_write16(CAN1_AM25L, val)
217 #define bfin_write_CAN1_AM25H(val) bfin_write16(CAN1_AM25H, val)
219 #define bfin_write_CAN1_AM26L(val) bfin_write16(CAN1_AM26L, val)
221 #define bfin_write_CAN1_AM26H(val) bfin_write16(CAN1_AM26H, val)
223 #define bfin_write_CAN1_AM27L(val) bfin_write16(CAN1_AM27L, val)
225 #define bfin_write_CAN1_AM27H(val) bfin_write16(CAN1_AM27H, val)
227 #define bfin_write_CAN1_AM28L(val) bfin_write16(CAN1_AM28L, val)
229 #define bfin_write_CAN1_AM28H(val) bfin_write16(CAN1_AM28H, val)
231 #define bfin_write_CAN1_AM29L(val) bfin_write16(CAN1_AM29L, val)
233 #define bfin_write_CAN1_AM29H(val) bfin_write16(CAN1_AM29H, val)
235 #define bfin_write_CAN1_AM30L(val) bfin_write16(CAN1_AM30L, val)
237 #define bfin_write_CAN1_AM30H(val) bfin_write16(CAN1_AM30H, val)
239 #define bfin_write_CAN1_AM31L(val) bfin_write16(CAN1_AM31L, val)
241 #define bfin_write_CAN1_AM31H(val) bfin_write16(CAN1_AM31H, val)
246 #define bfin_write_CAN1_MB00_DATA0(val) bfin_write16(CAN1_MB00_DATA0, val)
248 #define bfin_write_CAN1_MB00_DATA1(val) bfin_write16(CAN1_MB00_DATA1, val)
250 #define bfin_write_CAN1_MB00_DATA2(val) bfin_write16(CAN1_MB00_DATA2, val)
252 #define bfin_write_CAN1_MB00_DATA3(val) bfin_write16(CAN1_MB00_DATA3, val)
254 #define bfin_write_CAN1_MB00_LENGTH(val) bfin_write16(CAN1_MB00_LENGTH, val)
256 #define bfin_write_CAN1_MB00_TIMESTAMP(val) bfin_write16(CAN1_MB00_TIMESTAMP, val)
258 #define bfin_write_CAN1_MB00_ID0(val) bfin_write16(CAN1_MB00_ID0, val)
260 #define bfin_write_CAN1_MB00_ID1(val) bfin_write16(CAN1_MB00_ID1, val)
262 #define bfin_write_CAN1_MB01_DATA0(val) bfin_write16(CAN1_MB01_DATA0, val)
264 #define bfin_write_CAN1_MB01_DATA1(val) bfin_write16(CAN1_MB01_DATA1, val)
266 #define bfin_write_CAN1_MB01_DATA2(val) bfin_write16(CAN1_MB01_DATA2, val)
268 #define bfin_write_CAN1_MB01_DATA3(val) bfin_write16(CAN1_MB01_DATA3, val)
270 #define bfin_write_CAN1_MB01_LENGTH(val) bfin_write16(CAN1_MB01_LENGTH, val)
272 #define bfin_write_CAN1_MB01_TIMESTAMP(val) bfin_write16(CAN1_MB01_TIMESTAMP, val)
274 #define bfin_write_CAN1_MB01_ID0(val) bfin_write16(CAN1_MB01_ID0, val)
276 #define bfin_write_CAN1_MB01_ID1(val) bfin_write16(CAN1_MB01_ID1, val)
278 #define bfin_write_CAN1_MB02_DATA0(val) bfin_write16(CAN1_MB02_DATA0, val)
280 #define bfin_write_CAN1_MB02_DATA1(val) bfin_write16(CAN1_MB02_DATA1, val)
282 #define bfin_write_CAN1_MB02_DATA2(val) bfin_write16(CAN1_MB02_DATA2, val)
284 #define bfin_write_CAN1_MB02_DATA3(val) bfin_write16(CAN1_MB02_DATA3, val)
286 #define bfin_write_CAN1_MB02_LENGTH(val) bfin_write16(CAN1_MB02_LENGTH, val)
288 #define bfin_write_CAN1_MB02_TIMESTAMP(val) bfin_write16(CAN1_MB02_TIMESTAMP, val)
290 #define bfin_write_CAN1_MB02_ID0(val) bfin_write16(CAN1_MB02_ID0, val)
292 #define bfin_write_CAN1_MB02_ID1(val) bfin_write16(CAN1_MB02_ID1, val)
294 #define bfin_write_CAN1_MB03_DATA0(val) bfin_write16(CAN1_MB03_DATA0, val)
296 #define bfin_write_CAN1_MB03_DATA1(val) bfin_write16(CAN1_MB03_DATA1, val)
298 #define bfin_write_CAN1_MB03_DATA2(val) bfin_write16(CAN1_MB03_DATA2, val)
300 #define bfin_write_CAN1_MB03_DATA3(val) bfin_write16(CAN1_MB03_DATA3, val)
302 #define bfin_write_CAN1_MB03_LENGTH(val) bfin_write16(CAN1_MB03_LENGTH, val)
304 #define bfin_write_CAN1_MB03_TIMESTAMP(val) bfin_write16(CAN1_MB03_TIMESTAMP, val)
306 #define bfin_write_CAN1_MB03_ID0(val) bfin_write16(CAN1_MB03_ID0, val)
308 #define bfin_write_CAN1_MB03_ID1(val) bfin_write16(CAN1_MB03_ID1, val)
310 #define bfin_write_CAN1_MB04_DATA0(val) bfin_write16(CAN1_MB04_DATA0, val)
312 #define bfin_write_CAN1_MB04_DATA1(val) bfin_write16(CAN1_MB04_DATA1, val)
314 #define bfin_write_CAN1_MB04_DATA2(val) bfin_write16(CAN1_MB04_DATA2, val)
316 #define bfin_write_CAN1_MB04_DATA3(val) bfin_write16(CAN1_MB04_DATA3, val)
318 #define bfin_write_CAN1_MB04_LENGTH(val) bfin_write16(CAN1_MB04_LENGTH, val)
320 #define bfin_write_CAN1_MB04_TIMESTAMP(val) bfin_write16(CAN1_MB04_TIMESTAMP, val)
322 #define bfin_write_CAN1_MB04_ID0(val) bfin_write16(CAN1_MB04_ID0, val)
324 #define bfin_write_CAN1_MB04_ID1(val) bfin_write16(CAN1_MB04_ID1, val)
326 #define bfin_write_CAN1_MB05_DATA0(val) bfin_write16(CAN1_MB05_DATA0, val)
328 #define bfin_write_CAN1_MB05_DATA1(val) bfin_write16(CAN1_MB05_DATA1, val)
330 #define bfin_write_CAN1_MB05_DATA2(val) bfin_write16(CAN1_MB05_DATA2, val)
332 #define bfin_write_CAN1_MB05_DATA3(val) bfin_write16(CAN1_MB05_DATA3, val)
334 #define bfin_write_CAN1_MB05_LENGTH(val) bfin_write16(CAN1_MB05_LENGTH, val)
336 #define bfin_write_CAN1_MB05_TIMESTAMP(val) bfin_write16(CAN1_MB05_TIMESTAMP, val)
338 #define bfin_write_CAN1_MB05_ID0(val) bfin_write16(CAN1_MB05_ID0, val)
340 #define bfin_write_CAN1_MB05_ID1(val) bfin_write16(CAN1_MB05_ID1, val)
342 #define bfin_write_CAN1_MB06_DATA0(val) bfin_write16(CAN1_MB06_DATA0, val)
344 #define bfin_write_CAN1_MB06_DATA1(val) bfin_write16(CAN1_MB06_DATA1, val)
346 #define bfin_write_CAN1_MB06_DATA2(val) bfin_write16(CAN1_MB06_DATA2, val)
348 #define bfin_write_CAN1_MB06_DATA3(val) bfin_write16(CAN1_MB06_DATA3, val)
350 #define bfin_write_CAN1_MB06_LENGTH(val) bfin_write16(CAN1_MB06_LENGTH, val)
352 #define bfin_write_CAN1_MB06_TIMESTAMP(val) bfin_write16(CAN1_MB06_TIMESTAMP, val)
354 #define bfin_write_CAN1_MB06_ID0(val) bfin_write16(CAN1_MB06_ID0, val)
356 #define bfin_write_CAN1_MB06_ID1(val) bfin_write16(CAN1_MB06_ID1, val)
358 #define bfin_write_CAN1_MB07_DATA0(val) bfin_write16(CAN1_MB07_DATA0, val)
360 #define bfin_write_CAN1_MB07_DATA1(val) bfin_write16(CAN1_MB07_DATA1, val)
362 #define bfin_write_CAN1_MB07_DATA2(val) bfin_write16(CAN1_MB07_DATA2, val)
364 #define bfin_write_CAN1_MB07_DATA3(val) bfin_write16(CAN1_MB07_DATA3, val)
366 #define bfin_write_CAN1_MB07_LENGTH(val) bfin_write16(CAN1_MB07_LENGTH, val)
368 #define bfin_write_CAN1_MB07_TIMESTAMP(val) bfin_write16(CAN1_MB07_TIMESTAMP, val)
370 #define bfin_write_CAN1_MB07_ID0(val) bfin_write16(CAN1_MB07_ID0, val)
372 #define bfin_write_CAN1_MB07_ID1(val) bfin_write16(CAN1_MB07_ID1, val)
374 #define bfin_write_CAN1_MB08_DATA0(val) bfin_write16(CAN1_MB08_DATA0, val)
376 #define bfin_write_CAN1_MB08_DATA1(val) bfin_write16(CAN1_MB08_DATA1, val)
378 #define bfin_write_CAN1_MB08_DATA2(val) bfin_write16(CAN1_MB08_DATA2, val)
380 #define bfin_write_CAN1_MB08_DATA3(val) bfin_write16(CAN1_MB08_DATA3, val)
382 #define bfin_write_CAN1_MB08_LENGTH(val) bfin_write16(CAN1_MB08_LENGTH, val)
384 #define bfin_write_CAN1_MB08_TIMESTAMP(val) bfin_write16(CAN1_MB08_TIMESTAMP, val)
386 #define bfin_write_CAN1_MB08_ID0(val) bfin_write16(CAN1_MB08_ID0, val)
388 #define bfin_write_CAN1_MB08_ID1(val) bfin_write16(CAN1_MB08_ID1, val)
390 #define bfin_write_CAN1_MB09_DATA0(val) bfin_write16(CAN1_MB09_DATA0, val)
392 #define bfin_write_CAN1_MB09_DATA1(val) bfin_write16(CAN1_MB09_DATA1, val)
394 #define bfin_write_CAN1_MB09_DATA2(val) bfin_write16(CAN1_MB09_DATA2, val)
396 #define bfin_write_CAN1_MB09_DATA3(val) bfin_write16(CAN1_MB09_DATA3, val)
398 #define bfin_write_CAN1_MB09_LENGTH(val) bfin_write16(CAN1_MB09_LENGTH, val)
400 #define bfin_write_CAN1_MB09_TIMESTAMP(val) bfin_write16(CAN1_MB09_TIMESTAMP, val)
402 #define bfin_write_CAN1_MB09_ID0(val) bfin_write16(CAN1_MB09_ID0, val)
404 #define bfin_write_CAN1_MB09_ID1(val) bfin_write16(CAN1_MB09_ID1, val)
406 #define bfin_write_CAN1_MB10_DATA0(val) bfin_write16(CAN1_MB10_DATA0, val)
408 #define bfin_write_CAN1_MB10_DATA1(val) bfin_write16(CAN1_MB10_DATA1, val)
410 #define bfin_write_CAN1_MB10_DATA2(val) bfin_write16(CAN1_MB10_DATA2, val)
412 #define bfin_write_CAN1_MB10_DATA3(val) bfin_write16(CAN1_MB10_DATA3, val)
414 #define bfin_write_CAN1_MB10_LENGTH(val) bfin_write16(CAN1_MB10_LENGTH, val)
416 #define bfin_write_CAN1_MB10_TIMESTAMP(val) bfin_write16(CAN1_MB10_TIMESTAMP, val)
418 #define bfin_write_CAN1_MB10_ID0(val) bfin_write16(CAN1_MB10_ID0, val)
420 #define bfin_write_CAN1_MB10_ID1(val) bfin_write16(CAN1_MB10_ID1, val)
422 #define bfin_write_CAN1_MB11_DATA0(val) bfin_write16(CAN1_MB11_DATA0, val)
424 #define bfin_write_CAN1_MB11_DATA1(val) bfin_write16(CAN1_MB11_DATA1, val)
426 #define bfin_write_CAN1_MB11_DATA2(val) bfin_write16(CAN1_MB11_DATA2, val)
428 #define bfin_write_CAN1_MB11_DATA3(val) bfin_write16(CAN1_MB11_DATA3, val)
430 #define bfin_write_CAN1_MB11_LENGTH(val) bfin_write16(CAN1_MB11_LENGTH, val)
432 #define bfin_write_CAN1_MB11_TIMESTAMP(val) bfin_write16(CAN1_MB11_TIMESTAMP, val)
434 #define bfin_write_CAN1_MB11_ID0(val) bfin_write16(CAN1_MB11_ID0, val)
436 #define bfin_write_CAN1_MB11_ID1(val) bfin_write16(CAN1_MB11_ID1, val)
438 #define bfin_write_CAN1_MB12_DATA0(val) bfin_write16(CAN1_MB12_DATA0, val)
440 #define bfin_write_CAN1_MB12_DATA1(val) bfin_write16(CAN1_MB12_DATA1, val)
442 #define bfin_write_CAN1_MB12_DATA2(val) bfin_write16(CAN1_MB12_DATA2, val)
444 #define bfin_write_CAN1_MB12_DATA3(val) bfin_write16(CAN1_MB12_DATA3, val)
446 #define bfin_write_CAN1_MB12_LENGTH(val) bfin_write16(CAN1_MB12_LENGTH, val)
448 #define bfin_write_CAN1_MB12_TIMESTAMP(val) bfin_write16(CAN1_MB12_TIMESTAMP, val)
450 #define bfin_write_CAN1_MB12_ID0(val) bfin_write16(CAN1_MB12_ID0, val)
452 #define bfin_write_CAN1_MB12_ID1(val) bfin_write16(CAN1_MB12_ID1, val)
454 #define bfin_write_CAN1_MB13_DATA0(val) bfin_write16(CAN1_MB13_DATA0, val)
456 #define bfin_write_CAN1_MB13_DATA1(val) bfin_write16(CAN1_MB13_DATA1, val)
458 #define bfin_write_CAN1_MB13_DATA2(val) bfin_write16(CAN1_MB13_DATA2, val)
460 #define bfin_write_CAN1_MB13_DATA3(val) bfin_write16(CAN1_MB13_DATA3, val)
462 #define bfin_write_CAN1_MB13_LENGTH(val) bfin_write16(CAN1_MB13_LENGTH, val)
464 #define bfin_write_CAN1_MB13_TIMESTAMP(val) bfin_write16(CAN1_MB13_TIMESTAMP, val)
466 #define bfin_write_CAN1_MB13_ID0(val) bfin_write16(CAN1_MB13_ID0, val)
468 #define bfin_write_CAN1_MB13_ID1(val) bfin_write16(CAN1_MB13_ID1, val)
470 #define bfin_write_CAN1_MB14_DATA0(val) bfin_write16(CAN1_MB14_DATA0, val)
472 #define bfin_write_CAN1_MB14_DATA1(val) bfin_write16(CAN1_MB14_DATA1, val)
474 #define bfin_write_CAN1_MB14_DATA2(val) bfin_write16(CAN1_MB14_DATA2, val)
476 #define bfin_write_CAN1_MB14_DATA3(val) bfin_write16(CAN1_MB14_DATA3, val)
478 #define bfin_write_CAN1_MB14_LENGTH(val) bfin_write16(CAN1_MB14_LENGTH, val)
480 #define bfin_write_CAN1_MB14_TIMESTAMP(val) bfin_write16(CAN1_MB14_TIMESTAMP, val)
482 #define bfin_write_CAN1_MB14_ID0(val) bfin_write16(CAN1_MB14_ID0, val)
484 #define bfin_write_CAN1_MB14_ID1(val) bfin_write16(CAN1_MB14_ID1, val)
486 #define bfin_write_CAN1_MB15_DATA0(val) bfin_write16(CAN1_MB15_DATA0, val)
488 #define bfin_write_CAN1_MB15_DATA1(val) bfin_write16(CAN1_MB15_DATA1, val)
490 #define bfin_write_CAN1_MB15_DATA2(val) bfin_write16(CAN1_MB15_DATA2, val)
492 #define bfin_write_CAN1_MB15_DATA3(val) bfin_write16(CAN1_MB15_DATA3, val)
494 #define bfin_write_CAN1_MB15_LENGTH(val) bfin_write16(CAN1_MB15_LENGTH, val)
496 #define bfin_write_CAN1_MB15_TIMESTAMP(val) bfin_write16(CAN1_MB15_TIMESTAMP, val)
498 #define bfin_write_CAN1_MB15_ID0(val) bfin_write16(CAN1_MB15_ID0, val)
500 #define bfin_write_CAN1_MB15_ID1(val) bfin_write16(CAN1_MB15_ID1, val)
505 #define bfin_write_CAN1_MB16_DATA0(val) bfin_write16(CAN1_MB16_DATA0, val)
507 #define bfin_write_CAN1_MB16_DATA1(val) bfin_write16(CAN1_MB16_DATA1, val)
509 #define bfin_write_CAN1_MB16_DATA2(val) bfin_write16(CAN1_MB16_DATA2, val)
511 #define bfin_write_CAN1_MB16_DATA3(val) bfin_write16(CAN1_MB16_DATA3, val)
513 #define bfin_write_CAN1_MB16_LENGTH(val) bfin_write16(CAN1_MB16_LENGTH, val)
515 #define bfin_write_CAN1_MB16_TIMESTAMP(val) bfin_write16(CAN1_MB16_TIMESTAMP, val)
517 #define bfin_write_CAN1_MB16_ID0(val) bfin_write16(CAN1_MB16_ID0, val)
519 #define bfin_write_CAN1_MB16_ID1(val) bfin_write16(CAN1_MB16_ID1, val)
521 #define bfin_write_CAN1_MB17_DATA0(val) bfin_write16(CAN1_MB17_DATA0, val)
523 #define bfin_write_CAN1_MB17_DATA1(val) bfin_write16(CAN1_MB17_DATA1, val)
525 #define bfin_write_CAN1_MB17_DATA2(val) bfin_write16(CAN1_MB17_DATA2, val)
527 #define bfin_write_CAN1_MB17_DATA3(val) bfin_write16(CAN1_MB17_DATA3, val)
529 #define bfin_write_CAN1_MB17_LENGTH(val) bfin_write16(CAN1_MB17_LENGTH, val)
531 #define bfin_write_CAN1_MB17_TIMESTAMP(val) bfin_write16(CAN1_MB17_TIMESTAMP, val)
533 #define bfin_write_CAN1_MB17_ID0(val) bfin_write16(CAN1_MB17_ID0, val)
535 #define bfin_write_CAN1_MB17_ID1(val) bfin_write16(CAN1_MB17_ID1, val)
537 #define bfin_write_CAN1_MB18_DATA0(val) bfin_write16(CAN1_MB18_DATA0, val)
539 #define bfin_write_CAN1_MB18_DATA1(val) bfin_write16(CAN1_MB18_DATA1, val)
541 #define bfin_write_CAN1_MB18_DATA2(val) bfin_write16(CAN1_MB18_DATA2, val)
543 #define bfin_write_CAN1_MB18_DATA3(val) bfin_write16(CAN1_MB18_DATA3, val)
545 #define bfin_write_CAN1_MB18_LENGTH(val) bfin_write16(CAN1_MB18_LENGTH, val)
547 #define bfin_write_CAN1_MB18_TIMESTAMP(val) bfin_write16(CAN1_MB18_TIMESTAMP, val)
549 #define bfin_write_CAN1_MB18_ID0(val) bfin_write16(CAN1_MB18_ID0, val)
551 #define bfin_write_CAN1_MB18_ID1(val) bfin_write16(CAN1_MB18_ID1, val)
553 #define bfin_write_CAN1_MB19_DATA0(val) bfin_write16(CAN1_MB19_DATA0, val)
555 #define bfin_write_CAN1_MB19_DATA1(val) bfin_write16(CAN1_MB19_DATA1, val)
557 #define bfin_write_CAN1_MB19_DATA2(val) bfin_write16(CAN1_MB19_DATA2, val)
559 #define bfin_write_CAN1_MB19_DATA3(val) bfin_write16(CAN1_MB19_DATA3, val)
561 #define bfin_write_CAN1_MB19_LENGTH(val) bfin_write16(CAN1_MB19_LENGTH, val)
563 #define bfin_write_CAN1_MB19_TIMESTAMP(val) bfin_write16(CAN1_MB19_TIMESTAMP, val)
565 #define bfin_write_CAN1_MB19_ID0(val) bfin_write16(CAN1_MB19_ID0, val)
567 #define bfin_write_CAN1_MB19_ID1(val) bfin_write16(CAN1_MB19_ID1, val)
569 #define bfin_write_CAN1_MB20_DATA0(val) bfin_write16(CAN1_MB20_DATA0, val)
571 #define bfin_write_CAN1_MB20_DATA1(val) bfin_write16(CAN1_MB20_DATA1, val)
573 #define bfin_write_CAN1_MB20_DATA2(val) bfin_write16(CAN1_MB20_DATA2, val)
575 #define bfin_write_CAN1_MB20_DATA3(val) bfin_write16(CAN1_MB20_DATA3, val)
577 #define bfin_write_CAN1_MB20_LENGTH(val) bfin_write16(CAN1_MB20_LENGTH, val)
579 #define bfin_write_CAN1_MB20_TIMESTAMP(val) bfin_write16(CAN1_MB20_TIMESTAMP, val)
581 #define bfin_write_CAN1_MB20_ID0(val) bfin_write16(CAN1_MB20_ID0, val)
583 #define bfin_write_CAN1_MB20_ID1(val) bfin_write16(CAN1_MB20_ID1, val)
585 #define bfin_write_CAN1_MB21_DATA0(val) bfin_write16(CAN1_MB21_DATA0, val)
587 #define bfin_write_CAN1_MB21_DATA1(val) bfin_write16(CAN1_MB21_DATA1, val)
589 #define bfin_write_CAN1_MB21_DATA2(val) bfin_write16(CAN1_MB21_DATA2, val)
591 #define bfin_write_CAN1_MB21_DATA3(val) bfin_write16(CAN1_MB21_DATA3, val)
593 #define bfin_write_CAN1_MB21_LENGTH(val) bfin_write16(CAN1_MB21_LENGTH, val)
595 #define bfin_write_CAN1_MB21_TIMESTAMP(val) bfin_write16(CAN1_MB21_TIMESTAMP, val)
597 #define bfin_write_CAN1_MB21_ID0(val) bfin_write16(CAN1_MB21_ID0, val)
599 #define bfin_write_CAN1_MB21_ID1(val) bfin_write16(CAN1_MB21_ID1, val)
601 #define bfin_write_CAN1_MB22_DATA0(val) bfin_write16(CAN1_MB22_DATA0, val)
603 #define bfin_write_CAN1_MB22_DATA1(val) bfin_write16(CAN1_MB22_DATA1, val)
605 #define bfin_write_CAN1_MB22_DATA2(val) bfin_write16(CAN1_MB22_DATA2, val)
607 #define bfin_write_CAN1_MB22_DATA3(val) bfin_write16(CAN1_MB22_DATA3, val)
609 #define bfin_write_CAN1_MB22_LENGTH(val) bfin_write16(CAN1_MB22_LENGTH, val)
611 #define bfin_write_CAN1_MB22_TIMESTAMP(val) bfin_write16(CAN1_MB22_TIMESTAMP, val)
613 #define bfin_write_CAN1_MB22_ID0(val) bfin_write16(CAN1_MB22_ID0, val)
615 #define bfin_write_CAN1_MB22_ID1(val) bfin_write16(CAN1_MB22_ID1, val)
617 #define bfin_write_CAN1_MB23_DATA0(val) bfin_write16(CAN1_MB23_DATA0, val)
619 #define bfin_write_CAN1_MB23_DATA1(val) bfin_write16(CAN1_MB23_DATA1, val)
621 #define bfin_write_CAN1_MB23_DATA2(val) bfin_write16(CAN1_MB23_DATA2, val)
623 #define bfin_write_CAN1_MB23_DATA3(val) bfin_write16(CAN1_MB23_DATA3, val)
625 #define bfin_write_CAN1_MB23_LENGTH(val) bfin_write16(CAN1_MB23_LENGTH, val)
627 #define bfin_write_CAN1_MB23_TIMESTAMP(val) bfin_write16(CAN1_MB23_TIMESTAMP, val)
629 #define bfin_write_CAN1_MB23_ID0(val) bfin_write16(CAN1_MB23_ID0, val)
631 #define bfin_write_CAN1_MB23_ID1(val) bfin_write16(CAN1_MB23_ID1, val)
633 #define bfin_write_CAN1_MB24_DATA0(val) bfin_write16(CAN1_MB24_DATA0, val)
635 #define bfin_write_CAN1_MB24_DATA1(val) bfin_write16(CAN1_MB24_DATA1, val)
637 #define bfin_write_CAN1_MB24_DATA2(val) bfin_write16(CAN1_MB24_DATA2, val)
639 #define bfin_write_CAN1_MB24_DATA3(val) bfin_write16(CAN1_MB24_DATA3, val)
641 #define bfin_write_CAN1_MB24_LENGTH(val) bfin_write16(CAN1_MB24_LENGTH, val)
643 #define bfin_write_CAN1_MB24_TIMESTAMP(val) bfin_write16(CAN1_MB24_TIMESTAMP, val)
645 #define bfin_write_CAN1_MB24_ID0(val) bfin_write16(CAN1_MB24_ID0, val)
647 #define bfin_write_CAN1_MB24_ID1(val) bfin_write16(CAN1_MB24_ID1, val)
649 #define bfin_write_CAN1_MB25_DATA0(val) bfin_write16(CAN1_MB25_DATA0, val)
651 #define bfin_write_CAN1_MB25_DATA1(val) bfin_write16(CAN1_MB25_DATA1, val)
653 #define bfin_write_CAN1_MB25_DATA2(val) bfin_write16(CAN1_MB25_DATA2, val)
655 #define bfin_write_CAN1_MB25_DATA3(val) bfin_write16(CAN1_MB25_DATA3, val)
657 #define bfin_write_CAN1_MB25_LENGTH(val) bfin_write16(CAN1_MB25_LENGTH, val)
659 #define bfin_write_CAN1_MB25_TIMESTAMP(val) bfin_write16(CAN1_MB25_TIMESTAMP, val)
661 #define bfin_write_CAN1_MB25_ID0(val) bfin_write16(CAN1_MB25_ID0, val)
663 #define bfin_write_CAN1_MB25_ID1(val) bfin_write16(CAN1_MB25_ID1, val)
665 #define bfin_write_CAN1_MB26_DATA0(val) bfin_write16(CAN1_MB26_DATA0, val)
667 #define bfin_write_CAN1_MB26_DATA1(val) bfin_write16(CAN1_MB26_DATA1, val)
669 #define bfin_write_CAN1_MB26_DATA2(val) bfin_write16(CAN1_MB26_DATA2, val)
671 #define bfin_write_CAN1_MB26_DATA3(val) bfin_write16(CAN1_MB26_DATA3, val)
673 #define bfin_write_CAN1_MB26_LENGTH(val) bfin_write16(CAN1_MB26_LENGTH, val)
675 #define bfin_write_CAN1_MB26_TIMESTAMP(val) bfin_write16(CAN1_MB26_TIMESTAMP, val)
677 #define bfin_write_CAN1_MB26_ID0(val) bfin_write16(CAN1_MB26_ID0, val)
679 #define bfin_write_CAN1_MB26_ID1(val) bfin_write16(CAN1_MB26_ID1, val)
681 #define bfin_write_CAN1_MB27_DATA0(val) bfin_write16(CAN1_MB27_DATA0, val)
683 #define bfin_write_CAN1_MB27_DATA1(val) bfin_write16(CAN1_MB27_DATA1, val)
685 #define bfin_write_CAN1_MB27_DATA2(val) bfin_write16(CAN1_MB27_DATA2, val)
687 #define bfin_write_CAN1_MB27_DATA3(val) bfin_write16(CAN1_MB27_DATA3, val)
689 #define bfin_write_CAN1_MB27_LENGTH(val) bfin_write16(CAN1_MB27_LENGTH, val)
691 #define bfin_write_CAN1_MB27_TIMESTAMP(val) bfin_write16(CAN1_MB27_TIMESTAMP, val)
693 #define bfin_write_CAN1_MB27_ID0(val) bfin_write16(CAN1_MB27_ID0, val)
695 #define bfin_write_CAN1_MB27_ID1(val) bfin_write16(CAN1_MB27_ID1, val)
697 #define bfin_write_CAN1_MB28_DATA0(val) bfin_write16(CAN1_MB28_DATA0, val)
699 #define bfin_write_CAN1_MB28_DATA1(val) bfin_write16(CAN1_MB28_DATA1, val)
701 #define bfin_write_CAN1_MB28_DATA2(val) bfin_write16(CAN1_MB28_DATA2, val)
703 #define bfin_write_CAN1_MB28_DATA3(val) bfin_write16(CAN1_MB28_DATA3, val)
705 #define bfin_write_CAN1_MB28_LENGTH(val) bfin_write16(CAN1_MB28_LENGTH, val)
707 #define bfin_write_CAN1_MB28_TIMESTAMP(val) bfin_write16(CAN1_MB28_TIMESTAMP, val)
709 #define bfin_write_CAN1_MB28_ID0(val) bfin_write16(CAN1_MB28_ID0, val)
711 #define bfin_write_CAN1_MB28_ID1(val) bfin_write16(CAN1_MB28_ID1, val)
713 #define bfin_write_CAN1_MB29_DATA0(val) bfin_write16(CAN1_MB29_DATA0, val)
715 #define bfin_write_CAN1_MB29_DATA1(val) bfin_write16(CAN1_MB29_DATA1, val)
717 #define bfin_write_CAN1_MB29_DATA2(val) bfin_write16(CAN1_MB29_DATA2, val)
719 #define bfin_write_CAN1_MB29_DATA3(val) bfin_write16(CAN1_MB29_DATA3, val)
721 #define bfin_write_CAN1_MB29_LENGTH(val) bfin_write16(CAN1_MB29_LENGTH, val)
723 #define bfin_write_CAN1_MB29_TIMESTAMP(val) bfin_write16(CAN1_MB29_TIMESTAMP, val)
725 #define bfin_write_CAN1_MB29_ID0(val) bfin_write16(CAN1_MB29_ID0, val)
727 #define bfin_write_CAN1_MB29_ID1(val) bfin_write16(CAN1_MB29_ID1, val)
729 #define bfin_write_CAN1_MB30_DATA0(val) bfin_write16(CAN1_MB30_DATA0, val)
731 #define bfin_write_CAN1_MB30_DATA1(val) bfin_write16(CAN1_MB30_DATA1, val)
733 #define bfin_write_CAN1_MB30_DATA2(val) bfin_write16(CAN1_MB30_DATA2, val)
735 #define bfin_write_CAN1_MB30_DATA3(val) bfin_write16(CAN1_MB30_DATA3, val)
737 #define bfin_write_CAN1_MB30_LENGTH(val) bfin_write16(CAN1_MB30_LENGTH, val)
739 #define bfin_write_CAN1_MB30_TIMESTAMP(val) bfin_write16(CAN1_MB30_TIMESTAMP, val)
741 #define bfin_write_CAN1_MB30_ID0(val) bfin_write16(CAN1_MB30_ID0, val)
743 #define bfin_write_CAN1_MB30_ID1(val) bfin_write16(CAN1_MB30_ID1, val)
745 #define bfin_write_CAN1_MB31_DATA0(val) bfin_write16(CAN1_MB31_DATA0, val)
747 #define bfin_write_CAN1_MB31_DATA1(val) bfin_write16(CAN1_MB31_DATA1, val)
749 #define bfin_write_CAN1_MB31_DATA2(val) bfin_write16(CAN1_MB31_DATA2, val)
751 #define bfin_write_CAN1_MB31_DATA3(val) bfin_write16(CAN1_MB31_DATA3, val)
753 #define bfin_write_CAN1_MB31_LENGTH(val) bfin_write16(CAN1_MB31_LENGTH, val)
755 #define bfin_write_CAN1_MB31_TIMESTAMP(val) bfin_write16(CAN1_MB31_TIMESTAMP, val)
757 #define bfin_write_CAN1_MB31_ID0(val) bfin_write16(CAN1_MB31_ID0, val)
759 #define bfin_write_CAN1_MB31_ID1(val) bfin_write16(CAN1_MB31_ID1, val)
H A DcdefBF542.h18 #define bfin_write_ATAPI_CONTROL(val) bfin_write16(ATAPI_CONTROL, val)
20 #define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val)
22 #define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val)
24 #define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val)
26 #define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val)
28 #define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val)
30 #define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val)
32 #define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val)
34 #define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val)
36 #define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val)
38 #define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val)
40 #define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val)
42 #define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val)
44 #define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val)
46 #define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
48 #define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val)
50 #define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val)
52 #define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val)
54 #define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val)
56 #define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val)
58 #define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val)
60 #define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val)
62 #define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val)
64 #define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val)
66 #define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val)
71 #define bfin_write_SDH_PWR_CTL(val) bfin_write16(SDH_PWR_CTL, val)
73 #define bfin_write_SDH_CLK_CTL(val) bfin_write16(SDH_CLK_CTL, val)
75 #define bfin_write_SDH_ARGUMENT(val) bfin_write32(SDH_ARGUMENT, val)
77 #define bfin_write_SDH_COMMAND(val) bfin_write16(SDH_COMMAND, val)
79 #define bfin_write_SDH_RESP_CMD(val) bfin_write16(SDH_RESP_CMD, val)
81 #define bfin_write_SDH_RESPONSE0(val) bfin_write32(SDH_RESPONSE0, val)
83 #define bfin_write_SDH_RESPONSE1(val) bfin_write32(SDH_RESPONSE1, val)
85 #define bfin_write_SDH_RESPONSE2(val) bfin_write32(SDH_RESPONSE2, val)
87 #define bfin_write_SDH_RESPONSE3(val) bfin_write32(SDH_RESPONSE3, val)
89 #define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val)
91 #define bfin_write_SDH_DATA_LGTH(val) bfin_write16(SDH_DATA_LGTH, val)
93 #define bfin_write_SDH_DATA_CTL(val) bfin_write16(SDH_DATA_CTL, val)
95 #define bfin_write_SDH_DATA_CNT(val) bfin_write16(SDH_DATA_CNT, val)
97 #define bfin_write_SDH_STATUS(val) bfin_write32(SDH_STATUS, val)
99 #define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val)
101 #define bfin_write_SDH_MASK0(val) bfin_write32(SDH_MASK0, val)
103 #define bfin_write_SDH_MASK1(val) bfin_write32(SDH_MASK1, val)
105 #define bfin_write_SDH_FIFO_CNT(val) bfin_write16(SDH_FIFO_CNT, val)
107 #define bfin_write_SDH_FIFO(val) bfin_write32(SDH_FIFO, val)
109 #define bfin_write_SDH_E_STATUS(val) bfin_write16(SDH_E_STATUS, val)
111 #define bfin_write_SDH_E_MASK(val) bfin_write16(SDH_E_MASK, val)
113 #define bfin_write_SDH_CFG(val) bfin_write16(SDH_CFG, val)
115 #define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val)
117 #define bfin_write_SDH_PID0(val) bfin_write16(SDH_PID0, val)
119 #define bfin_write_SDH_PID1(val) bfin_write16(SDH_PID1, val)
121 #define bfin_write_SDH_PID2(val) bfin_write16(SDH_PID2, val)
123 #define bfin_write_SDH_PID3(val) bfin_write16(SDH_PID3, val)
125 #define bfin_write_SDH_PID4(val) bfin_write16(SDH_PID4, val)
127 #define bfin_write_SDH_PID5(val) bfin_write16(SDH_PID5, val)
129 #define bfin_write_SDH_PID6(val) bfin_write16(SDH_PID6, val)
131 #define bfin_write_SDH_PID7(val) bfin_write16(SDH_PID7, val)
136 #define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
138 #define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val)
140 #define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val)
142 #define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val)
144 #define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val)
146 #define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val)
148 #define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val)
150 #define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val)
152 #define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val)
154 #define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val)
156 #define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val)
158 #define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val)
160 #define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
165 #define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
167 #define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val)
169 #define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val)
171 #define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
173 #define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val)
175 #define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val)
177 #define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val)
179 #define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val)
181 #define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val)
183 #define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
185 #define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val)
187 #define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
189 #define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val)
194 #define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val)
196 #define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val)
198 #define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val)
200 #define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val)
202 #define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val)
204 #define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val)
206 #define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val)
208 #define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val)
213 #define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
215 #define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
217 #define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
222 #define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val)
224 #define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val)
226 #define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val)
228 #define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val)
230 #define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val)
235 #define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
240 #define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
242 #define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
245 #define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
247 #define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
252 #define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
254 #define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
256 #define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
258 #define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
260 #define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
262 #define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
264 #define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
266 #define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
268 #define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
273 #define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
275 #define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
277 #define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
279 #define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
281 #define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
283 #define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
285 #define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
287 #define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
289 #define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
291 #define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
296 #define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
298 #define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
300 #define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
302 #define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
304 #define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
306 #define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
308 #define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
310 #define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
312 #define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
314 #define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
319 #define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
321 #define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
323 #define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
325 #define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
327 #define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
329 #define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
331 #define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
333 #define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
335 #define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
337 #define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
342 #define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
344 #define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
346 #define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
348 #define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
350 #define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
352 #define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
354 #define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
356 #define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
358 #define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
360 #define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
365 #define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
367 #define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
369 #define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
371 #define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
373 #define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
375 #define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
377 #define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
379 #define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
381 #define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
383 #define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
388 #define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
390 #define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
392 #define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
394 #define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
396 #define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
398 #define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
400 #define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
402 #define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
404 #define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
406 #define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
411 #define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
413 #define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
415 #define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
417 #define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
419 #define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
421 #define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
423 #define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
425 #define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
427 #define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
429 #define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
431 #define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
433 #define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
438 #define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val)
440 #define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val)
442 #define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val)
444 #define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val)
446 #define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val)
451 #define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val)
453 #define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val)
455 #define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val)
457 #define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val)
459 #define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val)
464 #define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val)
466 #define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val)
468 #define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val)
470 #define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val)
472 #define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val)
477 #define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val)
479 #define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val)
481 #define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val)
483 #define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val)
485 #define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val)
490 #define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val)
492 #define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val)
494 #define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val)
496 #define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val)
498 #define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val)
503 #define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val)
505 #define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val)
507 #define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val)
509 #define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val)
511 #define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val)
516 #define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val)
518 #define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val)
520 #define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val)
522 #define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val)
524 #define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val)
529 #define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val)
531 #define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val)
533 #define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val)
535 #define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val)
537 #define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val)
542 #define bfin_write_KPAD_CTL(val) bfin_write16(KPAD_CTL, val)
544 #define bfin_write_KPAD_PRESCALE(val) bfin_write16(KPAD_PRESCALE, val)
546 #define bfin_write_KPAD_MSEL(val) bfin_write16(KPAD_MSEL, val)
548 #define bfin_write_KPAD_ROWCOL(val) bfin_write16(KPAD_ROWCOL, val)
550 #define bfin_write_KPAD_STAT(val) bfin_write16(KPAD_STAT, val)
552 #define bfin_write_KPAD_SOFTEVAL(val) bfin_write16(KPAD_SOFTEVAL, val)
H A DcdefBF547.h18 #define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val)
20 #define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
22 #define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val)
24 #define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val)
26 #define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val)
28 #define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
30 #define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val)
32 #define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val)
34 #define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
36 #define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
38 #define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
40 #define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val)
45 #define bfin_write_TIMER_ENABLE1(val) bfin_write16(TIMER_ENABLE1, val)
47 #define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)
49 #define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val)
54 #define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
56 #define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
58 #define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
60 #define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
62 #define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
64 #define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
66 #define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
68 #define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
70 #define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
72 #define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
74 #define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
76 #define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
78 #define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
80 #define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
82 #define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
84 #define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
86 #define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
88 #define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
90 #define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
92 #define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
94 #define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
96 #define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
101 #define bfin_write_EPPI0_STATUS(val) bfin_write16(EPPI0_STATUS, val)
103 #define bfin_write_EPPI0_HCOUNT(val) bfin_write16(EPPI0_HCOUNT, val)
105 #define bfin_write_EPPI0_HDELAY(val) bfin_write16(EPPI0_HDELAY, val)
107 #define bfin_write_EPPI0_VCOUNT(val) bfin_write16(EPPI0_VCOUNT, val)
109 #define bfin_write_EPPI0_VDELAY(val) bfin_write16(EPPI0_VDELAY, val)
111 #define bfin_write_EPPI0_FRAME(val) bfin_write16(EPPI0_FRAME, val)
113 #define bfin_write_EPPI0_LINE(val) bfin_write16(EPPI0_LINE, val)
115 #define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val)
117 #define bfin_write_EPPI0_CONTROL(val) bfin_write32(EPPI0_CONTROL, val)
119 #define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val)
121 #define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)
123 #define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val)
125 #define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)
127 #define bfin_write_EPPI0_CLIP(val) bfin_write32(EPPI0_CLIP, val)
132 #define bfin_write_UART2_DLL(val) bfin_write16(UART2_DLL, val)
134 #define bfin_write_UART2_DLH(val) bfin_write16(UART2_DLH, val)
136 #define bfin_write_UART2_GCTL(val) bfin_write16(UART2_GCTL, val)
138 #define bfin_write_UART2_LCR(val) bfin_write16(UART2_LCR, val)
140 #define bfin_write_UART2_MCR(val) bfin_write16(UART2_MCR, val)
142 #define bfin_write_UART2_LSR(val) bfin_write16(UART2_LSR, val)
144 #define bfin_write_UART2_MSR(val) bfin_write16(UART2_MSR, val)
146 #define bfin_write_UART2_SCR(val) bfin_write16(UART2_SCR, val)
148 #define bfin_write_UART2_IER_SET(val) bfin_write16(UART2_IER_SET, val)
150 #define bfin_write_UART2_IER_CLEAR(val) bfin_write16(UART2_IER_CLEAR, val)
152 #define bfin_write_UART2_RBR(val) bfin_write16(UART2_RBR, val)
159 #define bfin_write_SPI2_CTL(val) bfin_write16(SPI2_CTL, val)
161 #define bfin_write_SPI2_FLG(val) bfin_write16(SPI2_FLG, val)
163 #define bfin_write_SPI2_STAT(val) bfin_write16(SPI2_STAT, val)
165 #define bfin_write_SPI2_TDBR(val) bfin_write16(SPI2_TDBR, val)
167 #define bfin_write_SPI2_RDBR(val) bfin_write16(SPI2_RDBR, val)
169 #define bfin_write_SPI2_BAUD(val) bfin_write16(SPI2_BAUD, val)
171 #define bfin_write_SPI2_SHADOW(val) bfin_write16(SPI2_SHADOW, val)
176 #define bfin_write_ATAPI_CONTROL(val) bfin_write16(ATAPI_CONTROL, val)
178 #define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val)
180 #define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val)
182 #define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val)
184 #define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val)
186 #define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val)
188 #define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val)
190 #define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val)
192 #define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val)
194 #define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val)
196 #define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val)
198 #define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val)
200 #define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val)
202 #define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val)
204 #define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
206 #define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val)
208 #define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val)
210 #define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val)
212 #define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val)
214 #define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val)
216 #define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val)
218 #define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val)
220 #define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val)
222 #define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val)
224 #define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val)
229 #define bfin_write_SDH_PWR_CTL(val) bfin_write16(SDH_PWR_CTL, val)
231 #define bfin_write_SDH_CLK_CTL(val) bfin_write16(SDH_CLK_CTL, val)
233 #define bfin_write_SDH_ARGUMENT(val) bfin_write32(SDH_ARGUMENT, val)
235 #define bfin_write_SDH_COMMAND(val) bfin_write16(SDH_COMMAND, val)
237 #define bfin_write_SDH_RESP_CMD(val) bfin_write16(SDH_RESP_CMD, val)
239 #define bfin_write_SDH_RESPONSE0(val) bfin_write32(SDH_RESPONSE0, val)
241 #define bfin_write_SDH_RESPONSE1(val) bfin_write32(SDH_RESPONSE1, val)
243 #define bfin_write_SDH_RESPONSE2(val) bfin_write32(SDH_RESPONSE2, val)
245 #define bfin_write_SDH_RESPONSE3(val) bfin_write32(SDH_RESPONSE3, val)
247 #define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val)
249 #define bfin_write_SDH_DATA_LGTH(val) bfin_write16(SDH_DATA_LGTH, val)
251 #define bfin_write_SDH_DATA_CTL(val) bfin_write16(SDH_DATA_CTL, val)
253 #define bfin_write_SDH_DATA_CNT(val) bfin_write16(SDH_DATA_CNT, val)
255 #define bfin_write_SDH_STATUS(val) bfin_write32(SDH_STATUS, val)
257 #define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val)
259 #define bfin_write_SDH_MASK0(val) bfin_write32(SDH_MASK0, val)
261 #define bfin_write_SDH_MASK1(val) bfin_write32(SDH_MASK1, val)
263 #define bfin_write_SDH_FIFO_CNT(val) bfin_write16(SDH_FIFO_CNT, val)
265 #define bfin_write_SDH_FIFO(val) bfin_write32(SDH_FIFO, val)
267 #define bfin_write_SDH_E_STATUS(val) bfin_write16(SDH_E_STATUS, val)
269 #define bfin_write_SDH_E_MASK(val) bfin_write16(SDH_E_MASK, val)
271 #define bfin_write_SDH_CFG(val) bfin_write16(SDH_CFG, val)
273 #define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val)
275 #define bfin_write_SDH_PID0(val) bfin_write16(SDH_PID0, val)
277 #define bfin_write_SDH_PID1(val) bfin_write16(SDH_PID1, val)
279 #define bfin_write_SDH_PID2(val) bfin_write16(SDH_PID2, val)
281 #define bfin_write_SDH_PID3(val) bfin_write16(SDH_PID3, val)
283 #define bfin_write_SDH_PID4(val) bfin_write16(SDH_PID4, val)
285 #define bfin_write_SDH_PID5(val) bfin_write16(SDH_PID5, val)
287 #define bfin_write_SDH_PID6(val) bfin_write16(SDH_PID6, val)
289 #define bfin_write_SDH_PID7(val) bfin_write16(SDH_PID7, val)
294 #define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val)
296 #define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val)
298 #define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val)
303 #define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
305 #define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val)
307 #define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val)
309 #define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val)
311 #define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val)
313 #define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val)
315 #define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val)
317 #define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val)
319 #define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val)
321 #define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val)
323 #define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val)
325 #define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val)
327 #define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
332 #define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
334 #define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val)
336 #define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val)
338 #define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
340 #define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val)
342 #define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val)
344 #define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val)
346 #define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val)
348 #define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val)
350 #define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
352 #define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val)
354 #define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
356 #define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val)
361 #define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val)
363 #define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val)
365 #define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val)
367 #define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val)
369 #define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val)
371 #define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val)
373 #define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val)
375 #define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val)
380 #define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
382 #define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
384 #define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
389 #define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val)
391 #define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val)
393 #define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val)
395 #define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val)
397 #define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val)
402 #define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
407 #define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
409 #define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
412 #define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
414 #define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
419 #define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
421 #define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
423 #define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
425 #define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
427 #define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
429 #define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
431 #define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
433 #define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
435 #define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
440 #define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
442 #define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
444 #define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
446 #define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
448 #define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
450 #define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
452 #define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
454 #define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
456 #define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
458 #define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
463 #define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
465 #define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
467 #define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
469 #define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
471 #define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
473 #define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
475 #define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
477 #define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
479 #define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
481 #define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
486 #define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
488 #define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
490 #define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
492 #define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
494 #define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
496 #define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
498 #define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
500 #define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
502 #define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
504 #define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
509 #define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
511 #define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
513 #define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
515 #define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
517 #define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
519 #define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
521 #define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
523 #define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
525 #define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
527 #define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
532 #define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
534 #define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
536 #define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
538 #define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
540 #define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
542 #define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
544 #define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
546 #define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
548 #define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
550 #define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
555 #define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
557 #define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
559 #define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
561 #define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
563 #define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
565 #define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
567 #define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
569 #define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
571 #define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
573 #define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
578 #define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
580 #define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
582 #define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
584 #define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
586 #define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
588 #define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
590 #define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
592 #define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
594 #define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
596 #define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
598 #define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
600 #define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
605 #define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val)
607 #define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val)
609 #define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val)
611 #define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val)
613 #define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val)
618 #define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val)
620 #define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val)
622 #define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val)
624 #define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val)
626 #define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val)
631 #define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val)
633 #define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val)
635 #define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val)
637 #define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val)
639 #define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val)
644 #define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val)
646 #define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val)
648 #define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val)
650 #define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val)
652 #define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val)
657 #define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val)
659 #define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val)
661 #define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val)
663 #define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val)
665 #define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val)
670 #define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val)
672 #define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val)
674 #define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val)
676 #define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val)
678 #define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val)
683 #define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val)
685 #define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val)
687 #define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val)
689 #define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val)
691 #define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val)
696 #define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val)
698 #define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val)
700 #define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val)
702 #define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val)
704 #define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val)
709 #define bfin_write_KPAD_CTL(val) bfin_write16(KPAD_CTL, val)
711 #define bfin_write_KPAD_PRESCALE(val) bfin_write16(KPAD_PRESCALE, val)
713 #define bfin_write_KPAD_MSEL(val) bfin_write16(KPAD_MSEL, val)
715 #define bfin_write_KPAD_ROWCOL(val) bfin_write16(KPAD_ROWCOL, val)
717 #define bfin_write_KPAD_STAT(val) bfin_write16(KPAD_STAT, val)
719 #define bfin_write_KPAD_SOFTEVAL(val) bfin_write16(KPAD_SOFTEVAL, val)
724 #define bfin_write_PIXC_CTL(val) bfin_write16(PIXC_CTL, val)
726 #define bfin_write_PIXC_PPL(val) bfin_write16(PIXC_PPL, val)
728 #define bfin_write_PIXC_LPF(val) bfin_write16(PIXC_LPF, val)
730 #define bfin_write_PIXC_AHSTART(val) bfin_write16(PIXC_AHSTART, val)
732 #define bfin_write_PIXC_AHEND(val) bfin_write16(PIXC_AHEND, val)
734 #define bfin_write_PIXC_AVSTART(val) bfin_write16(PIXC_AVSTART, val)
736 #define bfin_write_PIXC_AVEND(val) bfin_write16(PIXC_AVEND, val)
738 #define bfin_write_PIXC_ATRANSP(val) bfin_write16(PIXC_ATRANSP, val)
740 #define bfin_write_PIXC_BHSTART(val) bfin_write16(PIXC_BHSTART, val)
742 #define bfin_write_PIXC_BHEND(val) bfin_write16(PIXC_BHEND, val)
744 #define bfin_write_PIXC_BVSTART(val) bfin_write16(PIXC_BVSTART, val)
746 #define bfin_write_PIXC_BVEND(val) bfin_write16(PIXC_BVEND, val)
748 #define bfin_write_PIXC_BTRANSP(val) bfin_write16(PIXC_BTRANSP, val)
750 #define bfin_write_PIXC_INTRSTAT(val) bfin_write16(PIXC_INTRSTAT, val)
752 #define bfin_write_PIXC_RYCON(val) bfin_write32(PIXC_RYCON, val)
754 #define bfin_write_PIXC_GUCON(val) bfin_write32(PIXC_GUCON, val)
756 #define bfin_write_PIXC_BVCON(val) bfin_write32(PIXC_BVCON, val)
758 #define bfin_write_PIXC_CCBIAS(val) bfin_write32(PIXC_CCBIAS, val)
760 #define bfin_write_PIXC_TC(val) bfin_write32(PIXC_TC, val)
765 #define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
767 #define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
769 #define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
771 #define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
773 #define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
775 #define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
777 #define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
782 #define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
784 #define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
786 #define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
788 #define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
790 #define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
792 #define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
794 #define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
H A DcdefBF544.h18 #define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val)
20 #define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
22 #define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val)
24 #define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val)
26 #define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val)
28 #define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
30 #define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val)
32 #define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val)
34 #define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
36 #define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
38 #define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
40 #define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val)
45 #define bfin_write_TIMER_ENABLE1(val) bfin_write16(TIMER_ENABLE1, val)
47 #define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)
49 #define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val)
54 #define bfin_write_EPPI0_STATUS(val) bfin_write16(EPPI0_STATUS, val)
56 #define bfin_write_EPPI0_HCOUNT(val) bfin_write16(EPPI0_HCOUNT, val)
58 #define bfin_write_EPPI0_HDELAY(val) bfin_write16(EPPI0_HDELAY, val)
60 #define bfin_write_EPPI0_VCOUNT(val) bfin_write16(EPPI0_VCOUNT, val)
62 #define bfin_write_EPPI0_VDELAY(val) bfin_write16(EPPI0_VDELAY, val)
64 #define bfin_write_EPPI0_FRAME(val) bfin_write16(EPPI0_FRAME, val)
66 #define bfin_write_EPPI0_LINE(val) bfin_write16(EPPI0_LINE, val)
68 #define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val)
70 #define bfin_write_EPPI0_CONTROL(val) bfin_write32(EPPI0_CONTROL, val)
72 #define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val)
74 #define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)
76 #define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val)
78 #define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)
80 #define bfin_write_EPPI0_CLIP(val) bfin_write32(EPPI0_CLIP, val)
87 #define bfin_write_CAN1_MC1(val) bfin_write16(CAN1_MC1, val)
89 #define bfin_write_CAN1_MD1(val) bfin_write16(CAN1_MD1, val)
91 #define bfin_write_CAN1_TRS1(val) bfin_write16(CAN1_TRS1, val)
93 #define bfin_write_CAN1_TRR1(val) bfin_write16(CAN1_TRR1, val)
95 #define bfin_write_CAN1_TA1(val) bfin_write16(CAN1_TA1, val)
97 #define bfin_write_CAN1_AA1(val) bfin_write16(CAN1_AA1, val)
99 #define bfin_write_CAN1_RMP1(val) bfin_write16(CAN1_RMP1, val)
101 #define bfin_write_CAN1_RML1(val) bfin_write16(CAN1_RML1, val)
103 #define bfin_write_CAN1_MBTIF1(val) bfin_write16(CAN1_MBTIF1, val)
105 #define bfin_write_CAN1_MBRIF1(val) bfin_write16(CAN1_MBRIF1, val)
107 #define bfin_write_CAN1_MBIM1(val) bfin_write16(CAN1_MBIM1, val)
109 #define bfin_write_CAN1_RFH1(val) bfin_write16(CAN1_RFH1, val)
111 #define bfin_write_CAN1_OPSS1(val) bfin_write16(CAN1_OPSS1, val)
116 #define bfin_write_CAN1_MC2(val) bfin_write16(CAN1_MC2, val)
118 #define bfin_write_CAN1_MD2(val) bfin_write16(CAN1_MD2, val)
120 #define bfin_write_CAN1_TRS2(val) bfin_write16(CAN1_TRS2, val)
122 #define bfin_write_CAN1_TRR2(val) bfin_write16(CAN1_TRR2, val)
124 #define bfin_write_CAN1_TA2(val) bfin_write16(CAN1_TA2, val)
126 #define bfin_write_CAN1_AA2(val) bfin_write16(CAN1_AA2, val)
128 #define bfin_write_CAN1_RMP2(val) bfin_write16(CAN1_RMP2, val)
130 #define bfin_write_CAN1_RML2(val) bfin_write16(CAN1_RML2, val)
132 #define bfin_write_CAN1_MBTIF2(val) bfin_write16(CAN1_MBTIF2, val)
134 #define bfin_write_CAN1_MBRIF2(val) bfin_write16(CAN1_MBRIF2, val)
136 #define bfin_write_CAN1_MBIM2(val) bfin_write16(CAN1_MBIM2, val)
138 #define bfin_write_CAN1_RFH2(val) bfin_write16(CAN1_RFH2, val)
140 #define bfin_write_CAN1_OPSS2(val) bfin_write16(CAN1_OPSS2, val)
145 #define bfin_write_CAN1_CLOCK(val) bfin_write16(CAN1_CLOCK, val)
147 #define bfin_write_CAN1_TIMING(val) bfin_write16(CAN1_TIMING, val)
149 #define bfin_write_CAN1_DEBUG(val) bfin_write16(CAN1_DEBUG, val)
151 #define bfin_write_CAN1_STATUS(val) bfin_write16(CAN1_STATUS, val)
153 #define bfin_write_CAN1_CEC(val) bfin_write16(CAN1_CEC, val)
155 #define bfin_write_CAN1_GIS(val) bfin_write16(CAN1_GIS, val)
157 #define bfin_write_CAN1_GIM(val) bfin_write16(CAN1_GIM, val)
159 #define bfin_write_CAN1_GIF(val) bfin_write16(CAN1_GIF, val)
161 #define bfin_write_CAN1_CONTROL(val) bfin_write16(CAN1_CONTROL, val)
163 #define bfin_write_CAN1_INTR(val) bfin_write16(CAN1_INTR, val)
165 #define bfin_write_CAN1_MBTD(val) bfin_write16(CAN1_MBTD, val)
167 #define bfin_write_CAN1_EWR(val) bfin_write16(CAN1_EWR, val)
169 #define bfin_write_CAN1_ESR(val) bfin_write16(CAN1_ESR, val)
171 #define bfin_write_CAN1_UCCNT(val) bfin_write16(CAN1_UCCNT, val)
173 #define bfin_write_CAN1_UCRC(val) bfin_write16(CAN1_UCRC, val)
175 #define bfin_write_CAN1_UCCNF(val) bfin_write16(CAN1_UCCNF, val)
180 #define bfin_write_CAN1_AM00L(val) bfin_write16(CAN1_AM00L, val)
182 #define bfin_write_CAN1_AM00H(val) bfin_write16(CAN1_AM00H, val)
184 #define bfin_write_CAN1_AM01L(val) bfin_write16(CAN1_AM01L, val)
186 #define bfin_write_CAN1_AM01H(val) bfin_write16(CAN1_AM01H, val)
188 #define bfin_write_CAN1_AM02L(val) bfin_write16(CAN1_AM02L, val)
190 #define bfin_write_CAN1_AM02H(val) bfin_write16(CAN1_AM02H, val)
192 #define bfin_write_CAN1_AM03L(val) bfin_write16(CAN1_AM03L, val)
194 #define bfin_write_CAN1_AM03H(val) bfin_write16(CAN1_AM03H, val)
196 #define bfin_write_CAN1_AM04L(val) bfin_write16(CAN1_AM04L, val)
198 #define bfin_write_CAN1_AM04H(val) bfin_write16(CAN1_AM04H, val)
200 #define bfin_write_CAN1_AM05L(val) bfin_write16(CAN1_AM05L, val)
202 #define bfin_write_CAN1_AM05H(val) bfin_write16(CAN1_AM05H, val)
204 #define bfin_write_CAN1_AM06L(val) bfin_write16(CAN1_AM06L, val)
206 #define bfin_write_CAN1_AM06H(val) bfin_write16(CAN1_AM06H, val)
208 #define bfin_write_CAN1_AM07L(val) bfin_write16(CAN1_AM07L, val)
210 #define bfin_write_CAN1_AM07H(val) bfin_write16(CAN1_AM07H, val)
212 #define bfin_write_CAN1_AM08L(val) bfin_write16(CAN1_AM08L, val)
214 #define bfin_write_CAN1_AM08H(val) bfin_write16(CAN1_AM08H, val)
216 #define bfin_write_CAN1_AM09L(val) bfin_write16(CAN1_AM09L, val)
218 #define bfin_write_CAN1_AM09H(val) bfin_write16(CAN1_AM09H, val)
220 #define bfin_write_CAN1_AM10L(val) bfin_write16(CAN1_AM10L, val)
222 #define bfin_write_CAN1_AM10H(val) bfin_write16(CAN1_AM10H, val)
224 #define bfin_write_CAN1_AM11L(val) bfin_write16(CAN1_AM11L, val)
226 #define bfin_write_CAN1_AM11H(val) bfin_write16(CAN1_AM11H, val)
228 #define bfin_write_CAN1_AM12L(val) bfin_write16(CAN1_AM12L, val)
230 #define bfin_write_CAN1_AM12H(val) bfin_write16(CAN1_AM12H, val)
232 #define bfin_write_CAN1_AM13L(val) bfin_write16(CAN1_AM13L, val)
234 #define bfin_write_CAN1_AM13H(val) bfin_write16(CAN1_AM13H, val)
236 #define bfin_write_CAN1_AM14L(val) bfin_write16(CAN1_AM14L, val)
238 #define bfin_write_CAN1_AM14H(val) bfin_write16(CAN1_AM14H, val)
240 #define bfin_write_CAN1_AM15L(val) bfin_write16(CAN1_AM15L, val)
242 #define bfin_write_CAN1_AM15H(val) bfin_write16(CAN1_AM15H, val)
247 #define bfin_write_CAN1_AM16L(val) bfin_write16(CAN1_AM16L, val)
249 #define bfin_write_CAN1_AM16H(val) bfin_write16(CAN1_AM16H, val)
251 #define bfin_write_CAN1_AM17L(val) bfin_write16(CAN1_AM17L, val)
253 #define bfin_write_CAN1_AM17H(val) bfin_write16(CAN1_AM17H, val)
255 #define bfin_write_CAN1_AM18L(val) bfin_write16(CAN1_AM18L, val)
257 #define bfin_write_CAN1_AM18H(val) bfin_write16(CAN1_AM18H, val)
259 #define bfin_write_CAN1_AM19L(val) bfin_write16(CAN1_AM19L, val)
261 #define bfin_write_CAN1_AM19H(val) bfin_write16(CAN1_AM19H, val)
263 #define bfin_write_CAN1_AM20L(val) bfin_write16(CAN1_AM20L, val)
265 #define bfin_write_CAN1_AM20H(val) bfin_write16(CAN1_AM20H, val)
267 #define bfin_write_CAN1_AM21L(val) bfin_write16(CAN1_AM21L, val)
269 #define bfin_write_CAN1_AM21H(val) bfin_write16(CAN1_AM21H, val)
271 #define bfin_write_CAN1_AM22L(val) bfin_write16(CAN1_AM22L, val)
273 #define bfin_write_CAN1_AM22H(val) bfin_write16(CAN1_AM22H, val)
275 #define bfin_write_CAN1_AM23L(val) bfin_write16(CAN1_AM23L, val)
277 #define bfin_write_CAN1_AM23H(val) bfin_write16(CAN1_AM23H, val)
279 #define bfin_write_CAN1_AM24L(val) bfin_write16(CAN1_AM24L, val)
281 #define bfin_write_CAN1_AM24H(val) bfin_write16(CAN1_AM24H, val)
283 #define bfin_write_CAN1_AM25L(val) bfin_write16(CAN1_AM25L, val)
285 #define bfin_write_CAN1_AM25H(val) bfin_write16(CAN1_AM25H, val)
287 #define bfin_write_CAN1_AM26L(val) bfin_write16(CAN1_AM26L, val)
289 #define bfin_write_CAN1_AM26H(val) bfin_write16(CAN1_AM26H, val)
291 #define bfin_write_CAN1_AM27L(val) bfin_write16(CAN1_AM27L, val)
293 #define bfin_write_CAN1_AM27H(val) bfin_write16(CAN1_AM27H, val)
295 #define bfin_write_CAN1_AM28L(val) bfin_write16(CAN1_AM28L, val)
297 #define bfin_write_CAN1_AM28H(val) bfin_write16(CAN1_AM28H, val)
299 #define bfin_write_CAN1_AM29L(val) bfin_write16(CAN1_AM29L, val)
301 #define bfin_write_CAN1_AM29H(val) bfin_write16(CAN1_AM29H, val)
303 #define bfin_write_CAN1_AM30L(val) bfin_write16(CAN1_AM30L, val)
305 #define bfin_write_CAN1_AM30H(val) bfin_write16(CAN1_AM30H, val)
307 #define bfin_write_CAN1_AM31L(val) bfin_write16(CAN1_AM31L, val)
309 #define bfin_write_CAN1_AM31H(val) bfin_write16(CAN1_AM31H, val)
314 #define bfin_write_CAN1_MB00_DATA0(val) bfin_write16(CAN1_MB00_DATA0, val)
316 #define bfin_write_CAN1_MB00_DATA1(val) bfin_write16(CAN1_MB00_DATA1, val)
318 #define bfin_write_CAN1_MB00_DATA2(val) bfin_write16(CAN1_MB00_DATA2, val)
320 #define bfin_write_CAN1_MB00_DATA3(val) bfin_write16(CAN1_MB00_DATA3, val)
322 #define bfin_write_CAN1_MB00_LENGTH(val) bfin_write16(CAN1_MB00_LENGTH, val)
324 #define bfin_write_CAN1_MB00_TIMESTAMP(val) bfin_write16(CAN1_MB00_TIMESTAMP, val)
326 #define bfin_write_CAN1_MB00_ID0(val) bfin_write16(CAN1_MB00_ID0, val)
328 #define bfin_write_CAN1_MB00_ID1(val) bfin_write16(CAN1_MB00_ID1, val)
330 #define bfin_write_CAN1_MB01_DATA0(val) bfin_write16(CAN1_MB01_DATA0, val)
332 #define bfin_write_CAN1_MB01_DATA1(val) bfin_write16(CAN1_MB01_DATA1, val)
334 #define bfin_write_CAN1_MB01_DATA2(val) bfin_write16(CAN1_MB01_DATA2, val)
336 #define bfin_write_CAN1_MB01_DATA3(val) bfin_write16(CAN1_MB01_DATA3, val)
338 #define bfin_write_CAN1_MB01_LENGTH(val) bfin_write16(CAN1_MB01_LENGTH, val)
340 #define bfin_write_CAN1_MB01_TIMESTAMP(val) bfin_write16(CAN1_MB01_TIMESTAMP, val)
342 #define bfin_write_CAN1_MB01_ID0(val) bfin_write16(CAN1_MB01_ID0, val)
344 #define bfin_write_CAN1_MB01_ID1(val) bfin_write16(CAN1_MB01_ID1, val)
346 #define bfin_write_CAN1_MB02_DATA0(val) bfin_write16(CAN1_MB02_DATA0, val)
348 #define bfin_write_CAN1_MB02_DATA1(val) bfin_write16(CAN1_MB02_DATA1, val)
350 #define bfin_write_CAN1_MB02_DATA2(val) bfin_write16(CAN1_MB02_DATA2, val)
352 #define bfin_write_CAN1_MB02_DATA3(val) bfin_write16(CAN1_MB02_DATA3, val)
354 #define bfin_write_CAN1_MB02_LENGTH(val) bfin_write16(CAN1_MB02_LENGTH, val)
356 #define bfin_write_CAN1_MB02_TIMESTAMP(val) bfin_write16(CAN1_MB02_TIMESTAMP, val)
358 #define bfin_write_CAN1_MB02_ID0(val) bfin_write16(CAN1_MB02_ID0, val)
360 #define bfin_write_CAN1_MB02_ID1(val) bfin_write16(CAN1_MB02_ID1, val)
362 #define bfin_write_CAN1_MB03_DATA0(val) bfin_write16(CAN1_MB03_DATA0, val)
364 #define bfin_write_CAN1_MB03_DATA1(val) bfin_write16(CAN1_MB03_DATA1, val)
366 #define bfin_write_CAN1_MB03_DATA2(val) bfin_write16(CAN1_MB03_DATA2, val)
368 #define bfin_write_CAN1_MB03_DATA3(val) bfin_write16(CAN1_MB03_DATA3, val)
370 #define bfin_write_CAN1_MB03_LENGTH(val) bfin_write16(CAN1_MB03_LENGTH, val)
372 #define bfin_write_CAN1_MB03_TIMESTAMP(val) bfin_write16(CAN1_MB03_TIMESTAMP, val)
374 #define bfin_write_CAN1_MB03_ID0(val) bfin_write16(CAN1_MB03_ID0, val)
376 #define bfin_write_CAN1_MB03_ID1(val) bfin_write16(CAN1_MB03_ID1, val)
378 #define bfin_write_CAN1_MB04_DATA0(val) bfin_write16(CAN1_MB04_DATA0, val)
380 #define bfin_write_CAN1_MB04_DATA1(val) bfin_write16(CAN1_MB04_DATA1, val)
382 #define bfin_write_CAN1_MB04_DATA2(val) bfin_write16(CAN1_MB04_DATA2, val)
384 #define bfin_write_CAN1_MB04_DATA3(val) bfin_write16(CAN1_MB04_DATA3, val)
386 #define bfin_write_CAN1_MB04_LENGTH(val) bfin_write16(CAN1_MB04_LENGTH, val)
388 #define bfin_write_CAN1_MB04_TIMESTAMP(val) bfin_write16(CAN1_MB04_TIMESTAMP, val)
390 #define bfin_write_CAN1_MB04_ID0(val) bfin_write16(CAN1_MB04_ID0, val)
392 #define bfin_write_CAN1_MB04_ID1(val) bfin_write16(CAN1_MB04_ID1, val)
394 #define bfin_write_CAN1_MB05_DATA0(val) bfin_write16(CAN1_MB05_DATA0, val)
396 #define bfin_write_CAN1_MB05_DATA1(val) bfin_write16(CAN1_MB05_DATA1, val)
398 #define bfin_write_CAN1_MB05_DATA2(val) bfin_write16(CAN1_MB05_DATA2, val)
400 #define bfin_write_CAN1_MB05_DATA3(val) bfin_write16(CAN1_MB05_DATA3, val)
402 #define bfin_write_CAN1_MB05_LENGTH(val) bfin_write16(CAN1_MB05_LENGTH, val)
404 #define bfin_write_CAN1_MB05_TIMESTAMP(val) bfin_write16(CAN1_MB05_TIMESTAMP, val)
406 #define bfin_write_CAN1_MB05_ID0(val) bfin_write16(CAN1_MB05_ID0, val)
408 #define bfin_write_CAN1_MB05_ID1(val) bfin_write16(CAN1_MB05_ID1, val)
410 #define bfin_write_CAN1_MB06_DATA0(val) bfin_write16(CAN1_MB06_DATA0, val)
412 #define bfin_write_CAN1_MB06_DATA1(val) bfin_write16(CAN1_MB06_DATA1, val)
414 #define bfin_write_CAN1_MB06_DATA2(val) bfin_write16(CAN1_MB06_DATA2, val)
416 #define bfin_write_CAN1_MB06_DATA3(val) bfin_write16(CAN1_MB06_DATA3, val)
418 #define bfin_write_CAN1_MB06_LENGTH(val) bfin_write16(CAN1_MB06_LENGTH, val)
420 #define bfin_write_CAN1_MB06_TIMESTAMP(val) bfin_write16(CAN1_MB06_TIMESTAMP, val)
422 #define bfin_write_CAN1_MB06_ID0(val) bfin_write16(CAN1_MB06_ID0, val)
424 #define bfin_write_CAN1_MB06_ID1(val) bfin_write16(CAN1_MB06_ID1, val)
426 #define bfin_write_CAN1_MB07_DATA0(val) bfin_write16(CAN1_MB07_DATA0, val)
428 #define bfin_write_CAN1_MB07_DATA1(val) bfin_write16(CAN1_MB07_DATA1, val)
430 #define bfin_write_CAN1_MB07_DATA2(val) bfin_write16(CAN1_MB07_DATA2, val)
432 #define bfin_write_CAN1_MB07_DATA3(val) bfin_write16(CAN1_MB07_DATA3, val)
434 #define bfin_write_CAN1_MB07_LENGTH(val) bfin_write16(CAN1_MB07_LENGTH, val)
436 #define bfin_write_CAN1_MB07_TIMESTAMP(val) bfin_write16(CAN1_MB07_TIMESTAMP, val)
438 #define bfin_write_CAN1_MB07_ID0(val) bfin_write16(CAN1_MB07_ID0, val)
440 #define bfin_write_CAN1_MB07_ID1(val) bfin_write16(CAN1_MB07_ID1, val)
442 #define bfin_write_CAN1_MB08_DATA0(val) bfin_write16(CAN1_MB08_DATA0, val)
444 #define bfin_write_CAN1_MB08_DATA1(val) bfin_write16(CAN1_MB08_DATA1, val)
446 #define bfin_write_CAN1_MB08_DATA2(val) bfin_write16(CAN1_MB08_DATA2, val)
448 #define bfin_write_CAN1_MB08_DATA3(val) bfin_write16(CAN1_MB08_DATA3, val)
450 #define bfin_write_CAN1_MB08_LENGTH(val) bfin_write16(CAN1_MB08_LENGTH, val)
452 #define bfin_write_CAN1_MB08_TIMESTAMP(val) bfin_write16(CAN1_MB08_TIMESTAMP, val)
454 #define bfin_write_CAN1_MB08_ID0(val) bfin_write16(CAN1_MB08_ID0, val)
456 #define bfin_write_CAN1_MB08_ID1(val) bfin_write16(CAN1_MB08_ID1, val)
458 #define bfin_write_CAN1_MB09_DATA0(val) bfin_write16(CAN1_MB09_DATA0, val)
460 #define bfin_write_CAN1_MB09_DATA1(val) bfin_write16(CAN1_MB09_DATA1, val)
462 #define bfin_write_CAN1_MB09_DATA2(val) bfin_write16(CAN1_MB09_DATA2, val)
464 #define bfin_write_CAN1_MB09_DATA3(val) bfin_write16(CAN1_MB09_DATA3, val)
466 #define bfin_write_CAN1_MB09_LENGTH(val) bfin_write16(CAN1_MB09_LENGTH, val)
468 #define bfin_write_CAN1_MB09_TIMESTAMP(val) bfin_write16(CAN1_MB09_TIMESTAMP, val)
470 #define bfin_write_CAN1_MB09_ID0(val) bfin_write16(CAN1_MB09_ID0, val)
472 #define bfin_write_CAN1_MB09_ID1(val) bfin_write16(CAN1_MB09_ID1, val)
474 #define bfin_write_CAN1_MB10_DATA0(val) bfin_write16(CAN1_MB10_DATA0, val)
476 #define bfin_write_CAN1_MB10_DATA1(val) bfin_write16(CAN1_MB10_DATA1, val)
478 #define bfin_write_CAN1_MB10_DATA2(val) bfin_write16(CAN1_MB10_DATA2, val)
480 #define bfin_write_CAN1_MB10_DATA3(val) bfin_write16(CAN1_MB10_DATA3, val)
482 #define bfin_write_CAN1_MB10_LENGTH(val) bfin_write16(CAN1_MB10_LENGTH, val)
484 #define bfin_write_CAN1_MB10_TIMESTAMP(val) bfin_write16(CAN1_MB10_TIMESTAMP, val)
486 #define bfin_write_CAN1_MB10_ID0(val) bfin_write16(CAN1_MB10_ID0, val)
488 #define bfin_write_CAN1_MB10_ID1(val) bfin_write16(CAN1_MB10_ID1, val)
490 #define bfin_write_CAN1_MB11_DATA0(val) bfin_write16(CAN1_MB11_DATA0, val)
492 #define bfin_write_CAN1_MB11_DATA1(val) bfin_write16(CAN1_MB11_DATA1, val)
494 #define bfin_write_CAN1_MB11_DATA2(val) bfin_write16(CAN1_MB11_DATA2, val)
496 #define bfin_write_CAN1_MB11_DATA3(val) bfin_write16(CAN1_MB11_DATA3, val)
498 #define bfin_write_CAN1_MB11_LENGTH(val) bfin_write16(CAN1_MB11_LENGTH, val)
500 #define bfin_write_CAN1_MB11_TIMESTAMP(val) bfin_write16(CAN1_MB11_TIMESTAMP, val)
502 #define bfin_write_CAN1_MB11_ID0(val) bfin_write16(CAN1_MB11_ID0, val)
504 #define bfin_write_CAN1_MB11_ID1(val) bfin_write16(CAN1_MB11_ID1, val)
506 #define bfin_write_CAN1_MB12_DATA0(val) bfin_write16(CAN1_MB12_DATA0, val)
508 #define bfin_write_CAN1_MB12_DATA1(val) bfin_write16(CAN1_MB12_DATA1, val)
510 #define bfin_write_CAN1_MB12_DATA2(val) bfin_write16(CAN1_MB12_DATA2, val)
512 #define bfin_write_CAN1_MB12_DATA3(val) bfin_write16(CAN1_MB12_DATA3, val)
514 #define bfin_write_CAN1_MB12_LENGTH(val) bfin_write16(CAN1_MB12_LENGTH, val)
516 #define bfin_write_CAN1_MB12_TIMESTAMP(val) bfin_write16(CAN1_MB12_TIMESTAMP, val)
518 #define bfin_write_CAN1_MB12_ID0(val) bfin_write16(CAN1_MB12_ID0, val)
520 #define bfin_write_CAN1_MB12_ID1(val) bfin_write16(CAN1_MB12_ID1, val)
522 #define bfin_write_CAN1_MB13_DATA0(val) bfin_write16(CAN1_MB13_DATA0, val)
524 #define bfin_write_CAN1_MB13_DATA1(val) bfin_write16(CAN1_MB13_DATA1, val)
526 #define bfin_write_CAN1_MB13_DATA2(val) bfin_write16(CAN1_MB13_DATA2, val)
528 #define bfin_write_CAN1_MB13_DATA3(val) bfin_write16(CAN1_MB13_DATA3, val)
530 #define bfin_write_CAN1_MB13_LENGTH(val) bfin_write16(CAN1_MB13_LENGTH, val)
532 #define bfin_write_CAN1_MB13_TIMESTAMP(val) bfin_write16(CAN1_MB13_TIMESTAMP, val)
534 #define bfin_write_CAN1_MB13_ID0(val) bfin_write16(CAN1_MB13_ID0, val)
536 #define bfin_write_CAN1_MB13_ID1(val) bfin_write16(CAN1_MB13_ID1, val)
538 #define bfin_write_CAN1_MB14_DATA0(val) bfin_write16(CAN1_MB14_DATA0, val)
540 #define bfin_write_CAN1_MB14_DATA1(val) bfin_write16(CAN1_MB14_DATA1, val)
542 #define bfin_write_CAN1_MB14_DATA2(val) bfin_write16(CAN1_MB14_DATA2, val)
544 #define bfin_write_CAN1_MB14_DATA3(val) bfin_write16(CAN1_MB14_DATA3, val)
546 #define bfin_write_CAN1_MB14_LENGTH(val) bfin_write16(CAN1_MB14_LENGTH, val)
548 #define bfin_write_CAN1_MB14_TIMESTAMP(val) bfin_write16(CAN1_MB14_TIMESTAMP, val)
550 #define bfin_write_CAN1_MB14_ID0(val) bfin_write16(CAN1_MB14_ID0, val)
552 #define bfin_write_CAN1_MB14_ID1(val) bfin_write16(CAN1_MB14_ID1, val)
554 #define bfin_write_CAN1_MB15_DATA0(val) bfin_write16(CAN1_MB15_DATA0, val)
556 #define bfin_write_CAN1_MB15_DATA1(val) bfin_write16(CAN1_MB15_DATA1, val)
558 #define bfin_write_CAN1_MB15_DATA2(val) bfin_write16(CAN1_MB15_DATA2, val)
560 #define bfin_write_CAN1_MB15_DATA3(val) bfin_write16(CAN1_MB15_DATA3, val)
562 #define bfin_write_CAN1_MB15_LENGTH(val) bfin_write16(CAN1_MB15_LENGTH, val)
564 #define bfin_write_CAN1_MB15_TIMESTAMP(val) bfin_write16(CAN1_MB15_TIMESTAMP, val)
566 #define bfin_write_CAN1_MB15_ID0(val) bfin_write16(CAN1_MB15_ID0, val)
568 #define bfin_write_CAN1_MB15_ID1(val) bfin_write16(CAN1_MB15_ID1, val)
573 #define bfin_write_CAN1_MB16_DATA0(val) bfin_write16(CAN1_MB16_DATA0, val)
575 #define bfin_write_CAN1_MB16_DATA1(val) bfin_write16(CAN1_MB16_DATA1, val)
577 #define bfin_write_CAN1_MB16_DATA2(val) bfin_write16(CAN1_MB16_DATA2, val)
579 #define bfin_write_CAN1_MB16_DATA3(val) bfin_write16(CAN1_MB16_DATA3, val)
581 #define bfin_write_CAN1_MB16_LENGTH(val) bfin_write16(CAN1_MB16_LENGTH, val)
583 #define bfin_write_CAN1_MB16_TIMESTAMP(val) bfin_write16(CAN1_MB16_TIMESTAMP, val)
585 #define bfin_write_CAN1_MB16_ID0(val) bfin_write16(CAN1_MB16_ID0, val)
587 #define bfin_write_CAN1_MB16_ID1(val) bfin_write16(CAN1_MB16_ID1, val)
589 #define bfin_write_CAN1_MB17_DATA0(val) bfin_write16(CAN1_MB17_DATA0, val)
591 #define bfin_write_CAN1_MB17_DATA1(val) bfin_write16(CAN1_MB17_DATA1, val)
593 #define bfin_write_CAN1_MB17_DATA2(val) bfin_write16(CAN1_MB17_DATA2, val)
595 #define bfin_write_CAN1_MB17_DATA3(val) bfin_write16(CAN1_MB17_DATA3, val)
597 #define bfin_write_CAN1_MB17_LENGTH(val) bfin_write16(CAN1_MB17_LENGTH, val)
599 #define bfin_write_CAN1_MB17_TIMESTAMP(val) bfin_write16(CAN1_MB17_TIMESTAMP, val)
601 #define bfin_write_CAN1_MB17_ID0(val) bfin_write16(CAN1_MB17_ID0, val)
603 #define bfin_write_CAN1_MB17_ID1(val) bfin_write16(CAN1_MB17_ID1, val)
605 #define bfin_write_CAN1_MB18_DATA0(val) bfin_write16(CAN1_MB18_DATA0, val)
607 #define bfin_write_CAN1_MB18_DATA1(val) bfin_write16(CAN1_MB18_DATA1, val)
609 #define bfin_write_CAN1_MB18_DATA2(val) bfin_write16(CAN1_MB18_DATA2, val)
611 #define bfin_write_CAN1_MB18_DATA3(val) bfin_write16(CAN1_MB18_DATA3, val)
613 #define bfin_write_CAN1_MB18_LENGTH(val) bfin_write16(CAN1_MB18_LENGTH, val)
615 #define bfin_write_CAN1_MB18_TIMESTAMP(val) bfin_write16(CAN1_MB18_TIMESTAMP, val)
617 #define bfin_write_CAN1_MB18_ID0(val) bfin_write16(CAN1_MB18_ID0, val)
619 #define bfin_write_CAN1_MB18_ID1(val) bfin_write16(CAN1_MB18_ID1, val)
621 #define bfin_write_CAN1_MB19_DATA0(val) bfin_write16(CAN1_MB19_DATA0, val)
623 #define bfin_write_CAN1_MB19_DATA1(val) bfin_write16(CAN1_MB19_DATA1, val)
625 #define bfin_write_CAN1_MB19_DATA2(val) bfin_write16(CAN1_MB19_DATA2, val)
627 #define bfin_write_CAN1_MB19_DATA3(val) bfin_write16(CAN1_MB19_DATA3, val)
629 #define bfin_write_CAN1_MB19_LENGTH(val) bfin_write16(CAN1_MB19_LENGTH, val)
631 #define bfin_write_CAN1_MB19_TIMESTAMP(val) bfin_write16(CAN1_MB19_TIMESTAMP, val)
633 #define bfin_write_CAN1_MB19_ID0(val) bfin_write16(CAN1_MB19_ID0, val)
635 #define bfin_write_CAN1_MB19_ID1(val) bfin_write16(CAN1_MB19_ID1, val)
637 #define bfin_write_CAN1_MB20_DATA0(val) bfin_write16(CAN1_MB20_DATA0, val)
639 #define bfin_write_CAN1_MB20_DATA1(val) bfin_write16(CAN1_MB20_DATA1, val)
641 #define bfin_write_CAN1_MB20_DATA2(val) bfin_write16(CAN1_MB20_DATA2, val)
643 #define bfin_write_CAN1_MB20_DATA3(val) bfin_write16(CAN1_MB20_DATA3, val)
645 #define bfin_write_CAN1_MB20_LENGTH(val) bfin_write16(CAN1_MB20_LENGTH, val)
647 #define bfin_write_CAN1_MB20_TIMESTAMP(val) bfin_write16(CAN1_MB20_TIMESTAMP, val)
649 #define bfin_write_CAN1_MB20_ID0(val) bfin_write16(CAN1_MB20_ID0, val)
651 #define bfin_write_CAN1_MB20_ID1(val) bfin_write16(CAN1_MB20_ID1, val)
653 #define bfin_write_CAN1_MB21_DATA0(val) bfin_write16(CAN1_MB21_DATA0, val)
655 #define bfin_write_CAN1_MB21_DATA1(val) bfin_write16(CAN1_MB21_DATA1, val)
657 #define bfin_write_CAN1_MB21_DATA2(val) bfin_write16(CAN1_MB21_DATA2, val)
659 #define bfin_write_CAN1_MB21_DATA3(val) bfin_write16(CAN1_MB21_DATA3, val)
661 #define bfin_write_CAN1_MB21_LENGTH(val) bfin_write16(CAN1_MB21_LENGTH, val)
663 #define bfin_write_CAN1_MB21_TIMESTAMP(val) bfin_write16(CAN1_MB21_TIMESTAMP, val)
665 #define bfin_write_CAN1_MB21_ID0(val) bfin_write16(CAN1_MB21_ID0, val)
667 #define bfin_write_CAN1_MB21_ID1(val) bfin_write16(CAN1_MB21_ID1, val)
669 #define bfin_write_CAN1_MB22_DATA0(val) bfin_write16(CAN1_MB22_DATA0, val)
671 #define bfin_write_CAN1_MB22_DATA1(val) bfin_write16(CAN1_MB22_DATA1, val)
673 #define bfin_write_CAN1_MB22_DATA2(val) bfin_write16(CAN1_MB22_DATA2, val)
675 #define bfin_write_CAN1_MB22_DATA3(val) bfin_write16(CAN1_MB22_DATA3, val)
677 #define bfin_write_CAN1_MB22_LENGTH(val) bfin_write16(CAN1_MB22_LENGTH, val)
679 #define bfin_write_CAN1_MB22_TIMESTAMP(val) bfin_write16(CAN1_MB22_TIMESTAMP, val)
681 #define bfin_write_CAN1_MB22_ID0(val) bfin_write16(CAN1_MB22_ID0, val)
683 #define bfin_write_CAN1_MB22_ID1(val) bfin_write16(CAN1_MB22_ID1, val)
685 #define bfin_write_CAN1_MB23_DATA0(val) bfin_write16(CAN1_MB23_DATA0, val)
687 #define bfin_write_CAN1_MB23_DATA1(val) bfin_write16(CAN1_MB23_DATA1, val)
689 #define bfin_write_CAN1_MB23_DATA2(val) bfin_write16(CAN1_MB23_DATA2, val)
691 #define bfin_write_CAN1_MB23_DATA3(val) bfin_write16(CAN1_MB23_DATA3, val)
693 #define bfin_write_CAN1_MB23_LENGTH(val) bfin_write16(CAN1_MB23_LENGTH, val)
695 #define bfin_write_CAN1_MB23_TIMESTAMP(val) bfin_write16(CAN1_MB23_TIMESTAMP, val)
697 #define bfin_write_CAN1_MB23_ID0(val) bfin_write16(CAN1_MB23_ID0, val)
699 #define bfin_write_CAN1_MB23_ID1(val) bfin_write16(CAN1_MB23_ID1, val)
701 #define bfin_write_CAN1_MB24_DATA0(val) bfin_write16(CAN1_MB24_DATA0, val)
703 #define bfin_write_CAN1_MB24_DATA1(val) bfin_write16(CAN1_MB24_DATA1, val)
705 #define bfin_write_CAN1_MB24_DATA2(val) bfin_write16(CAN1_MB24_DATA2, val)
707 #define bfin_write_CAN1_MB24_DATA3(val) bfin_write16(CAN1_MB24_DATA3, val)
709 #define bfin_write_CAN1_MB24_LENGTH(val) bfin_write16(CAN1_MB24_LENGTH, val)
711 #define bfin_write_CAN1_MB24_TIMESTAMP(val) bfin_write16(CAN1_MB24_TIMESTAMP, val)
713 #define bfin_write_CAN1_MB24_ID0(val) bfin_write16(CAN1_MB24_ID0, val)
715 #define bfin_write_CAN1_MB24_ID1(val) bfin_write16(CAN1_MB24_ID1, val)
717 #define bfin_write_CAN1_MB25_DATA0(val) bfin_write16(CAN1_MB25_DATA0, val)
719 #define bfin_write_CAN1_MB25_DATA1(val) bfin_write16(CAN1_MB25_DATA1, val)
721 #define bfin_write_CAN1_MB25_DATA2(val) bfin_write16(CAN1_MB25_DATA2, val)
723 #define bfin_write_CAN1_MB25_DATA3(val) bfin_write16(CAN1_MB25_DATA3, val)
725 #define bfin_write_CAN1_MB25_LENGTH(val) bfin_write16(CAN1_MB25_LENGTH, val)
727 #define bfin_write_CAN1_MB25_TIMESTAMP(val) bfin_write16(CAN1_MB25_TIMESTAMP, val)
729 #define bfin_write_CAN1_MB25_ID0(val) bfin_write16(CAN1_MB25_ID0, val)
731 #define bfin_write_CAN1_MB25_ID1(val) bfin_write16(CAN1_MB25_ID1, val)
733 #define bfin_write_CAN1_MB26_DATA0(val) bfin_write16(CAN1_MB26_DATA0, val)
735 #define bfin_write_CAN1_MB26_DATA1(val) bfin_write16(CAN1_MB26_DATA1, val)
737 #define bfin_write_CAN1_MB26_DATA2(val) bfin_write16(CAN1_MB26_DATA2, val)
739 #define bfin_write_CAN1_MB26_DATA3(val) bfin_write16(CAN1_MB26_DATA3, val)
741 #define bfin_write_CAN1_MB26_LENGTH(val) bfin_write16(CAN1_MB26_LENGTH, val)
743 #define bfin_write_CAN1_MB26_TIMESTAMP(val) bfin_write16(CAN1_MB26_TIMESTAMP, val)
745 #define bfin_write_CAN1_MB26_ID0(val) bfin_write16(CAN1_MB26_ID0, val)
747 #define bfin_write_CAN1_MB26_ID1(val) bfin_write16(CAN1_MB26_ID1, val)
749 #define bfin_write_CAN1_MB27_DATA0(val) bfin_write16(CAN1_MB27_DATA0, val)
751 #define bfin_write_CAN1_MB27_DATA1(val) bfin_write16(CAN1_MB27_DATA1, val)
753 #define bfin_write_CAN1_MB27_DATA2(val) bfin_write16(CAN1_MB27_DATA2, val)
755 #define bfin_write_CAN1_MB27_DATA3(val) bfin_write16(CAN1_MB27_DATA3, val)
757 #define bfin_write_CAN1_MB27_LENGTH(val) bfin_write16(CAN1_MB27_LENGTH, val)
759 #define bfin_write_CAN1_MB27_TIMESTAMP(val) bfin_write16(CAN1_MB27_TIMESTAMP, val)
761 #define bfin_write_CAN1_MB27_ID0(val) bfin_write16(CAN1_MB27_ID0, val)
763 #define bfin_write_CAN1_MB27_ID1(val) bfin_write16(CAN1_MB27_ID1, val)
765 #define bfin_write_CAN1_MB28_DATA0(val) bfin_write16(CAN1_MB28_DATA0, val)
767 #define bfin_write_CAN1_MB28_DATA1(val) bfin_write16(CAN1_MB28_DATA1, val)
769 #define bfin_write_CAN1_MB28_DATA2(val) bfin_write16(CAN1_MB28_DATA2, val)
771 #define bfin_write_CAN1_MB28_DATA3(val) bfin_write16(CAN1_MB28_DATA3, val)
773 #define bfin_write_CAN1_MB28_LENGTH(val) bfin_write16(CAN1_MB28_LENGTH, val)
775 #define bfin_write_CAN1_MB28_TIMESTAMP(val) bfin_write16(CAN1_MB28_TIMESTAMP, val)
777 #define bfin_write_CAN1_MB28_ID0(val) bfin_write16(CAN1_MB28_ID0, val)
779 #define bfin_write_CAN1_MB28_ID1(val) bfin_write16(CAN1_MB28_ID1, val)
781 #define bfin_write_CAN1_MB29_DATA0(val) bfin_write16(CAN1_MB29_DATA0, val)
783 #define bfin_write_CAN1_MB29_DATA1(val) bfin_write16(CAN1_MB29_DATA1, val)
785 #define bfin_write_CAN1_MB29_DATA2(val) bfin_write16(CAN1_MB29_DATA2, val)
787 #define bfin_write_CAN1_MB29_DATA3(val) bfin_write16(CAN1_MB29_DATA3, val)
789 #define bfin_write_CAN1_MB29_LENGTH(val) bfin_write16(CAN1_MB29_LENGTH, val)
791 #define bfin_write_CAN1_MB29_TIMESTAMP(val) bfin_write16(CAN1_MB29_TIMESTAMP, val)
793 #define bfin_write_CAN1_MB29_ID0(val) bfin_write16(CAN1_MB29_ID0, val)
795 #define bfin_write_CAN1_MB29_ID1(val) bfin_write16(CAN1_MB29_ID1, val)
797 #define bfin_write_CAN1_MB30_DATA0(val) bfin_write16(CAN1_MB30_DATA0, val)
799 #define bfin_write_CAN1_MB30_DATA1(val) bfin_write16(CAN1_MB30_DATA1, val)
801 #define bfin_write_CAN1_MB30_DATA2(val) bfin_write16(CAN1_MB30_DATA2, val)
803 #define bfin_write_CAN1_MB30_DATA3(val) bfin_write16(CAN1_MB30_DATA3, val)
805 #define bfin_write_CAN1_MB30_LENGTH(val) bfin_write16(CAN1_MB30_LENGTH, val)
807 #define bfin_write_CAN1_MB30_TIMESTAMP(val) bfin_write16(CAN1_MB30_TIMESTAMP, val)
809 #define bfin_write_CAN1_MB30_ID0(val) bfin_write16(CAN1_MB30_ID0, val)
811 #define bfin_write_CAN1_MB30_ID1(val) bfin_write16(CAN1_MB30_ID1, val)
813 #define bfin_write_CAN1_MB31_DATA0(val) bfin_write16(CAN1_MB31_DATA0, val)
815 #define bfin_write_CAN1_MB31_DATA1(val) bfin_write16(CAN1_MB31_DATA1, val)
817 #define bfin_write_CAN1_MB31_DATA2(val) bfin_write16(CAN1_MB31_DATA2, val)
819 #define bfin_write_CAN1_MB31_DATA3(val) bfin_write16(CAN1_MB31_DATA3, val)
821 #define bfin_write_CAN1_MB31_LENGTH(val) bfin_write16(CAN1_MB31_LENGTH, val)
823 #define bfin_write_CAN1_MB31_TIMESTAMP(val) bfin_write16(CAN1_MB31_TIMESTAMP, val)
825 #define bfin_write_CAN1_MB31_ID0(val) bfin_write16(CAN1_MB31_ID0, val)
827 #define bfin_write_CAN1_MB31_ID1(val) bfin_write16(CAN1_MB31_ID1, val)
832 #define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val)
834 #define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val)
836 #define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val)
841 #define bfin_write_PIXC_CTL(val) bfin_write16(PIXC_CTL, val)
843 #define bfin_write_PIXC_PPL(val) bfin_write16(PIXC_PPL, val)
845 #define bfin_write_PIXC_LPF(val) bfin_write16(PIXC_LPF, val)
847 #define bfin_write_PIXC_AHSTART(val) bfin_write16(PIXC_AHSTART, val)
849 #define bfin_write_PIXC_AHEND(val) bfin_write16(PIXC_AHEND, val)
851 #define bfin_write_PIXC_AVSTART(val) bfin_write16(PIXC_AVSTART, val)
853 #define bfin_write_PIXC_AVEND(val) bfin_write16(PIXC_AVEND, val)
855 #define bfin_write_PIXC_ATRANSP(val) bfin_write16(PIXC_ATRANSP, val)
857 #define bfin_write_PIXC_BHSTART(val) bfin_write16(PIXC_BHSTART, val)
859 #define bfin_write_PIXC_BHEND(val) bfin_write16(PIXC_BHEND, val)
861 #define bfin_write_PIXC_BVSTART(val) bfin_write16(PIXC_BVSTART, val)
863 #define bfin_write_PIXC_BVEND(val) bfin_write16(PIXC_BVEND, val)
865 #define bfin_write_PIXC_BTRANSP(val) bfin_write16(PIXC_BTRANSP, val)
867 #define bfin_write_PIXC_INTRSTAT(val) bfin_write16(PIXC_INTRSTAT, val)
869 #define bfin_write_PIXC_RYCON(val) bfin_write32(PIXC_RYCON, val)
871 #define bfin_write_PIXC_GUCON(val) bfin_write32(PIXC_GUCON, val)
873 #define bfin_write_PIXC_BVCON(val) bfin_write32(PIXC_BVCON, val)
875 #define bfin_write_PIXC_CCBIAS(val) bfin_write32(PIXC_CCBIAS, val)
877 #define bfin_write_PIXC_TC(val) bfin_write32(PIXC_TC, val)
882 #define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
884 #define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
886 #define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
888 #define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
890 #define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
892 #define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
894 #define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
899 #define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
901 #define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
903 #define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
905 #define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
907 #define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
909 #define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
911 #define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
H A DcdefBF549.h19 #define bfin_write_MXVR_CONFIG(val) bfin_write16(MXVR_CONFIG, val)
21 #define bfin_write_MXVR_STATE_0(val) bfin_write32(MXVR_STATE_0, val)
23 #define bfin_write_MXVR_STATE_1(val) bfin_write32(MXVR_STATE_1, val)
25 #define bfin_write_MXVR_INT_STAT_0(val) bfin_write32(MXVR_INT_STAT_0, val)
27 #define bfin_write_MXVR_INT_STAT_1(val) bfin_write32(MXVR_INT_STAT_1, val)
29 #define bfin_write_MXVR_INT_EN_0(val) bfin_write32(MXVR_INT_EN_0, val)
31 #define bfin_write_MXVR_INT_EN_1(val) bfin_write32(MXVR_INT_EN_1, val)
33 #define bfin_write_MXVR_POSITION(val) bfin_write16(MXVR_POSITION, val)
35 #define bfin_write_MXVR_MAX_POSITION(val) bfin_write16(MXVR_MAX_POSITION, val)
37 #define bfin_write_MXVR_DELAY(val) bfin_write16(MXVR_DELAY, val)
39 #define bfin_write_MXVR_MAX_DELAY(val) bfin_write16(MXVR_MAX_DELAY, val)
41 #define bfin_write_MXVR_LADDR(val) bfin_write32(MXVR_LADDR, val)
43 #define bfin_write_MXVR_GADDR(val) bfin_write16(MXVR_GADDR, val)
45 #define bfin_write_MXVR_AADDR(val) bfin_write32(MXVR_AADDR, val)
50 #define bfin_write_MXVR_ALLOC_0(val) bfin_write32(MXVR_ALLOC_0, val)
52 #define bfin_write_MXVR_ALLOC_1(val) bfin_write32(MXVR_ALLOC_1, val)
54 #define bfin_write_MXVR_ALLOC_2(val) bfin_write32(MXVR_ALLOC_2, val)
56 #define bfin_write_MXVR_ALLOC_3(val) bfin_write32(MXVR_ALLOC_3, val)
58 #define bfin_write_MXVR_ALLOC_4(val) bfin_write32(MXVR_ALLOC_4, val)
60 #define bfin_write_MXVR_ALLOC_5(val) bfin_write32(MXVR_ALLOC_5, val)
62 #define bfin_write_MXVR_ALLOC_6(val) bfin_write32(MXVR_ALLOC_6, val)
64 #define bfin_write_MXVR_ALLOC_7(val) bfin_write32(MXVR_ALLOC_7, val)
66 #define bfin_write_MXVR_ALLOC_8(val) bfin_write32(MXVR_ALLOC_8, val)
68 #define bfin_write_MXVR_ALLOC_9(val) bfin_write32(MXVR_ALLOC_9, val)
70 #define bfin_write_MXVR_ALLOC_10(val) bfin_write32(MXVR_ALLOC_10, val)
72 #define bfin_write_MXVR_ALLOC_11(val) bfin_write32(MXVR_ALLOC_11, val)
74 #define bfin_write_MXVR_ALLOC_12(val) bfin_write32(MXVR_ALLOC_12, val)
76 #define bfin_write_MXVR_ALLOC_13(val) bfin_write32(MXVR_ALLOC_13, val)
78 #define bfin_write_MXVR_ALLOC_14(val) bfin_write32(MXVR_ALLOC_14, val)
83 #define bfin_write_MXVR_SYNC_LCHAN_0(val) bfin_write32(MXVR_SYNC_LCHAN_0, val)
85 #define bfin_write_MXVR_SYNC_LCHAN_1(val) bfin_write32(MXVR_SYNC_LCHAN_1, val)
87 #define bfin_write_MXVR_SYNC_LCHAN_2(val) bfin_write32(MXVR_SYNC_LCHAN_2, val)
89 #define bfin_write_MXVR_SYNC_LCHAN_3(val) bfin_write32(MXVR_SYNC_LCHAN_3, val)
91 #define bfin_write_MXVR_SYNC_LCHAN_4(val) bfin_write32(MXVR_SYNC_LCHAN_4, val)
93 #define bfin_write_MXVR_SYNC_LCHAN_5(val) bfin_write32(MXVR_SYNC_LCHAN_5, val)
95 #define bfin_write_MXVR_SYNC_LCHAN_6(val) bfin_write32(MXVR_SYNC_LCHAN_6, val)
97 #define bfin_write_MXVR_SYNC_LCHAN_7(val) bfin_write32(MXVR_SYNC_LCHAN_7, val)
102 #define bfin_write_MXVR_DMA0_CONFIG(val) bfin_write32(MXVR_DMA0_CONFIG, val)
104 #define bfin_write_MXVR_DMA0_START_ADDR(val) bfin_write32(MXVR_DMA0_START_ADDR)
106 #define bfin_write_MXVR_DMA0_COUNT(val) bfin_write16(MXVR_DMA0_COUNT, val)
108 #define bfin_write_MXVR_DMA0_CURR_ADDR(val) bfin_write32(MXVR_DMA0_CURR_ADDR)
110 #define bfin_write_MXVR_DMA0_CURR_COUNT(val) bfin_write16(MXVR_DMA0_CURR_COUNT, val)
115 #define bfin_write_MXVR_DMA1_CONFIG(val) bfin_write32(MXVR_DMA1_CONFIG, val)
117 #define bfin_write_MXVR_DMA1_START_ADDR(val) bfin_write32(MXVR_DMA1_START_ADDR)
119 #define bfin_write_MXVR_DMA1_COUNT(val) bfin_write16(MXVR_DMA1_COUNT, val)
121 #define bfin_write_MXVR_DMA1_CURR_ADDR(val) bfin_write32(MXVR_DMA1_CURR_ADDR)
123 #define bfin_write_MXVR_DMA1_CURR_COUNT(val) bfin_write16(MXVR_DMA1_CURR_COUNT, val)
128 #define bfin_write_MXVR_DMA2_CONFIG(val) bfin_write32(MXVR_DMA2_CONFIG, val)
130 #define bfin_write_MXVR_DMA2_START_ADDR(val) bfin_write32(MXVR_DMA2_START_ADDR)
132 #define bfin_write_MXVR_DMA2_COUNT(val) bfin_write16(MXVR_DMA2_COUNT, val)
134 #define bfin_write_MXVR_DMA2_CURR_ADDR(val) bfin_write32(MXVR_DMA2_CURR_ADDR)
136 #define bfin_write_MXVR_DMA2_CURR_COUNT(val) bfin_write16(MXVR_DMA2_CURR_COUNT, val)
141 #define bfin_write_MXVR_DMA3_CONFIG(val) bfin_write32(MXVR_DMA3_CONFIG, val)
143 #define bfin_write_MXVR_DMA3_START_ADDR(val) bfin_write32(MXVR_DMA3_START_ADDR)
145 #define bfin_write_MXVR_DMA3_COUNT(val) bfin_write16(MXVR_DMA3_COUNT, val)
147 #define bfin_write_MXVR_DMA3_CURR_ADDR(val) bfin_write32(MXVR_DMA3_CURR_ADDR)
149 #define bfin_write_MXVR_DMA3_CURR_COUNT(val) bfin_write16(MXVR_DMA3_CURR_COUNT, val)
154 #define bfin_write_MXVR_DMA4_CONFIG(val) bfin_write32(MXVR_DMA4_CONFIG, val)
156 #define bfin_write_MXVR_DMA4_START_ADDR(val) bfin_write32(MXVR_DMA4_START_ADDR)
158 #define bfin_write_MXVR_DMA4_COUNT(val) bfin_write16(MXVR_DMA4_COUNT, val)
160 #define bfin_write_MXVR_DMA4_CURR_ADDR(val) bfin_write32(MXVR_DMA4_CURR_ADDR)
162 #define bfin_write_MXVR_DMA4_CURR_COUNT(val) bfin_write16(MXVR_DMA4_CURR_COUNT, val)
167 #define bfin_write_MXVR_DMA5_CONFIG(val) bfin_write32(MXVR_DMA5_CONFIG, val)
169 #define bfin_write_MXVR_DMA5_START_ADDR(val) bfin_write32(MXVR_DMA5_START_ADDR)
171 #define bfin_write_MXVR_DMA5_COUNT(val) bfin_write16(MXVR_DMA5_COUNT, val)
173 #define bfin_write_MXVR_DMA5_CURR_ADDR(val) bfin_write32(MXVR_DMA5_CURR_ADDR)
175 #define bfin_write_MXVR_DMA5_CURR_COUNT(val) bfin_write16(MXVR_DMA5_CURR_COUNT, val)
180 #define bfin_write_MXVR_DMA6_CONFIG(val) bfin_write32(MXVR_DMA6_CONFIG, val)
182 #define bfin_write_MXVR_DMA6_START_ADDR(val) bfin_write32(MXVR_DMA6_START_ADDR)
184 #define bfin_write_MXVR_DMA6_COUNT(val) bfin_write16(MXVR_DMA6_COUNT, val)
186 #define bfin_write_MXVR_DMA6_CURR_ADDR(val) bfin_write32(MXVR_DMA6_CURR_ADDR)
188 #define bfin_write_MXVR_DMA6_CURR_COUNT(val) bfin_write16(MXVR_DMA6_CURR_COUNT, val)
193 #define bfin_write_MXVR_DMA7_CONFIG(val) bfin_write32(MXVR_DMA7_CONFIG, val)
195 #define bfin_write_MXVR_DMA7_START_ADDR(val) bfin_write32(MXVR_DMA7_START_ADDR)
197 #define bfin_write_MXVR_DMA7_COUNT(val) bfin_write16(MXVR_DMA7_COUNT, val)
199 #define bfin_write_MXVR_DMA7_CURR_ADDR(val) bfin_write32(MXVR_DMA7_CURR_ADDR)
201 #define bfin_write_MXVR_DMA7_CURR_COUNT(val) bfin_write16(MXVR_DMA7_CURR_COUNT, val)
206 #define bfin_write_MXVR_AP_CTL(val) bfin_write16(MXVR_AP_CTL, val)
208 #define bfin_write_MXVR_APRB_START_ADDR(val) bfin_write32(MXVR_APRB_START_ADDR)
210 #define bfin_write_MXVR_APRB_CURR_ADDR(val) bfin_write32(MXVR_APRB_CURR_ADDR)
212 #define bfin_write_MXVR_APTB_START_ADDR(val) bfin_write32(MXVR_APTB_START_ADDR)
214 #define bfin_write_MXVR_APTB_CURR_ADDR(val) bfin_write32(MXVR_APTB_CURR_ADDR)
219 #define bfin_write_MXVR_CM_CTL(val) bfin_write32(MXVR_CM_CTL, val)
221 #define bfin_write_MXVR_CMRB_START_ADDR(val) bfin_write32(MXVR_CMRB_START_ADDR)
223 #define bfin_write_MXVR_CMRB_CURR_ADDR(val) bfin_write32(MXVR_CMRB_CURR_ADDR)
225 #define bfin_write_MXVR_CMTB_START_ADDR(val) bfin_write32(MXVR_CMTB_START_ADDR)
227 #define bfin_write_MXVR_CMTB_CURR_ADDR(val) bfin_write32(MXVR_CMTB_CURR_ADDR)
232 #define bfin_write_MXVR_RRDB_START_ADDR(val) bfin_write32(MXVR_RRDB_START_ADDR)
234 #define bfin_write_MXVR_RRDB_CURR_ADDR(val) bfin_write32(MXVR_RRDB_CURR_ADDR)
239 #define bfin_write_MXVR_PAT_DATA_0(val) bfin_write32(MXVR_PAT_DATA_0, val)
241 #define bfin_write_MXVR_PAT_EN_0(val) bfin_write32(MXVR_PAT_EN_0, val)
243 #define bfin_write_MXVR_PAT_DATA_1(val) bfin_write32(MXVR_PAT_DATA_1, val)
245 #define bfin_write_MXVR_PAT_EN_1(val) bfin_write32(MXVR_PAT_EN_1, val)
250 #define bfin_write_MXVR_FRAME_CNT_0(val) bfin_write16(MXVR_FRAME_CNT_0, val)
252 #define bfin_write_MXVR_FRAME_CNT_1(val) bfin_write16(MXVR_FRAME_CNT_1, val)
257 #define bfin_write_MXVR_ROUTING_0(val) bfin_write32(MXVR_ROUTING_0, val)
259 #define bfin_write_MXVR_ROUTING_1(val) bfin_write32(MXVR_ROUTING_1, val)
261 #define bfin_write_MXVR_ROUTING_2(val) bfin_write32(MXVR_ROUTING_2, val)
263 #define bfin_write_MXVR_ROUTING_3(val) bfin_write32(MXVR_ROUTING_3, val)
265 #define bfin_write_MXVR_ROUTING_4(val) bfin_write32(MXVR_ROUTING_4, val)
267 #define bfin_write_MXVR_ROUTING_5(val) bfin_write32(MXVR_ROUTING_5, val)
269 #define bfin_write_MXVR_ROUTING_6(val) bfin_write32(MXVR_ROUTING_6, val)
271 #define bfin_write_MXVR_ROUTING_7(val) bfin_write32(MXVR_ROUTING_7, val)
273 #define bfin_write_MXVR_ROUTING_8(val) bfin_write32(MXVR_ROUTING_8, val)
275 #define bfin_write_MXVR_ROUTING_9(val) bfin_write32(MXVR_ROUTING_9, val)
277 #define bfin_write_MXVR_ROUTING_10(val) bfin_write32(MXVR_ROUTING_10, val)
279 #define bfin_write_MXVR_ROUTING_11(val) bfin_write32(MXVR_ROUTING_11, val)
281 #define bfin_write_MXVR_ROUTING_12(val) bfin_write32(MXVR_ROUTING_12, val)
283 #define bfin_write_MXVR_ROUTING_13(val) bfin_write32(MXVR_ROUTING_13, val)
285 #define bfin_write_MXVR_ROUTING_14(val) bfin_write32(MXVR_ROUTING_14, val)
290 #define bfin_write_MXVR_BLOCK_CNT(val) bfin_write16(MXVR_BLOCK_CNT, val)
292 #define bfin_write_MXVR_CLK_CTL(val) bfin_write32(MXVR_CLK_CTL, val)
294 #define bfin_write_MXVR_CDRPLL_CTL(val) bfin_write32(MXVR_CDRPLL_CTL, val)
296 #define bfin_write_MXVR_FMPLL_CTL(val) bfin_write32(MXVR_FMPLL_CTL, val)
298 #define bfin_write_MXVR_PIN_CTL(val) bfin_write16(MXVR_PIN_CTL, val)
300 #define bfin_write_MXVR_SCLK_CNT(val) bfin_write16(MXVR_SCLK_CNT, val)
H A DcdefBF54x_base.h18 #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
21 #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
23 #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
28 #define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
33 #define bfin_write_SWRST(val) bfin_write16(SWRST, val)
35 #define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
40 #define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val)
42 #define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
44 #define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
46 #define bfin_write_SIC_IMASK2(val) bfin_write32(SIC_IMASK2, val)
48 #define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 2)), val)
51 #define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
53 #define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
55 #define bfin_write_SIC_ISR2(val) bfin_write32(SIC_ISR2, val)
57 #define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 2)), val)
60 #define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
62 #define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val)
64 #define bfin_write_SIC_IWR2(val) bfin_write32(SIC_IWR2, val)
66 #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
68 #define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
70 #define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
72 #define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
74 #define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val)
76 #define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val)
78 #define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val)
80 #define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val)
82 #define bfin_write_SIC_IAR8(val) bfin_write32(SIC_IAR8, val)
84 #define bfin_write_SIC_IAR9(val) bfin_write32(SIC_IAR9, val)
86 #define bfin_write_SIC_IAR10(val) bfin_write32(SIC_IAR10, val)
88 #define bfin_write_SIC_IAR11(val) bfin_write32(SIC_IAR11, val)
93 #define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
95 #define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
97 #define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
102 #define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val)
104 #define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val)
106 #define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val)
108 #define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val)
110 #define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val)
112 #define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val)
117 #define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val)
119 #define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val)
121 #define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val)
123 #define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val)
125 #define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val)
127 #define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val)
129 #define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val)
131 #define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val)
133 #define bfin_write_UART0_IER_SET(val) bfin_write16(UART0_IER_SET, val)
135 #define bfin_write_UART0_IER_CLEAR(val) bfin_write16(UART0_IER_CLEAR, val)
137 #define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val)
139 #define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val)
144 #define bfin_write_SPI0_CTL(val) bfin_write16(SPI0_CTL, val)
146 #define bfin_write_SPI0_FLG(val) bfin_write16(SPI0_FLG, val)
148 #define bfin_write_SPI0_STAT(val) bfin_write16(SPI0_STAT, val)
150 #define bfin_write_SPI0_TDBR(val) bfin_write16(SPI0_TDBR, val)
152 #define bfin_write_SPI0_RDBR(val) bfin_write16(SPI0_RDBR, val)
154 #define bfin_write_SPI0_BAUD(val) bfin_write16(SPI0_BAUD, val)
156 #define bfin_write_SPI0_SHADOW(val) bfin_write16(SPI0_SHADOW, val)
167 #define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val)
169 #define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val)
171 #define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
173 #define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
175 #define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
177 #define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
179 #define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
181 #define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val)
183 #define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
185 #define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val)
187 #define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val)
189 #define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val)
191 #define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val)
193 #define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val)
195 #define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val)
197 #define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val)
199 #define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val)
201 #define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val)
203 #define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val)
205 #define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val)
207 #define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val)
209 #define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val)
214 #define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val)
216 #define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
218 #define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
220 #define bfin_write_EBIU_MBSCTL(val) bfin_write16(EBIU_MBSCTL, val)
222 #define bfin_write_EBIU_ARBSTAT(val) bfin_write32(EBIU_ARBSTAT, val)
224 #define bfin_write_EBIU_MODE(val) bfin_write32(EBIU_MODE, val)
226 #define bfin_write_EBIU_FCTL(val) bfin_write16(EBIU_FCTL, val)
231 #define bfin_write_EBIU_DDRCTL0(val) bfin_write32(EBIU_DDRCTL0, val)
233 #define bfin_write_EBIU_DDRCTL1(val) bfin_write32(EBIU_DDRCTL1, val)
235 #define bfin_write_EBIU_DDRCTL2(val) bfin_write32(EBIU_DDRCTL2, val)
237 #define bfin_write_EBIU_DDRCTL3(val) bfin_write32(EBIU_DDRCTL3, val)
239 #define bfin_write_EBIU_DDRQUE(val) bfin_write32(EBIU_DDRQUE, val)
241 #define bfin_write_EBIU_ERRADD(val) bfin_write32(EBIU_ERRADD, val)
243 #define bfin_write_EBIU_ERRMST(val) bfin_write16(EBIU_ERRMST, val)
245 #define bfin_write_EBIU_RSTCTL(val) bfin_write16(EBIU_RSTCTL, val)
250 #define bfin_write_EBIU_DDRBRC0(val) bfin_write32(EBIU_DDRBRC0, val)
252 #define bfin_write_EBIU_DDRBRC1(val) bfin_write32(EBIU_DDRBRC1, val)
254 #define bfin_write_EBIU_DDRBRC2(val) bfin_write32(EBIU_DDRBRC2, val)
256 #define bfin_write_EBIU_DDRBRC3(val) bfin_write32(EBIU_DDRBRC3, val)
258 #define bfin_write_EBIU_DDRBRC4(val) bfin_write32(EBIU_DDRBRC4, val)
260 #define bfin_write_EBIU_DDRBRC5(val) bfin_write32(EBIU_DDRBRC5, val)
262 #define bfin_write_EBIU_DDRBRC6(val) bfin_write32(EBIU_DDRBRC6, val)
264 #define bfin_write_EBIU_DDRBRC7(val) bfin_write32(EBIU_DDRBRC7, val)
266 #define bfin_write_EBIU_DDRBWC0(val) bfin_write32(EBIU_DDRBWC0, val)
268 #define bfin_write_EBIU_DDRBWC1(val) bfin_write32(EBIU_DDRBWC1, val)
270 #define bfin_write_EBIU_DDRBWC2(val) bfin_write32(EBIU_DDRBWC2, val)
272 #define bfin_write_EBIU_DDRBWC3(val) bfin_write32(EBIU_DDRBWC3, val)
274 #define bfin_write_EBIU_DDRBWC4(val) bfin_write32(EBIU_DDRBWC4, val)
276 #define bfin_write_EBIU_DDRBWC5(val) bfin_write32(EBIU_DDRBWC5, val)
278 #define bfin_write_EBIU_DDRBWC6(val) bfin_write32(EBIU_DDRBWC6, val)
280 #define bfin_write_EBIU_DDRBWC7(val) bfin_write32(EBIU_DDRBWC7, val)
282 #define bfin_write_EBIU_DDRACCT(val) bfin_write32(EBIU_DDRACCT, val)
284 #define bfin_write_EBIU_DDRTACT(val) bfin_write32(EBIU_DDRTACT, val)
286 #define bfin_write_EBIU_DDRARCT(val) bfin_write32(EBIU_DDRARCT, val)
288 #define bfin_write_EBIU_DDRGC0(val) bfin_write32(EBIU_DDRGC0, val)
290 #define bfin_write_EBIU_DDRGC1(val) bfin_write32(EBIU_DDRGC1, val)
292 #define bfin_write_EBIU_DDRGC2(val) bfin_write32(EBIU_DDRGC2, val)
294 #define bfin_write_EBIU_DDRGC3(val) bfin_write32(EBIU_DDRGC3, val)
296 #define bfin_write_EBIU_DDRMCEN(val) bfin_write32(EBIU_DDRMCEN, val)
298 #define bfin_write_EBIU_DDRMCCL(val) bfin_write32(EBIU_DDRMCCL, val)
303 #define bfin_write_DMAC0_TC_PER(val) bfin_write16(DMAC0_TC_PER, val)
305 #define bfin_write_DMAC0_TC_CNT(val) bfin_write16(DMAC0_TC_CNT, val)
310 #define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val)
312 #define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val)
314 #define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val)
316 #define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val)
318 #define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val)
320 #define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val)
322 #define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val)
324 #define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val)
326 #define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val)
328 #define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
330 #define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
332 #define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
334 #define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
339 #define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val)
341 #define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val)
343 #define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
345 #define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val)
347 #define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val)
349 #define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val)
351 #define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val)
353 #define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val)
355 #define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val)
357 #define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
359 #define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
361 #define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
363 #define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
368 #define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val)
370 #define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val)
372 #define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val)
374 #define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val)
376 #define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val)
378 #define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val)
380 #define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val)
382 #define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val)
384 #define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val)
386 #define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
388 #define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
390 #define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
392 #define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
397 #define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val)
399 #define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val)
401 #define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
403 #define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val)
405 #define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val)
407 #define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val)
409 #define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val)
411 #define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val)
413 #define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val)
415 #define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
417 #define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
419 #define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
421 #define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
426 #define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val)
428 #define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val)
430 #define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val)
432 #define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val)
434 #define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val)
436 #define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val)
438 #define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val)
440 #define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val)
442 #define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val)
444 #define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
446 #define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
448 #define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
450 #define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
455 #define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val)
457 #define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val)
459 #define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
461 #define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val)
463 #define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val)
465 #define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
467 #define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val)
469 #define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val)
471 #define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val)
473 #define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
475 #define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
477 #define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
479 #define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
484 #define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
486 #define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val)
488 #define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val)
490 #define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val)
492 #define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val)
494 #define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val)
496 #define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val)
498 #define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val)
500 #define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val)
502 #define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
504 #define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
506 #define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
508 #define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
513 #define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val)
515 #define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val)
517 #define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val)
519 #define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val)
521 #define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val)
523 #define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val)
525 #define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val)
527 #define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val)
529 #define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val)
531 #define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
533 #define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
535 #define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
537 #define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
542 #define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR, val)
544 #define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR, val)
546 #define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val)
548 #define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val)
550 #define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val)
552 #define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val)
554 #define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val)
556 #define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR, val)
558 #define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR, val)
560 #define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
562 #define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
564 #define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
566 #define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
571 #define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR, val)
573 #define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR, val)
575 #define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val)
577 #define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val)
579 #define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val)
581 #define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val)
583 #define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val)
585 #define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR, val)
587 #define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR, val)
589 #define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
591 #define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
593 #define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
595 #define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
600 #define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR, val)
602 #define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR, val)
604 #define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val)
606 #define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val)
608 #define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
610 #define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val)
612 #define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
614 #define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR, val)
616 #define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR, val)
618 #define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
620 #define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
622 #define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
624 #define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
629 #define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR, val)
631 #define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR, val)
633 #define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val)
635 #define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val)
637 #define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
639 #define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val)
641 #define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
643 #define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR, val)
645 #define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR, val)
647 #define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
649 #define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
651 #define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
653 #define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
658 #define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR, val)
660 #define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val)
662 #define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
664 #define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
666 #define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
668 #define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
670 #define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
672 #define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val)
674 #define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val)
676 #define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
678 #define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
680 #define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
682 #define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
684 #define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val)
686 #define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val)
688 #define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
690 #define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
692 #define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
694 #define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
696 #define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
698 #define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val)
700 #define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val)
702 #define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
704 #define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
706 #define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
708 #define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
713 #define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val)
715 #define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val)
717 #define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
719 #define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
721 #define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
723 #define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
725 #define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
727 #define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val)
729 #define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val)
731 #define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
733 #define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
735 #define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
737 #define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
739 #define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val)
741 #define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val)
743 #define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
745 #define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
747 #define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
749 #define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
751 #define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
753 #define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val)
755 #define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val)
757 #define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
759 #define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
761 #define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
763 #define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
768 #define bfin_write_EPPI1_STATUS(val) bfin_write16(EPPI1_STATUS, val)
770 #define bfin_write_EPPI1_HCOUNT(val) bfin_write16(EPPI1_HCOUNT, val)
772 #define bfin_write_EPPI1_HDELAY(val) bfin_write16(EPPI1_HDELAY, val)
774 #define bfin_write_EPPI1_VCOUNT(val) bfin_write16(EPPI1_VCOUNT, val)
776 #define bfin_write_EPPI1_VDELAY(val) bfin_write16(EPPI1_VDELAY, val)
778 #define bfin_write_EPPI1_FRAME(val) bfin_write16(EPPI1_FRAME, val)
780 #define bfin_write_EPPI1_LINE(val) bfin_write16(EPPI1_LINE, val)
782 #define bfin_write_EPPI1_CLKDIV(val) bfin_write16(EPPI1_CLKDIV, val)
784 #define bfin_write_EPPI1_CONTROL(val) bfin_write32(EPPI1_CONTROL, val)
786 #define bfin_write_EPPI1_FS1W_HBL(val) bfin_write32(EPPI1_FS1W_HBL, val)
788 #define bfin_write_EPPI1_FS1P_AVPL(val) bfin_write32(EPPI1_FS1P_AVPL, val)
790 #define bfin_write_EPPI1_FS2W_LVB(val) bfin_write32(EPPI1_FS2W_LVB, val)
792 #define bfin_write_EPPI1_FS2P_LAVF(val) bfin_write32(EPPI1_FS2P_LAVF, val)
794 #define bfin_write_EPPI1_CLIP(val) bfin_write32(EPPI1_CLIP, val)
799 #define bfin_write_PINT0_MASK_SET(val) bfin_write32(PINT0_MASK_SET, val)
801 #define bfin_write_PINT0_MASK_CLEAR(val) bfin_write32(PINT0_MASK_CLEAR, val)
803 #define bfin_write_PINT0_REQUEST(val) bfin_write32(PINT0_REQUEST, val)
805 #define bfin_write_PINT0_ASSIGN(val) bfin_write32(PINT0_ASSIGN, val)
807 #define bfin_write_PINT0_EDGE_SET(val) bfin_write32(PINT0_EDGE_SET, val)
809 #define bfin_write_PINT0_EDGE_CLEAR(val) bfin_write32(PINT0_EDGE_CLEAR, val)
811 #define bfin_write_PINT0_INVERT_SET(val) bfin_write32(PINT0_INVERT_SET, val)
813 #define bfin_write_PINT0_INVERT_CLEAR(val) bfin_write32(PINT0_INVERT_CLEAR, val)
815 #define bfin_write_PINT0_PINSTATE(val) bfin_write32(PINT0_PINSTATE, val)
817 #define bfin_write_PINT0_LATCH(val) bfin_write32(PINT0_LATCH, val)
822 #define bfin_write_PINT1_MASK_SET(val) bfin_write32(PINT1_MASK_SET, val)
824 #define bfin_write_PINT1_MASK_CLEAR(val) bfin_write32(PINT1_MASK_CLEAR, val)
826 #define bfin_write_PINT1_REQUEST(val) bfin_write32(PINT1_REQUEST, val)
828 #define bfin_write_PINT1_ASSIGN(val) bfin_write32(PINT1_ASSIGN, val)
830 #define bfin_write_PINT1_EDGE_SET(val) bfin_write32(PINT1_EDGE_SET, val)
832 #define bfin_write_PINT1_EDGE_CLEAR(val) bfin_write32(PINT1_EDGE_CLEAR, val)
834 #define bfin_write_PINT1_INVERT_SET(val) bfin_write32(PINT1_INVERT_SET, val)
836 #define bfin_write_PINT1_INVERT_CLEAR(val) bfin_write32(PINT1_INVERT_CLEAR, val)
838 #define bfin_write_PINT1_PINSTATE(val) bfin_write32(PINT1_PINSTATE, val)
840 #define bfin_write_PINT1_LATCH(val) bfin_write32(PINT1_LATCH, val)
845 #define bfin_write_PINT2_MASK_SET(val) bfin_write32(PINT2_MASK_SET, val)
847 #define bfin_write_PINT2_MASK_CLEAR(val) bfin_write32(PINT2_MASK_CLEAR, val)
849 #define bfin_write_PINT2_REQUEST(val) bfin_write32(PINT2_REQUEST, val)
851 #define bfin_write_PINT2_ASSIGN(val) bfin_write32(PINT2_ASSIGN, val)
853 #define bfin_write_PINT2_EDGE_SET(val) bfin_write32(PINT2_EDGE_SET, val)
855 #define bfin_write_PINT2_EDGE_CLEAR(val) bfin_write32(PINT2_EDGE_CLEAR, val)
857 #define bfin_write_PINT2_INVERT_SET(val) bfin_write32(PINT2_INVERT_SET, val)
859 #define bfin_write_PINT2_INVERT_CLEAR(val) bfin_write32(PINT2_INVERT_CLEAR, val)
861 #define bfin_write_PINT2_PINSTATE(val) bfin_write32(PINT2_PINSTATE, val)
863 #define bfin_write_PINT2_LATCH(val) bfin_write32(PINT2_LATCH, val)
868 #define bfin_write_PINT3_MASK_SET(val) bfin_write32(PINT3_MASK_SET, val)
870 #define bfin_write_PINT3_MASK_CLEAR(val) bfin_write32(PINT3_MASK_CLEAR, val)
872 #define bfin_write_PINT3_REQUEST(val) bfin_write32(PINT3_REQUEST, val)
874 #define bfin_write_PINT3_ASSIGN(val) bfin_write32(PINT3_ASSIGN, val)
876 #define bfin_write_PINT3_EDGE_SET(val) bfin_write32(PINT3_EDGE_SET, val)
878 #define bfin_write_PINT3_EDGE_CLEAR(val) bfin_write32(PINT3_EDGE_CLEAR, val)
880 #define bfin_write_PINT3_INVERT_SET(val) bfin_write32(PINT3_INVERT_SET, val)
882 #define bfin_write_PINT3_INVERT_CLEAR(val) bfin_write32(PINT3_INVERT_CLEAR, val)
884 #define bfin_write_PINT3_PINSTATE(val) bfin_write32(PINT3_PINSTATE, val)
886 #define bfin_write_PINT3_LATCH(val) bfin_write32(PINT3_LATCH, val)
891 #define bfin_write_PORTA_FER(val) bfin_write16(PORTA_FER, val)
893 #define bfin_write_PORTA(val) bfin_write16(PORTA, val)
895 #define bfin_write_PORTA_SET(val) bfin_write16(PORTA_SET, val)
897 #define bfin_write_PORTA_CLEAR(val) bfin_write16(PORTA_CLEAR, val)
899 #define bfin_write_PORTA_DIR_SET(val) bfin_write16(PORTA_DIR_SET, val)
901 #define bfin_write_PORTA_DIR_CLEAR(val) bfin_write16(PORTA_DIR_CLEAR, val)
903 #define bfin_write_PORTA_INEN(val) bfin_write16(PORTA_INEN, val)
905 #define bfin_write_PORTA_MUX(val) bfin_write32(PORTA_MUX, val)
910 #define bfin_write_PORTB_FER(val) bfin_write16(PORTB_FER, val)
912 #define bfin_write_PORTB(val) bfin_write16(PORTB, val)
914 #define bfin_write_PORTB_SET(val) bfin_write16(PORTB_SET, val)
916 #define bfin_write_PORTB_CLEAR(val) bfin_write16(PORTB_CLEAR, val)
918 #define bfin_write_PORTB_DIR_SET(val) bfin_write16(PORTB_DIR_SET, val)
920 #define bfin_write_PORTB_DIR_CLEAR(val) bfin_write16(PORTB_DIR_CLEAR, val)
922 #define bfin_write_PORTB_INEN(val) bfin_write16(PORTB_INEN, val)
924 #define bfin_write_PORTB_MUX(val) bfin_write32(PORTB_MUX, val)
929 #define bfin_write_PORTC_FER(val) bfin_write16(PORTC_FER, val)
931 #define bfin_write_PORTC(val) bfin_write16(PORTC, val)
933 #define bfin_write_PORTC_SET(val) bfin_write16(PORTC_SET, val)
935 #define bfin_write_PORTC_CLEAR(val) bfin_write16(PORTC_CLEAR, val)
937 #define bfin_write_PORTC_DIR_SET(val) bfin_write16(PORTC_DIR_SET, val)
939 #define bfin_write_PORTC_DIR_CLEAR(val) bfin_write16(PORTC_DIR_CLEAR, val)
941 #define bfin_write_PORTC_INEN(val) bfin_write16(PORTC_INEN, val)
943 #define bfin_write_PORTC_MUX(val) bfin_write32(PORTC_MUX, val)
948 #define bfin_write_PORTD_FER(val) bfin_write16(PORTD_FER, val)
950 #define bfin_write_PORTD(val) bfin_write16(PORTD, val)
952 #define bfin_write_PORTD_SET(val) bfin_write16(PORTD_SET, val)
954 #define bfin_write_PORTD_CLEAR(val) bfin_write16(PORTD_CLEAR, val)
956 #define bfin_write_PORTD_DIR_SET(val) bfin_write16(PORTD_DIR_SET, val)
958 #define bfin_write_PORTD_DIR_CLEAR(val) bfin_write16(PORTD_DIR_CLEAR, val)
960 #define bfin_write_PORTD_INEN(val) bfin_write16(PORTD_INEN, val)
962 #define bfin_write_PORTD_MUX(val) bfin_write32(PORTD_MUX, val)
967 #define bfin_write_PORTE_FER(val) bfin_write16(PORTE_FER, val)
969 #define bfin_write_PORTE(val) bfin_write16(PORTE, val)
971 #define bfin_write_PORTE_SET(val) bfin_write16(PORTE_SET, val)
973 #define bfin_write_PORTE_CLEAR(val) bfin_write16(PORTE_CLEAR, val)
975 #define bfin_write_PORTE_DIR_SET(val) bfin_write16(PORTE_DIR_SET, val)
977 #define bfin_write_PORTE_DIR_CLEAR(val) bfin_write16(PORTE_DIR_CLEAR, val)
979 #define bfin_write_PORTE_INEN(val) bfin_write16(PORTE_INEN, val)
981 #define bfin_write_PORTE_MUX(val) bfin_write32(PORTE_MUX, val)
986 #define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val)
988 #define bfin_write_PORTF(val) bfin_write16(PORTF, val)
990 #define bfin_write_PORTF_SET(val) bfin_write16(PORTF_SET, val)
992 #define bfin_write_PORTF_CLEAR(val) bfin_write16(PORTF_CLEAR, val)
994 #define bfin_write_PORTF_DIR_SET(val) bfin_write16(PORTF_DIR_SET, val)
996 #define bfin_write_PORTF_DIR_CLEAR(val) bfin_write16(PORTF_DIR_CLEAR, val)
998 #define bfin_write_PORTF_INEN(val) bfin_write16(PORTF_INEN, val)
1000 #define bfin_write_PORTF_MUX(val) bfin_write32(PORTF_MUX, val)
1005 #define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val)
1007 #define bfin_write_PORTG(val) bfin_write16(PORTG, val)
1009 #define bfin_write_PORTG_SET(val) bfin_write16(PORTG_SET, val)
1011 #define bfin_write_PORTG_CLEAR(val) bfin_write16(PORTG_CLEAR, val)
1013 #define bfin_write_PORTG_DIR_SET(val) bfin_write16(PORTG_DIR_SET, val)
1015 #define bfin_write_PORTG_DIR_CLEAR(val) bfin_write16(PORTG_DIR_CLEAR, val)
1017 #define bfin_write_PORTG_INEN(val) bfin_write16(PORTG_INEN, val)
1019 #define bfin_write_PORTG_MUX(val) bfin_write32(PORTG_MUX, val)
1024 #define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val)
1026 #define bfin_write_PORTH(val) bfin_write16(PORTH, val)
1028 #define bfin_write_PORTH_SET(val) bfin_write16(PORTH_SET, val)
1030 #define bfin_write_PORTH_CLEAR(val) bfin_write16(PORTH_CLEAR, val)
1032 #define bfin_write_PORTH_DIR_SET(val) bfin_write16(PORTH_DIR_SET, val)
1034 #define bfin_write_PORTH_DIR_CLEAR(val) bfin_write16(PORTH_DIR_CLEAR, val)
1036 #define bfin_write_PORTH_INEN(val) bfin_write16(PORTH_INEN, val)
1038 #define bfin_write_PORTH_MUX(val) bfin_write32(PORTH_MUX, val)
1043 #define bfin_write_PORTI_FER(val) bfin_write16(PORTI_FER, val)
1045 #define bfin_write_PORTI(val) bfin_write16(PORTI, val)
1047 #define bfin_write_PORTI_SET(val) bfin_write16(PORTI_SET, val)
1049 #define bfin_write_PORTI_CLEAR(val) bfin_write16(PORTI_CLEAR, val)
1051 #define bfin_write_PORTI_DIR_SET(val) bfin_write16(PORTI_DIR_SET, val)
1053 #define bfin_write_PORTI_DIR_CLEAR(val) bfin_write16(PORTI_DIR_CLEAR, val)
1055 #define bfin_write_PORTI_INEN(val) bfin_write16(PORTI_INEN, val)
1057 #define bfin_write_PORTI_MUX(val) bfin_write32(PORTI_MUX, val)
1062 #define bfin_write_PORTJ_FER(val) bfin_write16(PORTJ_FER, val)
1064 #define bfin_write_PORTJ(val) bfin_write16(PORTJ, val)
1066 #define bfin_write_PORTJ_SET(val) bfin_write16(PORTJ_SET, val)
1068 #define bfin_write_PORTJ_CLEAR(val) bfin_write16(PORTJ_CLEAR, val)
1070 #define bfin_write_PORTJ_DIR_SET(val) bfin_write16(PORTJ_DIR_SET, val)
1072 #define bfin_write_PORTJ_DIR_CLEAR(val) bfin_write16(PORTJ_DIR_CLEAR, val)
1074 #define bfin_write_PORTJ_INEN(val) bfin_write16(PORTJ_INEN, val)
1076 #define bfin_write_PORTJ_MUX(val) bfin_write32(PORTJ_MUX, val)
1081 #define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
1083 #define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
1085 #define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
1087 #define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
1089 #define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
1091 #define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
1093 #define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
1095 #define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
1097 #define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
1099 #define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
1101 #define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
1103 #define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
1105 #define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val)
1107 #define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
1109 #define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val)
1111 #define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val)
1113 #define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val)
1115 #define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
1117 #define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val)
1119 #define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val)
1121 #define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val)
1123 #define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
1125 #define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val)
1127 #define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val)
1129 #define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val)
1131 #define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
1133 #define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val)
1135 #define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val)
1137 #define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val)
1139 #define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
1141 #define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val)
1143 #define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val)
1148 #define bfin_write_TIMER_ENABLE0(val) bfin_write16(TIMER_ENABLE0, val)
1150 #define bfin_write_TIMER_DISABLE0(val) bfin_write16(TIMER_DISABLE0, val)
1152 #define bfin_write_TIMER_STATUS0(val) bfin_write32(TIMER_STATUS0, val)
1157 #define bfin_write_DMAC1_TC_PER(val) bfin_write16(DMAC1_TC_PER, val)
1159 #define bfin_write_DMAC1_TC_CNT(val) bfin_write16(DMAC1_TC_CNT, val)
1164 #define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_write32(DMA12_NEXT_DESC_PTR, val)
1166 #define bfin_write_DMA12_START_ADDR(val) bfin_write32(DMA12_START_ADDR, val)
1168 #define bfin_write_DMA12_CONFIG(val) bfin_write16(DMA12_CONFIG, val)
1170 #define bfin_write_DMA12_X_COUNT(val) bfin_write16(DMA12_X_COUNT, val)
1172 #define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val)
1174 #define bfin_write_DMA12_Y_COUNT(val) bfin_write16(DMA12_Y_COUNT, val)
1176 #define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val)
1178 #define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_write32(DMA12_CURR_DESC_PTR, val)
1180 #define bfin_write_DMA12_CURR_ADDR(val) bfin_write32(DMA12_CURR_ADDR, val)
1182 #define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val)
1184 #define bfin_write_DMA12_PERIPHERAL_MAP(val) bfin_write16(DMA12_PERIPHERAL_MAP, val)
1186 #define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write16(DMA12_CURR_X_COUNT, val)
1188 #define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write16(DMA12_CURR_Y_COUNT, val)
1193 #define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_write32(DMA13_NEXT_DESC_PTR, val)
1195 #define bfin_write_DMA13_START_ADDR(val) bfin_write32(DMA13_START_ADDR, val)
1197 #define bfin_write_DMA13_CONFIG(val) bfin_write16(DMA13_CONFIG, val)
1199 #define bfin_write_DMA13_X_COUNT(val) bfin_write16(DMA13_X_COUNT, val)
1201 #define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val)
1203 #define bfin_write_DMA13_Y_COUNT(val) bfin_write16(DMA13_Y_COUNT, val)
1205 #define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val)
1207 #define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_write32(DMA13_CURR_DESC_PTR, val)
1209 #define bfin_write_DMA13_CURR_ADDR(val) bfin_write32(DMA13_CURR_ADDR, val)
1211 #define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val)
1213 #define bfin_write_DMA13_PERIPHERAL_MAP(val) bfin_write16(DMA13_PERIPHERAL_MAP, val)
1215 #define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write16(DMA13_CURR_X_COUNT, val)
1217 #define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write16(DMA13_CURR_Y_COUNT, val)
1222 #define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_write32(DMA14_NEXT_DESC_PTR, val)
1224 #define bfin_write_DMA14_START_ADDR(val) bfin_write32(DMA14_START_ADDR, val)
1226 #define bfin_write_DMA14_CONFIG(val) bfin_write16(DMA14_CONFIG, val)
1228 #define bfin_write_DMA14_X_COUNT(val) bfin_write16(DMA14_X_COUNT, val)
1230 #define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val)
1232 #define bfin_write_DMA14_Y_COUNT(val) bfin_write16(DMA14_Y_COUNT, val)
1234 #define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val)
1236 #define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_write32(DMA14_CURR_DESC_PTR, val)
1238 #define bfin_write_DMA14_CURR_ADDR(val) bfin_write32(DMA14_CURR_ADDR, val)
1240 #define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val)
1242 #define bfin_write_DMA14_PERIPHERAL_MAP(val) bfin_write16(DMA14_PERIPHERAL_MAP, val)
1244 #define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write16(DMA14_CURR_X_COUNT, val)
1246 #define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write16(DMA14_CURR_Y_COUNT, val)
1251 #define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_write32(DMA15_NEXT_DESC_PTR, val)
1253 #define bfin_write_DMA15_START_ADDR(val) bfin_write32(DMA15_START_ADDR, val)
1255 #define bfin_write_DMA15_CONFIG(val) bfin_write16(DMA15_CONFIG, val)
1257 #define bfin_write_DMA15_X_COUNT(val) bfin_write16(DMA15_X_COUNT, val)
1259 #define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val)
1261 #define bfin_write_DMA15_Y_COUNT(val) bfin_write16(DMA15_Y_COUNT, val)
1263 #define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val)
1265 #define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_write32(DMA15_CURR_DESC_PTR, val)
1267 #define bfin_write_DMA15_CURR_ADDR(val) bfin_write32(DMA15_CURR_ADDR, val)
1269 #define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val)
1271 #define bfin_write_DMA15_PERIPHERAL_MAP(val) bfin_write16(DMA15_PERIPHERAL_MAP, val)
1273 #define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write16(DMA15_CURR_X_COUNT, val)
1275 #define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write16(DMA15_CURR_Y_COUNT, val)
1280 #define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_write32(DMA16_NEXT_DESC_PTR, val)
1282 #define bfin_write_DMA16_START_ADDR(val) bfin_write32(DMA16_START_ADDR, val)
1284 #define bfin_write_DMA16_CONFIG(val) bfin_write16(DMA16_CONFIG, val)
1286 #define bfin_write_DMA16_X_COUNT(val) bfin_write16(DMA16_X_COUNT, val)
1288 #define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val)
1290 #define bfin_write_DMA16_Y_COUNT(val) bfin_write16(DMA16_Y_COUNT, val)
1292 #define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val)
1294 #define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_write32(DMA16_CURR_DESC_PTR, val)
1296 #define bfin_write_DMA16_CURR_ADDR(val) bfin_write32(DMA16_CURR_ADDR, val)
1298 #define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val)
1300 #define bfin_write_DMA16_PERIPHERAL_MAP(val) bfin_write16(DMA16_PERIPHERAL_MAP, val)
1302 #define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write16(DMA16_CURR_X_COUNT, val)
1304 #define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write16(DMA16_CURR_Y_COUNT, val)
1309 #define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_write32(DMA17_NEXT_DESC_PTR, val)
1311 #define bfin_write_DMA17_START_ADDR(val) bfin_write32(DMA17_START_ADDR, val)
1313 #define bfin_write_DMA17_CONFIG(val) bfin_write16(DMA17_CONFIG, val)
1315 #define bfin_write_DMA17_X_COUNT(val) bfin_write16(DMA17_X_COUNT, val)
1317 #define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val)
1319 #define bfin_write_DMA17_Y_COUNT(val) bfin_write16(DMA17_Y_COUNT, val)
1321 #define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val)
1323 #define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_write32(DMA17_CURR_DESC_PTR, val)
1325 #define bfin_write_DMA17_CURR_ADDR(val) bfin_write32(DMA17_CURR_ADDR, val)
1327 #define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val)
1329 #define bfin_write_DMA17_PERIPHERAL_MAP(val) bfin_write16(DMA17_PERIPHERAL_MAP, val)
1331 #define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write16(DMA17_CURR_X_COUNT, val)
1333 #define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write16(DMA17_CURR_Y_COUNT, val)
1338 #define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_write32(DMA18_NEXT_DESC_PTR, val)
1340 #define bfin_write_DMA18_START_ADDR(val) bfin_write32(DMA18_START_ADDR, val)
1342 #define bfin_write_DMA18_CONFIG(val) bfin_write16(DMA18_CONFIG, val)
1344 #define bfin_write_DMA18_X_COUNT(val) bfin_write16(DMA18_X_COUNT, val)
1346 #define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val)
1348 #define bfin_write_DMA18_Y_COUNT(val) bfin_write16(DMA18_Y_COUNT, val)
1350 #define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val)
1352 #define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_write32(DMA18_CURR_DESC_PTR, val)
1354 #define bfin_write_DMA18_CURR_ADDR(val) bfin_write32(DMA18_CURR_ADDR, val)
1356 #define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val)
1358 #define bfin_write_DMA18_PERIPHERAL_MAP(val) bfin_write16(DMA18_PERIPHERAL_MAP, val)
1360 #define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write16(DMA18_CURR_X_COUNT, val)
1362 #define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write16(DMA18_CURR_Y_COUNT, val)
1367 #define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_write32(DMA19_NEXT_DESC_PTR, val)
1369 #define bfin_write_DMA19_START_ADDR(val) bfin_write32(DMA19_START_ADDR, val)
1371 #define bfin_write_DMA19_CONFIG(val) bfin_write16(DMA19_CONFIG, val)
1373 #define bfin_write_DMA19_X_COUNT(val) bfin_write16(DMA19_X_COUNT, val)
1375 #define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val)
1377 #define bfin_write_DMA19_Y_COUNT(val) bfin_write16(DMA19_Y_COUNT, val)
1379 #define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val)
1381 #define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_write32(DMA19_CURR_DESC_PTR, val)
1383 #define bfin_write_DMA19_CURR_ADDR(val) bfin_write32(DMA19_CURR_ADDR, val)
1385 #define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val)
1387 #define bfin_write_DMA19_PERIPHERAL_MAP(val) bfin_write16(DMA19_PERIPHERAL_MAP, val)
1389 #define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val)
1391 #define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val)
1396 #define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_write32(DMA20_NEXT_DESC_PTR, val)
1398 #define bfin_write_DMA20_START_ADDR(val) bfin_write32(DMA20_START_ADDR, val)
1400 #define bfin_write_DMA20_CONFIG(val) bfin_write16(DMA20_CONFIG, val)
1402 #define bfin_write_DMA20_X_COUNT(val) bfin_write16(DMA20_X_COUNT, val)
1404 #define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY, val)
1406 #define bfin_write_DMA20_Y_COUNT(val) bfin_write16(DMA20_Y_COUNT, val)
1408 #define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY, val)
1410 #define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_write32(DMA20_CURR_DESC_PTR, val)
1412 #define bfin_write_DMA20_CURR_ADDR(val) bfin_write32(DMA20_CURR_ADDR, val)
1414 #define bfin_write_DMA20_IRQ_STATUS(val) bfin_write16(DMA20_IRQ_STATUS, val)
1416 #define bfin_write_DMA20_PERIPHERAL_MAP(val) bfin_write16(DMA20_PERIPHERAL_MAP, val)
1418 #define bfin_write_DMA20_CURR_X_COUNT(val) bfin_write16(DMA20_CURR_X_COUNT, val)
1420 #define bfin_write_DMA20_CURR_Y_COUNT(val) bfin_write16(DMA20_CURR_Y_COUNT, val)
1425 #define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_write32(DMA21_NEXT_DESC_PTR, val)
1427 #define bfin_write_DMA21_START_ADDR(val) bfin_write32(DMA21_START_ADDR, val)
1429 #define bfin_write_DMA21_CONFIG(val) bfin_write16(DMA21_CONFIG, val)
1431 #define bfin_write_DMA21_X_COUNT(val) bfin_write16(DMA21_X_COUNT, val)
1433 #define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY, val)
1435 #define bfin_write_DMA21_Y_COUNT(val) bfin_write16(DMA21_Y_COUNT, val)
1437 #define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY, val)
1439 #define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_write32(DMA21_CURR_DESC_PTR, val)
1441 #define bfin_write_DMA21_CURR_ADDR(val) bfin_write32(DMA21_CURR_ADDR, val)
1443 #define bfin_write_DMA21_IRQ_STATUS(val) bfin_write16(DMA21_IRQ_STATUS, val)
1445 #define bfin_write_DMA21_PERIPHERAL_MAP(val) bfin_write16(DMA21_PERIPHERAL_MAP, val)
1447 #define bfin_write_DMA21_CURR_X_COUNT(val) bfin_write16(DMA21_CURR_X_COUNT, val)
1449 #define bfin_write_DMA21_CURR_Y_COUNT(val) bfin_write16(DMA21_CURR_Y_COUNT, val)
1454 #define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_write32(DMA22_NEXT_DESC_PTR, val)
1456 #define bfin_write_DMA22_START_ADDR(val) bfin_write32(DMA22_START_ADDR, val)
1458 #define bfin_write_DMA22_CONFIG(val) bfin_write16(DMA22_CONFIG, val)
1460 #define bfin_write_DMA22_X_COUNT(val) bfin_write16(DMA22_X_COUNT, val)
1462 #define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY, val)
1464 #define bfin_write_DMA22_Y_COUNT(val) bfin_write16(DMA22_Y_COUNT, val)
1466 #define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY, val)
1468 #define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_write32(DMA22_CURR_DESC_PTR, val)
1470 #define bfin_write_DMA22_CURR_ADDR(val) bfin_write32(DMA22_CURR_ADDR, val)
1472 #define bfin_write_DMA22_IRQ_STATUS(val) bfin_write16(DMA22_IRQ_STATUS, val)
1474 #define bfin_write_DMA22_PERIPHERAL_MAP(val) bfin_write16(DMA22_PERIPHERAL_MAP, val)
1476 #define bfin_write_DMA22_CURR_X_COUNT(val) bfin_write16(DMA22_CURR_X_COUNT, val)
1478 #define bfin_write_DMA22_CURR_Y_COUNT(val) bfin_write16(DMA22_CURR_Y_COUNT, val)
1483 #define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_write32(DMA23_NEXT_DESC_PTR, val)
1485 #define bfin_write_DMA23_START_ADDR(val) bfin_write32(DMA23_START_ADDR, val)
1487 #define bfin_write_DMA23_CONFIG(val) bfin_write16(DMA23_CONFIG, val)
1489 #define bfin_write_DMA23_X_COUNT(val) bfin_write16(DMA23_X_COUNT, val)
1491 #define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY, val)
1493 #define bfin_write_DMA23_Y_COUNT(val) bfin_write16(DMA23_Y_COUNT, val)
1495 #define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY, val)
1497 #define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_write32(DMA23_CURR_DESC_PTR, val)
1499 #define bfin_write_DMA23_CURR_ADDR(val) bfin_write32(DMA23_CURR_ADDR, val)
1501 #define bfin_write_DMA23_IRQ_STATUS(val) bfin_write16(DMA23_IRQ_STATUS, val)
1503 #define bfin_write_DMA23_PERIPHERAL_MAP(val) bfin_write16(DMA23_PERIPHERAL_MAP, val)
1505 #define bfin_write_DMA23_CURR_X_COUNT(val) bfin_write16(DMA23_CURR_X_COUNT, val)
1507 #define bfin_write_DMA23_CURR_Y_COUNT(val) bfin_write16(DMA23_CURR_Y_COUNT, val)
1512 #define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_write32(MDMA_D2_NEXT_DESC_PTR, val)
1514 #define bfin_write_MDMA_D2_START_ADDR(val) bfin_write32(MDMA_D2_START_ADDR, val)
1516 #define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val)
1518 #define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val)
1520 #define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val)
1522 #define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val)
1524 #define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val)
1526 #define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_write32(MDMA_D2_CURR_DESC_PTR, val)
1528 #define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_write32(MDMA_D2_CURR_ADDR, val)
1530 #define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val)
1532 #define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP, val)
1534 #define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT, val)
1536 #define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val)
1538 #define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_write32(MDMA_S2_NEXT_DESC_PTR, val)
1540 #define bfin_write_MDMA_S2_START_ADDR(val) bfin_write32(MDMA_S2_START_ADDR, val)
1542 #define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val)
1544 #define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val)
1546 #define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val)
1548 #define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val)
1550 #define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val)
1552 #define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_write32(MDMA_S2_CURR_DESC_PTR, val)
1554 #define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_write32(MDMA_S2_CURR_ADDR, val)
1556 #define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val)
1558 #define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP, val)
1560 #define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT, val)
1562 #define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT, val)
1567 #define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_write32(MDMA_D3_NEXT_DESC_PTR, val)
1569 #define bfin_write_MDMA_D3_START_ADDR(val) bfin_write32(MDMA_D3_START_ADDR, val)
1571 #define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val)
1573 #define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val)
1575 #define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val)
1577 #define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val)
1579 #define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val)
1581 #define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_write32(MDMA_D3_CURR_DESC_PTR, val)
1583 #define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_write32(MDMA_D3_CURR_ADDR, val)
1585 #define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val)
1587 #define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP, val)
1589 #define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT, val)
1591 #define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val)
1593 #define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_write32(MDMA_S3_NEXT_DESC_PTR, val)
1595 #define bfin_write_MDMA_S3_START_ADDR(val) bfin_write32(MDMA_S3_START_ADDR, val)
1597 #define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val)
1599 #define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val)
1601 #define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val)
1603 #define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val)
1605 #define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val)
1607 #define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_write32(MDMA_S3_CURR_DESC_PTR, val)
1609 #define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_write32(MDMA_S3_CURR_ADDR, val)
1611 #define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val)
1613 #define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP, val)
1615 #define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT, val)
1617 #define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT, val)
1622 #define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val)
1624 #define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val)
1626 #define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val)
1628 #define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val)
1630 #define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val)
1632 #define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val)
1634 #define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val)
1636 #define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val)
1638 #define bfin_write_UART1_IER_SET(val) bfin_write16(UART1_IER_SET, val)
1640 #define bfin_write_UART1_IER_CLEAR(val) bfin_write16(UART1_IER_CLEAR, val)
1642 #define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val)
1644 #define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val)
1651 #define bfin_write_SPI1_CTL(val) bfin_write16(SPI1_CTL, val)
1653 #define bfin_write_SPI1_FLG(val) bfin_write16(SPI1_FLG, val)
1655 #define bfin_write_SPI1_STAT(val) bfin_write16(SPI1_STAT, val)
1657 #define bfin_write_SPI1_TDBR(val) bfin_write16(SPI1_TDBR, val)
1659 #define bfin_write_SPI1_RDBR(val) bfin_write16(SPI1_RDBR, val)
1661 #define bfin_write_SPI1_BAUD(val) bfin_write16(SPI1_BAUD, val)
1663 #define bfin_write_SPI1_SHADOW(val) bfin_write16(SPI1_SHADOW, val)
1668 #define bfin_write_SPORT2_TCR1(val) bfin_write16(SPORT2_TCR1, val)
1670 #define bfin_write_SPORT2_TCR2(val) bfin_write16(SPORT2_TCR2, val)
1672 #define bfin_write_SPORT2_TCLKDIV(val) bfin_write16(SPORT2_TCLKDIV, val)
1674 #define bfin_write_SPORT2_TFSDIV(val) bfin_write16(SPORT2_TFSDIV, val)
1676 #define bfin_write_SPORT2_TX(val) bfin_write32(SPORT2_TX, val)
1678 #define bfin_write_SPORT2_RX(val) bfin_write32(SPORT2_RX, val)
1680 #define bfin_write_SPORT2_RCR1(val) bfin_write16(SPORT2_RCR1, val)
1682 #define bfin_write_SPORT2_RCR2(val) bfin_write16(SPORT2_RCR2, val)
1684 #define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val)
1686 #define bfin_write_SPORT2_RFSDIV(val) bfin_write16(SPORT2_RFSDIV, val)
1688 #define bfin_write_SPORT2_STAT(val) bfin_write16(SPORT2_STAT, val)
1690 #define bfin_write_SPORT2_CHNL(val) bfin_write16(SPORT2_CHNL, val)
1692 #define bfin_write_SPORT2_MCMC1(val) bfin_write16(SPORT2_MCMC1, val)
1694 #define bfin_write_SPORT2_MCMC2(val) bfin_write16(SPORT2_MCMC2, val)
1696 #define bfin_write_SPORT2_MTCS0(val) bfin_write32(SPORT2_MTCS0, val)
1698 #define bfin_write_SPORT2_MTCS1(val) bfin_write32(SPORT2_MTCS1, val)
1700 #define bfin_write_SPORT2_MTCS2(val) bfin_write32(SPORT2_MTCS2, val)
1702 #define bfin_write_SPORT2_MTCS3(val) bfin_write32(SPORT2_MTCS3, val)
1704 #define bfin_write_SPORT2_MRCS0(val) bfin_write32(SPORT2_MRCS0, val)
1706 #define bfin_write_SPORT2_MRCS1(val) bfin_write32(SPORT2_MRCS1, val)
1708 #define bfin_write_SPORT2_MRCS2(val) bfin_write32(SPORT2_MRCS2, val)
1710 #define bfin_write_SPORT2_MRCS3(val) bfin_write32(SPORT2_MRCS3, val)
1715 #define bfin_write_SPORT3_TCR1(val) bfin_write16(SPORT3_TCR1, val)
1717 #define bfin_write_SPORT3_TCR2(val) bfin_write16(SPORT3_TCR2, val)
1719 #define bfin_write_SPORT3_TCLKDIV(val) bfin_write16(SPORT3_TCLKDIV, val)
1721 #define bfin_write_SPORT3_TFSDIV(val) bfin_write16(SPORT3_TFSDIV, val)
1723 #define bfin_write_SPORT3_TX(val) bfin_write32(SPORT3_TX, val)
1725 #define bfin_write_SPORT3_RX(val) bfin_write32(SPORT3_RX, val)
1727 #define bfin_write_SPORT3_RCR1(val) bfin_write16(SPORT3_RCR1, val)
1729 #define bfin_write_SPORT3_RCR2(val) bfin_write16(SPORT3_RCR2, val)
1731 #define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val)
1733 #define bfin_write_SPORT3_RFSDIV(val) bfin_write16(SPORT3_RFSDIV, val)
1735 #define bfin_write_SPORT3_STAT(val) bfin_write16(SPORT3_STAT, val)
1737 #define bfin_write_SPORT3_CHNL(val) bfin_write16(SPORT3_CHNL, val)
1739 #define bfin_write_SPORT3_MCMC1(val) bfin_write16(SPORT3_MCMC1, val)
1741 #define bfin_write_SPORT3_MCMC2(val) bfin_write16(SPORT3_MCMC2, val)
1743 #define bfin_write_SPORT3_MTCS0(val) bfin_write32(SPORT3_MTCS0, val)
1745 #define bfin_write_SPORT3_MTCS1(val) bfin_write32(SPORT3_MTCS1, val)
1747 #define bfin_write_SPORT3_MTCS2(val) bfin_write32(SPORT3_MTCS2, val)
1749 #define bfin_write_SPORT3_MTCS3(val) bfin_write32(SPORT3_MTCS3, val)
1751 #define bfin_write_SPORT3_MRCS0(val) bfin_write32(SPORT3_MRCS0, val)
1753 #define bfin_write_SPORT3_MRCS1(val) bfin_write32(SPORT3_MRCS1, val)
1755 #define bfin_write_SPORT3_MRCS2(val) bfin_write32(SPORT3_MRCS2, val)
1757 #define bfin_write_SPORT3_MRCS3(val) bfin_write32(SPORT3_MRCS3, val)
1762 #define bfin_write_EPPI2_STATUS(val) bfin_write16(EPPI2_STATUS, val)
1764 #define bfin_write_EPPI2_HCOUNT(val) bfin_write16(EPPI2_HCOUNT, val)
1766 #define bfin_write_EPPI2_HDELAY(val) bfin_write16(EPPI2_HDELAY, val)
1768 #define bfin_write_EPPI2_VCOUNT(val) bfin_write16(EPPI2_VCOUNT, val)
1770 #define bfin_write_EPPI2_VDELAY(val) bfin_write16(EPPI2_VDELAY, val)
1772 #define bfin_write_EPPI2_FRAME(val) bfin_write16(EPPI2_FRAME, val)
1774 #define bfin_write_EPPI2_LINE(val) bfin_write16(EPPI2_LINE, val)
1776 #define bfin_write_EPPI2_CLKDIV(val) bfin_write16(EPPI2_CLKDIV, val)
1778 #define bfin_write_EPPI2_CONTROL(val) bfin_write32(EPPI2_CONTROL, val)
1780 #define bfin_write_EPPI2_FS1W_HBL(val) bfin_write32(EPPI2_FS1W_HBL, val)
1782 #define bfin_write_EPPI2_FS1P_AVPL(val) bfin_write32(EPPI2_FS1P_AVPL, val)
1784 #define bfin_write_EPPI2_FS2W_LVB(val) bfin_write32(EPPI2_FS2W_LVB, val)
1786 #define bfin_write_EPPI2_FS2P_LAVF(val) bfin_write32(EPPI2_FS2P_LAVF, val)
1788 #define bfin_write_EPPI2_CLIP(val) bfin_write32(EPPI2_CLIP, val)
1793 #define bfin_write_CAN0_MC1(val) bfin_write16(CAN0_MC1, val)
1795 #define bfin_write_CAN0_MD1(val) bfin_write16(CAN0_MD1, val)
1797 #define bfin_write_CAN0_TRS1(val) bfin_write16(CAN0_TRS1, val)
1799 #define bfin_write_CAN0_TRR1(val) bfin_write16(CAN0_TRR1, val)
1801 #define bfin_write_CAN0_TA1(val) bfin_write16(CAN0_TA1, val)
1803 #define bfin_write_CAN0_AA1(val) bfin_write16(CAN0_AA1, val)
1805 #define bfin_write_CAN0_RMP1(val) bfin_write16(CAN0_RMP1, val)
1807 #define bfin_write_CAN0_RML1(val) bfin_write16(CAN0_RML1, val)
1809 #define bfin_write_CAN0_MBTIF1(val) bfin_write16(CAN0_MBTIF1, val)
1811 #define bfin_write_CAN0_MBRIF1(val) bfin_write16(CAN0_MBRIF1, val)
1813 #define bfin_write_CAN0_MBIM1(val) bfin_write16(CAN0_MBIM1, val)
1815 #define bfin_write_CAN0_RFH1(val) bfin_write16(CAN0_RFH1, val)
1817 #define bfin_write_CAN0_OPSS1(val) bfin_write16(CAN0_OPSS1, val)
1822 #define bfin_write_CAN0_MC2(val) bfin_write16(CAN0_MC2, val)
1824 #define bfin_write_CAN0_MD2(val) bfin_write16(CAN0_MD2, val)
1826 #define bfin_write_CAN0_TRS2(val) bfin_write16(CAN0_TRS2, val)
1828 #define bfin_write_CAN0_TRR2(val) bfin_write16(CAN0_TRR2, val)
1830 #define bfin_write_CAN0_TA2(val) bfin_write16(CAN0_TA2, val)
1832 #define bfin_write_CAN0_AA2(val) bfin_write16(CAN0_AA2, val)
1834 #define bfin_write_CAN0_RMP2(val) bfin_write16(CAN0_RMP2, val)
1836 #define bfin_write_CAN0_RML2(val) bfin_write16(CAN0_RML2, val)
1838 #define bfin_write_CAN0_MBTIF2(val) bfin_write16(CAN0_MBTIF2, val)
1840 #define bfin_write_CAN0_MBRIF2(val) bfin_write16(CAN0_MBRIF2, val)
1842 #define bfin_write_CAN0_MBIM2(val) bfin_write16(CAN0_MBIM2, val)
1844 #define bfin_write_CAN0_RFH2(val) bfin_write16(CAN0_RFH2, val)
1846 #define bfin_write_CAN0_OPSS2(val) bfin_write16(CAN0_OPSS2, val)
1851 #define bfin_write_CAN0_CLOCK(val) bfin_write16(CAN0_CLOCK, val)
1853 #define bfin_write_CAN0_TIMING(val) bfin_write16(CAN0_TIMING, val)
1855 #define bfin_write_CAN0_DEBUG(val) bfin_write16(CAN0_DEBUG, val)
1857 #define bfin_write_CAN0_STATUS(val) bfin_write16(CAN0_STATUS, val)
1859 #define bfin_write_CAN0_CEC(val) bfin_write16(CAN0_CEC, val)
1861 #define bfin_write_CAN0_GIS(val) bfin_write16(CAN0_GIS, val)
1863 #define bfin_write_CAN0_GIM(val) bfin_write16(CAN0_GIM, val)
1865 #define bfin_write_CAN0_GIF(val) bfin_write16(CAN0_GIF, val)
1867 #define bfin_write_CAN0_CONTROL(val) bfin_write16(CAN0_CONTROL, val)
1869 #define bfin_write_CAN0_INTR(val) bfin_write16(CAN0_INTR, val)
1871 #define bfin_write_CAN0_MBTD(val) bfin_write16(CAN0_MBTD, val)
1873 #define bfin_write_CAN0_EWR(val) bfin_write16(CAN0_EWR, val)
1875 #define bfin_write_CAN0_ESR(val) bfin_write16(CAN0_ESR, val)
1877 #define bfin_write_CAN0_UCCNT(val) bfin_write16(CAN0_UCCNT, val)
1879 #define bfin_write_CAN0_UCRC(val) bfin_write16(CAN0_UCRC, val)
1881 #define bfin_write_CAN0_UCCNF(val) bfin_write16(CAN0_UCCNF, val)
1886 #define bfin_write_CAN0_AM00L(val) bfin_write16(CAN0_AM00L, val)
1888 #define bfin_write_CAN0_AM00H(val) bfin_write16(CAN0_AM00H, val)
1890 #define bfin_write_CAN0_AM01L(val) bfin_write16(CAN0_AM01L, val)
1892 #define bfin_write_CAN0_AM01H(val) bfin_write16(CAN0_AM01H, val)
1894 #define bfin_write_CAN0_AM02L(val) bfin_write16(CAN0_AM02L, val)
1896 #define bfin_write_CAN0_AM02H(val) bfin_write16(CAN0_AM02H, val)
1898 #define bfin_write_CAN0_AM03L(val) bfin_write16(CAN0_AM03L, val)
1900 #define bfin_write_CAN0_AM03H(val) bfin_write16(CAN0_AM03H, val)
1902 #define bfin_write_CAN0_AM04L(val) bfin_write16(CAN0_AM04L, val)
1904 #define bfin_write_CAN0_AM04H(val) bfin_write16(CAN0_AM04H, val)
1906 #define bfin_write_CAN0_AM05L(val) bfin_write16(CAN0_AM05L, val)
1908 #define bfin_write_CAN0_AM05H(val) bfin_write16(CAN0_AM05H, val)
1910 #define bfin_write_CAN0_AM06L(val) bfin_write16(CAN0_AM06L, val)
1912 #define bfin_write_CAN0_AM06H(val) bfin_write16(CAN0_AM06H, val)
1914 #define bfin_write_CAN0_AM07L(val) bfin_write16(CAN0_AM07L, val)
1916 #define bfin_write_CAN0_AM07H(val) bfin_write16(CAN0_AM07H, val)
1918 #define bfin_write_CAN0_AM08L(val) bfin_write16(CAN0_AM08L, val)
1920 #define bfin_write_CAN0_AM08H(val) bfin_write16(CAN0_AM08H, val)
1922 #define bfin_write_CAN0_AM09L(val) bfin_write16(CAN0_AM09L, val)
1924 #define bfin_write_CAN0_AM09H(val) bfin_write16(CAN0_AM09H, val)
1926 #define bfin_write_CAN0_AM10L(val) bfin_write16(CAN0_AM10L, val)
1928 #define bfin_write_CAN0_AM10H(val) bfin_write16(CAN0_AM10H, val)
1930 #define bfin_write_CAN0_AM11L(val) bfin_write16(CAN0_AM11L, val)
1932 #define bfin_write_CAN0_AM11H(val) bfin_write16(CAN0_AM11H, val)
1934 #define bfin_write_CAN0_AM12L(val) bfin_write16(CAN0_AM12L, val)
1936 #define bfin_write_CAN0_AM12H(val) bfin_write16(CAN0_AM12H, val)
1938 #define bfin_write_CAN0_AM13L(val) bfin_write16(CAN0_AM13L, val)
1940 #define bfin_write_CAN0_AM13H(val) bfin_write16(CAN0_AM13H, val)
1942 #define bfin_write_CAN0_AM14L(val) bfin_write16(CAN0_AM14L, val)
1944 #define bfin_write_CAN0_AM14H(val) bfin_write16(CAN0_AM14H, val)
1946 #define bfin_write_CAN0_AM15L(val) bfin_write16(CAN0_AM15L, val)
1948 #define bfin_write_CAN0_AM15H(val) bfin_write16(CAN0_AM15H, val)
1953 #define bfin_write_CAN0_AM16L(val) bfin_write16(CAN0_AM16L, val)
1955 #define bfin_write_CAN0_AM16H(val) bfin_write16(CAN0_AM16H, val)
1957 #define bfin_write_CAN0_AM17L(val) bfin_write16(CAN0_AM17L, val)
1959 #define bfin_write_CAN0_AM17H(val) bfin_write16(CAN0_AM17H, val)
1961 #define bfin_write_CAN0_AM18L(val) bfin_write16(CAN0_AM18L, val)
1963 #define bfin_write_CAN0_AM18H(val) bfin_write16(CAN0_AM18H, val)
1965 #define bfin_write_CAN0_AM19L(val) bfin_write16(CAN0_AM19L, val)
1967 #define bfin_write_CAN0_AM19H(val) bfin_write16(CAN0_AM19H, val)
1969 #define bfin_write_CAN0_AM20L(val) bfin_write16(CAN0_AM20L, val)
1971 #define bfin_write_CAN0_AM20H(val) bfin_write16(CAN0_AM20H, val)
1973 #define bfin_write_CAN0_AM21L(val) bfin_write16(CAN0_AM21L, val)
1975 #define bfin_write_CAN0_AM21H(val) bfin_write16(CAN0_AM21H, val)
1977 #define bfin_write_CAN0_AM22L(val) bfin_write16(CAN0_AM22L, val)
1979 #define bfin_write_CAN0_AM22H(val) bfin_write16(CAN0_AM22H, val)
1981 #define bfin_write_CAN0_AM23L(val) bfin_write16(CAN0_AM23L, val)
1983 #define bfin_write_CAN0_AM23H(val) bfin_write16(CAN0_AM23H, val)
1985 #define bfin_write_CAN0_AM24L(val) bfin_write16(CAN0_AM24L, val)
1987 #define bfin_write_CAN0_AM24H(val) bfin_write16(CAN0_AM24H, val)
1989 #define bfin_write_CAN0_AM25L(val) bfin_write16(CAN0_AM25L, val)
1991 #define bfin_write_CAN0_AM25H(val) bfin_write16(CAN0_AM25H, val)
1993 #define bfin_write_CAN0_AM26L(val) bfin_write16(CAN0_AM26L, val)
1995 #define bfin_write_CAN0_AM26H(val) bfin_write16(CAN0_AM26H, val)
1997 #define bfin_write_CAN0_AM27L(val) bfin_write16(CAN0_AM27L, val)
1999 #define bfin_write_CAN0_AM27H(val) bfin_write16(CAN0_AM27H, val)
2001 #define bfin_write_CAN0_AM28L(val) bfin_write16(CAN0_AM28L, val)
2003 #define bfin_write_CAN0_AM28H(val) bfin_write16(CAN0_AM28H, val)
2005 #define bfin_write_CAN0_AM29L(val) bfin_write16(CAN0_AM29L, val)
2007 #define bfin_write_CAN0_AM29H(val) bfin_write16(CAN0_AM29H, val)
2009 #define bfin_write_CAN0_AM30L(val) bfin_write16(CAN0_AM30L, val)
2011 #define bfin_write_CAN0_AM30H(val) bfin_write16(CAN0_AM30H, val)
2013 #define bfin_write_CAN0_AM31L(val) bfin_write16(CAN0_AM31L, val)
2015 #define bfin_write_CAN0_AM31H(val) bfin_write16(CAN0_AM31H, val)
2020 #define bfin_write_CAN0_MB00_DATA0(val) bfin_write16(CAN0_MB00_DATA0, val)
2022 #define bfin_write_CAN0_MB00_DATA1(val) bfin_write16(CAN0_MB00_DATA1, val)
2024 #define bfin_write_CAN0_MB00_DATA2(val) bfin_write16(CAN0_MB00_DATA2, val)
2026 #define bfin_write_CAN0_MB00_DATA3(val) bfin_write16(CAN0_MB00_DATA3, val)
2028 #define bfin_write_CAN0_MB00_LENGTH(val) bfin_write16(CAN0_MB00_LENGTH, val)
2030 #define bfin_write_CAN0_MB00_TIMESTAMP(val) bfin_write16(CAN0_MB00_TIMESTAMP, val)
2032 #define bfin_write_CAN0_MB00_ID0(val) bfin_write16(CAN0_MB00_ID0, val)
2034 #define bfin_write_CAN0_MB00_ID1(val) bfin_write16(CAN0_MB00_ID1, val)
2036 #define bfin_write_CAN0_MB01_DATA0(val) bfin_write16(CAN0_MB01_DATA0, val)
2038 #define bfin_write_CAN0_MB01_DATA1(val) bfin_write16(CAN0_MB01_DATA1, val)
2040 #define bfin_write_CAN0_MB01_DATA2(val) bfin_write16(CAN0_MB01_DATA2, val)
2042 #define bfin_write_CAN0_MB01_DATA3(val) bfin_write16(CAN0_MB01_DATA3, val)
2044 #define bfin_write_CAN0_MB01_LENGTH(val) bfin_write16(CAN0_MB01_LENGTH, val)
2046 #define bfin_write_CAN0_MB01_TIMESTAMP(val) bfin_write16(CAN0_MB01_TIMESTAMP, val)
2048 #define bfin_write_CAN0_MB01_ID0(val) bfin_write16(CAN0_MB01_ID0, val)
2050 #define bfin_write_CAN0_MB01_ID1(val) bfin_write16(CAN0_MB01_ID1, val)
2052 #define bfin_write_CAN0_MB02_DATA0(val) bfin_write16(CAN0_MB02_DATA0, val)
2054 #define bfin_write_CAN0_MB02_DATA1(val) bfin_write16(CAN0_MB02_DATA1, val)
2056 #define bfin_write_CAN0_MB02_DATA2(val) bfin_write16(CAN0_MB02_DATA2, val)
2058 #define bfin_write_CAN0_MB02_DATA3(val) bfin_write16(CAN0_MB02_DATA3, val)
2060 #define bfin_write_CAN0_MB02_LENGTH(val) bfin_write16(CAN0_MB02_LENGTH, val)
2062 #define bfin_write_CAN0_MB02_TIMESTAMP(val) bfin_write16(CAN0_MB02_TIMESTAMP, val)
2064 #define bfin_write_CAN0_MB02_ID0(val) bfin_write16(CAN0_MB02_ID0, val)
2066 #define bfin_write_CAN0_MB02_ID1(val) bfin_write16(CAN0_MB02_ID1, val)
2068 #define bfin_write_CAN0_MB03_DATA0(val) bfin_write16(CAN0_MB03_DATA0, val)
2070 #define bfin_write_CAN0_MB03_DATA1(val) bfin_write16(CAN0_MB03_DATA1, val)
2072 #define bfin_write_CAN0_MB03_DATA2(val) bfin_write16(CAN0_MB03_DATA2, val)
2074 #define bfin_write_CAN0_MB03_DATA3(val) bfin_write16(CAN0_MB03_DATA3, val)
2076 #define bfin_write_CAN0_MB03_LENGTH(val) bfin_write16(CAN0_MB03_LENGTH, val)
2078 #define bfin_write_CAN0_MB03_TIMESTAMP(val) bfin_write16(CAN0_MB03_TIMESTAMP, val)
2080 #define bfin_write_CAN0_MB03_ID0(val) bfin_write16(CAN0_MB03_ID0, val)
2082 #define bfin_write_CAN0_MB03_ID1(val) bfin_write16(CAN0_MB03_ID1, val)
2084 #define bfin_write_CAN0_MB04_DATA0(val) bfin_write16(CAN0_MB04_DATA0, val)
2086 #define bfin_write_CAN0_MB04_DATA1(val) bfin_write16(CAN0_MB04_DATA1, val)
2088 #define bfin_write_CAN0_MB04_DATA2(val) bfin_write16(CAN0_MB04_DATA2, val)
2090 #define bfin_write_CAN0_MB04_DATA3(val) bfin_write16(CAN0_MB04_DATA3, val)
2092 #define bfin_write_CAN0_MB04_LENGTH(val) bfin_write16(CAN0_MB04_LENGTH, val)
2094 #define bfin_write_CAN0_MB04_TIMESTAMP(val) bfin_write16(CAN0_MB04_TIMESTAMP, val)
2096 #define bfin_write_CAN0_MB04_ID0(val) bfin_write16(CAN0_MB04_ID0, val)
2098 #define bfin_write_CAN0_MB04_ID1(val) bfin_write16(CAN0_MB04_ID1, val)
2100 #define bfin_write_CAN0_MB05_DATA0(val) bfin_write16(CAN0_MB05_DATA0, val)
2102 #define bfin_write_CAN0_MB05_DATA1(val) bfin_write16(CAN0_MB05_DATA1, val)
2104 #define bfin_write_CAN0_MB05_DATA2(val) bfin_write16(CAN0_MB05_DATA2, val)
2106 #define bfin_write_CAN0_MB05_DATA3(val) bfin_write16(CAN0_MB05_DATA3, val)
2108 #define bfin_write_CAN0_MB05_LENGTH(val) bfin_write16(CAN0_MB05_LENGTH, val)
2110 #define bfin_write_CAN0_MB05_TIMESTAMP(val) bfin_write16(CAN0_MB05_TIMESTAMP, val)
2112 #define bfin_write_CAN0_MB05_ID0(val) bfin_write16(CAN0_MB05_ID0, val)
2114 #define bfin_write_CAN0_MB05_ID1(val) bfin_write16(CAN0_MB05_ID1, val)
2116 #define bfin_write_CAN0_MB06_DATA0(val) bfin_write16(CAN0_MB06_DATA0, val)
2118 #define bfin_write_CAN0_MB06_DATA1(val) bfin_write16(CAN0_MB06_DATA1, val)
2120 #define bfin_write_CAN0_MB06_DATA2(val) bfin_write16(CAN0_MB06_DATA2, val)
2122 #define bfin_write_CAN0_MB06_DATA3(val) bfin_write16(CAN0_MB06_DATA3, val)
2124 #define bfin_write_CAN0_MB06_LENGTH(val) bfin_write16(CAN0_MB06_LENGTH, val)
2126 #define bfin_write_CAN0_MB06_TIMESTAMP(val) bfin_write16(CAN0_MB06_TIMESTAMP, val)
2128 #define bfin_write_CAN0_MB06_ID0(val) bfin_write16(CAN0_MB06_ID0, val)
2130 #define bfin_write_CAN0_MB06_ID1(val) bfin_write16(CAN0_MB06_ID1, val)
2132 #define bfin_write_CAN0_MB07_DATA0(val) bfin_write16(CAN0_MB07_DATA0, val)
2134 #define bfin_write_CAN0_MB07_DATA1(val) bfin_write16(CAN0_MB07_DATA1, val)
2136 #define bfin_write_CAN0_MB07_DATA2(val) bfin_write16(CAN0_MB07_DATA2, val)
2138 #define bfin_write_CAN0_MB07_DATA3(val) bfin_write16(CAN0_MB07_DATA3, val)
2140 #define bfin_write_CAN0_MB07_LENGTH(val) bfin_write16(CAN0_MB07_LENGTH, val)
2142 #define bfin_write_CAN0_MB07_TIMESTAMP(val) bfin_write16(CAN0_MB07_TIMESTAMP, val)
2144 #define bfin_write_CAN0_MB07_ID0(val) bfin_write16(CAN0_MB07_ID0, val)
2146 #define bfin_write_CAN0_MB07_ID1(val) bfin_write16(CAN0_MB07_ID1, val)
2148 #define bfin_write_CAN0_MB08_DATA0(val) bfin_write16(CAN0_MB08_DATA0, val)
2150 #define bfin_write_CAN0_MB08_DATA1(val) bfin_write16(CAN0_MB08_DATA1, val)
2152 #define bfin_write_CAN0_MB08_DATA2(val) bfin_write16(CAN0_MB08_DATA2, val)
2154 #define bfin_write_CAN0_MB08_DATA3(val) bfin_write16(CAN0_MB08_DATA3, val)
2156 #define bfin_write_CAN0_MB08_LENGTH(val) bfin_write16(CAN0_MB08_LENGTH, val)
2158 #define bfin_write_CAN0_MB08_TIMESTAMP(val) bfin_write16(CAN0_MB08_TIMESTAMP, val)
2160 #define bfin_write_CAN0_MB08_ID0(val) bfin_write16(CAN0_MB08_ID0, val)
2162 #define bfin_write_CAN0_MB08_ID1(val) bfin_write16(CAN0_MB08_ID1, val)
2164 #define bfin_write_CAN0_MB09_DATA0(val) bfin_write16(CAN0_MB09_DATA0, val)
2166 #define bfin_write_CAN0_MB09_DATA1(val) bfin_write16(CAN0_MB09_DATA1, val)
2168 #define bfin_write_CAN0_MB09_DATA2(val) bfin_write16(CAN0_MB09_DATA2, val)
2170 #define bfin_write_CAN0_MB09_DATA3(val) bfin_write16(CAN0_MB09_DATA3, val)
2172 #define bfin_write_CAN0_MB09_LENGTH(val) bfin_write16(CAN0_MB09_LENGTH, val)
2174 #define bfin_write_CAN0_MB09_TIMESTAMP(val) bfin_write16(CAN0_MB09_TIMESTAMP, val)
2176 #define bfin_write_CAN0_MB09_ID0(val) bfin_write16(CAN0_MB09_ID0, val)
2178 #define bfin_write_CAN0_MB09_ID1(val) bfin_write16(CAN0_MB09_ID1, val)
2180 #define bfin_write_CAN0_MB10_DATA0(val) bfin_write16(CAN0_MB10_DATA0, val)
2182 #define bfin_write_CAN0_MB10_DATA1(val) bfin_write16(CAN0_MB10_DATA1, val)
2184 #define bfin_write_CAN0_MB10_DATA2(val) bfin_write16(CAN0_MB10_DATA2, val)
2186 #define bfin_write_CAN0_MB10_DATA3(val) bfin_write16(CAN0_MB10_DATA3, val)
2188 #define bfin_write_CAN0_MB10_LENGTH(val) bfin_write16(CAN0_MB10_LENGTH, val)
2190 #define bfin_write_CAN0_MB10_TIMESTAMP(val) bfin_write16(CAN0_MB10_TIMESTAMP, val)
2192 #define bfin_write_CAN0_MB10_ID0(val) bfin_write16(CAN0_MB10_ID0, val)
2194 #define bfin_write_CAN0_MB10_ID1(val) bfin_write16(CAN0_MB10_ID1, val)
2196 #define bfin_write_CAN0_MB11_DATA0(val) bfin_write16(CAN0_MB11_DATA0, val)
2198 #define bfin_write_CAN0_MB11_DATA1(val) bfin_write16(CAN0_MB11_DATA1, val)
2200 #define bfin_write_CAN0_MB11_DATA2(val) bfin_write16(CAN0_MB11_DATA2, val)
2202 #define bfin_write_CAN0_MB11_DATA3(val) bfin_write16(CAN0_MB11_DATA3, val)
2204 #define bfin_write_CAN0_MB11_LENGTH(val) bfin_write16(CAN0_MB11_LENGTH, val)
2206 #define bfin_write_CAN0_MB11_TIMESTAMP(val) bfin_write16(CAN0_MB11_TIMESTAMP, val)
2208 #define bfin_write_CAN0_MB11_ID0(val) bfin_write16(CAN0_MB11_ID0, val)
2210 #define bfin_write_CAN0_MB11_ID1(val) bfin_write16(CAN0_MB11_ID1, val)
2212 #define bfin_write_CAN0_MB12_DATA0(val) bfin_write16(CAN0_MB12_DATA0, val)
2214 #define bfin_write_CAN0_MB12_DATA1(val) bfin_write16(CAN0_MB12_DATA1, val)
2216 #define bfin_write_CAN0_MB12_DATA2(val) bfin_write16(CAN0_MB12_DATA2, val)
2218 #define bfin_write_CAN0_MB12_DATA3(val) bfin_write16(CAN0_MB12_DATA3, val)
2220 #define bfin_write_CAN0_MB12_LENGTH(val) bfin_write16(CAN0_MB12_LENGTH, val)
2222 #define bfin_write_CAN0_MB12_TIMESTAMP(val) bfin_write16(CAN0_MB12_TIMESTAMP, val)
2224 #define bfin_write_CAN0_MB12_ID0(val) bfin_write16(CAN0_MB12_ID0, val)
2226 #define bfin_write_CAN0_MB12_ID1(val) bfin_write16(CAN0_MB12_ID1, val)
2228 #define bfin_write_CAN0_MB13_DATA0(val) bfin_write16(CAN0_MB13_DATA0, val)
2230 #define bfin_write_CAN0_MB13_DATA1(val) bfin_write16(CAN0_MB13_DATA1, val)
2232 #define bfin_write_CAN0_MB13_DATA2(val) bfin_write16(CAN0_MB13_DATA2, val)
2234 #define bfin_write_CAN0_MB13_DATA3(val) bfin_write16(CAN0_MB13_DATA3, val)
2236 #define bfin_write_CAN0_MB13_LENGTH(val) bfin_write16(CAN0_MB13_LENGTH, val)
2238 #define bfin_write_CAN0_MB13_TIMESTAMP(val) bfin_write16(CAN0_MB13_TIMESTAMP, val)
2240 #define bfin_write_CAN0_MB13_ID0(val) bfin_write16(CAN0_MB13_ID0, val)
2242 #define bfin_write_CAN0_MB13_ID1(val) bfin_write16(CAN0_MB13_ID1, val)
2244 #define bfin_write_CAN0_MB14_DATA0(val) bfin_write16(CAN0_MB14_DATA0, val)
2246 #define bfin_write_CAN0_MB14_DATA1(val) bfin_write16(CAN0_MB14_DATA1, val)
2248 #define bfin_write_CAN0_MB14_DATA2(val) bfin_write16(CAN0_MB14_DATA2, val)
2250 #define bfin_write_CAN0_MB14_DATA3(val) bfin_write16(CAN0_MB14_DATA3, val)
2252 #define bfin_write_CAN0_MB14_LENGTH(val) bfin_write16(CAN0_MB14_LENGTH, val)
2254 #define bfin_write_CAN0_MB14_TIMESTAMP(val) bfin_write16(CAN0_MB14_TIMESTAMP, val)
2256 #define bfin_write_CAN0_MB14_ID0(val) bfin_write16(CAN0_MB14_ID0, val)
2258 #define bfin_write_CAN0_MB14_ID1(val) bfin_write16(CAN0_MB14_ID1, val)
2260 #define bfin_write_CAN0_MB15_DATA0(val) bfin_write16(CAN0_MB15_DATA0, val)
2262 #define bfin_write_CAN0_MB15_DATA1(val) bfin_write16(CAN0_MB15_DATA1, val)
2264 #define bfin_write_CAN0_MB15_DATA2(val) bfin_write16(CAN0_MB15_DATA2, val)
2266 #define bfin_write_CAN0_MB15_DATA3(val) bfin_write16(CAN0_MB15_DATA3, val)
2268 #define bfin_write_CAN0_MB15_LENGTH(val) bfin_write16(CAN0_MB15_LENGTH, val)
2270 #define bfin_write_CAN0_MB15_TIMESTAMP(val) bfin_write16(CAN0_MB15_TIMESTAMP, val)
2272 #define bfin_write_CAN0_MB15_ID0(val) bfin_write16(CAN0_MB15_ID0, val)
2274 #define bfin_write_CAN0_MB15_ID1(val) bfin_write16(CAN0_MB15_ID1, val)
2279 #define bfin_write_CAN0_MB16_DATA0(val) bfin_write16(CAN0_MB16_DATA0, val)
2281 #define bfin_write_CAN0_MB16_DATA1(val) bfin_write16(CAN0_MB16_DATA1, val)
2283 #define bfin_write_CAN0_MB16_DATA2(val) bfin_write16(CAN0_MB16_DATA2, val)
2285 #define bfin_write_CAN0_MB16_DATA3(val) bfin_write16(CAN0_MB16_DATA3, val)
2287 #define bfin_write_CAN0_MB16_LENGTH(val) bfin_write16(CAN0_MB16_LENGTH, val)
2289 #define bfin_write_CAN0_MB16_TIMESTAMP(val) bfin_write16(CAN0_MB16_TIMESTAMP, val)
2291 #define bfin_write_CAN0_MB16_ID0(val) bfin_write16(CAN0_MB16_ID0, val)
2293 #define bfin_write_CAN0_MB16_ID1(val) bfin_write16(CAN0_MB16_ID1, val)
2295 #define bfin_write_CAN0_MB17_DATA0(val) bfin_write16(CAN0_MB17_DATA0, val)
2297 #define bfin_write_CAN0_MB17_DATA1(val) bfin_write16(CAN0_MB17_DATA1, val)
2299 #define bfin_write_CAN0_MB17_DATA2(val) bfin_write16(CAN0_MB17_DATA2, val)
2301 #define bfin_write_CAN0_MB17_DATA3(val) bfin_write16(CAN0_MB17_DATA3, val)
2303 #define bfin_write_CAN0_MB17_LENGTH(val) bfin_write16(CAN0_MB17_LENGTH, val)
2305 #define bfin_write_CAN0_MB17_TIMESTAMP(val) bfin_write16(CAN0_MB17_TIMESTAMP, val)
2307 #define bfin_write_CAN0_MB17_ID0(val) bfin_write16(CAN0_MB17_ID0, val)
2309 #define bfin_write_CAN0_MB17_ID1(val) bfin_write16(CAN0_MB17_ID1, val)
2311 #define bfin_write_CAN0_MB18_DATA0(val) bfin_write16(CAN0_MB18_DATA0, val)
2313 #define bfin_write_CAN0_MB18_DATA1(val) bfin_write16(CAN0_MB18_DATA1, val)
2315 #define bfin_write_CAN0_MB18_DATA2(val) bfin_write16(CAN0_MB18_DATA2, val)
2317 #define bfin_write_CAN0_MB18_DATA3(val) bfin_write16(CAN0_MB18_DATA3, val)
2319 #define bfin_write_CAN0_MB18_LENGTH(val) bfin_write16(CAN0_MB18_LENGTH, val)
2321 #define bfin_write_CAN0_MB18_TIMESTAMP(val) bfin_write16(CAN0_MB18_TIMESTAMP, val)
2323 #define bfin_write_CAN0_MB18_ID0(val) bfin_write16(CAN0_MB18_ID0, val)
2325 #define bfin_write_CAN0_MB18_ID1(val) bfin_write16(CAN0_MB18_ID1, val)
2327 #define bfin_write_CAN0_MB19_DATA0(val) bfin_write16(CAN0_MB19_DATA0, val)
2329 #define bfin_write_CAN0_MB19_DATA1(val) bfin_write16(CAN0_MB19_DATA1, val)
2331 #define bfin_write_CAN0_MB19_DATA2(val) bfin_write16(CAN0_MB19_DATA2, val)
2333 #define bfin_write_CAN0_MB19_DATA3(val) bfin_write16(CAN0_MB19_DATA3, val)
2335 #define bfin_write_CAN0_MB19_LENGTH(val) bfin_write16(CAN0_MB19_LENGTH, val)
2337 #define bfin_write_CAN0_MB19_TIMESTAMP(val) bfin_write16(CAN0_MB19_TIMESTAMP, val)
2339 #define bfin_write_CAN0_MB19_ID0(val) bfin_write16(CAN0_MB19_ID0, val)
2341 #define bfin_write_CAN0_MB19_ID1(val) bfin_write16(CAN0_MB19_ID1, val)
2343 #define bfin_write_CAN0_MB20_DATA0(val) bfin_write16(CAN0_MB20_DATA0, val)
2345 #define bfin_write_CAN0_MB20_DATA1(val) bfin_write16(CAN0_MB20_DATA1, val)
2347 #define bfin_write_CAN0_MB20_DATA2(val) bfin_write16(CAN0_MB20_DATA2, val)
2349 #define bfin_write_CAN0_MB20_DATA3(val) bfin_write16(CAN0_MB20_DATA3, val)
2351 #define bfin_write_CAN0_MB20_LENGTH(val) bfin_write16(CAN0_MB20_LENGTH, val)
2353 #define bfin_write_CAN0_MB20_TIMESTAMP(val) bfin_write16(CAN0_MB20_TIMESTAMP, val)
2355 #define bfin_write_CAN0_MB20_ID0(val) bfin_write16(CAN0_MB20_ID0, val)
2357 #define bfin_write_CAN0_MB20_ID1(val) bfin_write16(CAN0_MB20_ID1, val)
2359 #define bfin_write_CAN0_MB21_DATA0(val) bfin_write16(CAN0_MB21_DATA0, val)
2361 #define bfin_write_CAN0_MB21_DATA1(val) bfin_write16(CAN0_MB21_DATA1, val)
2363 #define bfin_write_CAN0_MB21_DATA2(val) bfin_write16(CAN0_MB21_DATA2, val)
2365 #define bfin_write_CAN0_MB21_DATA3(val) bfin_write16(CAN0_MB21_DATA3, val)
2367 #define bfin_write_CAN0_MB21_LENGTH(val) bfin_write16(CAN0_MB21_LENGTH, val)
2369 #define bfin_write_CAN0_MB21_TIMESTAMP(val) bfin_write16(CAN0_MB21_TIMESTAMP, val)
2371 #define bfin_write_CAN0_MB21_ID0(val) bfin_write16(CAN0_MB21_ID0, val)
2373 #define bfin_write_CAN0_MB21_ID1(val) bfin_write16(CAN0_MB21_ID1, val)
2375 #define bfin_write_CAN0_MB22_DATA0(val) bfin_write16(CAN0_MB22_DATA0, val)
2377 #define bfin_write_CAN0_MB22_DATA1(val) bfin_write16(CAN0_MB22_DATA1, val)
2379 #define bfin_write_CAN0_MB22_DATA2(val) bfin_write16(CAN0_MB22_DATA2, val)
2381 #define bfin_write_CAN0_MB22_DATA3(val) bfin_write16(CAN0_MB22_DATA3, val)
2383 #define bfin_write_CAN0_MB22_LENGTH(val) bfin_write16(CAN0_MB22_LENGTH, val)
2385 #define bfin_write_CAN0_MB22_TIMESTAMP(val) bfin_write16(CAN0_MB22_TIMESTAMP, val)
2387 #define bfin_write_CAN0_MB22_ID0(val) bfin_write16(CAN0_MB22_ID0, val)
2389 #define bfin_write_CAN0_MB22_ID1(val) bfin_write16(CAN0_MB22_ID1, val)
2391 #define bfin_write_CAN0_MB23_DATA0(val) bfin_write16(CAN0_MB23_DATA0, val)
2393 #define bfin_write_CAN0_MB23_DATA1(val) bfin_write16(CAN0_MB23_DATA1, val)
2395 #define bfin_write_CAN0_MB23_DATA2(val) bfin_write16(CAN0_MB23_DATA2, val)
2397 #define bfin_write_CAN0_MB23_DATA3(val) bfin_write16(CAN0_MB23_DATA3, val)
2399 #define bfin_write_CAN0_MB23_LENGTH(val) bfin_write16(CAN0_MB23_LENGTH, val)
2401 #define bfin_write_CAN0_MB23_TIMESTAMP(val) bfin_write16(CAN0_MB23_TIMESTAMP, val)
2403 #define bfin_write_CAN0_MB23_ID0(val) bfin_write16(CAN0_MB23_ID0, val)
2405 #define bfin_write_CAN0_MB23_ID1(val) bfin_write16(CAN0_MB23_ID1, val)
2407 #define bfin_write_CAN0_MB24_DATA0(val) bfin_write16(CAN0_MB24_DATA0, val)
2409 #define bfin_write_CAN0_MB24_DATA1(val) bfin_write16(CAN0_MB24_DATA1, val)
2411 #define bfin_write_CAN0_MB24_DATA2(val) bfin_write16(CAN0_MB24_DATA2, val)
2413 #define bfin_write_CAN0_MB24_DATA3(val) bfin_write16(CAN0_MB24_DATA3, val)
2415 #define bfin_write_CAN0_MB24_LENGTH(val) bfin_write16(CAN0_MB24_LENGTH, val)
2417 #define bfin_write_CAN0_MB24_TIMESTAMP(val) bfin_write16(CAN0_MB24_TIMESTAMP, val)
2419 #define bfin_write_CAN0_MB24_ID0(val) bfin_write16(CAN0_MB24_ID0, val)
2421 #define bfin_write_CAN0_MB24_ID1(val) bfin_write16(CAN0_MB24_ID1, val)
2423 #define bfin_write_CAN0_MB25_DATA0(val) bfin_write16(CAN0_MB25_DATA0, val)
2425 #define bfin_write_CAN0_MB25_DATA1(val) bfin_write16(CAN0_MB25_DATA1, val)
2427 #define bfin_write_CAN0_MB25_DATA2(val) bfin_write16(CAN0_MB25_DATA2, val)
2429 #define bfin_write_CAN0_MB25_DATA3(val) bfin_write16(CAN0_MB25_DATA3, val)
2431 #define bfin_write_CAN0_MB25_LENGTH(val) bfin_write16(CAN0_MB25_LENGTH, val)
2433 #define bfin_write_CAN0_MB25_TIMESTAMP(val) bfin_write16(CAN0_MB25_TIMESTAMP, val)
2435 #define bfin_write_CAN0_MB25_ID0(val) bfin_write16(CAN0_MB25_ID0, val)
2437 #define bfin_write_CAN0_MB25_ID1(val) bfin_write16(CAN0_MB25_ID1, val)
2439 #define bfin_write_CAN0_MB26_DATA0(val) bfin_write16(CAN0_MB26_DATA0, val)
2441 #define bfin_write_CAN0_MB26_DATA1(val) bfin_write16(CAN0_MB26_DATA1, val)
2443 #define bfin_write_CAN0_MB26_DATA2(val) bfin_write16(CAN0_MB26_DATA2, val)
2445 #define bfin_write_CAN0_MB26_DATA3(val) bfin_write16(CAN0_MB26_DATA3, val)
2447 #define bfin_write_CAN0_MB26_LENGTH(val) bfin_write16(CAN0_MB26_LENGTH, val)
2449 #define bfin_write_CAN0_MB26_TIMESTAMP(val) bfin_write16(CAN0_MB26_TIMESTAMP, val)
2451 #define bfin_write_CAN0_MB26_ID0(val) bfin_write16(CAN0_MB26_ID0, val)
2453 #define bfin_write_CAN0_MB26_ID1(val) bfin_write16(CAN0_MB26_ID1, val)
2455 #define bfin_write_CAN0_MB27_DATA0(val) bfin_write16(CAN0_MB27_DATA0, val)
2457 #define bfin_write_CAN0_MB27_DATA1(val) bfin_write16(CAN0_MB27_DATA1, val)
2459 #define bfin_write_CAN0_MB27_DATA2(val) bfin_write16(CAN0_MB27_DATA2, val)
2461 #define bfin_write_CAN0_MB27_DATA3(val) bfin_write16(CAN0_MB27_DATA3, val)
2463 #define bfin_write_CAN0_MB27_LENGTH(val) bfin_write16(CAN0_MB27_LENGTH, val)
2465 #define bfin_write_CAN0_MB27_TIMESTAMP(val) bfin_write16(CAN0_MB27_TIMESTAMP, val)
2467 #define bfin_write_CAN0_MB27_ID0(val) bfin_write16(CAN0_MB27_ID0, val)
2469 #define bfin_write_CAN0_MB27_ID1(val) bfin_write16(CAN0_MB27_ID1, val)
2471 #define bfin_write_CAN0_MB28_DATA0(val) bfin_write16(CAN0_MB28_DATA0, val)
2473 #define bfin_write_CAN0_MB28_DATA1(val) bfin_write16(CAN0_MB28_DATA1, val)
2475 #define bfin_write_CAN0_MB28_DATA2(val) bfin_write16(CAN0_MB28_DATA2, val)
2477 #define bfin_write_CAN0_MB28_DATA3(val) bfin_write16(CAN0_MB28_DATA3, val)
2479 #define bfin_write_CAN0_MB28_LENGTH(val) bfin_write16(CAN0_MB28_LENGTH, val)
2481 #define bfin_write_CAN0_MB28_TIMESTAMP(val) bfin_write16(CAN0_MB28_TIMESTAMP, val)
2483 #define bfin_write_CAN0_MB28_ID0(val) bfin_write16(CAN0_MB28_ID0, val)
2485 #define bfin_write_CAN0_MB28_ID1(val) bfin_write16(CAN0_MB28_ID1, val)
2487 #define bfin_write_CAN0_MB29_DATA0(val) bfin_write16(CAN0_MB29_DATA0, val)
2489 #define bfin_write_CAN0_MB29_DATA1(val) bfin_write16(CAN0_MB29_DATA1, val)
2491 #define bfin_write_CAN0_MB29_DATA2(val) bfin_write16(CAN0_MB29_DATA2, val)
2493 #define bfin_write_CAN0_MB29_DATA3(val) bfin_write16(CAN0_MB29_DATA3, val)
2495 #define bfin_write_CAN0_MB29_LENGTH(val) bfin_write16(CAN0_MB29_LENGTH, val)
2497 #define bfin_write_CAN0_MB29_TIMESTAMP(val) bfin_write16(CAN0_MB29_TIMESTAMP, val)
2499 #define bfin_write_CAN0_MB29_ID0(val) bfin_write16(CAN0_MB29_ID0, val)
2501 #define bfin_write_CAN0_MB29_ID1(val) bfin_write16(CAN0_MB29_ID1, val)
2503 #define bfin_write_CAN0_MB30_DATA0(val) bfin_write16(CAN0_MB30_DATA0, val)
2505 #define bfin_write_CAN0_MB30_DATA1(val) bfin_write16(CAN0_MB30_DATA1, val)
2507 #define bfin_write_CAN0_MB30_DATA2(val) bfin_write16(CAN0_MB30_DATA2, val)
2509 #define bfin_write_CAN0_MB30_DATA3(val) bfin_write16(CAN0_MB30_DATA3, val)
2511 #define bfin_write_CAN0_MB30_LENGTH(val) bfin_write16(CAN0_MB30_LENGTH, val)
2513 #define bfin_write_CAN0_MB30_TIMESTAMP(val) bfin_write16(CAN0_MB30_TIMESTAMP, val)
2515 #define bfin_write_CAN0_MB30_ID0(val) bfin_write16(CAN0_MB30_ID0, val)
2517 #define bfin_write_CAN0_MB30_ID1(val) bfin_write16(CAN0_MB30_ID1, val)
2519 #define bfin_write_CAN0_MB31_DATA0(val) bfin_write16(CAN0_MB31_DATA0, val)
2521 #define bfin_write_CAN0_MB31_DATA1(val) bfin_write16(CAN0_MB31_DATA1, val)
2523 #define bfin_write_CAN0_MB31_DATA2(val) bfin_write16(CAN0_MB31_DATA2, val)
2525 #define bfin_write_CAN0_MB31_DATA3(val) bfin_write16(CAN0_MB31_DATA3, val)
2527 #define bfin_write_CAN0_MB31_LENGTH(val) bfin_write16(CAN0_MB31_LENGTH, val)
2529 #define bfin_write_CAN0_MB31_TIMESTAMP(val) bfin_write16(CAN0_MB31_TIMESTAMP, val)
2531 #define bfin_write_CAN0_MB31_ID0(val) bfin_write16(CAN0_MB31_ID0, val)
2533 #define bfin_write_CAN0_MB31_ID1(val) bfin_write16(CAN0_MB31_ID1, val)
2538 #define bfin_write_UART3_DLL(val) bfin_write16(UART3_DLL, val)
2540 #define bfin_write_UART3_DLH(val) bfin_write16(UART3_DLH, val)
2542 #define bfin_write_UART3_GCTL(val) bfin_write16(UART3_GCTL, val)
2544 #define bfin_write_UART3_LCR(val) bfin_write16(UART3_LCR, val)
2546 #define bfin_write_UART3_MCR(val) bfin_write16(UART3_MCR, val)
2548 #define bfin_write_UART3_LSR(val) bfin_write16(UART3_LSR, val)
2550 #define bfin_write_UART3_MSR(val) bfin_write16(UART3_MSR, val)
2552 #define bfin_write_UART3_SCR(val) bfin_write16(UART3_SCR, val)
2554 #define bfin_write_UART3_IER_SET(val) bfin_write16(UART3_IER_SET, val)
2556 #define bfin_write_UART3_IER_CLEAR(val) bfin_write16(UART3_IER_CLEAR, val)
2558 #define bfin_write_UART3_THR(val) bfin_write16(UART3_THR, val)
2560 #define bfin_write_UART3_RBR(val) bfin_write16(UART3_RBR, val)
2565 #define bfin_write_NFC_CTL(val) bfin_write16(NFC_CTL, val)
2567 #define bfin_write_NFC_STAT(val) bfin_write16(NFC_STAT, val)
2569 #define bfin_write_NFC_IRQSTAT(val) bfin_write16(NFC_IRQSTAT, val)
2571 #define bfin_write_NFC_IRQMASK(val) bfin_write16(NFC_IRQMASK, val)
2573 #define bfin_write_NFC_ECC0(val) bfin_write16(NFC_ECC0, val)
2575 #define bfin_write_NFC_ECC1(val) bfin_write16(NFC_ECC1, val)
2577 #define bfin_write_NFC_ECC2(val) bfin_write16(NFC_ECC2, val)
2579 #define bfin_write_NFC_ECC3(val) bfin_write16(NFC_ECC3, val)
2581 #define bfin_write_NFC_COUNT(val) bfin_write16(NFC_COUNT, val)
2583 #define bfin_write_NFC_RST(val) bfin_write16(NFC_RST, val)
2585 #define bfin_write_NFC_PGCTL(val) bfin_write16(NFC_PGCTL, val)
2587 #define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val)
2589 #define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val)
2591 #define bfin_write_NFC_CMD(val) bfin_write16(NFC_CMD, val)
2593 #define bfin_write_NFC_DATA_WR(val) bfin_write16(NFC_DATA_WR, val)
2595 #define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val)
2600 #define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val)
2602 #define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val)
2604 #define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val)
2606 #define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val)
2608 #define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val)
2610 #define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val)
2612 #define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val)
2614 #define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val)
2619 #define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val)
2621 #define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
2623 #define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val)
2628 #define bfin_write_DMAC1_PERIMUX(val) bfin_write16(DMAC1_PERIMUX, val)
/linux-4.1.27/arch/blackfin/mach-bf518/include/mach/
H A DcdefBF512.h13 #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
16 #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
18 #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
20 #define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
25 #define bfin_write_SWRST(val) bfin_write16(SWRST, val)
27 #define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
30 #define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val)
32 #define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
34 #define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 6)), val)
37 #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
39 #define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
41 #define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
43 #define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
46 #define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
48 #define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 6)), val)
51 #define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
53 #define bfin_write_SIC_IWR(x, val) bfin_write32((SIC_IWR0 + (x << 6)), val)
58 #define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
60 #define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val)
62 #define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val)
64 #define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val)
66 #define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val)
68 #define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
70 #define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val)
74 #define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
76 #define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
78 #define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
83 #define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val)
85 #define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val)
87 #define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val)
89 #define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val)
91 #define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val)
93 #define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST, val)
95 #define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val)
100 #define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val)
102 #define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val)
104 #define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val)
106 #define bfin_write_UART0_IER(val) bfin_write16(UART0_IER, val)
108 #define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val)
110 #define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR, val)
112 #define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val)
114 #define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val)
116 #define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val)
118 #define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val)
120 #define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val)
122 #define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val)
127 #define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
129 #define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
131 #define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
133 #define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
136 #define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
138 #define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
140 #define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
142 #define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
145 #define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
147 #define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
149 #define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
151 #define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
154 #define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val)
156 #define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
158 #define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val)
160 #define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val)
163 #define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val)
165 #define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
167 #define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val)
169 #define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val)
172 #define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val)
174 #define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
176 #define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val)
178 #define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val)
181 #define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val)
183 #define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
185 #define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val)
187 #define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val)
190 #define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val)
192 #define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
194 #define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val)
196 #define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val)
199 #define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val)
201 #define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val)
203 #define bfin_write_TIMER_STATUS(val) bfin_write32(TIMER_STATUS, val)
208 #define bfin_write_PORTFIO(val) bfin_write16(PORTFIO, val)
210 #define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR, val)
212 #define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET, val)
214 #define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val)
216 #define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA, val)
218 #define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val)
220 #define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val)
222 #define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val)
224 #define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB, val)
226 #define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val)
228 #define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val)
230 #define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val)
232 #define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR, val)
234 #define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR, val)
236 #define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE, val)
238 #define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH, val)
240 #define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN, val)
245 #define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
247 #define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
249 #define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
251 #define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
253 #define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
255 #define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
257 #define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX, val)
259 #define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX, val)
261 #define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX, val)
263 #define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX, val)
265 #define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
267 #define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
269 #define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
271 #define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
273 #define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
275 #define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
277 #define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
279 #define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
281 #define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
283 #define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
285 #define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
287 #define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
289 #define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
291 #define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
293 #define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
295 #define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
300 #define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val)
302 #define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val)
304 #define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
306 #define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
308 #define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
310 #define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
312 #define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX, val)
314 #define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX, val)
316 #define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX, val)
318 #define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX, val)
320 #define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
322 #define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val)
324 #define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
326 #define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val)
328 #define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val)
330 #define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val)
332 #define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val)
334 #define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val)
336 #define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val)
338 #define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val)
340 #define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val)
342 #define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val)
344 #define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val)
346 #define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val)
348 #define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val)
350 #define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val)
355 #define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val)
357 #define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
359 #define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
361 #define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val)
363 #define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val)
365 #define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val)
367 #define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val)
372 #define bfin_write_DMAC_TC_PER(val) bfin_write16(DMAC_TC_PER, val)
374 #define bfin_write_DMAC_TC_CNT(val) bfin_write16(DMAC_TC_CNT, val)
378 #define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val)
380 #define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val)
382 #define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val)
384 #define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val)
386 #define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val)
388 #define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val)
390 #define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val)
392 #define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val)
394 #define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val)
396 #define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
398 #define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
400 #define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
402 #define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
405 #define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
407 #define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val)
409 #define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val)
411 #define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val)
413 #define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val)
415 #define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val)
417 #define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val)
419 #define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val)
421 #define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val)
423 #define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
425 #define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
427 #define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
429 #define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
432 #define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val)
434 #define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val)
436 #define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val)
438 #define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val)
440 #define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val)
442 #define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val)
444 #define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val)
446 #define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val)
448 #define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val)
450 #define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
452 #define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
454 #define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
456 #define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
459 #define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
461 #define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val)
463 #define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val)
465 #define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val)
467 #define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val)
469 #define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val)
471 #define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val)
473 #define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val)
475 #define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val)
477 #define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
479 #define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
481 #define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
483 #define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
486 #define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val)
488 #define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val)
490 #define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val)
492 #define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val)
494 #define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val)
496 #define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val)
498 #define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val)
500 #define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val)
502 #define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val)
504 #define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
506 #define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
508 #define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
510 #define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
513 #define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
515 #define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val)
517 #define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val)
519 #define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val)
521 #define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
523 #define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val)
525 #define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val)
527 #define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val)
529 #define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val)
531 #define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
533 #define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
535 #define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
537 #define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
540 #define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val)
542 #define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
544 #define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val)
546 #define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val)
548 #define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val)
550 #define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val)
552 #define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val)
554 #define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val)
556 #define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val)
558 #define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
560 #define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
562 #define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
564 #define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
567 #define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val)
569 #define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val)
571 #define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val)
573 #define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val)
575 #define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val)
577 #define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val)
579 #define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val)
581 #define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val)
583 #define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val)
585 #define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
587 #define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
589 #define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
591 #define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
594 #define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val)
596 #define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR, val)
598 #define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR, val)
600 #define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val)
602 #define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val)
604 #define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val)
606 #define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val)
608 #define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR, val)
610 #define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR, val)
612 #define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
614 #define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
616 #define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
618 #define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
621 #define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val)
623 #define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR, val)
625 #define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR, val)
627 #define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val)
629 #define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val)
631 #define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val)
633 #define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val)
635 #define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR, val)
637 #define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR, val)
639 #define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
641 #define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
643 #define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
645 #define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
648 #define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val)
650 #define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR, val)
652 #define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR, val)
654 #define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val)
656 #define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val)
658 #define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
660 #define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
662 #define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR, val)
664 #define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR, val)
666 #define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
668 #define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
670 #define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
672 #define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
675 #define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val)
677 #define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR, val)
679 #define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR, val)
681 #define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val)
683 #define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val)
685 #define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
687 #define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
689 #define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR, val)
691 #define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR, val)
693 #define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
695 #define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
697 #define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
699 #define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
702 #define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
704 #define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR, val)
706 #define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val)
708 #define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
710 #define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
712 #define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
714 #define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
716 #define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val)
718 #define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val)
720 #define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
722 #define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
724 #define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
726 #define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
729 #define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
731 #define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val)
733 #define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val)
735 #define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
737 #define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
739 #define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
741 #define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
743 #define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val)
745 #define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val)
747 #define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
749 #define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
751 #define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
753 #define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
756 #define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
758 #define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val)
760 #define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val)
762 #define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
764 #define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
766 #define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
768 #define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
770 #define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val)
772 #define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val)
774 #define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
776 #define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
778 #define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
780 #define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
783 #define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
785 #define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val)
787 #define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val)
789 #define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
791 #define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
793 #define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
795 #define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
797 #define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val)
799 #define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val)
801 #define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
803 #define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
805 #define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
807 #define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
812 #define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val)
814 #define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val)
817 #define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val)
819 #define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val)
821 #define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val)
828 #define bfin_write_PORTGIO(val) bfin_write16(PORTGIO, val)
830 #define bfin_write_PORTGIO_CLEAR(val) bfin_write16(PORTGIO_CLEAR, val)
832 #define bfin_write_PORTGIO_SET(val) bfin_write16(PORTGIO_SET, val)
834 #define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val)
836 #define bfin_write_PORTGIO_MASKA(val) bfin_write16(PORTGIO_MASKA, val)
838 #define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val)
840 #define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val)
842 #define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val)
844 #define bfin_write_PORTGIO_MASKB(val) bfin_write16(PORTGIO_MASKB, val)
846 #define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val)
848 #define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val)
850 #define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val)
852 #define bfin_write_PORTGIO_DIR(val) bfin_write16(PORTGIO_DIR, val)
854 #define bfin_write_PORTGIO_POLAR(val) bfin_write16(PORTGIO_POLAR, val)
856 #define bfin_write_PORTGIO_EDGE(val) bfin_write16(PORTGIO_EDGE, val)
858 #define bfin_write_PORTGIO_BOTH(val) bfin_write16(PORTGIO_BOTH, val)
860 #define bfin_write_PORTGIO_INEN(val) bfin_write16(PORTGIO_INEN, val)
865 #define bfin_write_PORTHIO(val) bfin_write16(PORTHIO, val)
867 #define bfin_write_PORTHIO_CLEAR(val) bfin_write16(PORTHIO_CLEAR, val)
869 #define bfin_write_PORTHIO_SET(val) bfin_write16(PORTHIO_SET, val)
871 #define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val)
873 #define bfin_write_PORTHIO_MASKA(val) bfin_write16(PORTHIO_MASKA, val)
875 #define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val)
877 #define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val)
879 #define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val)
881 #define bfin_write_PORTHIO_MASKB(val) bfin_write16(PORTHIO_MASKB, val)
883 #define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val)
885 #define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val)
887 #define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val)
889 #define bfin_write_PORTHIO_DIR(val) bfin_write16(PORTHIO_DIR, val)
891 #define bfin_write_PORTHIO_POLAR(val) bfin_write16(PORTHIO_POLAR, val)
893 #define bfin_write_PORTHIO_EDGE(val) bfin_write16(PORTHIO_EDGE, val)
895 #define bfin_write_PORTHIO_BOTH(val) bfin_write16(PORTHIO_BOTH, val)
897 #define bfin_write_PORTHIO_INEN(val) bfin_write16(PORTHIO_INEN, val)
902 #define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val)
904 #define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val)
906 #define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val)
908 #define bfin_write_UART1_IER(val) bfin_write16(UART1_IER, val)
910 #define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val)
912 #define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR, val)
914 #define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val)
916 #define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val)
918 #define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val)
920 #define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val)
922 #define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val)
924 #define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val)
930 #define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val)
932 #define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val)
934 #define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val)
936 #define bfin_write_PORT_MUX(val) bfin_write16(PORT_MUX, val)
941 #define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
943 #define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
945 #define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
947 #define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
949 #define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
951 #define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
953 #define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
956 #define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
958 #define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
960 #define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
962 #define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
964 #define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
966 #define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
968 #define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
975 #define bfin_write_PORTF_MUX(val) bfin_write16(PORTF_MUX, val)
977 #define bfin_write_PORTG_MUX(val) bfin_write16(PORTG_MUX, val)
979 #define bfin_write_PORTH_MUX(val) bfin_write16(PORTH_MUX, val)
982 #define bfin_write_PORTF_DRIVE(val) bfin_write16(PORTF_DRIVE, val)
984 #define bfin_write_PORTG_DRIVE(val) bfin_write16(PORTG_DRIVE, val)
986 #define bfin_write_PORTH_DRIVE(val) bfin_write16(PORTH_DRIVE, val)
988 #define bfin_write_PORTF_SLEW(val) bfin_write16(PORTF_SLEW, val)
990 #define bfin_write_PORTG_SLEW(val) bfin_write16(PORTG_SLEW, val)
992 #define bfin_write_PORTH_SLEW(val) bfin_write16(PORTH_SLEW, val)
994 #define bfin_write_PORTF_HYSTERESIS(val) bfin_write16(PORTF_HYSTERESIS, val)
996 #define bfin_write_PORTG_HYSTERESIS(val) bfin_write16(PORTG_HYSTERESIS, val)
998 #define bfin_write_PORTH_HYSTERESIS(val) bfin_write16(PORTH_HYSTERESIS, val)
1000 #define bfin_write_MISCPORT_DRIVE(val) bfin_write16(MISCPORT_DRIVE, val)
1002 #define bfin_write_MISCPORT_SLEW(val) bfin_write16(MISCPORT_SLEW, val)
1004 #define bfin_write_MISCPORT_HYSTERESIS(val) bfin_write16(MISCPORT_HYSTERESIS, val)
1009 #define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val)
1011 #define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val)
1013 #define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val)
1018 #define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val)
1020 #define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val)
1022 #define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val)
1024 #define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val)
1026 #define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val)
1028 #define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val)
1030 #define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val)
1032 #define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val)
1037 #define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val)
1039 #define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
1041 #define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val)
H A DcdefBF516.h16 #define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE, val)
18 #define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO, val)
20 #define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI, val)
22 #define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO, val)
24 #define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI, val)
26 #define bfin_write_EMAC_STAADD(val) bfin_write32(EMAC_STAADD, val)
28 #define bfin_write_EMAC_STADAT(val) bfin_write32(EMAC_STADAT, val)
30 #define bfin_write_EMAC_FLC(val) bfin_write32(EMAC_FLC, val)
32 #define bfin_write_EMAC_VLAN1(val) bfin_write32(EMAC_VLAN1, val)
34 #define bfin_write_EMAC_VLAN2(val) bfin_write32(EMAC_VLAN2, val)
36 #define bfin_write_EMAC_WKUP_CTL(val) bfin_write32(EMAC_WKUP_CTL, val)
38 #define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0, val)
40 #define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1, val)
42 #define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2, val)
44 #define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3, val)
46 #define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD, val)
48 #define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF, val)
50 #define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0, val)
52 #define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1, val)
55 #define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL, val)
57 #define bfin_write_EMAC_SYSTAT(val) bfin_write32(EMAC_SYSTAT, val)
59 #define bfin_write_EMAC_RX_STAT(val) bfin_write32(EMAC_RX_STAT, val)
61 #define bfin_write_EMAC_RX_STKY(val) bfin_write32(EMAC_RX_STKY, val)
63 #define bfin_write_EMAC_RX_IRQE(val) bfin_write32(EMAC_RX_IRQE, val)
65 #define bfin_write_EMAC_TX_STAT(val) bfin_write32(EMAC_TX_STAT, val)
67 #define bfin_write_EMAC_TX_STKY(val) bfin_write32(EMAC_TX_STKY, val)
69 #define bfin_write_EMAC_TX_IRQE(val) bfin_write32(EMAC_TX_IRQE, val)
72 #define bfin_write_EMAC_MMC_CTL(val) bfin_write32(EMAC_MMC_CTL, val)
74 #define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS, val)
76 #define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE, val)
78 #define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS, val)
80 #define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE, val)
83 #define bfin_write_EMAC_RXC_OK(val) bfin_write32(EMAC_RXC_OK, val)
85 #define bfin_write_EMAC_RXC_FCS(val) bfin_write32(EMAC_RXC_FCS, val)
87 #define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN, val)
89 #define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET, val)
91 #define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF, val)
93 #define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST, val)
95 #define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI, val)
97 #define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD, val)
99 #define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI, val)
101 #define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO, val)
103 #define bfin_write_EMAC_RXC_LONG(val) bfin_write32(EMAC_RXC_LONG, val)
105 #define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL, val)
107 #define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE, val)
109 #define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE, val)
111 #define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM, val)
113 #define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT, val)
115 #define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED, val)
117 #define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT, val)
119 #define bfin_write_EMAC_RXC_EQ64(val) bfin_write32(EMAC_RXC_EQ64, val)
121 #define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128, val)
123 #define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256, val)
125 #define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512, val)
127 #define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024, val)
129 #define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024, val)
132 #define bfin_write_EMAC_TXC_OK(val) bfin_write32(EMAC_TXC_OK, val)
134 #define bfin_write_EMAC_TXC_1COL(val) bfin_write32(EMAC_TXC_1COL, val)
136 #define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL, val)
138 #define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET, val)
140 #define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER, val)
142 #define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL, val)
144 #define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL, val)
146 #define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND, val)
148 #define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR, val)
150 #define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST, val)
152 #define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI, val)
154 #define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD, val)
156 #define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR, val)
158 #define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL, val)
160 #define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM, val)
162 #define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT, val)
164 #define bfin_write_EMAC_TXC_EQ64(val) bfin_write32(EMAC_TXC_EQ64, val)
166 #define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128, val)
168 #define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256, val)
170 #define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512, val)
172 #define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024, val)
174 #define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024, val)
176 #define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val)
H A DcdefBF514.h16 #define bfin_write_RSI_PWR_CTL(val) bfin_write16(RSI_PWR_CONTROL, val)
18 #define bfin_write_RSI_CLK_CTL(val) bfin_write16(RSI_CLK_CONTROL, val)
20 #define bfin_write_RSI_ARGUMENT(val) bfin_write32(RSI_ARGUMENT, val)
22 #define bfin_write_RSI_COMMAND(val) bfin_write16(RSI_COMMAND, val)
24 #define bfin_write_RSI_RESP_CMD(val) bfin_write16(RSI_RESP_CMD, val)
26 #define bfin_write_RSI_RESPONSE0(val) bfin_write32(RSI_RESPONSE0, val)
28 #define bfin_write_RSI_RESPONSE1(val) bfin_write32(RSI_RESPONSE1, val)
30 #define bfin_write_RSI_RESPONSE2(val) bfin_write32(RSI_RESPONSE2, val)
32 #define bfin_write_RSI_RESPONSE3(val) bfin_write32(RSI_RESPONSE3, val)
34 #define bfin_write_RSI_DATA_TIMER(val) bfin_write32(RSI_DATA_TIMER, val)
36 #define bfin_write_RSI_DATA_LGTH(val) bfin_write16(RSI_DATA_LGTH, val)
38 #define bfin_write_RSI_DATA_CTL(val) bfin_write16(RSI_DATA_CONTROL, val)
40 #define bfin_write_RSI_DATA_CNT(val) bfin_write16(RSI_DATA_CNT, val)
42 #define bfin_write_RSI_STATUS(val) bfin_write32(RSI_STATUS, val)
44 #define bfin_write_RSI_STATUS_CLR(val) bfin_write16(RSI_STATUSCL, val)
46 #define bfin_write_RSI_MASK0(val) bfin_write32(RSI_MASK0, val)
48 #define bfin_write_RSI_MASK1(val) bfin_write32(RSI_MASK1, val)
50 #define bfin_write_RSI_FIFO_CNT(val) bfin_write16(RSI_FIFO_CNT, val)
52 #define bfin_write_RSI_CEATA_CTL(val) bfin_write16(RSI_CEATA_CONTROL, val)
54 #define bfin_write_RSI_FIFO(val) bfin_write32(RSI_FIFO, val)
56 #define bfin_write_RSI_E_STATUS(val) bfin_write16(RSI_ESTAT, val)
58 #define bfin_write_RSI_E_MASK(val) bfin_write16(RSI_EMASK, val)
60 #define bfin_write_RSI_CFG(val) bfin_write16(RSI_CONFIG, val)
62 #define bfin_write_RSI_RD_WAIT_EN(val) bfin_write16(RSI_RD_WAIT_EN, val)
64 #define bfin_write_RSI_PID0(val) bfin_write16(RSI_PID0, val)
66 #define bfin_write_RSI_PID1(val) bfin_write16(RSI_PID1, val)
68 #define bfin_write_RSI_PID2(val) bfin_write16(RSI_PID2, val)
70 #define bfin_write_RSI_PID3(val) bfin_write16(RSI_PID3, val)
72 #define bfin_write_RSI_PID4(val) bfin_write16(RSI_PID4, val)
74 #define bfin_write_RSI_PID5(val) bfin_write16(RSI_PID5, val)
76 #define bfin_write_RSI_PID6(val) bfin_write16(RSI_PID6, val)
78 #define bfin_write_RSI_PID7(val) bfin_write16(RSI_PID7, val)
H A DcdefBF518.h16 #define bfin_write_EMAC_PTP_CTL(val) bfin_write16(EMAC_PTP_CTL, val)
18 #define bfin_write_EMAC_PTP_IE(val) bfin_write16(EMAC_PTP_IE, val)
20 #define bfin_write_EMAC_PTP_ISTAT(val) bfin_write16(EMAC_PTP_ISTAT, val)
22 #define bfin_write_EMAC_PTP_FOFF(val) bfin_write32(EMAC_PTP_FOFF, val)
24 #define bfin_write_EMAC_PTP_FV1(val) bfin_write32(EMAC_PTP_FV1, val)
26 #define bfin_write_EMAC_PTP_FV2(val) bfin_write32(EMAC_PTP_FV2, val)
28 #define bfin_write_EMAC_PTP_FV3(val) bfin_write32(EMAC_PTP_FV3, val)
30 #define bfin_write_EMAC_PTP_ADDEND(val) bfin_write32(EMAC_PTP_ADDEND, val)
32 #define bfin_write_EMAC_PTP_ACCR(val) bfin_write32(EMAC_PTP_ACCR, val)
34 #define bfin_write_EMAC_PTP_OFFSET(val) bfin_write32(EMAC_PTP_OFFSET, val)
36 #define bfin_write_EMAC_PTP_TIMELO(val) bfin_write32(EMAC_PTP_TIMELO, val)
38 #define bfin_write_EMAC_PTP_TIMEHI(val) bfin_write32(EMAC_PTP_TIMEHI, val)
44 #define bfin_write_EMAC_PTP_ALARMLO(val) bfin_write32(EMAC_PTP_ALARMLO, val)
46 #define bfin_write_EMAC_PTP_ALARMHI(val) bfin_write32(EMAC_PTP_ALARMHI, val)
48 #define bfin_write_EMAC_PTP_ID_OFF(val) bfin_write16(EMAC_PTP_ID_OFF, val)
50 #define bfin_write_EMAC_PTP_ID_SNAP(val) bfin_write32(EMAC_PTP_ID_SNAP, val)
52 #define bfin_write_EMAC_PTP_PPS_STARTHI(val) bfin_write32(EMAC_PTP_PPS_STARTHI, val)
54 #define bfin_write_EMAC_PTP_PPS_PERIOD(val) bfin_write32(EMAC_PTP_PPS_PERIOD, val)
/linux-4.1.27/drivers/media/tuners/
H A Dtda18271-maps.c31 u8 val; member in struct:tda18271_map
202 { .rfmax = 62000, .val = 0x00 },
203 { .rfmax = 84000, .val = 0x01 },
204 { .rfmax = 100000, .val = 0x02 },
205 { .rfmax = 140000, .val = 0x03 },
206 { .rfmax = 170000, .val = 0x04 },
207 { .rfmax = 180000, .val = 0x05 },
208 { .rfmax = 865000, .val = 0x06 },
209 { .rfmax = 0, .val = 0x00 }, /* end */
213 { .rfmax = 61100, .val = 0x74 },
214 { .rfmax = 350000, .val = 0x40 },
215 { .rfmax = 720000, .val = 0x30 },
216 { .rfmax = 865000, .val = 0x40 },
217 { .rfmax = 0, .val = 0x00 }, /* end */
221 { .rfmax = 47900, .val = 0x38 },
222 { .rfmax = 61100, .val = 0x44 },
223 { .rfmax = 350000, .val = 0x30 },
224 { .rfmax = 720000, .val = 0x24 },
225 { .rfmax = 865000, .val = 0x3c },
226 { .rfmax = 0, .val = 0x00 }, /* end */
230 { .rfmax = 47900, .val = 0x00 },
231 { .rfmax = 61100, .val = 0x01 },
232 { .rfmax = 152600, .val = 0x02 },
233 { .rfmax = 164700, .val = 0x03 },
234 { .rfmax = 203500, .val = 0x04 },
235 { .rfmax = 457800, .val = 0x05 },
236 { .rfmax = 865000, .val = 0x06 },
237 { .rfmax = 0, .val = 0x00 }, /* end */
241 { .rfmax = 45400, .val = 0x1f },
242 { .rfmax = 45800, .val = 0x1e },
243 { .rfmax = 46200, .val = 0x1d },
244 { .rfmax = 46700, .val = 0x1c },
245 { .rfmax = 47100, .val = 0x1b },
246 { .rfmax = 47500, .val = 0x1a },
247 { .rfmax = 47900, .val = 0x19 },
248 { .rfmax = 49600, .val = 0x17 },
249 { .rfmax = 51200, .val = 0x16 },
250 { .rfmax = 52900, .val = 0x15 },
251 { .rfmax = 54500, .val = 0x14 },
252 { .rfmax = 56200, .val = 0x13 },
253 { .rfmax = 57800, .val = 0x12 },
254 { .rfmax = 59500, .val = 0x11 },
255 { .rfmax = 61100, .val = 0x10 },
256 { .rfmax = 67600, .val = 0x0d },
257 { .rfmax = 74200, .val = 0x0c },
258 { .rfmax = 80700, .val = 0x0b },
259 { .rfmax = 87200, .val = 0x0a },
260 { .rfmax = 93800, .val = 0x09 },
261 { .rfmax = 100300, .val = 0x08 },
262 { .rfmax = 106900, .val = 0x07 },
263 { .rfmax = 113400, .val = 0x06 },
264 { .rfmax = 119900, .val = 0x05 },
265 { .rfmax = 126500, .val = 0x04 },
266 { .rfmax = 133000, .val = 0x03 },
267 { .rfmax = 139500, .val = 0x02 },
268 { .rfmax = 146100, .val = 0x01 },
269 { .rfmax = 152600, .val = 0x00 },
270 { .rfmax = 154300, .val = 0x1f },
271 { .rfmax = 156100, .val = 0x1e },
272 { .rfmax = 157800, .val = 0x1d },
273 { .rfmax = 159500, .val = 0x1c },
274 { .rfmax = 161200, .val = 0x1b },
275 { .rfmax = 163000, .val = 0x1a },
276 { .rfmax = 164700, .val = 0x19 },
277 { .rfmax = 170200, .val = 0x17 },
278 { .rfmax = 175800, .val = 0x16 },
279 { .rfmax = 181300, .val = 0x15 },
280 { .rfmax = 186900, .val = 0x14 },
281 { .rfmax = 192400, .val = 0x13 },
282 { .rfmax = 198000, .val = 0x12 },
283 { .rfmax = 203500, .val = 0x11 },
284 { .rfmax = 216200, .val = 0x14 },
285 { .rfmax = 228900, .val = 0x13 },
286 { .rfmax = 241600, .val = 0x12 },
287 { .rfmax = 254400, .val = 0x11 },
288 { .rfmax = 267100, .val = 0x10 },
289 { .rfmax = 279800, .val = 0x0f },
290 { .rfmax = 292500, .val = 0x0e },
291 { .rfmax = 305200, .val = 0x0d },
292 { .rfmax = 317900, .val = 0x0c },
293 { .rfmax = 330700, .val = 0x0b },
294 { .rfmax = 343400, .val = 0x0a },
295 { .rfmax = 356100, .val = 0x09 },
296 { .rfmax = 368800, .val = 0x08 },
297 { .rfmax = 381500, .val = 0x07 },
298 { .rfmax = 394200, .val = 0x06 },
299 { .rfmax = 406900, .val = 0x05 },
300 { .rfmax = 419700, .val = 0x04 },
301 { .rfmax = 432400, .val = 0x03 },
302 { .rfmax = 445100, .val = 0x02 },
303 { .rfmax = 457800, .val = 0x01 },
304 { .rfmax = 476300, .val = 0x19 },
305 { .rfmax = 494800, .val = 0x18 },
306 { .rfmax = 513300, .val = 0x17 },
307 { .rfmax = 531800, .val = 0x16 },
308 { .rfmax = 550300, .val = 0x15 },
309 { .rfmax = 568900, .val = 0x14 },
310 { .rfmax = 587400, .val = 0x13 },
311 { .rfmax = 605900, .val = 0x12 },
312 { .rfmax = 624400, .val = 0x11 },
313 { .rfmax = 642900, .val = 0x10 },
314 { .rfmax = 661400, .val = 0x0f },
315 { .rfmax = 679900, .val = 0x0e },
316 { .rfmax = 698400, .val = 0x0d },
317 { .rfmax = 716900, .val = 0x0c },
318 { .rfmax = 735400, .val = 0x0b },
319 { .rfmax = 753900, .val = 0x0a },
320 { .rfmax = 772500, .val = 0x09 },
321 { .rfmax = 791000, .val = 0x08 },
322 { .rfmax = 809500, .val = 0x07 },
323 { .rfmax = 828000, .val = 0x06 },
324 { .rfmax = 846500, .val = 0x05 },
325 { .rfmax = 865000, .val = 0x04 },
326 { .rfmax = 0, .val = 0x00 }, /* end */
330 { .rfmax = 41000, .val = 0x1e },
331 { .rfmax = 43000, .val = 0x30 },
332 { .rfmax = 45000, .val = 0x43 },
333 { .rfmax = 46000, .val = 0x4d },
334 { .rfmax = 47000, .val = 0x54 },
335 { .rfmax = 47900, .val = 0x64 },
336 { .rfmax = 49100, .val = 0x20 },
337 { .rfmax = 50000, .val = 0x22 },
338 { .rfmax = 51000, .val = 0x2a },
339 { .rfmax = 53000, .val = 0x32 },
340 { .rfmax = 55000, .val = 0x35 },
341 { .rfmax = 56000, .val = 0x3c },
342 { .rfmax = 57000, .val = 0x3f },
343 { .rfmax = 58000, .val = 0x48 },
344 { .rfmax = 59000, .val = 0x4d },
345 { .rfmax = 60000, .val = 0x58 },
346 { .rfmax = 61100, .val = 0x5f },
347 { .rfmax = 0, .val = 0x00 }, /* end */
351 { .rfmax = 41000, .val = 0x0f },
352 { .rfmax = 43000, .val = 0x1c },
353 { .rfmax = 45000, .val = 0x2f },
354 { .rfmax = 46000, .val = 0x39 },
355 { .rfmax = 47000, .val = 0x40 },
356 { .rfmax = 47900, .val = 0x50 },
357 { .rfmax = 49100, .val = 0x16 },
358 { .rfmax = 50000, .val = 0x18 },
359 { .rfmax = 51000, .val = 0x20 },
360 { .rfmax = 53000, .val = 0x28 },
361 { .rfmax = 55000, .val = 0x2b },
362 { .rfmax = 56000, .val = 0x32 },
363 { .rfmax = 57000, .val = 0x35 },
364 { .rfmax = 58000, .val = 0x3e },
365 { .rfmax = 59000, .val = 0x43 },
366 { .rfmax = 60000, .val = 0x4e },
367 { .rfmax = 61100, .val = 0x55 },
368 { .rfmax = 63000, .val = 0x0f },
369 { .rfmax = 64000, .val = 0x11 },
370 { .rfmax = 65000, .val = 0x12 },
371 { .rfmax = 66000, .val = 0x15 },
372 { .rfmax = 67000, .val = 0x16 },
373 { .rfmax = 68000, .val = 0x17 },
374 { .rfmax = 70000, .val = 0x19 },
375 { .rfmax = 71000, .val = 0x1c },
376 { .rfmax = 72000, .val = 0x1d },
377 { .rfmax = 73000, .val = 0x1f },
378 { .rfmax = 74000, .val = 0x20 },
379 { .rfmax = 75000, .val = 0x21 },
380 { .rfmax = 76000, .val = 0x24 },
381 { .rfmax = 77000, .val = 0x25 },
382 { .rfmax = 78000, .val = 0x27 },
383 { .rfmax = 80000, .val = 0x28 },
384 { .rfmax = 81000, .val = 0x29 },
385 { .rfmax = 82000, .val = 0x2d },
386 { .rfmax = 83000, .val = 0x2e },
387 { .rfmax = 84000, .val = 0x2f },
388 { .rfmax = 85000, .val = 0x31 },
389 { .rfmax = 86000, .val = 0x33 },
390 { .rfmax = 87000, .val = 0x34 },
391 { .rfmax = 88000, .val = 0x35 },
392 { .rfmax = 89000, .val = 0x37 },
393 { .rfmax = 90000, .val = 0x38 },
394 { .rfmax = 91000, .val = 0x39 },
395 { .rfmax = 93000, .val = 0x3c },
396 { .rfmax = 94000, .val = 0x3e },
397 { .rfmax = 95000, .val = 0x3f },
398 { .rfmax = 96000, .val = 0x40 },
399 { .rfmax = 97000, .val = 0x42 },
400 { .rfmax = 99000, .val = 0x45 },
401 { .rfmax = 100000, .val = 0x46 },
402 { .rfmax = 102000, .val = 0x48 },
403 { .rfmax = 103000, .val = 0x4a },
404 { .rfmax = 105000, .val = 0x4d },
405 { .rfmax = 106000, .val = 0x4e },
406 { .rfmax = 107000, .val = 0x50 },
407 { .rfmax = 108000, .val = 0x51 },
408 { .rfmax = 110000, .val = 0x54 },
409 { .rfmax = 111000, .val = 0x56 },
410 { .rfmax = 112000, .val = 0x57 },
411 { .rfmax = 113000, .val = 0x58 },
412 { .rfmax = 114000, .val = 0x59 },
413 { .rfmax = 115000, .val = 0x5c },
414 { .rfmax = 116000, .val = 0x5d },
415 { .rfmax = 117000, .val = 0x5f },
416 { .rfmax = 119000, .val = 0x60 },
417 { .rfmax = 120000, .val = 0x64 },
418 { .rfmax = 121000, .val = 0x65 },
419 { .rfmax = 122000, .val = 0x66 },
420 { .rfmax = 123000, .val = 0x68 },
421 { .rfmax = 124000, .val = 0x69 },
422 { .rfmax = 125000, .val = 0x6c },
423 { .rfmax = 126000, .val = 0x6d },
424 { .rfmax = 127000, .val = 0x6e },
425 { .rfmax = 128000, .val = 0x70 },
426 { .rfmax = 129000, .val = 0x71 },
427 { .rfmax = 130000, .val = 0x75 },
428 { .rfmax = 131000, .val = 0x77 },
429 { .rfmax = 132000, .val = 0x78 },
430 { .rfmax = 133000, .val = 0x7b },
431 { .rfmax = 134000, .val = 0x7e },
432 { .rfmax = 135000, .val = 0x81 },
433 { .rfmax = 136000, .val = 0x82 },
434 { .rfmax = 137000, .val = 0x87 },
435 { .rfmax = 138000, .val = 0x88 },
436 { .rfmax = 139000, .val = 0x8d },
437 { .rfmax = 140000, .val = 0x8e },
438 { .rfmax = 141000, .val = 0x91 },
439 { .rfmax = 142000, .val = 0x95 },
440 { .rfmax = 143000, .val = 0x9a },
441 { .rfmax = 144000, .val = 0x9d },
442 { .rfmax = 145000, .val = 0xa1 },
443 { .rfmax = 146000, .val = 0xa2 },
444 { .rfmax = 147000, .val = 0xa4 },
445 { .rfmax = 148000, .val = 0xa9 },
446 { .rfmax = 149000, .val = 0xae },
447 { .rfmax = 150000, .val = 0xb0 },
448 { .rfmax = 151000, .val = 0xb1 },
449 { .rfmax = 152000, .val = 0xb7 },
450 { .rfmax = 152600, .val = 0xbd },
451 { .rfmax = 154000, .val = 0x20 },
452 { .rfmax = 155000, .val = 0x22 },
453 { .rfmax = 156000, .val = 0x24 },
454 { .rfmax = 157000, .val = 0x25 },
455 { .rfmax = 158000, .val = 0x27 },
456 { .rfmax = 159000, .val = 0x29 },
457 { .rfmax = 160000, .val = 0x2c },
458 { .rfmax = 161000, .val = 0x2d },
459 { .rfmax = 163000, .val = 0x2e },
460 { .rfmax = 164000, .val = 0x2f },
461 { .rfmax = 164700, .val = 0x30 },
462 { .rfmax = 166000, .val = 0x11 },
463 { .rfmax = 167000, .val = 0x12 },
464 { .rfmax = 168000, .val = 0x13 },
465 { .rfmax = 169000, .val = 0x14 },
466 { .rfmax = 170000, .val = 0x15 },
467 { .rfmax = 172000, .val = 0x16 },
468 { .rfmax = 173000, .val = 0x17 },
469 { .rfmax = 174000, .val = 0x18 },
470 { .rfmax = 175000, .val = 0x1a },
471 { .rfmax = 176000, .val = 0x1b },
472 { .rfmax = 178000, .val = 0x1d },
473 { .rfmax = 179000, .val = 0x1e },
474 { .rfmax = 180000, .val = 0x1f },
475 { .rfmax = 181000, .val = 0x20 },
476 { .rfmax = 182000, .val = 0x21 },
477 { .rfmax = 183000, .val = 0x22 },
478 { .rfmax = 184000, .val = 0x24 },
479 { .rfmax = 185000, .val = 0x25 },
480 { .rfmax = 186000, .val = 0x26 },
481 { .rfmax = 187000, .val = 0x27 },
482 { .rfmax = 188000, .val = 0x29 },
483 { .rfmax = 189000, .val = 0x2a },
484 { .rfmax = 190000, .val = 0x2c },
485 { .rfmax = 191000, .val = 0x2d },
486 { .rfmax = 192000, .val = 0x2e },
487 { .rfmax = 193000, .val = 0x2f },
488 { .rfmax = 194000, .val = 0x30 },
489 { .rfmax = 195000, .val = 0x33 },
490 { .rfmax = 196000, .val = 0x35 },
491 { .rfmax = 198000, .val = 0x36 },
492 { .rfmax = 200000, .val = 0x38 },
493 { .rfmax = 201000, .val = 0x3c },
494 { .rfmax = 202000, .val = 0x3d },
495 { .rfmax = 203500, .val = 0x3e },
496 { .rfmax = 206000, .val = 0x0e },
497 { .rfmax = 208000, .val = 0x0f },
498 { .rfmax = 212000, .val = 0x10 },
499 { .rfmax = 216000, .val = 0x11 },
500 { .rfmax = 217000, .val = 0x12 },
501 { .rfmax = 218000, .val = 0x13 },
502 { .rfmax = 220000, .val = 0x14 },
503 { .rfmax = 222000, .val = 0x15 },
504 { .rfmax = 225000, .val = 0x16 },
505 { .rfmax = 228000, .val = 0x17 },
506 { .rfmax = 231000, .val = 0x18 },
507 { .rfmax = 234000, .val = 0x19 },
508 { .rfmax = 235000, .val = 0x1a },
509 { .rfmax = 236000, .val = 0x1b },
510 { .rfmax = 237000, .val = 0x1c },
511 { .rfmax = 240000, .val = 0x1d },
512 { .rfmax = 242000, .val = 0x1e },
513 { .rfmax = 244000, .val = 0x1f },
514 { .rfmax = 247000, .val = 0x20 },
515 { .rfmax = 249000, .val = 0x21 },
516 { .rfmax = 252000, .val = 0x22 },
517 { .rfmax = 253000, .val = 0x23 },
518 { .rfmax = 254000, .val = 0x24 },
519 { .rfmax = 256000, .val = 0x25 },
520 { .rfmax = 259000, .val = 0x26 },
521 { .rfmax = 262000, .val = 0x27 },
522 { .rfmax = 264000, .val = 0x28 },
523 { .rfmax = 267000, .val = 0x29 },
524 { .rfmax = 269000, .val = 0x2a },
525 { .rfmax = 271000, .val = 0x2b },
526 { .rfmax = 273000, .val = 0x2c },
527 { .rfmax = 275000, .val = 0x2d },
528 { .rfmax = 277000, .val = 0x2e },
529 { .rfmax = 279000, .val = 0x2f },
530 { .rfmax = 282000, .val = 0x30 },
531 { .rfmax = 284000, .val = 0x31 },
532 { .rfmax = 286000, .val = 0x32 },
533 { .rfmax = 287000, .val = 0x33 },
534 { .rfmax = 290000, .val = 0x34 },
535 { .rfmax = 293000, .val = 0x35 },
536 { .rfmax = 295000, .val = 0x36 },
537 { .rfmax = 297000, .val = 0x37 },
538 { .rfmax = 300000, .val = 0x38 },
539 { .rfmax = 303000, .val = 0x39 },
540 { .rfmax = 305000, .val = 0x3a },
541 { .rfmax = 306000, .val = 0x3b },
542 { .rfmax = 307000, .val = 0x3c },
543 { .rfmax = 310000, .val = 0x3d },
544 { .rfmax = 312000, .val = 0x3e },
545 { .rfmax = 315000, .val = 0x3f },
546 { .rfmax = 318000, .val = 0x40 },
547 { .rfmax = 320000, .val = 0x41 },
548 { .rfmax = 323000, .val = 0x42 },
549 { .rfmax = 324000, .val = 0x43 },
550 { .rfmax = 325000, .val = 0x44 },
551 { .rfmax = 327000, .val = 0x45 },
552 { .rfmax = 331000, .val = 0x46 },
553 { .rfmax = 334000, .val = 0x47 },
554 { .rfmax = 337000, .val = 0x48 },
555 { .rfmax = 339000, .val = 0x49 },
556 { .rfmax = 340000, .val = 0x4a },
557 { .rfmax = 341000, .val = 0x4b },
558 { .rfmax = 343000, .val = 0x4c },
559 { .rfmax = 345000, .val = 0x4d },
560 { .rfmax = 349000, .val = 0x4e },
561 { .rfmax = 352000, .val = 0x4f },
562 { .rfmax = 353000, .val = 0x50 },
563 { .rfmax = 355000, .val = 0x51 },
564 { .rfmax = 357000, .val = 0x52 },
565 { .rfmax = 359000, .val = 0x53 },
566 { .rfmax = 361000, .val = 0x54 },
567 { .rfmax = 362000, .val = 0x55 },
568 { .rfmax = 364000, .val = 0x56 },
569 { .rfmax = 368000, .val = 0x57 },
570 { .rfmax = 370000, .val = 0x58 },
571 { .rfmax = 372000, .val = 0x59 },
572 { .rfmax = 375000, .val = 0x5a },
573 { .rfmax = 376000, .val = 0x5b },
574 { .rfmax = 377000, .val = 0x5c },
575 { .rfmax = 379000, .val = 0x5d },
576 { .rfmax = 382000, .val = 0x5e },
577 { .rfmax = 384000, .val = 0x5f },
578 { .rfmax = 385000, .val = 0x60 },
579 { .rfmax = 386000, .val = 0x61 },
580 { .rfmax = 388000, .val = 0x62 },
581 { .rfmax = 390000, .val = 0x63 },
582 { .rfmax = 393000, .val = 0x64 },
583 { .rfmax = 394000, .val = 0x65 },
584 { .rfmax = 396000, .val = 0x66 },
585 { .rfmax = 397000, .val = 0x67 },
586 { .rfmax = 398000, .val = 0x68 },
587 { .rfmax = 400000, .val = 0x69 },
588 { .rfmax = 402000, .val = 0x6a },
589 { .rfmax = 403000, .val = 0x6b },
590 { .rfmax = 407000, .val = 0x6c },
591 { .rfmax = 408000, .val = 0x6d },
592 { .rfmax = 409000, .val = 0x6e },
593 { .rfmax = 410000, .val = 0x6f },
594 { .rfmax = 411000, .val = 0x70 },
595 { .rfmax = 412000, .val = 0x71 },
596 { .rfmax = 413000, .val = 0x72 },
597 { .rfmax = 414000, .val = 0x73 },
598 { .rfmax = 417000, .val = 0x74 },
599 { .rfmax = 418000, .val = 0x75 },
600 { .rfmax = 420000, .val = 0x76 },
601 { .rfmax = 422000, .val = 0x77 },
602 { .rfmax = 423000, .val = 0x78 },
603 { .rfmax = 424000, .val = 0x79 },
604 { .rfmax = 427000, .val = 0x7a },
605 { .rfmax = 428000, .val = 0x7b },
606 { .rfmax = 429000, .val = 0x7d },
607 { .rfmax = 432000, .val = 0x7f },
608 { .rfmax = 434000, .val = 0x80 },
609 { .rfmax = 435000, .val = 0x81 },
610 { .rfmax = 436000, .val = 0x83 },
611 { .rfmax = 437000, .val = 0x84 },
612 { .rfmax = 438000, .val = 0x85 },
613 { .rfmax = 439000, .val = 0x86 },
614 { .rfmax = 440000, .val = 0x87 },
615 { .rfmax = 441000, .val = 0x88 },
616 { .rfmax = 442000, .val = 0x89 },
617 { .rfmax = 445000, .val = 0x8a },
618 { .rfmax = 446000, .val = 0x8b },
619 { .rfmax = 447000, .val = 0x8c },
620 { .rfmax = 448000, .val = 0x8e },
621 { .rfmax = 449000, .val = 0x8f },
622 { .rfmax = 450000, .val = 0x90 },
623 { .rfmax = 452000, .val = 0x91 },
624 { .rfmax = 453000, .val = 0x93 },
625 { .rfmax = 454000, .val = 0x94 },
626 { .rfmax = 456000, .val = 0x96 },
627 { .rfmax = 457800, .val = 0x98 },
628 { .rfmax = 461000, .val = 0x11 },
629 { .rfmax = 468000, .val = 0x12 },
630 { .rfmax = 472000, .val = 0x13 },
631 { .rfmax = 473000, .val = 0x14 },
632 { .rfmax = 474000, .val = 0x15 },
633 { .rfmax = 481000, .val = 0x16 },
634 { .rfmax = 486000, .val = 0x17 },
635 { .rfmax = 491000, .val = 0x18 },
636 { .rfmax = 498000, .val = 0x19 },
637 { .rfmax = 499000, .val = 0x1a },
638 { .rfmax = 501000, .val = 0x1b },
639 { .rfmax = 506000, .val = 0x1c },
640 { .rfmax = 511000, .val = 0x1d },
641 { .rfmax = 516000, .val = 0x1e },
642 { .rfmax = 520000, .val = 0x1f },
643 { .rfmax = 521000, .val = 0x20 },
644 { .rfmax = 525000, .val = 0x21 },
645 { .rfmax = 529000, .val = 0x22 },
646 { .rfmax = 533000, .val = 0x23 },
647 { .rfmax = 539000, .val = 0x24 },
648 { .rfmax = 541000, .val = 0x25 },
649 { .rfmax = 547000, .val = 0x26 },
650 { .rfmax = 549000, .val = 0x27 },
651 { .rfmax = 551000, .val = 0x28 },
652 { .rfmax = 556000, .val = 0x29 },
653 { .rfmax = 561000, .val = 0x2a },
654 { .rfmax = 563000, .val = 0x2b },
655 { .rfmax = 565000, .val = 0x2c },
656 { .rfmax = 569000, .val = 0x2d },
657 { .rfmax = 571000, .val = 0x2e },
658 { .rfmax = 577000, .val = 0x2f },
659 { .rfmax = 580000, .val = 0x30 },
660 { .rfmax = 582000, .val = 0x31 },
661 { .rfmax = 584000, .val = 0x32 },
662 { .rfmax = 588000, .val = 0x33 },
663 { .rfmax = 591000, .val = 0x34 },
664 { .rfmax = 596000, .val = 0x35 },
665 { .rfmax = 598000, .val = 0x36 },
666 { .rfmax = 603000, .val = 0x37 },
667 { .rfmax = 604000, .val = 0x38 },
668 { .rfmax = 606000, .val = 0x39 },
669 { .rfmax = 612000, .val = 0x3a },
670 { .rfmax = 615000, .val = 0x3b },
671 { .rfmax = 617000, .val = 0x3c },
672 { .rfmax = 621000, .val = 0x3d },
673 { .rfmax = 622000, .val = 0x3e },
674 { .rfmax = 625000, .val = 0x3f },
675 { .rfmax = 632000, .val = 0x40 },
676 { .rfmax = 633000, .val = 0x41 },
677 { .rfmax = 634000, .val = 0x42 },
678 { .rfmax = 642000, .val = 0x43 },
679 { .rfmax = 643000, .val = 0x44 },
680 { .rfmax = 647000, .val = 0x45 },
681 { .rfmax = 650000, .val = 0x46 },
682 { .rfmax = 652000, .val = 0x47 },
683 { .rfmax = 657000, .val = 0x48 },
684 { .rfmax = 661000, .val = 0x49 },
685 { .rfmax = 662000, .val = 0x4a },
686 { .rfmax = 665000, .val = 0x4b },
687 { .rfmax = 667000, .val = 0x4c },
688 { .rfmax = 670000, .val = 0x4d },
689 { .rfmax = 673000, .val = 0x4e },
690 { .rfmax = 676000, .val = 0x4f },
691 { .rfmax = 677000, .val = 0x50 },
692 { .rfmax = 681000, .val = 0x51 },
693 { .rfmax = 683000, .val = 0x52 },
694 { .rfmax = 686000, .val = 0x53 },
695 { .rfmax = 688000, .val = 0x54 },
696 { .rfmax = 689000, .val = 0x55 },
697 { .rfmax = 691000, .val = 0x56 },
698 { .rfmax = 695000, .val = 0x57 },
699 { .rfmax = 698000, .val = 0x58 },
700 { .rfmax = 703000, .val = 0x59 },
701 { .rfmax = 704000, .val = 0x5a },
702 { .rfmax = 705000, .val = 0x5b },
703 { .rfmax = 707000, .val = 0x5c },
704 { .rfmax = 710000, .val = 0x5d },
705 { .rfmax = 712000, .val = 0x5e },
706 { .rfmax = 717000, .val = 0x5f },
707 { .rfmax = 718000, .val = 0x60 },
708 { .rfmax = 721000, .val = 0x61 },
709 { .rfmax = 722000, .val = 0x62 },
710 { .rfmax = 723000, .val = 0x63 },
711 { .rfmax = 725000, .val = 0x64 },
712 { .rfmax = 727000, .val = 0x65 },
713 { .rfmax = 730000, .val = 0x66 },
714 { .rfmax = 732000, .val = 0x67 },
715 { .rfmax = 735000, .val = 0x68 },
716 { .rfmax = 740000, .val = 0x69 },
717 { .rfmax = 741000, .val = 0x6a },
718 { .rfmax = 742000, .val = 0x6b },
719 { .rfmax = 743000, .val = 0x6c },
720 { .rfmax = 745000, .val = 0x6d },
721 { .rfmax = 747000, .val = 0x6e },
722 { .rfmax = 748000, .val = 0x6f },
723 { .rfmax = 750000, .val = 0x70 },
724 { .rfmax = 752000, .val = 0x71 },
725 { .rfmax = 754000, .val = 0x72 },
726 { .rfmax = 757000, .val = 0x73 },
727 { .rfmax = 758000, .val = 0x74 },
728 { .rfmax = 760000, .val = 0x75 },
729 { .rfmax = 763000, .val = 0x76 },
730 { .rfmax = 764000, .val = 0x77 },
731 { .rfmax = 766000, .val = 0x78 },
732 { .rfmax = 767000, .val = 0x79 },
733 { .rfmax = 768000, .val = 0x7a },
734 { .rfmax = 773000, .val = 0x7b },
735 { .rfmax = 774000, .val = 0x7c },
736 { .rfmax = 776000, .val = 0x7d },
737 { .rfmax = 777000, .val = 0x7e },
738 { .rfmax = 778000, .val = 0x7f },
739 { .rfmax = 779000, .val = 0x80 },
740 { .rfmax = 781000, .val = 0x81 },
741 { .rfmax = 783000, .val = 0x82 },
742 { .rfmax = 784000, .val = 0x83 },
743 { .rfmax = 785000, .val = 0x84 },
744 { .rfmax = 786000, .val = 0x85 },
745 { .rfmax = 793000, .val = 0x86 },
746 { .rfmax = 794000, .val = 0x87 },
747 { .rfmax = 795000, .val = 0x88 },
748 { .rfmax = 797000, .val = 0x89 },
749 { .rfmax = 799000, .val = 0x8a },
750 { .rfmax = 801000, .val = 0x8b },
751 { .rfmax = 802000, .val = 0x8c },
752 { .rfmax = 803000, .val = 0x8d },
753 { .rfmax = 804000, .val = 0x8e },
754 { .rfmax = 810000, .val = 0x90 },
755 { .rfmax = 811000, .val = 0x91 },
756 { .rfmax = 812000, .val = 0x92 },
757 { .rfmax = 814000, .val = 0x93 },
758 { .rfmax = 816000, .val = 0x94 },
759 { .rfmax = 817000, .val = 0x96 },
760 { .rfmax = 818000, .val = 0x97 },
761 { .rfmax = 820000, .val = 0x98 },
762 { .rfmax = 821000, .val = 0x99 },
763 { .rfmax = 822000, .val = 0x9a },
764 { .rfmax = 828000, .val = 0x9b },
765 { .rfmax = 829000, .val = 0x9d },
766 { .rfmax = 830000, .val = 0x9f },
767 { .rfmax = 831000, .val = 0xa0 },
768 { .rfmax = 833000, .val = 0xa1 },
769 { .rfmax = 835000, .val = 0xa2 },
770 { .rfmax = 836000, .val = 0xa3 },
771 { .rfmax = 837000, .val = 0xa4 },
772 { .rfmax = 838000, .val = 0xa6 },
773 { .rfmax = 840000, .val = 0xa8 },
774 { .rfmax = 842000, .val = 0xa9 },
775 { .rfmax = 845000, .val = 0xaa },
776 { .rfmax = 846000, .val = 0xab },
777 { .rfmax = 847000, .val = 0xad },
778 { .rfmax = 848000, .val = 0xae },
779 { .rfmax = 852000, .val = 0xaf },
780 { .rfmax = 853000, .val = 0xb0 },
781 { .rfmax = 858000, .val = 0xb1 },
782 { .rfmax = 860000, .val = 0xb2 },
783 { .rfmax = 861000, .val = 0xb3 },
784 { .rfmax = 862000, .val = 0xb4 },
785 { .rfmax = 863000, .val = 0xb6 },
786 { .rfmax = 864000, .val = 0xb8 },
787 { .rfmax = 865000, .val = 0xb9 },
788 { .rfmax = 0, .val = 0x00 }, /* end */
792 { .rfmax = 30000, .val = 4 },
793 { .rfmax = 200000, .val = 5 },
794 { .rfmax = 600000, .val = 6 },
795 { .rfmax = 865000, .val = 7 },
796 { .rfmax = 0, .val = 0 }, /* end */
800 { .rfmax = 47900, .val = 0x00 },
801 { .rfmax = 55000, .val = 0x00 },
802 { .rfmax = 61100, .val = 0x0a },
803 { .rfmax = 64000, .val = 0x0a },
804 { .rfmax = 82000, .val = 0x14 },
805 { .rfmax = 84000, .val = 0x19 },
806 { .rfmax = 119000, .val = 0x1c },
807 { .rfmax = 124000, .val = 0x20 },
808 { .rfmax = 129000, .val = 0x2a },
809 { .rfmax = 134000, .val = 0x32 },
810 { .rfmax = 139000, .val = 0x39 },
811 { .rfmax = 144000, .val = 0x3e },
812 { .rfmax = 149000, .val = 0x3f },
813 { .rfmax = 152600, .val = 0x40 },
814 { .rfmax = 154000, .val = 0x40 },
815 { .rfmax = 164700, .val = 0x41 },
816 { .rfmax = 203500, .val = 0x32 },
817 { .rfmax = 353000, .val = 0x19 },
818 { .rfmax = 356000, .val = 0x1a },
819 { .rfmax = 359000, .val = 0x1b },
820 { .rfmax = 363000, .val = 0x1c },
821 { .rfmax = 366000, .val = 0x1d },
822 { .rfmax = 369000, .val = 0x1e },
823 { .rfmax = 373000, .val = 0x1f },
824 { .rfmax = 376000, .val = 0x20 },
825 { .rfmax = 379000, .val = 0x21 },
826 { .rfmax = 383000, .val = 0x22 },
827 { .rfmax = 386000, .val = 0x23 },
828 { .rfmax = 389000, .val = 0x24 },
829 { .rfmax = 393000, .val = 0x25 },
830 { .rfmax = 396000, .val = 0x26 },
831 { .rfmax = 399000, .val = 0x27 },
832 { .rfmax = 402000, .val = 0x28 },
833 { .rfmax = 404000, .val = 0x29 },
834 { .rfmax = 407000, .val = 0x2a },
835 { .rfmax = 409000, .val = 0x2b },
836 { .rfmax = 412000, .val = 0x2c },
837 { .rfmax = 414000, .val = 0x2d },
838 { .rfmax = 417000, .val = 0x2e },
839 { .rfmax = 419000, .val = 0x2f },
840 { .rfmax = 422000, .val = 0x30 },
841 { .rfmax = 424000, .val = 0x31 },
842 { .rfmax = 427000, .val = 0x32 },
843 { .rfmax = 429000, .val = 0x33 },
844 { .rfmax = 432000, .val = 0x34 },
845 { .rfmax = 434000, .val = 0x35 },
846 { .rfmax = 437000, .val = 0x36 },
847 { .rfmax = 439000, .val = 0x37 },
848 { .rfmax = 442000, .val = 0x38 },
849 { .rfmax = 444000, .val = 0x39 },
850 { .rfmax = 447000, .val = 0x3a },
851 { .rfmax = 449000, .val = 0x3b },
852 { .rfmax = 457800, .val = 0x3c },
853 { .rfmax = 465000, .val = 0x0f },
854 { .rfmax = 477000, .val = 0x12 },
855 { .rfmax = 483000, .val = 0x14 },
856 { .rfmax = 502000, .val = 0x19 },
857 { .rfmax = 508000, .val = 0x1b },
858 { .rfmax = 519000, .val = 0x1c },
859 { .rfmax = 522000, .val = 0x1d },
860 { .rfmax = 524000, .val = 0x1e },
861 { .rfmax = 534000, .val = 0x1f },
862 { .rfmax = 549000, .val = 0x20 },
863 { .rfmax = 554000, .val = 0x22 },
864 { .rfmax = 584000, .val = 0x24 },
865 { .rfmax = 589000, .val = 0x26 },
866 { .rfmax = 658000, .val = 0x27 },
867 { .rfmax = 664000, .val = 0x2c },
868 { .rfmax = 669000, .val = 0x2d },
869 { .rfmax = 699000, .val = 0x2e },
870 { .rfmax = 704000, .val = 0x30 },
871 { .rfmax = 709000, .val = 0x31 },
872 { .rfmax = 714000, .val = 0x32 },
873 { .rfmax = 724000, .val = 0x33 },
874 { .rfmax = 729000, .val = 0x36 },
875 { .rfmax = 739000, .val = 0x38 },
876 { .rfmax = 744000, .val = 0x39 },
877 { .rfmax = 749000, .val = 0x3b },
878 { .rfmax = 754000, .val = 0x3c },
879 { .rfmax = 759000, .val = 0x3d },
880 { .rfmax = 764000, .val = 0x3e },
881 { .rfmax = 769000, .val = 0x3f },
882 { .rfmax = 774000, .val = 0x40 },
883 { .rfmax = 779000, .val = 0x41 },
884 { .rfmax = 784000, .val = 0x43 },
885 { .rfmax = 789000, .val = 0x46 },
886 { .rfmax = 794000, .val = 0x48 },
887 { .rfmax = 799000, .val = 0x4b },
888 { .rfmax = 804000, .val = 0x4f },
889 { .rfmax = 809000, .val = 0x54 },
890 { .rfmax = 814000, .val = 0x59 },
891 { .rfmax = 819000, .val = 0x5d },
892 { .rfmax = 824000, .val = 0x61 },
893 { .rfmax = 829000, .val = 0x68 },
894 { .rfmax = 834000, .val = 0x6e },
895 { .rfmax = 839000, .val = 0x75 },
896 { .rfmax = 844000, .val = 0x7e },
897 { .rfmax = 849000, .val = 0x82 },
898 { .rfmax = 854000, .val = 0x84 },
899 { .rfmax = 859000, .val = 0x8f },
900 { .rfmax = 865000, .val = 0x9a },
901 { .rfmax = 0, .val = 0x00 }, /* end */
936 int val, i = 0; tda18271_lookup_thermometer() local
945 val = tda18271_thermometer[i].r1; tda18271_lookup_thermometer()
947 val = tda18271_thermometer[i].r0; tda18271_lookup_thermometer()
949 tda_map("(%d) tm = %d\n", i, val); tda18271_lookup_thermometer()
951 return val; tda18271_lookup_thermometer()
1120 u32 *freq, u8 *val) tda18271_lookup_map()
1180 *val = map[i].val; tda18271_lookup_map()
1182 tda_map("(%d) %s: 0x%02x\n", i, map_name, *val); tda18271_lookup_map()
1118 tda18271_lookup_map(struct dvb_frontend *fe, enum tda18271_map_type map_type, u32 *freq, u8 *val) tda18271_lookup_map() argument
H A Dmc44s803.c37 static int mc44s803_writereg(struct mc44s803_priv *priv, u32 val) mc44s803_writereg() argument
44 buf[0] = (val & 0xff0000) >> 16; mc44s803_writereg()
45 buf[1] = (val & 0xff00) >> 8; mc44s803_writereg()
46 buf[2] = (val & 0xff); mc44s803_writereg()
56 static int mc44s803_readreg(struct mc44s803_priv *priv, u8 reg, u32 *val) mc44s803_readreg() argument
78 *val = (buf[0] << 16) | (buf[1] << 8) | buf[2]; mc44s803_readreg()
96 u32 val; mc44s803_init() local
103 val = MC44S803_REG_SM(MC44S803_REG_RESET, MC44S803_ADDR) | mc44s803_init()
106 err = mc44s803_writereg(priv, val); mc44s803_init()
110 val = MC44S803_REG_SM(MC44S803_REG_RESET, MC44S803_ADDR); mc44s803_init()
112 err = mc44s803_writereg(priv, val); mc44s803_init()
118 val = MC44S803_REG_SM(MC44S803_REG_REFOSC, MC44S803_ADDR) | mc44s803_init()
122 err = mc44s803_writereg(priv, val); mc44s803_init()
126 val = MC44S803_REG_SM(MC44S803_REG_POWER, MC44S803_ADDR) | mc44s803_init()
129 err = mc44s803_writereg(priv, val); mc44s803_init()
135 val = MC44S803_REG_SM(MC44S803_REG_REFOSC, MC44S803_ADDR) | mc44s803_init()
139 err = mc44s803_writereg(priv, val); mc44s803_init()
147 val = MC44S803_REG_SM(MC44S803_REG_MIXER, MC44S803_ADDR) | mc44s803_init()
151 err = mc44s803_writereg(priv, val); mc44s803_init()
157 val = MC44S803_REG_SM(MC44S803_REG_CIRCADJ, MC44S803_ADDR) | mc44s803_init()
167 err = mc44s803_writereg(priv, val); mc44s803_init()
171 val = MC44S803_REG_SM(MC44S803_REG_CIRCADJ, MC44S803_ADDR) | mc44s803_init()
179 err = mc44s803_writereg(priv, val); mc44s803_init()
185 val = MC44S803_REG_SM(MC44S803_REG_DIGTUNE, MC44S803_ADDR) | mc44s803_init()
188 err = mc44s803_writereg(priv, val); mc44s803_init()
194 val = MC44S803_REG_SM(MC44S803_REG_LNAAGC, MC44S803_ADDR) | mc44s803_init()
201 err = mc44s803_writereg(priv, val); mc44s803_init()
221 u32 r1, r2, n1, n2, lo1, lo2, freq, val; mc44s803_set_params() local
240 val = MC44S803_REG_SM(MC44S803_REG_REFDIV, MC44S803_ADDR) | mc44s803_set_params()
245 err = mc44s803_writereg(priv, val); mc44s803_set_params()
249 val = MC44S803_REG_SM(MC44S803_REG_LO1, MC44S803_ADDR) | mc44s803_set_params()
252 err = mc44s803_writereg(priv, val); mc44s803_set_params()
256 val = MC44S803_REG_SM(MC44S803_REG_LO2, MC44S803_ADDR) | mc44s803_set_params()
259 err = mc44s803_writereg(priv, val); mc44s803_set_params()
263 val = MC44S803_REG_SM(MC44S803_REG_DIGTUNE, MC44S803_ADDR) | mc44s803_set_params()
268 err = mc44s803_writereg(priv, val); mc44s803_set_params()
272 val = MC44S803_REG_SM(MC44S803_REG_DIGTUNE, MC44S803_ADDR) | mc44s803_set_params()
277 err = mc44s803_writereg(priv, val); mc44s803_set_params()
/linux-4.1.27/arch/blackfin/mach-bf537/include/mach/
H A DcdefBF537.h16 #define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE,val)
18 #define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO,val)
20 #define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI,val)
22 #define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO,val)
24 #define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI,val)
26 #define bfin_write_EMAC_STAADD(val) bfin_write32(EMAC_STAADD,val)
28 #define bfin_write_EMAC_STADAT(val) bfin_write32(EMAC_STADAT,val)
30 #define bfin_write_EMAC_FLC(val) bfin_write32(EMAC_FLC,val)
32 #define bfin_write_EMAC_VLAN1(val) bfin_write32(EMAC_VLAN1,val)
34 #define bfin_write_EMAC_VLAN2(val) bfin_write32(EMAC_VLAN2,val)
36 #define bfin_write_EMAC_WKUP_CTL(val) bfin_write32(EMAC_WKUP_CTL,val)
38 #define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0,val)
40 #define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1,val)
42 #define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2,val)
44 #define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3,val)
46 #define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD,val)
48 #define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF,val)
50 #define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0,val)
52 #define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1,val)
55 #define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL,val)
57 #define bfin_write_EMAC_SYSTAT(val) bfin_write32(EMAC_SYSTAT,val)
59 #define bfin_write_EMAC_RX_STAT(val) bfin_write32(EMAC_RX_STAT,val)
61 #define bfin_write_EMAC_RX_STKY(val) bfin_write32(EMAC_RX_STKY,val)
63 #define bfin_write_EMAC_RX_IRQE(val) bfin_write32(EMAC_RX_IRQE,val)
65 #define bfin_write_EMAC_TX_STAT(val) bfin_write32(EMAC_TX_STAT,val)
67 #define bfin_write_EMAC_TX_STKY(val) bfin_write32(EMAC_TX_STKY,val)
69 #define bfin_write_EMAC_TX_IRQE(val) bfin_write32(EMAC_TX_IRQE,val)
72 #define bfin_write_EMAC_MMC_CTL(val) bfin_write32(EMAC_MMC_CTL,val)
74 #define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS,val)
76 #define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE,val)
78 #define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS,val)
80 #define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE,val)
83 #define bfin_write_EMAC_RXC_OK(val) bfin_write32(EMAC_RXC_OK,val)
85 #define bfin_write_EMAC_RXC_FCS(val) bfin_write32(EMAC_RXC_FCS,val)
87 #define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN,val)
89 #define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET,val)
91 #define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF,val)
93 #define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST,val)
95 #define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI,val)
97 #define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD,val)
99 #define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI,val)
101 #define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO,val)
103 #define bfin_write_EMAC_RXC_LONG(val) bfin_write32(EMAC_RXC_LONG,val)
105 #define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL,val)
107 #define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE,val)
109 #define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE,val)
111 #define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM,val)
113 #define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT,val)
115 #define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED,val)
117 #define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT,val)
119 #define bfin_write_EMAC_RXC_EQ64(val) bfin_write32(EMAC_RXC_EQ64,val)
121 #define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128,val)
123 #define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256,val)
125 #define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512,val)
127 #define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024,val)
129 #define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024,val)
132 #define bfin_write_EMAC_TXC_OK(val) bfin_write32(EMAC_TXC_OK,val)
134 #define bfin_write_EMAC_TXC_1COL(val) bfin_write32(EMAC_TXC_1COL,val)
136 #define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL,val)
138 #define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET,val)
140 #define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER,val)
142 #define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL,val)
144 #define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL,val)
146 #define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND,val)
148 #define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR,val)
150 #define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST,val)
152 #define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI,val)
154 #define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD,val)
156 #define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR,val)
158 #define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL,val)
160 #define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM,val)
162 #define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT,val)
164 #define bfin_write_EMAC_TXC_EQ64(val) bfin_write32(EMAC_TXC_EQ64,val)
166 #define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128,val)
168 #define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256,val)
170 #define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512,val)
172 #define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024,val)
174 #define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024,val)
176 #define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT,val)
H A DcdefBF534.h13 #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val)
16 #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val)
18 #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val)
23 #define bfin_write_SWRST(val) bfin_write16(SWRST,val)
25 #define bfin_write_SYSCR(val) bfin_write16(SYSCR,val)
27 #define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT,val)
29 #define bfin_write_SIC_IMASK(val) bfin_write32(SIC_IMASK,val)
31 #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val)
33 #define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1,val)
35 #define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2,val)
37 #define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3,val)
39 #define bfin_write_SIC_ISR(val) bfin_write32(SIC_ISR,val)
41 #define bfin_write_SIC_IWR(val) bfin_write32(SIC_IWR,val)
45 #define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL,val)
47 #define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT,val)
49 #define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT,val)
53 #define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT,val)
55 #define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL,val)
57 #define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT,val)
59 #define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT,val)
61 #define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM,val)
63 #define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST,val)
65 #define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN,val)
69 #define bfin_write_UART0_THR(val) bfin_write16(UART0_THR,val)
71 #define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR,val)
73 #define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL,val)
75 #define bfin_write_UART0_IER(val) bfin_write16(UART0_IER,val)
77 #define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH,val)
79 #define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR,val)
81 #define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR,val)
83 #define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR,val)
85 #define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR,val)
87 #define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR,val)
89 #define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR,val)
91 #define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL,val)
95 #define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL,val)
97 #define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG,val)
99 #define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT,val)
101 #define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR,val)
103 #define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR,val)
105 #define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD,val)
107 #define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW,val)
111 #define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG,val)
113 #define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER,val)
115 #define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD,val)
117 #define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH,val)
120 #define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG,val)
122 #define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER,val)
124 #define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD,val)
126 #define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH,val)
129 #define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG,val)
131 #define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER,val)
133 #define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD,val)
135 #define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH,val)
138 #define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG,val)
140 #define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER,val)
142 #define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD,val)
144 #define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH,val)
147 #define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG,val)
149 #define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER,val)
151 #define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD,val)
153 #define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH,val)
156 #define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG,val)
158 #define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER,val)
160 #define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD,val)
162 #define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH,val)
165 #define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG,val)
167 #define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER,val)
169 #define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD,val)
171 #define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH,val)
174 #define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG,val)
176 #define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER,val)
178 #define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD,val)
180 #define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH,val)
183 #define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE,val)
185 #define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE,val)
187 #define bfin_write_TIMER_STATUS(val) bfin_write32(TIMER_STATUS,val)
191 #define bfin_write_PORTFIO(val) bfin_write16(PORTFIO,val)
193 #define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR,val)
195 #define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET,val)
197 #define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE,val)
199 #define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA,val)
201 #define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR,val)
203 #define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET,val)
205 #define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE,val)
207 #define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB,val)
209 #define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR,val)
211 #define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET,val)
213 #define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE,val)
215 #define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR,val)
217 #define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR,val)
219 #define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE,val)
221 #define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH,val)
223 #define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN,val)
227 #define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1,val)
229 #define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2,val)
231 #define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV,val)
233 #define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV,val)
235 #define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX,val)
237 #define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX,val)
239 #define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX,val)
241 #define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX,val)
243 #define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX,val)
245 #define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX,val)
247 #define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1,val)
249 #define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2,val)
251 #define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV,val)
253 #define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV,val)
255 #define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT,val)
257 #define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL,val)
259 #define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1,val)
261 #define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2,val)
263 #define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0,val)
265 #define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1,val)
267 #define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2,val)
269 #define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3,val)
271 #define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0,val)
273 #define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1,val)
275 #define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2,val)
277 #define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3,val)
281 #define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1,val)
283 #define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2,val)
285 #define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV,val)
287 #define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV,val)
289 #define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX,val)
291 #define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX,val)
293 #define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX,val)
295 #define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX,val)
297 #define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX,val)
299 #define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX,val)
301 #define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1,val)
303 #define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2,val)
305 #define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV,val)
307 #define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV,val)
309 #define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT,val)
311 #define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL,val)
313 #define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1,val)
315 #define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2,val)
317 #define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0,val)
319 #define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1,val)
321 #define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2,val)
323 #define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3,val)
325 #define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0,val)
327 #define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1,val)
329 #define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2,val)
331 #define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3,val)
335 #define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL,val)
337 #define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0,val)
339 #define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1,val)
341 #define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL,val)
343 #define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL,val)
345 #define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC,val)
347 #define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT,val)
351 #define bfin_write_DMAC_TC_PER(val) bfin_write16(DMAC_TC_PER,val)
353 #define bfin_write_DMAC_TC_CNT(val) bfin_write16(DMAC_TC_CNT,val)
357 #define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG,val)
359 #define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR,val)
361 #define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR,val)
363 #define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT,val)
365 #define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT,val)
367 #define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY,val)
369 #define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY,val)
371 #define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR,val)
373 #define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR,val)
375 #define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT,val)
377 #define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT,val)
379 #define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS,val)
381 #define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP,val)
384 #define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG,val)
386 #define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR,val)
388 #define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR,val)
390 #define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT,val)
392 #define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT,val)
394 #define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY,val)
396 #define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY,val)
398 #define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR,val)
400 #define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR,val)
402 #define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT,val)
404 #define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT,val)
406 #define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS,val)
408 #define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP,val)
411 #define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG,val)
413 #define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR,val)
415 #define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR,val)
417 #define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT,val)
419 #define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT,val)
421 #define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY,val)
423 #define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY,val)
425 #define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR,val)
427 #define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR,val)
429 #define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT,val)
431 #define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT,val)
433 #define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS,val)
435 #define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP,val)
438 #define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG,val)
440 #define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR,val)
442 #define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR,val)
444 #define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT,val)
446 #define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT,val)
448 #define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY,val)
450 #define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY,val)
452 #define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR,val)
454 #define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR,val)
456 #define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT,val)
458 #define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT,val)
460 #define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS,val)
462 #define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP,val)
465 #define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG,val)
467 #define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR,val)
469 #define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR,val)
471 #define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT,val)
473 #define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT,val)
475 #define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY,val)
477 #define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY,val)
479 #define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR,val)
481 #define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR,val)
483 #define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT,val)
485 #define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT,val)
487 #define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS,val)
489 #define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP,val)
492 #define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG,val)
494 #define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR,val)
496 #define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR,val)
498 #define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT,val)
500 #define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT,val)
502 #define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY,val)
504 #define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY,val)
506 #define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR,val)
508 #define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR,val)
510 #define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT,val)
512 #define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT,val)
514 #define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS,val)
516 #define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP,val)
519 #define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG,val)
521 #define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR,val)
523 #define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR,val)
525 #define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT,val)
527 #define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT,val)
529 #define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY,val)
531 #define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY,val)
533 #define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR,val)
535 #define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR,val)
537 #define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT,val)
539 #define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT,val)
541 #define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS,val)
543 #define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP,val)
546 #define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG,val)
548 #define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR,val)
550 #define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR,val)
552 #define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT,val)
554 #define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT,val)
556 #define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY,val)
558 #define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY,val)
560 #define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR,val)
562 #define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR,val)
564 #define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT,val)
566 #define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT,val)
568 #define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS,val)
570 #define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP,val)
573 #define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG,val)
575 #define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR,val)
577 #define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR,val)
579 #define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT,val)
581 #define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT,val)
583 #define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY,val)
585 #define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY,val)
587 #define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR,val)
589 #define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR,val)
591 #define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT,val)
593 #define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT,val)
595 #define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS,val)
597 #define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP,val)
600 #define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG,val)
602 #define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR,val)
604 #define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR,val)
606 #define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT,val)
608 #define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT,val)
610 #define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY,val)
612 #define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY,val)
614 #define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR,val)
616 #define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR,val)
618 #define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT,val)
620 #define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT,val)
622 #define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS,val)
624 #define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP,val)
627 #define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG,val)
629 #define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR,val)
631 #define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR,val)
633 #define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT,val)
635 #define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT,val)
637 #define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY,val)
639 #define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY,val)
641 #define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR,val)
643 #define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR,val)
645 #define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT,val)
647 #define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT,val)
649 #define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS,val)
651 #define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP,val)
654 #define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG,val)
656 #define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR,val)
658 #define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR,val)
660 #define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT,val)
662 #define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT,val)
664 #define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY,val)
666 #define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY,val)
668 #define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR,val)
670 #define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR,val)
672 #define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT,val)
674 #define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT,val)
676 #define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS,val)
678 #define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP,val)
681 #define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG,val)
683 #define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR,val)
685 #define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR,val)
687 #define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT,val)
689 #define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT,val)
691 #define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY,val)
693 #define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY,val)
695 #define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR,val)
697 #define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR,val)
699 #define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT,val)
701 #define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT,val)
703 #define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS,val)
705 #define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP,val)
708 #define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG,val)
710 #define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR,val)
712 #define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR,val)
714 #define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT,val)
716 #define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT,val)
718 #define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY,val)
720 #define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY,val)
722 #define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR,val)
724 #define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR,val)
726 #define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT,val)
728 #define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT,val)
730 #define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS,val)
732 #define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP,val)
735 #define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG,val)
737 #define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR,val)
739 #define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR,val)
741 #define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT,val)
743 #define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT,val)
745 #define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY,val)
747 #define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY,val)
749 #define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR,val)
751 #define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR,val)
753 #define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT,val)
755 #define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT,val)
757 #define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS,val)
759 #define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP,val)
762 #define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG,val)
764 #define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR,val)
766 #define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR,val)
768 #define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT,val)
770 #define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT,val)
772 #define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY,val)
774 #define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY,val)
776 #define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR,val)
778 #define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR,val)
780 #define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT,val)
782 #define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT,val)
784 #define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS,val)
786 #define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP,val)
790 #define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL,val)
792 #define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS,val)
795 #define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY,val)
797 #define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT,val)
799 #define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME,val)
805 #define bfin_write_PORTGIO(val) bfin_write16(PORTGIO,val)
807 #define bfin_write_PORTGIO_CLEAR(val) bfin_write16(PORTGIO_CLEAR,val)
809 #define bfin_write_PORTGIO_SET(val) bfin_write16(PORTGIO_SET,val)
811 #define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE,val)
813 #define bfin_write_PORTGIO_MASKA(val) bfin_write16(PORTGIO_MASKA,val)
815 #define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR,val)
817 #define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET,val)
819 #define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE,val)
821 #define bfin_write_PORTGIO_MASKB(val) bfin_write16(PORTGIO_MASKB,val)
823 #define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR,val)
825 #define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET,val)
827 #define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE,val)
829 #define bfin_write_PORTGIO_DIR(val) bfin_write16(PORTGIO_DIR,val)
831 #define bfin_write_PORTGIO_POLAR(val) bfin_write16(PORTGIO_POLAR,val)
833 #define bfin_write_PORTGIO_EDGE(val) bfin_write16(PORTGIO_EDGE,val)
835 #define bfin_write_PORTGIO_BOTH(val) bfin_write16(PORTGIO_BOTH,val)
837 #define bfin_write_PORTGIO_INEN(val) bfin_write16(PORTGIO_INEN,val)
841 #define bfin_write_PORTHIO(val) bfin_write16(PORTHIO,val)
843 #define bfin_write_PORTHIO_CLEAR(val) bfin_write16(PORTHIO_CLEAR,val)
845 #define bfin_write_PORTHIO_SET(val) bfin_write16(PORTHIO_SET,val)
847 #define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE,val)
849 #define bfin_write_PORTHIO_MASKA(val) bfin_write16(PORTHIO_MASKA,val)
851 #define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR,val)
853 #define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET,val)
855 #define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE,val)
857 #define bfin_write_PORTHIO_MASKB(val) bfin_write16(PORTHIO_MASKB,val)
859 #define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR,val)
861 #define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET,val)
863 #define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE,val)
865 #define bfin_write_PORTHIO_DIR(val) bfin_write16(PORTHIO_DIR,val)
867 #define bfin_write_PORTHIO_POLAR(val) bfin_write16(PORTHIO_POLAR,val)
869 #define bfin_write_PORTHIO_EDGE(val) bfin_write16(PORTHIO_EDGE,val)
871 #define bfin_write_PORTHIO_BOTH(val) bfin_write16(PORTHIO_BOTH,val)
873 #define bfin_write_PORTHIO_INEN(val) bfin_write16(PORTHIO_INEN,val)
877 #define bfin_write_UART1_THR(val) bfin_write16(UART1_THR,val)
879 #define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR,val)
881 #define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL,val)
883 #define bfin_write_UART1_IER(val) bfin_write16(UART1_IER,val)
885 #define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH,val)
887 #define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR,val)
889 #define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR,val)
891 #define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR,val)
893 #define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR,val)
895 #define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR,val)
897 #define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR,val)
899 #define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL,val)
904 #define bfin_write_CAN_MC1(val) bfin_write16(CAN_MC1,val)
906 #define bfin_write_CAN_MD1(val) bfin_write16(CAN_MD1,val)
908 #define bfin_write_CAN_TRS1(val) bfin_write16(CAN_TRS1,val)
910 #define bfin_write_CAN_TRR1(val) bfin_write16(CAN_TRR1,val)
912 #define bfin_write_CAN_TA1(val) bfin_write16(CAN_TA1,val)
914 #define bfin_write_CAN_AA1(val) bfin_write16(CAN_AA1,val)
916 #define bfin_write_CAN_RMP1(val) bfin_write16(CAN_RMP1,val)
918 #define bfin_write_CAN_RML1(val) bfin_write16(CAN_RML1,val)
920 #define bfin_write_CAN_MBTIF1(val) bfin_write16(CAN_MBTIF1,val)
922 #define bfin_write_CAN_MBRIF1(val) bfin_write16(CAN_MBRIF1,val)
924 #define bfin_write_CAN_MBIM1(val) bfin_write16(CAN_MBIM1,val)
926 #define bfin_write_CAN_RFH1(val) bfin_write16(CAN_RFH1,val)
928 #define bfin_write_CAN_OPSS1(val) bfin_write16(CAN_OPSS1,val)
932 #define bfin_write_CAN_MC2(val) bfin_write16(CAN_MC2,val)
934 #define bfin_write_CAN_MD2(val) bfin_write16(CAN_MD2,val)
936 #define bfin_write_CAN_TRS2(val) bfin_write16(CAN_TRS2,val)
938 #define bfin_write_CAN_TRR2(val) bfin_write16(CAN_TRR2,val)
940 #define bfin_write_CAN_TA2(val) bfin_write16(CAN_TA2,val)
942 #define bfin_write_CAN_AA2(val) bfin_write16(CAN_AA2,val)
944 #define bfin_write_CAN_RMP2(val) bfin_write16(CAN_RMP2,val)
946 #define bfin_write_CAN_RML2(val) bfin_write16(CAN_RML2,val)
948 #define bfin_write_CAN_MBTIF2(val) bfin_write16(CAN_MBTIF2,val)
950 #define bfin_write_CAN_MBRIF2(val) bfin_write16(CAN_MBRIF2,val)
952 #define bfin_write_CAN_MBIM2(val) bfin_write16(CAN_MBIM2,val)
954 #define bfin_write_CAN_RFH2(val) bfin_write16(CAN_RFH2,val)
956 #define bfin_write_CAN_OPSS2(val) bfin_write16(CAN_OPSS2,val)
959 #define bfin_write_CAN_CLOCK(val) bfin_write16(CAN_CLOCK,val)
961 #define bfin_write_CAN_TIMING(val) bfin_write16(CAN_TIMING,val)
963 #define bfin_write_CAN_DEBUG(val) bfin_write16(CAN_DEBUG,val)
965 #define bfin_write_CAN_STATUS(val) bfin_write16(CAN_STATUS,val)
967 #define bfin_write_CAN_CEC(val) bfin_write16(CAN_CEC,val)
969 #define bfin_write_CAN_GIS(val) bfin_write16(CAN_GIS,val)
971 #define bfin_write_CAN_GIM(val) bfin_write16(CAN_GIM,val)
973 #define bfin_write_CAN_GIF(val) bfin_write16(CAN_GIF,val)
975 #define bfin_write_CAN_CONTROL(val) bfin_write16(CAN_CONTROL,val)
977 #define bfin_write_CAN_INTR(val) bfin_write16(CAN_INTR,val)
979 #define bfin_write_CAN_SFCMVER(val) bfin_write16(CAN_SFCMVER,val)
981 #define bfin_write_CAN_MBTD(val) bfin_write16(CAN_MBTD,val)
983 #define bfin_write_CAN_EWR(val) bfin_write16(CAN_EWR,val)
985 #define bfin_write_CAN_ESR(val) bfin_write16(CAN_ESR,val)
987 #define bfin_write_CAN_UCREG(val) bfin_write16(CAN_UCREG,val)
989 #define bfin_write_CAN_UCCNT(val) bfin_write16(CAN_UCCNT,val)
991 #define bfin_write_CAN_UCRC(val) bfin_write16(CAN_UCRC,val)
993 #define bfin_write_CAN_UCCNF(val) bfin_write16(CAN_UCCNF,val)
997 #define bfin_write_CAN_AM00L(val) bfin_write16(CAN_AM00L,val)
999 #define bfin_write_CAN_AM00H(val) bfin_write16(CAN_AM00H,val)
1001 #define bfin_write_CAN_AM01L(val) bfin_write16(CAN_AM01L,val)
1003 #define bfin_write_CAN_AM01H(val) bfin_write16(CAN_AM01H,val)
1005 #define bfin_write_CAN_AM02L(val) bfin_write16(CAN_AM02L,val)
1007 #define bfin_write_CAN_AM02H(val) bfin_write16(CAN_AM02H,val)
1009 #define bfin_write_CAN_AM03L(val) bfin_write16(CAN_AM03L,val)
1011 #define bfin_write_CAN_AM03H(val) bfin_write16(CAN_AM03H,val)
1013 #define bfin_write_CAN_AM04L(val) bfin_write16(CAN_AM04L,val)
1015 #define bfin_write_CAN_AM04H(val) bfin_write16(CAN_AM04H,val)
1017 #define bfin_write_CAN_AM05L(val) bfin_write16(CAN_AM05L,val)
1019 #define bfin_write_CAN_AM05H(val) bfin_write16(CAN_AM05H,val)
1021 #define bfin_write_CAN_AM06L(val) bfin_write16(CAN_AM06L,val)
1023 #define bfin_write_CAN_AM06H(val) bfin_write16(CAN_AM06H,val)
1025 #define bfin_write_CAN_AM07L(val) bfin_write16(CAN_AM07L,val)
1027 #define bfin_write_CAN_AM07H(val) bfin_write16(CAN_AM07H,val)
1029 #define bfin_write_CAN_AM08L(val) bfin_write16(CAN_AM08L,val)
1031 #define bfin_write_CAN_AM08H(val) bfin_write16(CAN_AM08H,val)
1033 #define bfin_write_CAN_AM09L(val) bfin_write16(CAN_AM09L,val)
1035 #define bfin_write_CAN_AM09H(val) bfin_write16(CAN_AM09H,val)
1037 #define bfin_write_CAN_AM10L(val) bfin_write16(CAN_AM10L,val)
1039 #define bfin_write_CAN_AM10H(val) bfin_write16(CAN_AM10H,val)
1041 #define bfin_write_CAN_AM11L(val) bfin_write16(CAN_AM11L,val)
1043 #define bfin_write_CAN_AM11H(val) bfin_write16(CAN_AM11H,val)
1045 #define bfin_write_CAN_AM12L(val) bfin_write16(CAN_AM12L,val)
1047 #define bfin_write_CAN_AM12H(val) bfin_write16(CAN_AM12H,val)
1049 #define bfin_write_CAN_AM13L(val) bfin_write16(CAN_AM13L,val)
1051 #define bfin_write_CAN_AM13H(val) bfin_write16(CAN_AM13H,val)
1053 #define bfin_write_CAN_AM14L(val) bfin_write16(CAN_AM14L,val)
1055 #define bfin_write_CAN_AM14H(val) bfin_write16(CAN_AM14H,val)
1057 #define bfin_write_CAN_AM15L(val) bfin_write16(CAN_AM15L,val)
1059 #define bfin_write_CAN_AM15H(val) bfin_write16(CAN_AM15H,val)
1062 #define bfin_write_CAN_AM16L(val) bfin_write16(CAN_AM16L,val)
1064 #define bfin_write_CAN_AM16H(val) bfin_write16(CAN_AM16H,val)
1066 #define bfin_write_CAN_AM17L(val) bfin_write16(CAN_AM17L,val)
1068 #define bfin_write_CAN_AM17H(val) bfin_write16(CAN_AM17H,val)
1070 #define bfin_write_CAN_AM18L(val) bfin_write16(CAN_AM18L,val)
1072 #define bfin_write_CAN_AM18H(val) bfin_write16(CAN_AM18H,val)
1074 #define bfin_write_CAN_AM19L(val) bfin_write16(CAN_AM19L,val)
1076 #define bfin_write_CAN_AM19H(val) bfin_write16(CAN_AM19H,val)
1078 #define bfin_write_CAN_AM20L(val) bfin_write16(CAN_AM20L,val)
1080 #define bfin_write_CAN_AM20H(val) bfin_write16(CAN_AM20H,val)
1082 #define bfin_write_CAN_AM21L(val) bfin_write16(CAN_AM21L,val)
1084 #define bfin_write_CAN_AM21H(val) bfin_write16(CAN_AM21H,val)
1086 #define bfin_write_CAN_AM22L(val) bfin_write16(CAN_AM22L,val)
1088 #define bfin_write_CAN_AM22H(val) bfin_write16(CAN_AM22H,val)
1090 #define bfin_write_CAN_AM23L(val) bfin_write16(CAN_AM23L,val)
1092 #define bfin_write_CAN_AM23H(val) bfin_write16(CAN_AM23H,val)
1094 #define bfin_write_CAN_AM24L(val) bfin_write16(CAN_AM24L,val)
1096 #define bfin_write_CAN_AM24H(val) bfin_write16(CAN_AM24H,val)
1098 #define bfin_write_CAN_AM25L(val) bfin_write16(CAN_AM25L,val)
1100 #define bfin_write_CAN_AM25H(val) bfin_write16(CAN_AM25H,val)
1102 #define bfin_write_CAN_AM26L(val) bfin_write16(CAN_AM26L,val)
1104 #define bfin_write_CAN_AM26H(val) bfin_write16(CAN_AM26H,val)
1106 #define bfin_write_CAN_AM27L(val) bfin_write16(CAN_AM27L,val)
1108 #define bfin_write_CAN_AM27H(val) bfin_write16(CAN_AM27H,val)
1110 #define bfin_write_CAN_AM28L(val) bfin_write16(CAN_AM28L,val)
1112 #define bfin_write_CAN_AM28H(val) bfin_write16(CAN_AM28H,val)
1114 #define bfin_write_CAN_AM29L(val) bfin_write16(CAN_AM29L,val)
1116 #define bfin_write_CAN_AM29H(val) bfin_write16(CAN_AM29H,val)
1118 #define bfin_write_CAN_AM30L(val) bfin_write16(CAN_AM30L,val)
1120 #define bfin_write_CAN_AM30H(val) bfin_write16(CAN_AM30H,val)
1122 #define bfin_write_CAN_AM31L(val) bfin_write16(CAN_AM31L,val)
1124 #define bfin_write_CAN_AM31H(val) bfin_write16(CAN_AM31H,val)
1128 #define bfin_write_CAN_AM_L(x)(val) bfin_write16(CAN_AM_L(x),val)
1130 #define bfin_write_CAN_AM_H(x)(val) bfin_write16(CAN_AM_H(x),val)
1134 #define bfin_write_CAN_MB00_ID1(val) bfin_write16(CAN_MB00_ID1,val)
1136 #define bfin_write_CAN_MB00_ID0(val) bfin_write16(CAN_MB00_ID0,val)
1138 #define bfin_write_CAN_MB00_TIMESTAMP(val) bfin_write16(CAN_MB00_TIMESTAMP,val)
1140 #define bfin_write_CAN_MB00_LENGTH(val) bfin_write16(CAN_MB00_LENGTH,val)
1142 #define bfin_write_CAN_MB00_DATA3(val) bfin_write16(CAN_MB00_DATA3,val)
1144 #define bfin_write_CAN_MB00_DATA2(val) bfin_write16(CAN_MB00_DATA2,val)
1146 #define bfin_write_CAN_MB00_DATA1(val) bfin_write16(CAN_MB00_DATA1,val)
1148 #define bfin_write_CAN_MB00_DATA0(val) bfin_write16(CAN_MB00_DATA0,val)
1151 #define bfin_write_CAN_MB01_ID1(val) bfin_write16(CAN_MB01_ID1,val)
1153 #define bfin_write_CAN_MB01_ID0(val) bfin_write16(CAN_MB01_ID0,val)
1155 #define bfin_write_CAN_MB01_TIMESTAMP(val) bfin_write16(CAN_MB01_TIMESTAMP,val)
1157 #define bfin_write_CAN_MB01_LENGTH(val) bfin_write16(CAN_MB01_LENGTH,val)
1159 #define bfin_write_CAN_MB01_DATA3(val) bfin_write16(CAN_MB01_DATA3,val)
1161 #define bfin_write_CAN_MB01_DATA2(val) bfin_write16(CAN_MB01_DATA2,val)
1163 #define bfin_write_CAN_MB01_DATA1(val) bfin_write16(CAN_MB01_DATA1,val)
1165 #define bfin_write_CAN_MB01_DATA0(val) bfin_write16(CAN_MB01_DATA0,val)
1168 #define bfin_write_CAN_MB02_ID1(val) bfin_write16(CAN_MB02_ID1,val)
1170 #define bfin_write_CAN_MB02_ID0(val) bfin_write16(CAN_MB02_ID0,val)
1172 #define bfin_write_CAN_MB02_TIMESTAMP(val) bfin_write16(CAN_MB02_TIMESTAMP,val)
1174 #define bfin_write_CAN_MB02_LENGTH(val) bfin_write16(CAN_MB02_LENGTH,val)
1176 #define bfin_write_CAN_MB02_DATA3(val) bfin_write16(CAN_MB02_DATA3,val)
1178 #define bfin_write_CAN_MB02_DATA2(val) bfin_write16(CAN_MB02_DATA2,val)
1180 #define bfin_write_CAN_MB02_DATA1(val) bfin_write16(CAN_MB02_DATA1,val)
1182 #define bfin_write_CAN_MB02_DATA0(val) bfin_write16(CAN_MB02_DATA0,val)
1185 #define bfin_write_CAN_MB03_ID1(val) bfin_write16(CAN_MB03_ID1,val)
1187 #define bfin_write_CAN_MB03_ID0(val) bfin_write16(CAN_MB03_ID0,val)
1189 #define bfin_write_CAN_MB03_TIMESTAMP(val) bfin_write16(CAN_MB03_TIMESTAMP,val)
1191 #define bfin_write_CAN_MB03_LENGTH(val) bfin_write16(CAN_MB03_LENGTH,val)
1193 #define bfin_write_CAN_MB03_DATA3(val) bfin_write16(CAN_MB03_DATA3,val)
1195 #define bfin_write_CAN_MB03_DATA2(val) bfin_write16(CAN_MB03_DATA2,val)
1197 #define bfin_write_CAN_MB03_DATA1(val) bfin_write16(CAN_MB03_DATA1,val)
1199 #define bfin_write_CAN_MB03_DATA0(val) bfin_write16(CAN_MB03_DATA0,val)
1202 #define bfin_write_CAN_MB04_ID1(val) bfin_write16(CAN_MB04_ID1,val)
1204 #define bfin_write_CAN_MB04_ID0(val) bfin_write16(CAN_MB04_ID0,val)
1206 #define bfin_write_CAN_MB04_TIMESTAMP(val) bfin_write16(CAN_MB04_TIMESTAMP,val)
1208 #define bfin_write_CAN_MB04_LENGTH(val) bfin_write16(CAN_MB04_LENGTH,val)
1210 #define bfin_write_CAN_MB04_DATA3(val) bfin_write16(CAN_MB04_DATA3,val)
1212 #define bfin_write_CAN_MB04_DATA2(val) bfin_write16(CAN_MB04_DATA2,val)
1214 #define bfin_write_CAN_MB04_DATA1(val) bfin_write16(CAN_MB04_DATA1,val)
1216 #define bfin_write_CAN_MB04_DATA0(val) bfin_write16(CAN_MB04_DATA0,val)
1219 #define bfin_write_CAN_MB05_ID1(val) bfin_write16(CAN_MB05_ID1,val)
1221 #define bfin_write_CAN_MB05_ID0(val) bfin_write16(CAN_MB05_ID0,val)
1223 #define bfin_write_CAN_MB05_TIMESTAMP(val) bfin_write16(CAN_MB05_TIMESTAMP,val)
1225 #define bfin_write_CAN_MB05_LENGTH(val) bfin_write16(CAN_MB05_LENGTH,val)
1227 #define bfin_write_CAN_MB05_DATA3(val) bfin_write16(CAN_MB05_DATA3,val)
1229 #define bfin_write_CAN_MB05_DATA2(val) bfin_write16(CAN_MB05_DATA2,val)
1231 #define bfin_write_CAN_MB05_DATA1(val) bfin_write16(CAN_MB05_DATA1,val)
1233 #define bfin_write_CAN_MB05_DATA0(val) bfin_write16(CAN_MB05_DATA0,val)
1236 #define bfin_write_CAN_MB06_ID1(val) bfin_write16(CAN_MB06_ID1,val)
1238 #define bfin_write_CAN_MB06_ID0(val) bfin_write16(CAN_MB06_ID0,val)
1240 #define bfin_write_CAN_MB06_TIMESTAMP(val) bfin_write16(CAN_MB06_TIMESTAMP,val)
1242 #define bfin_write_CAN_MB06_LENGTH(val) bfin_write16(CAN_MB06_LENGTH,val)
1244 #define bfin_write_CAN_MB06_DATA3(val) bfin_write16(CAN_MB06_DATA3,val)
1246 #define bfin_write_CAN_MB06_DATA2(val) bfin_write16(CAN_MB06_DATA2,val)
1248 #define bfin_write_CAN_MB06_DATA1(val) bfin_write16(CAN_MB06_DATA1,val)
1250 #define bfin_write_CAN_MB06_DATA0(val) bfin_write16(CAN_MB06_DATA0,val)
1253 #define bfin_write_CAN_MB07_ID1(val) bfin_write16(CAN_MB07_ID1,val)
1255 #define bfin_write_CAN_MB07_ID0(val) bfin_write16(CAN_MB07_ID0,val)
1257 #define bfin_write_CAN_MB07_TIMESTAMP(val) bfin_write16(CAN_MB07_TIMESTAMP,val)
1259 #define bfin_write_CAN_MB07_LENGTH(val) bfin_write16(CAN_MB07_LENGTH,val)
1261 #define bfin_write_CAN_MB07_DATA3(val) bfin_write16(CAN_MB07_DATA3,val)
1263 #define bfin_write_CAN_MB07_DATA2(val) bfin_write16(CAN_MB07_DATA2,val)
1265 #define bfin_write_CAN_MB07_DATA1(val) bfin_write16(CAN_MB07_DATA1,val)
1267 #define bfin_write_CAN_MB07_DATA0(val) bfin_write16(CAN_MB07_DATA0,val)
1270 #define bfin_write_CAN_MB08_ID1(val) bfin_write16(CAN_MB08_ID1,val)
1272 #define bfin_write_CAN_MB08_ID0(val) bfin_write16(CAN_MB08_ID0,val)
1274 #define bfin_write_CAN_MB08_TIMESTAMP(val) bfin_write16(CAN_MB08_TIMESTAMP,val)
1276 #define bfin_write_CAN_MB08_LENGTH(val) bfin_write16(CAN_MB08_LENGTH,val)
1278 #define bfin_write_CAN_MB08_DATA3(val) bfin_write16(CAN_MB08_DATA3,val)
1280 #define bfin_write_CAN_MB08_DATA2(val) bfin_write16(CAN_MB08_DATA2,val)
1282 #define bfin_write_CAN_MB08_DATA1(val) bfin_write16(CAN_MB08_DATA1,val)
1284 #define bfin_write_CAN_MB08_DATA0(val) bfin_write16(CAN_MB08_DATA0,val)
1287 #define bfin_write_CAN_MB09_ID1(val) bfin_write16(CAN_MB09_ID1,val)
1289 #define bfin_write_CAN_MB09_ID0(val) bfin_write16(CAN_MB09_ID0,val)
1291 #define bfin_write_CAN_MB09_TIMESTAMP(val) bfin_write16(CAN_MB09_TIMESTAMP,val)
1293 #define bfin_write_CAN_MB09_LENGTH(val) bfin_write16(CAN_MB09_LENGTH,val)
1295 #define bfin_write_CAN_MB09_DATA3(val) bfin_write16(CAN_MB09_DATA3,val)
1297 #define bfin_write_CAN_MB09_DATA2(val) bfin_write16(CAN_MB09_DATA2,val)
1299 #define bfin_write_CAN_MB09_DATA1(val) bfin_write16(CAN_MB09_DATA1,val)
1301 #define bfin_write_CAN_MB09_DATA0(val) bfin_write16(CAN_MB09_DATA0,val)
1304 #define bfin_write_CAN_MB10_ID1(val) bfin_write16(CAN_MB10_ID1,val)
1306 #define bfin_write_CAN_MB10_ID0(val) bfin_write16(CAN_MB10_ID0,val)
1308 #define bfin_write_CAN_MB10_TIMESTAMP(val) bfin_write16(CAN_MB10_TIMESTAMP,val)
1310 #define bfin_write_CAN_MB10_LENGTH(val) bfin_write16(CAN_MB10_LENGTH,val)
1312 #define bfin_write_CAN_MB10_DATA3(val) bfin_write16(CAN_MB10_DATA3,val)
1314 #define bfin_write_CAN_MB10_DATA2(val) bfin_write16(CAN_MB10_DATA2,val)
1316 #define bfin_write_CAN_MB10_DATA1(val) bfin_write16(CAN_MB10_DATA1,val)
1318 #define bfin_write_CAN_MB10_DATA0(val) bfin_write16(CAN_MB10_DATA0,val)
1321 #define bfin_write_CAN_MB11_ID1(val) bfin_write16(CAN_MB11_ID1,val)
1323 #define bfin_write_CAN_MB11_ID0(val) bfin_write16(CAN_MB11_ID0,val)
1325 #define bfin_write_CAN_MB11_TIMESTAMP(val) bfin_write16(CAN_MB11_TIMESTAMP,val)
1327 #define bfin_write_CAN_MB11_LENGTH(val) bfin_write16(CAN_MB11_LENGTH,val)
1329 #define bfin_write_CAN_MB11_DATA3(val) bfin_write16(CAN_MB11_DATA3,val)
1331 #define bfin_write_CAN_MB11_DATA2(val) bfin_write16(CAN_MB11_DATA2,val)
1333 #define bfin_write_CAN_MB11_DATA1(val) bfin_write16(CAN_MB11_DATA1,val)
1335 #define bfin_write_CAN_MB11_DATA0(val) bfin_write16(CAN_MB11_DATA0,val)
1338 #define bfin_write_CAN_MB12_ID1(val) bfin_write16(CAN_MB12_ID1,val)
1340 #define bfin_write_CAN_MB12_ID0(val) bfin_write16(CAN_MB12_ID0,val)
1342 #define bfin_write_CAN_MB12_TIMESTAMP(val) bfin_write16(CAN_MB12_TIMESTAMP,val)
1344 #define bfin_write_CAN_MB12_LENGTH(val) bfin_write16(CAN_MB12_LENGTH,val)
1346 #define bfin_write_CAN_MB12_DATA3(val) bfin_write16(CAN_MB12_DATA3,val)
1348 #define bfin_write_CAN_MB12_DATA2(val) bfin_write16(CAN_MB12_DATA2,val)
1350 #define bfin_write_CAN_MB12_DATA1(val) bfin_write16(CAN_MB12_DATA1,val)
1352 #define bfin_write_CAN_MB12_DATA0(val) bfin_write16(CAN_MB12_DATA0,val)
1355 #define bfin_write_CAN_MB13_ID1(val) bfin_write16(CAN_MB13_ID1,val)
1357 #define bfin_write_CAN_MB13_ID0(val) bfin_write16(CAN_MB13_ID0,val)
1359 #define bfin_write_CAN_MB13_TIMESTAMP(val) bfin_write16(CAN_MB13_TIMESTAMP,val)
1361 #define bfin_write_CAN_MB13_LENGTH(val) bfin_write16(CAN_MB13_LENGTH,val)
1363 #define bfin_write_CAN_MB13_DATA3(val) bfin_write16(CAN_MB13_DATA3,val)
1365 #define bfin_write_CAN_MB13_DATA2(val) bfin_write16(CAN_MB13_DATA2,val)
1367 #define bfin_write_CAN_MB13_DATA1(val) bfin_write16(CAN_MB13_DATA1,val)
1369 #define bfin_write_CAN_MB13_DATA0(val) bfin_write16(CAN_MB13_DATA0,val)
1372 #define bfin_write_CAN_MB14_ID1(val) bfin_write16(CAN_MB14_ID1,val)
1374 #define bfin_write_CAN_MB14_ID0(val) bfin_write16(CAN_MB14_ID0,val)
1376 #define bfin_write_CAN_MB14_TIMESTAMP(val) bfin_write16(CAN_MB14_TIMESTAMP,val)
1378 #define bfin_write_CAN_MB14_LENGTH(val) bfin_write16(CAN_MB14_LENGTH,val)
1380 #define bfin_write_CAN_MB14_DATA3(val) bfin_write16(CAN_MB14_DATA3,val)
1382 #define bfin_write_CAN_MB14_DATA2(val) bfin_write16(CAN_MB14_DATA2,val)
1384 #define bfin_write_CAN_MB14_DATA1(val) bfin_write16(CAN_MB14_DATA1,val)
1386 #define bfin_write_CAN_MB14_DATA0(val) bfin_write16(CAN_MB14_DATA0,val)
1389 #define bfin_write_CAN_MB15_ID1(val) bfin_write16(CAN_MB15_ID1,val)
1391 #define bfin_write_CAN_MB15_ID0(val) bfin_write16(CAN_MB15_ID0,val)
1393 #define bfin_write_CAN_MB15_TIMESTAMP(val) bfin_write16(CAN_MB15_TIMESTAMP,val)
1395 #define bfin_write_CAN_MB15_LENGTH(val) bfin_write16(CAN_MB15_LENGTH,val)
1397 #define bfin_write_CAN_MB15_DATA3(val) bfin_write16(CAN_MB15_DATA3,val)
1399 #define bfin_write_CAN_MB15_DATA2(val) bfin_write16(CAN_MB15_DATA2,val)
1401 #define bfin_write_CAN_MB15_DATA1(val) bfin_write16(CAN_MB15_DATA1,val)
1403 #define bfin_write_CAN_MB15_DATA0(val) bfin_write16(CAN_MB15_DATA0,val)
1406 #define bfin_write_CAN_MB16_ID1(val) bfin_write16(CAN_MB16_ID1,val)
1408 #define bfin_write_CAN_MB16_ID0(val) bfin_write16(CAN_MB16_ID0,val)
1410 #define bfin_write_CAN_MB16_TIMESTAMP(val) bfin_write16(CAN_MB16_TIMESTAMP,val)
1412 #define bfin_write_CAN_MB16_LENGTH(val) bfin_write16(CAN_MB16_LENGTH,val)
1414 #define bfin_write_CAN_MB16_DATA3(val) bfin_write16(CAN_MB16_DATA3,val)
1416 #define bfin_write_CAN_MB16_DATA2(val) bfin_write16(CAN_MB16_DATA2,val)
1418 #define bfin_write_CAN_MB16_DATA1(val) bfin_write16(CAN_MB16_DATA1,val)
1420 #define bfin_write_CAN_MB16_DATA0(val) bfin_write16(CAN_MB16_DATA0,val)
1423 #define bfin_write_CAN_MB17_ID1(val) bfin_write16(CAN_MB17_ID1,val)
1425 #define bfin_write_CAN_MB17_ID0(val) bfin_write16(CAN_MB17_ID0,val)
1427 #define bfin_write_CAN_MB17_TIMESTAMP(val) bfin_write16(CAN_MB17_TIMESTAMP,val)
1429 #define bfin_write_CAN_MB17_LENGTH(val) bfin_write16(CAN_MB17_LENGTH,val)
1431 #define bfin_write_CAN_MB17_DATA3(val) bfin_write16(CAN_MB17_DATA3,val)
1433 #define bfin_write_CAN_MB17_DATA2(val) bfin_write16(CAN_MB17_DATA2,val)
1435 #define bfin_write_CAN_MB17_DATA1(val) bfin_write16(CAN_MB17_DATA1,val)
1437 #define bfin_write_CAN_MB17_DATA0(val) bfin_write16(CAN_MB17_DATA0,val)
1440 #define bfin_write_CAN_MB18_ID1(val) bfin_write16(CAN_MB18_ID1,val)
1442 #define bfin_write_CAN_MB18_ID0(val) bfin_write16(CAN_MB18_ID0,val)
1444 #define bfin_write_CAN_MB18_TIMESTAMP(val) bfin_write16(CAN_MB18_TIMESTAMP,val)
1446 #define bfin_write_CAN_MB18_LENGTH(val) bfin_write16(CAN_MB18_LENGTH,val)
1448 #define bfin_write_CAN_MB18_DATA3(val) bfin_write16(CAN_MB18_DATA3,val)
1450 #define bfin_write_CAN_MB18_DATA2(val) bfin_write16(CAN_MB18_DATA2,val)
1452 #define bfin_write_CAN_MB18_DATA1(val) bfin_write16(CAN_MB18_DATA1,val)
1454 #define bfin_write_CAN_MB18_DATA0(val) bfin_write16(CAN_MB18_DATA0,val)
1457 #define bfin_write_CAN_MB19_ID1(val) bfin_write16(CAN_MB19_ID1,val)
1459 #define bfin_write_CAN_MB19_ID0(val) bfin_write16(CAN_MB19_ID0,val)
1461 #define bfin_write_CAN_MB19_TIMESTAMP(val) bfin_write16(CAN_MB19_TIMESTAMP,val)
1463 #define bfin_write_CAN_MB19_LENGTH(val) bfin_write16(CAN_MB19_LENGTH,val)
1465 #define bfin_write_CAN_MB19_DATA3(val) bfin_write16(CAN_MB19_DATA3,val)
1467 #define bfin_write_CAN_MB19_DATA2(val) bfin_write16(CAN_MB19_DATA2,val)
1469 #define bfin_write_CAN_MB19_DATA1(val) bfin_write16(CAN_MB19_DATA1,val)
1471 #define bfin_write_CAN_MB19_DATA0(val) bfin_write16(CAN_MB19_DATA0,val)
1474 #define bfin_write_CAN_MB20_ID1(val) bfin_write16(CAN_MB20_ID1,val)
1476 #define bfin_write_CAN_MB20_ID0(val) bfin_write16(CAN_MB20_ID0,val)
1478 #define bfin_write_CAN_MB20_TIMESTAMP(val) bfin_write16(CAN_MB20_TIMESTAMP,val)
1480 #define bfin_write_CAN_MB20_LENGTH(val) bfin_write16(CAN_MB20_LENGTH,val)
1482 #define bfin_write_CAN_MB20_DATA3(val) bfin_write16(CAN_MB20_DATA3,val)
1484 #define bfin_write_CAN_MB20_DATA2(val) bfin_write16(CAN_MB20_DATA2,val)
1486 #define bfin_write_CAN_MB20_DATA1(val) bfin_write16(CAN_MB20_DATA1,val)
1488 #define bfin_write_CAN_MB20_DATA0(val) bfin_write16(CAN_MB20_DATA0,val)
1491 #define bfin_write_CAN_MB21_ID1(val) bfin_write16(CAN_MB21_ID1,val)
1493 #define bfin_write_CAN_MB21_ID0(val) bfin_write16(CAN_MB21_ID0,val)
1495 #define bfin_write_CAN_MB21_TIMESTAMP(val) bfin_write16(CAN_MB21_TIMESTAMP,val)
1497 #define bfin_write_CAN_MB21_LENGTH(val) bfin_write16(CAN_MB21_LENGTH,val)
1499 #define bfin_write_CAN_MB21_DATA3(val) bfin_write16(CAN_MB21_DATA3,val)
1501 #define bfin_write_CAN_MB21_DATA2(val) bfin_write16(CAN_MB21_DATA2,val)
1503 #define bfin_write_CAN_MB21_DATA1(val) bfin_write16(CAN_MB21_DATA1,val)
1505 #define bfin_write_CAN_MB21_DATA0(val) bfin_write16(CAN_MB21_DATA0,val)
1508 #define bfin_write_CAN_MB22_ID1(val) bfin_write16(CAN_MB22_ID1,val)
1510 #define bfin_write_CAN_MB22_ID0(val) bfin_write16(CAN_MB22_ID0,val)
1512 #define bfin_write_CAN_MB22_TIMESTAMP(val) bfin_write16(CAN_MB22_TIMESTAMP,val)
1514 #define bfin_write_CAN_MB22_LENGTH(val) bfin_write16(CAN_MB22_LENGTH,val)
1516 #define bfin_write_CAN_MB22_DATA3(val) bfin_write16(CAN_MB22_DATA3,val)
1518 #define bfin_write_CAN_MB22_DATA2(val) bfin_write16(CAN_MB22_DATA2,val)
1520 #define bfin_write_CAN_MB22_DATA1(val) bfin_write16(CAN_MB22_DATA1,val)
1522 #define bfin_write_CAN_MB22_DATA0(val) bfin_write16(CAN_MB22_DATA0,val)
1525 #define bfin_write_CAN_MB23_ID1(val) bfin_write16(CAN_MB23_ID1,val)
1527 #define bfin_write_CAN_MB23_ID0(val) bfin_write16(CAN_MB23_ID0,val)
1529 #define bfin_write_CAN_MB23_TIMESTAMP(val) bfin_write16(CAN_MB23_TIMESTAMP,val)
1531 #define bfin_write_CAN_MB23_LENGTH(val) bfin_write16(CAN_MB23_LENGTH,val)
1533 #define bfin_write_CAN_MB23_DATA3(val) bfin_write16(CAN_MB23_DATA3,val)
1535 #define bfin_write_CAN_MB23_DATA2(val) bfin_write16(CAN_MB23_DATA2,val)
1537 #define bfin_write_CAN_MB23_DATA1(val) bfin_write16(CAN_MB23_DATA1,val)
1539 #define bfin_write_CAN_MB23_DATA0(val) bfin_write16(CAN_MB23_DATA0,val)
1542 #define bfin_write_CAN_MB24_ID1(val) bfin_write16(CAN_MB24_ID1,val)
1544 #define bfin_write_CAN_MB24_ID0(val) bfin_write16(CAN_MB24_ID0,val)
1546 #define bfin_write_CAN_MB24_TIMESTAMP(val) bfin_write16(CAN_MB24_TIMESTAMP,val)
1548 #define bfin_write_CAN_MB24_LENGTH(val) bfin_write16(CAN_MB24_LENGTH,val)
1550 #define bfin_write_CAN_MB24_DATA3(val) bfin_write16(CAN_MB24_DATA3,val)
1552 #define bfin_write_CAN_MB24_DATA2(val) bfin_write16(CAN_MB24_DATA2,val)
1554 #define bfin_write_CAN_MB24_DATA1(val) bfin_write16(CAN_MB24_DATA1,val)
1556 #define bfin_write_CAN_MB24_DATA0(val) bfin_write16(CAN_MB24_DATA0,val)
1559 #define bfin_write_CAN_MB25_ID1(val) bfin_write16(CAN_MB25_ID1,val)
1561 #define bfin_write_CAN_MB25_ID0(val) bfin_write16(CAN_MB25_ID0,val)
1563 #define bfin_write_CAN_MB25_TIMESTAMP(val) bfin_write16(CAN_MB25_TIMESTAMP,val)
1565 #define bfin_write_CAN_MB25_LENGTH(val) bfin_write16(CAN_MB25_LENGTH,val)
1567 #define bfin_write_CAN_MB25_DATA3(val) bfin_write16(CAN_MB25_DATA3,val)
1569 #define bfin_write_CAN_MB25_DATA2(val) bfin_write16(CAN_MB25_DATA2,val)
1571 #define bfin_write_CAN_MB25_DATA1(val) bfin_write16(CAN_MB25_DATA1,val)
1573 #define bfin_write_CAN_MB25_DATA0(val) bfin_write16(CAN_MB25_DATA0,val)
1576 #define bfin_write_CAN_MB26_ID1(val) bfin_write16(CAN_MB26_ID1,val)
1578 #define bfin_write_CAN_MB26_ID0(val) bfin_write16(CAN_MB26_ID0,val)
1580 #define bfin_write_CAN_MB26_TIMESTAMP(val) bfin_write16(CAN_MB26_TIMESTAMP,val)
1582 #define bfin_write_CAN_MB26_LENGTH(val) bfin_write16(CAN_MB26_LENGTH,val)
1584 #define bfin_write_CAN_MB26_DATA3(val) bfin_write16(CAN_MB26_DATA3,val)
1586 #define bfin_write_CAN_MB26_DATA2(val) bfin_write16(CAN_MB26_DATA2,val)
1588 #define bfin_write_CAN_MB26_DATA1(val) bfin_write16(CAN_MB26_DATA1,val)
1590 #define bfin_write_CAN_MB26_DATA0(val) bfin_write16(CAN_MB26_DATA0,val)
1593 #define bfin_write_CAN_MB27_ID1(val) bfin_write16(CAN_MB27_ID1,val)
1595 #define bfin_write_CAN_MB27_ID0(val) bfin_write16(CAN_MB27_ID0,val)
1597 #define bfin_write_CAN_MB27_TIMESTAMP(val) bfin_write16(CAN_MB27_TIMESTAMP,val)
1599 #define bfin_write_CAN_MB27_LENGTH(val) bfin_write16(CAN_MB27_LENGTH,val)
1601 #define bfin_write_CAN_MB27_DATA3(val) bfin_write16(CAN_MB27_DATA3,val)
1603 #define bfin_write_CAN_MB27_DATA2(val) bfin_write16(CAN_MB27_DATA2,val)
1605 #define bfin_write_CAN_MB27_DATA1(val) bfin_write16(CAN_MB27_DATA1,val)
1607 #define bfin_write_CAN_MB27_DATA0(val) bfin_write16(CAN_MB27_DATA0,val)
1610 #define bfin_write_CAN_MB28_ID1(val) bfin_write16(CAN_MB28_ID1,val)
1612 #define bfin_write_CAN_MB28_ID0(val) bfin_write16(CAN_MB28_ID0,val)
1614 #define bfin_write_CAN_MB28_TIMESTAMP(val) bfin_write16(CAN_MB28_TIMESTAMP,val)
1616 #define bfin_write_CAN_MB28_LENGTH(val) bfin_write16(CAN_MB28_LENGTH,val)
1618 #define bfin_write_CAN_MB28_DATA3(val) bfin_write16(CAN_MB28_DATA3,val)
1620 #define bfin_write_CAN_MB28_DATA2(val) bfin_write16(CAN_MB28_DATA2,val)
1622 #define bfin_write_CAN_MB28_DATA1(val) bfin_write16(CAN_MB28_DATA1,val)
1624 #define bfin_write_CAN_MB28_DATA0(val) bfin_write16(CAN_MB28_DATA0,val)
1627 #define bfin_write_CAN_MB29_ID1(val) bfin_write16(CAN_MB29_ID1,val)
1629 #define bfin_write_CAN_MB29_ID0(val) bfin_write16(CAN_MB29_ID0,val)
1631 #define bfin_write_CAN_MB29_TIMESTAMP(val) bfin_write16(CAN_MB29_TIMESTAMP,val)
1633 #define bfin_write_CAN_MB29_LENGTH(val) bfin_write16(CAN_MB29_LENGTH,val)
1635 #define bfin_write_CAN_MB29_DATA3(val) bfin_write16(CAN_MB29_DATA3,val)
1637 #define bfin_write_CAN_MB29_DATA2(val) bfin_write16(CAN_MB29_DATA2,val)
1639 #define bfin_write_CAN_MB29_DATA1(val) bfin_write16(CAN_MB29_DATA1,val)
1641 #define bfin_write_CAN_MB29_DATA0(val) bfin_write16(CAN_MB29_DATA0,val)
1644 #define bfin_write_CAN_MB30_ID1(val) bfin_write16(CAN_MB30_ID1,val)
1646 #define bfin_write_CAN_MB30_ID0(val) bfin_write16(CAN_MB30_ID0,val)
1648 #define bfin_write_CAN_MB30_TIMESTAMP(val) bfin_write16(CAN_MB30_TIMESTAMP,val)
1650 #define bfin_write_CAN_MB30_LENGTH(val) bfin_write16(CAN_MB30_LENGTH,val)
1652 #define bfin_write_CAN_MB30_DATA3(val) bfin_write16(CAN_MB30_DATA3,val)
1654 #define bfin_write_CAN_MB30_DATA2(val) bfin_write16(CAN_MB30_DATA2,val)
1656 #define bfin_write_CAN_MB30_DATA1(val) bfin_write16(CAN_MB30_DATA1,val)
1658 #define bfin_write_CAN_MB30_DATA0(val) bfin_write16(CAN_MB30_DATA0,val)
1661 #define bfin_write_CAN_MB31_ID1(val) bfin_write16(CAN_MB31_ID1,val)
1663 #define bfin_write_CAN_MB31_ID0(val) bfin_write16(CAN_MB31_ID0,val)
1665 #define bfin_write_CAN_MB31_TIMESTAMP(val) bfin_write16(CAN_MB31_TIMESTAMP,val)
1667 #define bfin_write_CAN_MB31_LENGTH(val) bfin_write16(CAN_MB31_LENGTH,val)
1669 #define bfin_write_CAN_MB31_DATA3(val) bfin_write16(CAN_MB31_DATA3,val)
1671 #define bfin_write_CAN_MB31_DATA2(val) bfin_write16(CAN_MB31_DATA2,val)
1673 #define bfin_write_CAN_MB31_DATA1(val) bfin_write16(CAN_MB31_DATA1,val)
1675 #define bfin_write_CAN_MB31_DATA0(val) bfin_write16(CAN_MB31_DATA0,val)
1679 #define bfin_write_CAN_MB_ID1(x)(val) bfin_write16(CAN_MB_ID1(x),val)
1681 #define bfin_write_CAN_MB_ID0(x)(val) bfin_write16(CAN_MB_ID0(x),val)
1683 #define bfin_write_CAN_MB_TIMESTAMP(x)(val) bfin_write16(CAN_MB_TIMESTAMP(x),val)
1685 #define bfin_write_CAN_MB_LENGTH(x)(val) bfin_write16(CAN_MB_LENGTH(x),val)
1687 #define bfin_write_CAN_MB_DATA3(x)(val) bfin_write16(CAN_MB_DATA3(x),val)
1689 #define bfin_write_CAN_MB_DATA2(x)(val) bfin_write16(CAN_MB_DATA2(x),val)
1691 #define bfin_write_CAN_MB_DATA1(x)(val) bfin_write16(CAN_MB_DATA1(x),val)
1693 #define bfin_write_CAN_MB_DATA0(x)(val) bfin_write16(CAN_MB_DATA0(x),val)
1697 #define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER,val)
1699 #define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER,val)
1701 #define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER,val)
1703 #define bfin_write_PORT_MUX(val) bfin_write16(BFIN_PORT_MUX,val)
1707 #define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL,val)
1709 #define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT,val)
1711 #define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT,val)
1713 #define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT,val)
1715 #define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW,val)
1717 #define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT,val)
1719 #define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT,val)
1722 #define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL,val)
1724 #define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT,val)
1726 #define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT,val)
1728 #define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT,val)
1730 #define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW,val)
1732 #define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT,val)
1734 #define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT,val)
/linux-4.1.27/arch/x86/lib/
H A Dmisc.c2 * Count the digits of @val including a possible sign.
6 int num_digits(int val) num_digits() argument
11 if (val < 0) { num_digits()
13 val = -val; num_digits()
16 while (val >= m) { num_digits()
/linux-4.1.27/arch/alpha/lib/
H A Dfpreg.c8 #define STT(reg,val) asm volatile ("ftoit $f"#reg",%0" : "=r"(val));
10 #define STT(reg,val) asm volatile ("stt $f"#reg",%0" : "=m"(val));
16 unsigned long val; alpha_read_fp_reg() local
19 case 0: STT( 0, val); break; alpha_read_fp_reg()
20 case 1: STT( 1, val); break; alpha_read_fp_reg()
21 case 2: STT( 2, val); break; alpha_read_fp_reg()
22 case 3: STT( 3, val); break; alpha_read_fp_reg()
23 case 4: STT( 4, val); break; alpha_read_fp_reg()
24 case 5: STT( 5, val); break; alpha_read_fp_reg()
25 case 6: STT( 6, val); break; alpha_read_fp_reg()
26 case 7: STT( 7, val); break; alpha_read_fp_reg()
27 case 8: STT( 8, val); break; alpha_read_fp_reg()
28 case 9: STT( 9, val); break; alpha_read_fp_reg()
29 case 10: STT(10, val); break; alpha_read_fp_reg()
30 case 11: STT(11, val); break; alpha_read_fp_reg()
31 case 12: STT(12, val); break; alpha_read_fp_reg()
32 case 13: STT(13, val); break; alpha_read_fp_reg()
33 case 14: STT(14, val); break; alpha_read_fp_reg()
34 case 15: STT(15, val); break; alpha_read_fp_reg()
35 case 16: STT(16, val); break; alpha_read_fp_reg()
36 case 17: STT(17, val); break; alpha_read_fp_reg()
37 case 18: STT(18, val); break; alpha_read_fp_reg()
38 case 19: STT(19, val); break; alpha_read_fp_reg()
39 case 20: STT(20, val); break; alpha_read_fp_reg()
40 case 21: STT(21, val); break; alpha_read_fp_reg()
41 case 22: STT(22, val); break; alpha_read_fp_reg()
42 case 23: STT(23, val); break; alpha_read_fp_reg()
43 case 24: STT(24, val); break; alpha_read_fp_reg()
44 case 25: STT(25, val); break; alpha_read_fp_reg()
45 case 26: STT(26, val); break; alpha_read_fp_reg()
46 case 27: STT(27, val); break; alpha_read_fp_reg()
47 case 28: STT(28, val); break; alpha_read_fp_reg()
48 case 29: STT(29, val); break; alpha_read_fp_reg()
49 case 30: STT(30, val); break; alpha_read_fp_reg()
50 case 31: STT(31, val); break; alpha_read_fp_reg()
53 return val; alpha_read_fp_reg()
57 #define LDT(reg,val) asm volatile ("itoft %0,$f"#reg : : "r"(val));
59 #define LDT(reg,val) asm volatile ("ldt $f"#reg",%0" : : "m"(val));
63 alpha_write_fp_reg (unsigned long reg, unsigned long val) alpha_write_fp_reg() argument
66 case 0: LDT( 0, val); break; alpha_write_fp_reg()
67 case 1: LDT( 1, val); break; alpha_write_fp_reg()
68 case 2: LDT( 2, val); break; alpha_write_fp_reg()
69 case 3: LDT( 3, val); break; alpha_write_fp_reg()
70 case 4: LDT( 4, val); break; alpha_write_fp_reg()
71 case 5: LDT( 5, val); break; alpha_write_fp_reg()
72 case 6: LDT( 6, val); break; alpha_write_fp_reg()
73 case 7: LDT( 7, val); break; alpha_write_fp_reg()
74 case 8: LDT( 8, val); break; alpha_write_fp_reg()
75 case 9: LDT( 9, val); break; alpha_write_fp_reg()
76 case 10: LDT(10, val); break; alpha_write_fp_reg()
77 case 11: LDT(11, val); break; alpha_write_fp_reg()
78 case 12: LDT(12, val); break; alpha_write_fp_reg()
79 case 13: LDT(13, val); break; alpha_write_fp_reg()
80 case 14: LDT(14, val); break; alpha_write_fp_reg()
81 case 15: LDT(15, val); break; alpha_write_fp_reg()
82 case 16: LDT(16, val); break; alpha_write_fp_reg()
83 case 17: LDT(17, val); break; alpha_write_fp_reg()
84 case 18: LDT(18, val); break; alpha_write_fp_reg()
85 case 19: LDT(19, val); break; alpha_write_fp_reg()
86 case 20: LDT(20, val); break; alpha_write_fp_reg()
87 case 21: LDT(21, val); break; alpha_write_fp_reg()
88 case 22: LDT(22, val); break; alpha_write_fp_reg()
89 case 23: LDT(23, val); break; alpha_write_fp_reg()
90 case 24: LDT(24, val); break; alpha_write_fp_reg()
91 case 25: LDT(25, val); break; alpha_write_fp_reg()
92 case 26: LDT(26, val); break; alpha_write_fp_reg()
93 case 27: LDT(27, val); break; alpha_write_fp_reg()
94 case 28: LDT(28, val); break; alpha_write_fp_reg()
95 case 29: LDT(29, val); break; alpha_write_fp_reg()
96 case 30: LDT(30, val); break; alpha_write_fp_reg()
97 case 31: LDT(31, val); break; alpha_write_fp_reg()
102 #define STS(reg,val) asm volatile ("ftois $f"#reg",%0" : "=r"(val));
104 #define STS(reg,val) asm volatile ("sts $f"#reg",%0" : "=m"(val));
110 unsigned long val; alpha_read_fp_reg_s() local
113 case 0: STS( 0, val); break; alpha_read_fp_reg_s()
114 case 1: STS( 1, val); break; alpha_read_fp_reg_s()
115 case 2: STS( 2, val); break; alpha_read_fp_reg_s()
116 case 3: STS( 3, val); break; alpha_read_fp_reg_s()
117 case 4: STS( 4, val); break; alpha_read_fp_reg_s()
118 case 5: STS( 5, val); break; alpha_read_fp_reg_s()
119 case 6: STS( 6, val); break; alpha_read_fp_reg_s()
120 case 7: STS( 7, val); break; alpha_read_fp_reg_s()
121 case 8: STS( 8, val); break; alpha_read_fp_reg_s()
122 case 9: STS( 9, val); break; alpha_read_fp_reg_s()
123 case 10: STS(10, val); break; alpha_read_fp_reg_s()
124 case 11: STS(11, val); break; alpha_read_fp_reg_s()
125 case 12: STS(12, val); break; alpha_read_fp_reg_s()
126 case 13: STS(13, val); break; alpha_read_fp_reg_s()
127 case 14: STS(14, val); break; alpha_read_fp_reg_s()
128 case 15: STS(15, val); break; alpha_read_fp_reg_s()
129 case 16: STS(16, val); break; alpha_read_fp_reg_s()
130 case 17: STS(17, val); break; alpha_read_fp_reg_s()
131 case 18: STS(18, val); break; alpha_read_fp_reg_s()
132 case 19: STS(19, val); break; alpha_read_fp_reg_s()
133 case 20: STS(20, val); break; alpha_read_fp_reg_s()
134 case 21: STS(21, val); break; alpha_read_fp_reg_s()
135 case 22: STS(22, val); break; alpha_read_fp_reg_s()
136 case 23: STS(23, val); break; alpha_read_fp_reg_s()
137 case 24: STS(24, val); break; alpha_read_fp_reg_s()
138 case 25: STS(25, val); break; alpha_read_fp_reg_s()
139 case 26: STS(26, val); break; alpha_read_fp_reg_s()
140 case 27: STS(27, val); break; alpha_read_fp_reg_s()
141 case 28: STS(28, val); break; alpha_read_fp_reg_s()
142 case 29: STS(29, val); break; alpha_read_fp_reg_s()
143 case 30: STS(30, val); break; alpha_read_fp_reg_s()
144 case 31: STS(31, val); break; alpha_read_fp_reg_s()
147 return val; alpha_read_fp_reg_s()
151 #define LDS(reg,val) asm volatile ("itofs %0,$f"#reg : : "r"(val));
153 #define LDS(reg,val) asm volatile ("lds $f"#reg",%0" : : "m"(val));
157 alpha_write_fp_reg_s (unsigned long reg, unsigned long val) alpha_write_fp_reg_s() argument
160 case 0: LDS( 0, val); break; alpha_write_fp_reg_s()
161 case 1: LDS( 1, val); break; alpha_write_fp_reg_s()
162 case 2: LDS( 2, val); break; alpha_write_fp_reg_s()
163 case 3: LDS( 3, val); break; alpha_write_fp_reg_s()
164 case 4: LDS( 4, val); break; alpha_write_fp_reg_s()
165 case 5: LDS( 5, val); break; alpha_write_fp_reg_s()
166 case 6: LDS( 6, val); break; alpha_write_fp_reg_s()
167 case 7: LDS( 7, val); break; alpha_write_fp_reg_s()
168 case 8: LDS( 8, val); break; alpha_write_fp_reg_s()
169 case 9: LDS( 9, val); break; alpha_write_fp_reg_s()
170 case 10: LDS(10, val); break; alpha_write_fp_reg_s()
171 case 11: LDS(11, val); break; alpha_write_fp_reg_s()
172 case 12: LDS(12, val); break; alpha_write_fp_reg_s()
173 case 13: LDS(13, val); break; alpha_write_fp_reg_s()
174 case 14: LDS(14, val); break; alpha_write_fp_reg_s()
175 case 15: LDS(15, val); break; alpha_write_fp_reg_s()
176 case 16: LDS(16, val); break; alpha_write_fp_reg_s()
177 case 17: LDS(17, val); break; alpha_write_fp_reg_s()
178 case 18: LDS(18, val); break; alpha_write_fp_reg_s()
179 case 19: LDS(19, val); break; alpha_write_fp_reg_s()
180 case 20: LDS(20, val); break; alpha_write_fp_reg_s()
181 case 21: LDS(21, val); break; alpha_write_fp_reg_s()
182 case 22: LDS(22, val); break; alpha_write_fp_reg_s()
183 case 23: LDS(23, val); break; alpha_write_fp_reg_s()
184 case 24: LDS(24, val); break; alpha_write_fp_reg_s()
185 case 25: LDS(25, val); break; alpha_write_fp_reg_s()
186 case 26: LDS(26, val); break; alpha_write_fp_reg_s()
187 case 27: LDS(27, val); break; alpha_write_fp_reg_s()
188 case 28: LDS(28, val); break; alpha_write_fp_reg_s()
189 case 29: LDS(29, val); break; alpha_write_fp_reg_s()
190 case 30: LDS(30, val); break; alpha_write_fp_reg_s()
191 case 31: LDS(31, val); break; alpha_write_fp_reg_s()
/linux-4.1.27/arch/blackfin/mach-bf533/include/mach/
H A DcdefBF532.h13 #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val)
15 #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val)
18 #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val)
23 #define bfin_write_SWRST(val) bfin_write16(SWRST,val)
25 #define bfin_write_SYSCR(val) bfin_write16(SYSCR,val)
27 #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val)
29 #define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1,val)
31 #define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2,val)
33 #define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3,val)
35 #define bfin_write_SIC_IMASK(val) bfin_write32(SIC_IMASK,val)
37 #define bfin_write_SIC_ISR(val) bfin_write32(SIC_ISR,val)
39 #define bfin_write_SIC_IWR(val) bfin_write32(SIC_IWR,val)
43 #define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL,val)
45 #define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT,val)
47 #define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT,val)
51 #define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT,val)
53 #define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL,val)
55 #define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT,val)
57 #define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT,val)
59 #define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM,val)
61 #define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST,val)
63 #define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN,val)
67 #define bfin_write_DMAC_TC_PER(val) bfin_write16(DMAC_TC_PER,val)
69 #define bfin_write_DMAC_TC_CNT(val) bfin_write16(DMAC_TC_CNT,val)
73 #define bfin_write_FIO_DIR(val) bfin_write16(FIO_DIR,val)
75 #define bfin_write_FIO_MASKA_C(val) bfin_write16(FIO_MASKA_C,val)
77 #define bfin_write_FIO_MASKA_S(val) bfin_write16(FIO_MASKA_S,val)
79 #define bfin_write_FIO_MASKB_C(val) bfin_write16(FIO_MASKB_C,val)
81 #define bfin_write_FIO_MASKB_S(val) bfin_write16(FIO_MASKB_S,val)
83 #define bfin_write_FIO_POLAR(val) bfin_write16(FIO_POLAR,val)
85 #define bfin_write_FIO_EDGE(val) bfin_write16(FIO_EDGE,val)
87 #define bfin_write_FIO_BOTH(val) bfin_write16(FIO_BOTH,val)
89 #define bfin_write_FIO_INEN(val) bfin_write16(FIO_INEN,val)
91 #define bfin_write_FIO_MASKA_D(val) bfin_write16(FIO_MASKA_D,val)
93 #define bfin_write_FIO_MASKA_T(val) bfin_write16(FIO_MASKA_T,val)
95 #define bfin_write_FIO_MASKB_D(val) bfin_write16(FIO_MASKB_D,val)
97 #define bfin_write_FIO_MASKB_T(val) bfin_write16(FIO_MASKB_T,val)
101 #define BFIN_WRITE_FIO_FLAG(name, val) \
105 bfin_write16(FIO_FLAG_##name, val); \
109 #define bfin_write_FIO_FLAG_D(val) BFIN_WRITE_FIO_FLAG(D, val)
110 #define bfin_write_FIO_FLAG_C(val) BFIN_WRITE_FIO_FLAG(C, val)
111 #define bfin_write_FIO_FLAG_S(val) BFIN_WRITE_FIO_FLAG(S, val)
112 #define bfin_write_FIO_FLAG_T(val) BFIN_WRITE_FIO_FLAG(T, val)
130 #define bfin_write_FIO_FLAG_D(val) bfin_write16(FIO_FLAG_D, val)
131 #define bfin_write_FIO_FLAG_C(val) bfin_write16(FIO_FLAG_C, val)
132 #define bfin_write_FIO_FLAG_S(val) bfin_write16(FIO_FLAG_S, val)
133 #define bfin_write_FIO_FLAG_T(val) bfin_write16(FIO_FLAG_T, val)
142 #define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG,val)
144 #define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR,val)
146 #define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR,val)
148 #define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT,val)
150 #define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT,val)
152 #define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY,val)
154 #define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY,val)
156 #define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR,val)
158 #define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR,val)
160 #define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT,val)
162 #define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT,val)
164 #define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS,val)
166 #define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP,val)
169 #define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG,val)
171 #define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR,val)
173 #define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR,val)
175 #define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT,val)
177 #define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT,val)
179 #define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY,val)
181 #define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY,val)
183 #define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR,val)
185 #define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR,val)
187 #define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT,val)
189 #define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT,val)
191 #define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS,val)
193 #define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP,val)
196 #define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG,val)
198 #define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR,val)
200 #define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR,val)
202 #define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT,val)
204 #define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT,val)
206 #define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY,val)
208 #define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY,val)
210 #define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR,val)
212 #define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR,val)
214 #define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT,val)
216 #define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT,val)
218 #define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS,val)
220 #define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP,val)
223 #define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG,val)
225 #define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR,val)
227 #define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR,val)
229 #define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT,val)
231 #define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT,val)
233 #define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY,val)
235 #define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY,val)
237 #define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR,val)
239 #define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR,val)
241 #define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT,val)
243 #define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT,val)
245 #define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS,val)
247 #define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP,val)
250 #define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG,val)
252 #define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR,val)
254 #define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR,val)
256 #define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT,val)
258 #define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT,val)
260 #define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY,val)
262 #define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY,val)
264 #define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR,val)
266 #define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR,val)
268 #define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT,val)
270 #define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT,val)
272 #define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS,val)
274 #define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP,val)
277 #define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG,val)
279 #define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR,val)
281 #define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR,val)
283 #define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT,val)
285 #define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT,val)
287 #define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY,val)
289 #define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY,val)
291 #define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR,val)
293 #define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR,val)
295 #define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT,val)
297 #define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT,val)
299 #define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS,val)
301 #define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP,val)
304 #define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG,val)
306 #define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR,val)
308 #define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR,val)
310 #define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT,val)
312 #define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT,val)
314 #define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY,val)
316 #define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY,val)
318 #define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR,val)
320 #define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR,val)
322 #define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT,val)
324 #define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT,val)
326 #define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS,val)
328 #define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP,val)
331 #define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG,val)
333 #define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR,val)
335 #define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR,val)
337 #define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT,val)
339 #define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT,val)
341 #define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY,val)
343 #define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY,val)
345 #define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR,val)
347 #define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR,val)
349 #define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT,val)
351 #define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT,val)
353 #define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS,val)
355 #define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP,val)
358 #define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG,val)
360 #define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR,val)
362 #define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR,val)
364 #define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT,val)
366 #define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT,val)
368 #define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY,val)
370 #define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY,val)
372 #define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR,val)
374 #define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR,val)
376 #define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT,val)
378 #define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT,val)
380 #define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS,val)
382 #define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP,val)
385 #define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG,val)
387 #define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR,val)
389 #define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR,val)
391 #define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT,val)
393 #define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT,val)
395 #define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY,val)
397 #define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY,val)
399 #define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR,val)
401 #define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR,val)
403 #define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT,val)
405 #define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT,val)
407 #define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS,val)
409 #define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP,val)
412 #define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG,val)
414 #define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR,val)
416 #define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR,val)
418 #define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT,val)
420 #define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT,val)
422 #define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY,val)
424 #define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY,val)
426 #define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR,val)
428 #define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR,val)
430 #define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT,val)
432 #define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT,val)
434 #define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS,val)
436 #define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP,val)
439 #define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG,val)
441 #define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR,val)
443 #define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR,val)
445 #define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT,val)
447 #define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT,val)
449 #define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY,val)
451 #define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY,val)
453 #define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR,val)
455 #define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR,val)
457 #define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT,val)
459 #define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT,val)
461 #define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS,val)
463 #define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP,val)
467 #define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL,val)
469 #define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0,val)
471 #define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1,val)
475 #define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL,val)
477 #define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC,val)
479 #define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT,val)
481 #define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL,val)
485 #define bfin_write_UART_THR(val) bfin_write16(UART_THR,val)
487 #define bfin_write_UART_RBR(val) bfin_write16(UART_RBR,val)
489 #define bfin_write_UART_DLL(val) bfin_write16(UART_DLL,val)
491 #define bfin_write_UART_IER(val) bfin_write16(UART_IER,val)
493 #define bfin_write_UART_DLH(val) bfin_write16(UART_DLH,val)
495 #define bfin_write_UART_IIR(val) bfin_write16(UART_IIR,val)
497 #define bfin_write_UART_LCR(val) bfin_write16(UART_LCR,val)
499 #define bfin_write_UART_MCR(val) bfin_write16(UART_MCR,val)
501 #define bfin_write_UART_LSR(val) bfin_write16(UART_LSR,val)
506 #define bfin_write_UART_SCR(val) bfin_write16(UART_SCR,val)
508 #define bfin_write_UART_GCTL(val) bfin_write16(UART_GCTL,val)
512 #define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL,val)
514 #define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG,val)
516 #define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT,val)
518 #define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR,val)
520 #define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR,val)
522 #define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD,val)
524 #define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW,val)
528 #define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG,val)
530 #define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER,val)
532 #define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD,val)
534 #define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH,val)
537 #define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG,val)
539 #define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER,val)
541 #define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD,val)
543 #define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH,val)
546 #define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG,val)
548 #define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER,val)
550 #define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD,val)
552 #define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH,val)
555 #define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE,val)
557 #define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE,val)
559 #define bfin_write_TIMER_STATUS(val) bfin_write16(TIMER_STATUS,val)
563 #define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1,val)
565 #define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2,val)
567 #define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV,val)
569 #define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV,val)
571 #define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX,val)
573 #define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX,val)
575 #define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX,val)
577 #define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX,val)
579 #define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX,val)
581 #define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX,val)
583 #define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1,val)
585 #define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2,val)
587 #define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV,val)
589 #define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV,val)
591 #define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT,val)
593 #define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL,val)
595 #define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1,val)
597 #define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2,val)
599 #define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0,val)
601 #define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1,val)
603 #define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2,val)
605 #define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3,val)
607 #define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0,val)
609 #define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1,val)
611 #define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2,val)
613 #define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3,val)
617 #define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1,val)
619 #define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2,val)
621 #define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV,val)
623 #define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV,val)
625 #define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX,val)
627 #define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX,val)
629 #define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX,val)
631 #define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX,val)
633 #define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX,val)
635 #define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX,val)
637 #define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1,val)
639 #define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2,val)
641 #define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV,val)
643 #define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV,val)
645 #define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT,val)
647 #define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL,val)
649 #define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1,val)
651 #define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2,val)
653 #define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0,val)
655 #define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1,val)
657 #define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2,val)
659 #define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3,val)
661 #define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0,val)
663 #define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1,val)
665 #define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2,val)
667 #define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3,val)
671 #define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL,val)
673 #define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS,val)
676 #define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY,val)
678 #define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT,val)
680 #define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME,val)
/linux-4.1.27/arch/blackfin/include/asm/
H A Dcdef_LPBlackfin.h18 #define bfin_write_SRAM_BASE_ADDRESS(val) bfin_write32(SRAM_BASE_ADDRESS,val)
20 #define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL,val)
22 #define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS,val)
24 #define bfin_write_DCPLB_FAULT_ADDR(val) bfin_write32(DCPLB_FAULT_ADDR,val)
29 #define bfin_write_DCPLB_ADDR0(val) bfin_write32(DCPLB_ADDR0,val)
31 #define bfin_write_DCPLB_ADDR1(val) bfin_write32(DCPLB_ADDR1,val)
33 #define bfin_write_DCPLB_ADDR2(val) bfin_write32(DCPLB_ADDR2,val)
35 #define bfin_write_DCPLB_ADDR3(val) bfin_write32(DCPLB_ADDR3,val)
37 #define bfin_write_DCPLB_ADDR4(val) bfin_write32(DCPLB_ADDR4,val)
39 #define bfin_write_DCPLB_ADDR5(val) bfin_write32(DCPLB_ADDR5,val)
41 #define bfin_write_DCPLB_ADDR6(val) bfin_write32(DCPLB_ADDR6,val)
43 #define bfin_write_DCPLB_ADDR7(val) bfin_write32(DCPLB_ADDR7,val)
45 #define bfin_write_DCPLB_ADDR8(val) bfin_write32(DCPLB_ADDR8,val)
47 #define bfin_write_DCPLB_ADDR9(val) bfin_write32(DCPLB_ADDR9,val)
49 #define bfin_write_DCPLB_ADDR10(val) bfin_write32(DCPLB_ADDR10,val)
51 #define bfin_write_DCPLB_ADDR11(val) bfin_write32(DCPLB_ADDR11,val)
53 #define bfin_write_DCPLB_ADDR12(val) bfin_write32(DCPLB_ADDR12,val)
55 #define bfin_write_DCPLB_ADDR13(val) bfin_write32(DCPLB_ADDR13,val)
57 #define bfin_write_DCPLB_ADDR14(val) bfin_write32(DCPLB_ADDR14,val)
59 #define bfin_write_DCPLB_ADDR15(val) bfin_write32(DCPLB_ADDR15,val)
61 #define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0,val)
63 #define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1,val)
65 #define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2,val)
67 #define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3,val)
69 #define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4,val)
71 #define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5,val)
73 #define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6,val)
75 #define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7,val)
77 #define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8,val)
79 #define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9,val)
81 #define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10,val)
83 #define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11,val)
85 #define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12,val)
87 #define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13,val)
89 #define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14,val)
91 #define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15,val)
93 #define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND,val)
98 #define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0,val)
100 #define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1,val)
106 #define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL,val)
108 #define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS,val)
110 #define bfin_write_ICPLB_FAULT_ADDR(val) bfin_write32(ICPLB_FAULT_ADDR,val)
112 #define bfin_write_ICPLB_ADDR0(val) bfin_write32(ICPLB_ADDR0,val)
114 #define bfin_write_ICPLB_ADDR1(val) bfin_write32(ICPLB_ADDR1,val)
116 #define bfin_write_ICPLB_ADDR2(val) bfin_write32(ICPLB_ADDR2,val)
118 #define bfin_write_ICPLB_ADDR3(val) bfin_write32(ICPLB_ADDR3,val)
120 #define bfin_write_ICPLB_ADDR4(val) bfin_write32(ICPLB_ADDR4,val)
122 #define bfin_write_ICPLB_ADDR5(val) bfin_write32(ICPLB_ADDR5,val)
124 #define bfin_write_ICPLB_ADDR6(val) bfin_write32(ICPLB_ADDR6,val)
126 #define bfin_write_ICPLB_ADDR7(val) bfin_write32(ICPLB_ADDR7,val)
128 #define bfin_write_ICPLB_ADDR8(val) bfin_write32(ICPLB_ADDR8,val)
130 #define bfin_write_ICPLB_ADDR9(val) bfin_write32(ICPLB_ADDR9,val)
132 #define bfin_write_ICPLB_ADDR10(val) bfin_write32(ICPLB_ADDR10,val)
134 #define bfin_write_ICPLB_ADDR11(val) bfin_write32(ICPLB_ADDR11,val)
136 #define bfin_write_ICPLB_ADDR12(val) bfin_write32(ICPLB_ADDR12,val)
138 #define bfin_write_ICPLB_ADDR13(val) bfin_write32(ICPLB_ADDR13,val)
140 #define bfin_write_ICPLB_ADDR14(val) bfin_write32(ICPLB_ADDR14,val)
142 #define bfin_write_ICPLB_ADDR15(val) bfin_write32(ICPLB_ADDR15,val)
144 #define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0,val)
146 #define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1,val)
148 #define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2,val)
150 #define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3,val)
152 #define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4,val)
154 #define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5,val)
156 #define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6,val)
158 #define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7,val)
160 #define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8,val)
162 #define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9,val)
164 #define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10,val)
166 #define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11,val)
168 #define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12,val)
170 #define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13,val)
172 #define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14,val)
174 #define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15,val)
175 #define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND,val)
179 #define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0,val)
180 #define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1,val)
191 #define bfin_write_EVT0(val) bfin_write32(EVT0,val)
193 #define bfin_write_EVT1(val) bfin_write32(EVT1,val)
195 #define bfin_write_EVT2(val) bfin_write32(EVT2,val)
197 #define bfin_write_EVT3(val) bfin_write32(EVT3,val)
199 #define bfin_write_EVT4(val) bfin_write32(EVT4,val)
201 #define bfin_write_EVT5(val) bfin_write32(EVT5,val)
203 #define bfin_write_EVT6(val) bfin_write32(EVT6,val)
205 #define bfin_write_EVT7(val) bfin_write32(EVT7,val)
207 #define bfin_write_EVT8(val) bfin_write32(EVT8,val)
209 #define bfin_write_EVT9(val) bfin_write32(EVT9,val)
211 #define bfin_write_EVT10(val) bfin_write32(EVT10,val)
213 #define bfin_write_EVT11(val) bfin_write32(EVT11,val)
215 #define bfin_write_EVT12(val) bfin_write32(EVT12,val)
217 #define bfin_write_EVT13(val) bfin_write32(EVT13,val)
219 #define bfin_write_EVT14(val) bfin_write32(EVT14,val)
221 #define bfin_write_EVT15(val) bfin_write32(EVT15,val)
223 #define bfin_write_EVT_OVERRIDE(val) bfin_write32(EVT_OVERRIDE,val)
225 #define bfin_write_IMASK(val) bfin_write32(IMASK,val)
227 #define bfin_write_IPEND(val) bfin_write32(IPEND,val)
229 #define bfin_write_ILAT(val) bfin_write32(ILAT,val)
231 #define bfin_write_IPRIO(val) bfin_write32(IPRIO,val)
235 #define bfin_write_TCNTL(val) bfin_write32(TCNTL,val)
237 #define bfin_write_TPERIOD(val) bfin_write32(TPERIOD,val)
239 #define bfin_write_TSCALE(val) bfin_write32(TSCALE,val)
241 #define bfin_write_TCOUNT(val) bfin_write32(TCOUNT,val)
245 #define bfin_write_DSPID(val) bfin_write32(DSPID,val)
247 #define bfin_write_DBGCTL(val) bfin_write32(DBGCTL,val)
249 #define bfin_write_DBGSTAT(val) bfin_write32(DBGSTAT,val)
251 #define bfin_write_EMUDAT(val) bfin_write32(EMUDAT,val)
255 #define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL,val)
257 #define bfin_write_TBUFSTAT(val) bfin_write32(TBUFSTAT,val)
259 #define bfin_write_TBUF(val) bfin_write32(TBUF,val)
263 #define bfin_write_WPIACTL(val) bfin_write32(WPIACTL,val)
265 #define bfin_write_WPIA0(val) bfin_write32(WPIA0,val)
267 #define bfin_write_WPIA1(val) bfin_write32(WPIA1,val)
269 #define bfin_write_WPIA2(val) bfin_write32(WPIA2,val)
271 #define bfin_write_WPIA3(val) bfin_write32(WPIA3,val)
273 #define bfin_write_WPIA4(val) bfin_write32(WPIA4,val)
275 #define bfin_write_WPIA5(val) bfin_write32(WPIA5,val)
277 #define bfin_write_WPIACNT0(val) bfin_write32(WPIACNT0,val)
279 #define bfin_write_WPIACNT1(val) bfin_write32(WPIACNT1,val)
281 #define bfin_write_WPIACNT2(val) bfin_write32(WPIACNT2,val)
283 #define bfin_write_WPIACNT3(val) bfin_write32(WPIACNT3,val)
285 #define bfin_write_WPIACNT4(val) bfin_write32(WPIACNT4,val)
287 #define bfin_write_WPIACNT5(val) bfin_write32(WPIACNT5,val)
289 #define bfin_write_WPDACTL(val) bfin_write32(WPDACTL,val)
291 #define bfin_write_WPDA0(val) bfin_write32(WPDA0,val)
293 #define bfin_write_WPDA1(val) bfin_write32(WPDA1,val)
295 #define bfin_write_WPDACNT0(val) bfin_write32(WPDACNT0,val)
297 #define bfin_write_WPDACNT1(val) bfin_write32(WPDACNT1,val)
299 #define bfin_write_WPSTAT(val) bfin_write32(WPSTAT,val)
303 #define bfin_write_PFCTL(val) bfin_write32(PFCTL,val)
305 #define bfin_write_PFCNTR0(val) bfin_write32(PFCNTR0,val)
307 #define bfin_write_PFCNTR1(val) bfin_write32(PFCNTR1,val)
/linux-4.1.27/arch/x86/include/uapi/asm/
H A Dswab.h7 static inline __attribute_const__ __u32 __arch_swab32(__u32 val) __arch_swab32() argument
9 asm("bswapl %0" : "=r" (val) : "0" (val)); __arch_swab32()
10 return val; __arch_swab32()
14 static inline __attribute_const__ __u64 __arch_swab64(__u64 val) __arch_swab64() argument
24 v.u = val; __arch_swab64()
30 asm("bswapq %0" : "=r" (val) : "0" (val)); __arch_swab64()
31 return val; __arch_swab64()
/linux-4.1.27/drivers/hwtracing/coresight/
H A Dcoresight-etm-cp14.c22 int etm_readl_cp14(u32 reg, unsigned int *val) etm_readl_cp14() argument
26 *val = etm_read(ETMCR); etm_readl_cp14()
29 *val = etm_read(ETMCCR); etm_readl_cp14()
32 *val = etm_read(ETMTRIGGER); etm_readl_cp14()
35 *val = etm_read(ETMSR); etm_readl_cp14()
38 *val = etm_read(ETMSCR); etm_readl_cp14()
41 *val = etm_read(ETMTSSCR); etm_readl_cp14()
44 *val = etm_read(ETMTEEVR); etm_readl_cp14()
47 *val = etm_read(ETMTECR1); etm_readl_cp14()
50 *val = etm_read(ETMFFLR); etm_readl_cp14()
53 *val = etm_read(ETMACVR0); etm_readl_cp14()
56 *val = etm_read(ETMACVR1); etm_readl_cp14()
59 *val = etm_read(ETMACVR2); etm_readl_cp14()
62 *val = etm_read(ETMACVR3); etm_readl_cp14()
65 *val = etm_read(ETMACVR4); etm_readl_cp14()
68 *val = etm_read(ETMACVR5); etm_readl_cp14()
71 *val = etm_read(ETMACVR6); etm_readl_cp14()
74 *val = etm_read(ETMACVR7); etm_readl_cp14()
77 *val = etm_read(ETMACVR8); etm_readl_cp14()
80 *val = etm_read(ETMACVR9); etm_readl_cp14()
83 *val = etm_read(ETMACVR10); etm_readl_cp14()
86 *val = etm_read(ETMACVR11); etm_readl_cp14()
89 *val = etm_read(ETMACVR12); etm_readl_cp14()
92 *val = etm_read(ETMACVR13); etm_readl_cp14()
95 *val = etm_read(ETMACVR14); etm_readl_cp14()
98 *val = etm_read(ETMACVR15); etm_readl_cp14()
101 *val = etm_read(ETMACTR0); etm_readl_cp14()
104 *val = etm_read(ETMACTR1); etm_readl_cp14()
107 *val = etm_read(ETMACTR2); etm_readl_cp14()
110 *val = etm_read(ETMACTR3); etm_readl_cp14()
113 *val = etm_read(ETMACTR4); etm_readl_cp14()
116 *val = etm_read(ETMACTR5); etm_readl_cp14()
119 *val = etm_read(ETMACTR6); etm_readl_cp14()
122 *val = etm_read(ETMACTR7); etm_readl_cp14()
125 *val = etm_read(ETMACTR8); etm_readl_cp14()
128 *val = etm_read(ETMACTR9); etm_readl_cp14()
131 *val = etm_read(ETMACTR10); etm_readl_cp14()
134 *val = etm_read(ETMACTR11); etm_readl_cp14()
137 *val = etm_read(ETMACTR12); etm_readl_cp14()
140 *val = etm_read(ETMACTR13); etm_readl_cp14()
143 *val = etm_read(ETMACTR14); etm_readl_cp14()
146 *val = etm_read(ETMACTR15); etm_readl_cp14()
149 *val = etm_read(ETMCNTRLDVR0); etm_readl_cp14()
152 *val = etm_read(ETMCNTRLDVR1); etm_readl_cp14()
155 *val = etm_read(ETMCNTRLDVR2); etm_readl_cp14()
158 *val = etm_read(ETMCNTRLDVR3); etm_readl_cp14()
161 *val = etm_read(ETMCNTENR0); etm_readl_cp14()
164 *val = etm_read(ETMCNTENR1); etm_readl_cp14()
167 *val = etm_read(ETMCNTENR2); etm_readl_cp14()
170 *val = etm_read(ETMCNTENR3); etm_readl_cp14()
173 *val = etm_read(ETMCNTRLDEVR0); etm_readl_cp14()
176 *val = etm_read(ETMCNTRLDEVR1); etm_readl_cp14()
179 *val = etm_read(ETMCNTRLDEVR2); etm_readl_cp14()
182 *val = etm_read(ETMCNTRLDEVR3); etm_readl_cp14()
185 *val = etm_read(ETMCNTVR0); etm_readl_cp14()
188 *val = etm_read(ETMCNTVR1); etm_readl_cp14()
191 *val = etm_read(ETMCNTVR2); etm_readl_cp14()
194 *val = etm_read(ETMCNTVR3); etm_readl_cp14()
197 *val = etm_read(ETMSQ12EVR); etm_readl_cp14()
200 *val = etm_read(ETMSQ21EVR); etm_readl_cp14()
203 *val = etm_read(ETMSQ23EVR); etm_readl_cp14()
206 *val = etm_read(ETMSQ31EVR); etm_readl_cp14()
209 *val = etm_read(ETMSQ32EVR); etm_readl_cp14()
212 *val = etm_read(ETMSQ13EVR); etm_readl_cp14()
215 *val = etm_read(ETMSQR); etm_readl_cp14()
218 *val = etm_read(ETMEXTOUTEVR0); etm_readl_cp14()
221 *val = etm_read(ETMEXTOUTEVR1); etm_readl_cp14()
224 *val = etm_read(ETMEXTOUTEVR2); etm_readl_cp14()
227 *val = etm_read(ETMEXTOUTEVR3); etm_readl_cp14()
230 *val = etm_read(ETMCIDCVR0); etm_readl_cp14()
233 *val = etm_read(ETMCIDCVR1); etm_readl_cp14()
236 *val = etm_read(ETMCIDCVR2); etm_readl_cp14()
239 *val = etm_read(ETMCIDCMR); etm_readl_cp14()
242 *val = etm_read(ETMIMPSPEC0); etm_readl_cp14()
245 *val = etm_read(ETMIMPSPEC1); etm_readl_cp14()
248 *val = etm_read(ETMIMPSPEC2); etm_readl_cp14()
251 *val = etm_read(ETMIMPSPEC3); etm_readl_cp14()
254 *val = etm_read(ETMIMPSPEC4); etm_readl_cp14()
257 *val = etm_read(ETMIMPSPEC5); etm_readl_cp14()
260 *val = etm_read(ETMIMPSPEC6); etm_readl_cp14()
263 *val = etm_read(ETMIMPSPEC7); etm_readl_cp14()
266 *val = etm_read(ETMSYNCFR); etm_readl_cp14()
269 *val = etm_read(ETMIDR); etm_readl_cp14()
272 *val = etm_read(ETMCCER); etm_readl_cp14()
275 *val = etm_read(ETMEXTINSELR); etm_readl_cp14()
278 *val = etm_read(ETMTESSEICR); etm_readl_cp14()
281 *val = etm_read(ETMEIBCR); etm_readl_cp14()
284 *val = etm_read(ETMTSEVR); etm_readl_cp14()
287 *val = etm_read(ETMAUXCR); etm_readl_cp14()
290 *val = etm_read(ETMTRACEIDR); etm_readl_cp14()
293 *val = etm_read(ETMVMIDCVR); etm_readl_cp14()
296 *val = etm_read(ETMOSLSR); etm_readl_cp14()
299 *val = etm_read(ETMOSSRR); etm_readl_cp14()
302 *val = etm_read(ETMPDCR); etm_readl_cp14()
305 *val = etm_read(ETMPDSR); etm_readl_cp14()
308 *val = 0; etm_readl_cp14()
313 int etm_writel_cp14(u32 reg, u32 val) etm_writel_cp14() argument
317 etm_write(val, ETMCR); etm_writel_cp14()
320 etm_write(val, ETMTRIGGER); etm_writel_cp14()
323 etm_write(val, ETMSR); etm_writel_cp14()
326 etm_write(val, ETMTSSCR); etm_writel_cp14()
329 etm_write(val, ETMTEEVR); etm_writel_cp14()
332 etm_write(val, ETMTECR1); etm_writel_cp14()
335 etm_write(val, ETMFFLR); etm_writel_cp14()
338 etm_write(val, ETMACVR0); etm_writel_cp14()
341 etm_write(val, ETMACVR1); etm_writel_cp14()
344 etm_write(val, ETMACVR2); etm_writel_cp14()
347 etm_write(val, ETMACVR3); etm_writel_cp14()
350 etm_write(val, ETMACVR4); etm_writel_cp14()
353 etm_write(val, ETMACVR5); etm_writel_cp14()
356 etm_write(val, ETMACVR6); etm_writel_cp14()
359 etm_write(val, ETMACVR7); etm_writel_cp14()
362 etm_write(val, ETMACVR8); etm_writel_cp14()
365 etm_write(val, ETMACVR9); etm_writel_cp14()
368 etm_write(val, ETMACVR10); etm_writel_cp14()
371 etm_write(val, ETMACVR11); etm_writel_cp14()
374 etm_write(val, ETMACVR12); etm_writel_cp14()
377 etm_write(val, ETMACVR13); etm_writel_cp14()
380 etm_write(val, ETMACVR14); etm_writel_cp14()
383 etm_write(val, ETMACVR15); etm_writel_cp14()
386 etm_write(val, ETMACTR0); etm_writel_cp14()
389 etm_write(val, ETMACTR1); etm_writel_cp14()
392 etm_write(val, ETMACTR2); etm_writel_cp14()
395 etm_write(val, ETMACTR3); etm_writel_cp14()
398 etm_write(val, ETMACTR4); etm_writel_cp14()
401 etm_write(val, ETMACTR5); etm_writel_cp14()
404 etm_write(val, ETMACTR6); etm_writel_cp14()
407 etm_write(val, ETMACTR7); etm_writel_cp14()
410 etm_write(val, ETMACTR8); etm_writel_cp14()
413 etm_write(val, ETMACTR9); etm_writel_cp14()
416 etm_write(val, ETMACTR10); etm_writel_cp14()
419 etm_write(val, ETMACTR11); etm_writel_cp14()
422 etm_write(val, ETMACTR12); etm_writel_cp14()
425 etm_write(val, ETMACTR13); etm_writel_cp14()
428 etm_write(val, ETMACTR14); etm_writel_cp14()
431 etm_write(val, ETMACTR15); etm_writel_cp14()
434 etm_write(val, ETMCNTRLDVR0); etm_writel_cp14()
437 etm_write(val, ETMCNTRLDVR1); etm_writel_cp14()
440 etm_write(val, ETMCNTRLDVR2); etm_writel_cp14()
443 etm_write(val, ETMCNTRLDVR3); etm_writel_cp14()
446 etm_write(val, ETMCNTENR0); etm_writel_cp14()
449 etm_write(val, ETMCNTENR1); etm_writel_cp14()
452 etm_write(val, ETMCNTENR2); etm_writel_cp14()
455 etm_write(val, ETMCNTENR3); etm_writel_cp14()
458 etm_write(val, ETMCNTRLDEVR0); etm_writel_cp14()
461 etm_write(val, ETMCNTRLDEVR1); etm_writel_cp14()
464 etm_write(val, ETMCNTRLDEVR2); etm_writel_cp14()
467 etm_write(val, ETMCNTRLDEVR3); etm_writel_cp14()
470 etm_write(val, ETMCNTVR0); etm_writel_cp14()
473 etm_write(val, ETMCNTVR1); etm_writel_cp14()
476 etm_write(val, ETMCNTVR2); etm_writel_cp14()
479 etm_write(val, ETMCNTVR3); etm_writel_cp14()
482 etm_write(val, ETMSQ12EVR); etm_writel_cp14()
485 etm_write(val, ETMSQ21EVR); etm_writel_cp14()
488 etm_write(val, ETMSQ23EVR); etm_writel_cp14()
491 etm_write(val, ETMSQ31EVR); etm_writel_cp14()
494 etm_write(val, ETMSQ32EVR); etm_writel_cp14()
497 etm_write(val, ETMSQ13EVR); etm_writel_cp14()
500 etm_write(val, ETMSQR); etm_writel_cp14()
503 etm_write(val, ETMEXTOUTEVR0); etm_writel_cp14()
506 etm_write(val, ETMEXTOUTEVR1); etm_writel_cp14()
509 etm_write(val, ETMEXTOUTEVR2); etm_writel_cp14()
512 etm_write(val, ETMEXTOUTEVR3); etm_writel_cp14()
515 etm_write(val, ETMCIDCVR0); etm_writel_cp14()
518 etm_write(val, ETMCIDCVR1); etm_writel_cp14()
521 etm_write(val, ETMCIDCVR2); etm_writel_cp14()
524 etm_write(val, ETMCIDCMR); etm_writel_cp14()
527 etm_write(val, ETMIMPSPEC0); etm_writel_cp14()
530 etm_write(val, ETMIMPSPEC1); etm_writel_cp14()
533 etm_write(val, ETMIMPSPEC2); etm_writel_cp14()
536 etm_write(val, ETMIMPSPEC3); etm_writel_cp14()
539 etm_write(val, ETMIMPSPEC4); etm_writel_cp14()
542 etm_write(val, ETMIMPSPEC5); etm_writel_cp14()
545 etm_write(val, ETMIMPSPEC6); etm_writel_cp14()
548 etm_write(val, ETMIMPSPEC7); etm_writel_cp14()
551 etm_write(val, ETMSYNCFR); etm_writel_cp14()
554 etm_write(val, ETMEXTINSELR); etm_writel_cp14()
557 etm_write(val, ETMTESSEICR); etm_writel_cp14()
560 etm_write(val, ETMEIBCR); etm_writel_cp14()
563 etm_write(val, ETMTSEVR); etm_writel_cp14()
566 etm_write(val, ETMAUXCR); etm_writel_cp14()
569 etm_write(val, ETMTRACEIDR); etm_writel_cp14()
572 etm_write(val, ETMVMIDCVR); etm_writel_cp14()
575 etm_write(val, ETMOSLAR); etm_writel_cp14()
578 etm_write(val, ETMOSSRR); etm_writel_cp14()
581 etm_write(val, ETMPDCR); etm_writel_cp14()
584 etm_write(val, ETMPDSR); etm_writel_cp14()
H A Dcoresight-etm3x.c45 u32 val, u32 off) etm_writel()
48 if (etm_writel_cp14(off, val)) { etm_writel()
53 writel_relaxed(val, drvdata->base + off); etm_writel()
59 u32 val; etm_readl() local
62 if (etm_readl_cp14(off, &val)) { etm_readl()
67 val = readl_relaxed(drvdata->base + off); etm_readl()
70 return val; etm_readl()
152 u32 val; coresight_timeout_etm() local
155 val = etm_readl(drvdata, offset); coresight_timeout_etm()
158 if (val & BIT(position)) coresight_timeout_etm()
162 if (!(val & BIT(position))) coresight_timeout_etm()
445 unsigned long val; nr_addr_cmp_show() local
448 val = drvdata->nr_addr_cmp; nr_addr_cmp_show()
449 return sprintf(buf, "%#lx\n", val); nr_addr_cmp_show()
455 { unsigned long val; nr_cntr_show() local
458 val = drvdata->nr_cntr; nr_cntr_show()
459 return sprintf(buf, "%#lx\n", val); nr_cntr_show()
466 unsigned long val; nr_ctxid_cmp_show() local
469 val = drvdata->nr_ctxid_cmp; nr_ctxid_cmp_show()
470 return sprintf(buf, "%#lx\n", val); nr_ctxid_cmp_show()
478 unsigned long flags, val; etmsr_show() local
488 val = etm_readl(drvdata, ETMSR); etmsr_show()
494 return sprintf(buf, "%#lx\n", val); etmsr_show()
503 unsigned long val; reset_store() local
506 ret = kstrtoul(buf, 16, &val); reset_store()
510 if (val) { reset_store()
535 unsigned long val; mode_show() local
538 val = drvdata->mode; mode_show()
539 return sprintf(buf, "%#lx\n", val); mode_show()
547 unsigned long val; mode_store() local
550 ret = kstrtoul(buf, 16, &val); mode_store()
555 drvdata->mode = val & ETM_MODE_ALL; mode_store()
604 unsigned long val; trigger_event_show() local
607 val = drvdata->trigger_event; trigger_event_show()
608 return sprintf(buf, "%#lx\n", val); trigger_event_show()
616 unsigned long val; trigger_event_store() local
619 ret = kstrtoul(buf, 16, &val); trigger_event_store()
623 drvdata->trigger_event = val & ETM_EVENT_MASK; trigger_event_store()
632 unsigned long val; enable_event_show() local
635 val = drvdata->enable_event; enable_event_show()
636 return sprintf(buf, "%#lx\n", val); enable_event_show()
644 unsigned long val; enable_event_store() local
647 ret = kstrtoul(buf, 16, &val); enable_event_store()
651 drvdata->enable_event = val & ETM_EVENT_MASK; enable_event_store()
660 unsigned long val; fifofull_level_show() local
663 val = drvdata->fifofull_level; fifofull_level_show()
664 return sprintf(buf, "%#lx\n", val); fifofull_level_show()
672 unsigned long val; fifofull_level_store() local
675 ret = kstrtoul(buf, 16, &val); fifofull_level_store()
679 drvdata->fifofull_level = val; fifofull_level_store()
688 unsigned long val; addr_idx_show() local
691 val = drvdata->addr_idx; addr_idx_show()
692 return sprintf(buf, "%#lx\n", val); addr_idx_show()
700 unsigned long val; addr_idx_store() local
703 ret = kstrtoul(buf, 16, &val); addr_idx_store()
707 if (val >= drvdata->nr_addr_cmp) addr_idx_store()
715 drvdata->addr_idx = val; addr_idx_store()
726 unsigned long val; addr_single_show() local
737 val = drvdata->addr_val[idx]; addr_single_show()
740 return sprintf(buf, "%#lx\n", val); addr_single_show()
749 unsigned long val; addr_single_store() local
752 ret = kstrtoul(buf, 16, &val); addr_single_store()
764 drvdata->addr_val[idx] = val; addr_single_store()
843 unsigned long val; addr_start_show() local
854 val = drvdata->addr_val[idx]; addr_start_show()
857 return sprintf(buf, "%#lx\n", val); addr_start_show()
866 unsigned long val; addr_start_store() local
869 ret = kstrtoul(buf, 16, &val); addr_start_store()
881 drvdata->addr_val[idx] = val; addr_start_store()
895 unsigned long val; addr_stop_show() local
906 val = drvdata->addr_val[idx]; addr_stop_show()
909 return sprintf(buf, "%#lx\n", val); addr_stop_show()
918 unsigned long val; addr_stop_store() local
921 ret = kstrtoul(buf, 16, &val); addr_stop_store()
933 drvdata->addr_val[idx] = val; addr_stop_store()
946 unsigned long val; addr_acctype_show() local
950 val = drvdata->addr_acctype[drvdata->addr_idx]; addr_acctype_show()
953 return sprintf(buf, "%#lx\n", val); addr_acctype_show()
961 unsigned long val; addr_acctype_store() local
964 ret = kstrtoul(buf, 16, &val); addr_acctype_store()
969 drvdata->addr_acctype[drvdata->addr_idx] = val; addr_acctype_store()
979 unsigned long val; cntr_idx_show() local
982 val = drvdata->cntr_idx; cntr_idx_show()
983 return sprintf(buf, "%#lx\n", val); cntr_idx_show()
991 unsigned long val; cntr_idx_store() local
994 ret = kstrtoul(buf, 16, &val); cntr_idx_store()
998 if (val >= drvdata->nr_cntr) cntr_idx_store()
1005 drvdata->cntr_idx = val; cntr_idx_store()
1015 unsigned long val; cntr_rld_val_show() local
1019 val = drvdata->cntr_rld_val[drvdata->cntr_idx]; cntr_rld_val_show()
1022 return sprintf(buf, "%#lx\n", val); cntr_rld_val_show()
1030 unsigned long val; cntr_rld_val_store() local
1033 ret = kstrtoul(buf, 16, &val); cntr_rld_val_store()
1038 drvdata->cntr_rld_val[drvdata->cntr_idx] = val; cntr_rld_val_store()
1048 unsigned long val; cntr_event_show() local
1052 val = drvdata->cntr_event[drvdata->cntr_idx]; cntr_event_show()
1055 return sprintf(buf, "%#lx\n", val); cntr_event_show()
1063 unsigned long val; cntr_event_store() local
1066 ret = kstrtoul(buf, 16, &val); cntr_event_store()
1071 drvdata->cntr_event[drvdata->cntr_idx] = val & ETM_EVENT_MASK; cntr_event_store()
1081 unsigned long val; cntr_rld_event_show() local
1085 val = drvdata->cntr_rld_event[drvdata->cntr_idx]; cntr_rld_event_show()
1088 return sprintf(buf, "%#lx\n", val); cntr_rld_event_show()
1096 unsigned long val; cntr_rld_event_store() local
1099 ret = kstrtoul(buf, 16, &val); cntr_rld_event_store()
1104 drvdata->cntr_rld_event[drvdata->cntr_idx] = val & ETM_EVENT_MASK; cntr_rld_event_store()
1115 u32 val; cntr_val_show() local
1128 val = etm_readl(drvdata, ETMCNTVRn(i)); cntr_val_show()
1129 ret += sprintf(buf, "counter %d: %x\n", i, val); cntr_val_show()
1140 unsigned long val; cntr_val_store() local
1143 ret = kstrtoul(buf, 16, &val); cntr_val_store()
1148 drvdata->cntr_val[drvdata->cntr_idx] = val; cntr_val_store()
1158 unsigned long val; seq_12_event_show() local
1161 val = drvdata->seq_12_event; seq_12_event_show()
1162 return sprintf(buf, "%#lx\n", val); seq_12_event_show()
1170 unsigned long val; seq_12_event_store() local
1173 ret = kstrtoul(buf, 16, &val); seq_12_event_store()
1177 drvdata->seq_12_event = val & ETM_EVENT_MASK; seq_12_event_store()
1185 unsigned long val; seq_21_event_show() local
1188 val = drvdata->seq_21_event; seq_21_event_show()
1189 return sprintf(buf, "%#lx\n", val); seq_21_event_show()
1197 unsigned long val; seq_21_event_store() local
1200 ret = kstrtoul(buf, 16, &val); seq_21_event_store()
1204 drvdata->seq_21_event = val & ETM_EVENT_MASK; seq_21_event_store()
1212 unsigned long val; seq_23_event_show() local
1215 val = drvdata->seq_23_event; seq_23_event_show()
1216 return sprintf(buf, "%#lx\n", val); seq_23_event_show()
1224 unsigned long val; seq_23_event_store() local
1227 ret = kstrtoul(buf, 16, &val); seq_23_event_store()
1231 drvdata->seq_23_event = val & ETM_EVENT_MASK; seq_23_event_store()
1239 unsigned long val; seq_31_event_show() local
1242 val = drvdata->seq_31_event; seq_31_event_show()
1243 return sprintf(buf, "%#lx\n", val); seq_31_event_show()
1251 unsigned long val; seq_31_event_store() local
1254 ret = kstrtoul(buf, 16, &val); seq_31_event_store()
1258 drvdata->seq_31_event = val & ETM_EVENT_MASK; seq_31_event_store()
1266 unsigned long val; seq_32_event_show() local
1269 val = drvdata->seq_32_event; seq_32_event_show()
1270 return sprintf(buf, "%#lx\n", val); seq_32_event_show()
1278 unsigned long val; seq_32_event_store() local
1281 ret = kstrtoul(buf, 16, &val); seq_32_event_store()
1285 drvdata->seq_32_event = val & ETM_EVENT_MASK; seq_32_event_store()
1293 unsigned long val; seq_13_event_show() local
1296 val = drvdata->seq_13_event; seq_13_event_show()
1297 return sprintf(buf, "%#lx\n", val); seq_13_event_show()
1305 unsigned long val; seq_13_event_store() local
1308 ret = kstrtoul(buf, 16, &val); seq_13_event_store()
1312 drvdata->seq_13_event = val & ETM_EVENT_MASK; seq_13_event_store()
1321 unsigned long val, flags; seq_curr_state_show() local
1325 val = drvdata->seq_curr_state; seq_curr_state_show()
1336 val = (etm_readl(drvdata, ETMSQR) & ETM_SQR_MASK); seq_curr_state_show()
1342 return sprintf(buf, "%#lx\n", val); seq_curr_state_show()
1350 unsigned long val; seq_curr_state_store() local
1353 ret = kstrtoul(buf, 16, &val); seq_curr_state_store()
1357 if (val > ETM_SEQ_STATE_MAX_VAL) seq_curr_state_store()
1360 drvdata->seq_curr_state = val; seq_curr_state_store()
1369 unsigned long val; ctxid_idx_show() local
1372 val = drvdata->ctxid_idx; ctxid_idx_show()
1373 return sprintf(buf, "%#lx\n", val); ctxid_idx_show()
1381 unsigned long val; ctxid_idx_store() local
1384 ret = kstrtoul(buf, 16, &val); ctxid_idx_store()
1388 if (val >= drvdata->nr_ctxid_cmp) ctxid_idx_store()
1396 drvdata->ctxid_idx = val; ctxid_idx_store()
1406 unsigned long val; ctxid_val_show() local
1410 val = drvdata->ctxid_val[drvdata->ctxid_idx]; ctxid_val_show()
1413 return sprintf(buf, "%#lx\n", val); ctxid_val_show()
1421 unsigned long val; ctxid_val_store() local
1424 ret = kstrtoul(buf, 16, &val); ctxid_val_store()
1429 drvdata->ctxid_val[drvdata->ctxid_idx] = val; ctxid_val_store()
1439 unsigned long val; ctxid_mask_show() local
1442 val = drvdata->ctxid_mask; ctxid_mask_show()
1443 return sprintf(buf, "%#lx\n", val); ctxid_mask_show()
1451 unsigned long val; ctxid_mask_store() local
1454 ret = kstrtoul(buf, 16, &val); ctxid_mask_store()
1458 drvdata->ctxid_mask = val; ctxid_mask_store()
1466 unsigned long val; sync_freq_show() local
1469 val = drvdata->sync_freq; sync_freq_show()
1470 return sprintf(buf, "%#lx\n", val); sync_freq_show()
1478 unsigned long val; sync_freq_store() local
1481 ret = kstrtoul(buf, 16, &val); sync_freq_store()
1485 drvdata->sync_freq = val & ETM_SYNC_MASK; sync_freq_store()
1493 unsigned long val; timestamp_event_show() local
1496 val = drvdata->timestamp_event; timestamp_event_show()
1497 return sprintf(buf, "%#lx\n", val); timestamp_event_show()
1505 unsigned long val; timestamp_event_store() local
1508 ret = kstrtoul(buf, 16, &val); timestamp_event_store()
1512 drvdata->timestamp_event = val & ETM_EVENT_MASK; timestamp_event_store()
1563 unsigned long val, flags; traceid_show() local
1567 val = drvdata->traceid; traceid_show()
1578 val = (etm_readl(drvdata, ETMTRACEIDR) & ETM_TRACEID_MASK); traceid_show()
1584 return sprintf(buf, "%#lx\n", val); traceid_show()
1592 unsigned long val; traceid_store() local
1595 ret = kstrtoul(buf, 16, &val); traceid_store()
1599 drvdata->traceid = val & ETM_TRACEID_MASK; traceid_store()
44 etm_writel(struct etm_drvdata *drvdata, u32 val, u32 off) etm_writel() argument
/linux-4.1.27/arch/m68k/include/uapi/asm/
H A Dswab.h10 static inline __attribute_const__ __u32 __arch_swab32(__u32 val) __arch_swab32() argument
12 __asm__("byterev %0" : "=d" (val) : "0" (val)); __arch_swab32()
13 return val; __arch_swab32()
19 static inline __attribute_const__ __u32 __arch_swab32(__u32 val) __arch_swab32() argument
21 __asm__("rolw #8,%0; swap %0; rolw #8,%0" : "=d" (val) : "0" (val)); __arch_swab32()
22 return val; __arch_swab32()
/linux-4.1.27/drivers/net/ethernet/neterion/vxge/
H A Dvxge-reg.h23 * vxge_vBIT(val, loc, sz) - set bits at offset
25 #define vxge_vBIT(val, loc, sz) (((u64)(val)) << (64-(loc)-(sz)))
26 #define vxge_vBIT32(val, loc, sz) (((u32)(val)) << (32-(loc)-(sz)))
54 #define VXGE_EPROM_IMG_MAJOR(val) (u32) vxge_bVALn(val, 48, 4)
55 #define VXGE_EPROM_IMG_MINOR(val) (u32) vxge_bVALn(val, 52, 4)
56 #define VXGE_EPROM_IMG_FIX(val) (u32) vxge_bVALn(val, 56, 4)
57 #define VXGE_EPROM_IMG_BUILD(val) (u32) vxge_bVALn(val, 60, 4)
59 #define VXGE_HW_GET_EPROM_IMAGE_INDEX(val) vxge_bVALn(val, 16, 8)
60 #define VXGE_HW_GET_EPROM_IMAGE_VALID(val) vxge_bVALn(val, 31, 1)
61 #define VXGE_HW_GET_EPROM_IMAGE_TYPE(val) vxge_bVALn(val, 40, 8)
62 #define VXGE_HW_GET_EPROM_IMAGE_REV(val) vxge_bVALn(val, 48, 16)
63 #define VXGE_HW_RTS_ACCESS_STEER_ROM_IMAGE_INDEX(val) vxge_vBIT(val, 16, 8)
66 #define VXGE_HW_GET_FUNC_MODE_VAL(val) (val & 0xFF)
76 #define VXGE_HW_UPGRADE_GET_RET_ERR_CODE(val) (val & 0xff)
77 #define VXGE_HW_UPGRADE_GET_SEC_ERR_CODE(val) ((val >> 8) & 0xff)
113 #define VXGE_HW_TOC_GET_KDFC_INITIAL_OFFSET(val) \
114 (val&~VXGE_HW_TOC_KDFC_INITIAL_BIR(7))
115 #define VXGE_HW_TOC_GET_KDFC_INITIAL_BIR(val) \
116 vxge_bVALn(val, 61, 3)
117 #define VXGE_HW_TOC_GET_USDC_INITIAL_OFFSET(val) \
118 (val&~VXGE_HW_TOC_USDC_INITIAL_BIR(7))
119 #define VXGE_HW_TOC_GET_USDC_INITIAL_BIR(val) \
120 vxge_bVALn(val, 61, 3)
132 #define VXGE_HW_KDFC_TRPL_FIFO_OFFSET_KDFC_VAPTH_NUM(val) vxge_vBIT(val, 42, 5)
133 #define VXGE_HW_KDFC_TRPL_FIFO_OFFSET_KDFC_FIFO_NUM(val) vxge_vBIT(val, 47, 2)
134 #define VXGE_HW_KDFC_TRPL_FIFO_OFFSET_KDFC_FIFO_OFFSET(val) \
135 vxge_vBIT(val, 49, 15)
165 #define VXGE_HW_RTS_MGR_STEER_DATA0_DA_MAC_ADDR(val) vxge_vBIT(val, 0, 48)
169 #define VXGE_HW_RTS_MGR_STEER_DATA1_DA_MAC_ADDR_MASK(val) vxge_vBIT(val, 0, 48)
174 #define VXGE_HW_RTS_MGR_STEER_DATA1_DA_MAC_ADDR_ADD_VPATH(val) \
175 vxge_vBIT(val, 55, 5)
178 #define VXGE_HW_RTS_MGR_STEER_DATA1_DA_MAC_ADDR_MODE(val) vxge_vBIT(val, 62, 2)
206 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_DA_MAC_ADDR(val) vxge_vBIT(val, 0, 48)
209 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_VLAN_ID(val) vxge_vBIT(val, 0, 12)
212 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_ETYPE(val) vxge_vBIT(val, 0, 16)
222 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_PN_PORT_NUM(val) vxge_vBIT(val, 8, 16)
229 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_BUCKET_SIZE(val) \
230 vxge_vBIT(val, 4, 4)
233 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL(val) \
234 vxge_vBIT(val, 10, 2)
268 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_SOLO_IT_BUCKET_DATA(val) \
269 vxge_vBIT(val, 9, 7)
273 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_BUCKET_NUM(val) \
274 vxge_vBIT(val, 0, 8)
280 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_BUCKET_DATA(val) \
281 vxge_vBIT(val, 9, 7)
284 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_BUCKET_NUM(val) \
285 vxge_vBIT(val, 16, 8)
291 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_BUCKET_DATA(val) \
292 vxge_vBIT(val, 25, 7)
295 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_BUCKET_NUM(val) \
296 vxge_vBIT(val, 0, 8)
302 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_BUCKET_DATA(val) \
303 vxge_vBIT(val, 9, 7)
306 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_BUCKET_NUM(val) \
307 vxge_vBIT(val, 16, 8)
313 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_BUCKET_DATA(val) \
314 vxge_vBIT(val, 25, 7)
318 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_JHASH_CFG_GOLDEN_RATIO(val) \
319 vxge_vBIT(val, 0, 32)
322 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_JHASH_CFG_INIT_VALUE(val) \
323 vxge_vBIT(val, 32, 32)
327 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_MASK_IPV6_SA_MASK(val) \
328 vxge_vBIT(val, 0, 16)
331 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_MASK_IPV6_DA_MASK(val) \
332 vxge_vBIT(val, 16, 16)
335 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_MASK_IPV4_SA_MASK(val) \
336 vxge_vBIT(val, 32, 4)
339 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_MASK_IPV4_DA_MASK(val) \
340 vxge_vBIT(val, 36, 4)
343 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_MASK_L4SP_MASK(val) \
344 vxge_vBIT(val, 40, 2)
347 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_MASK_L4DP_MASK(val) \
348 vxge_vBIT(val, 42, 2)
352 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_KEY_KEY vxge_vBIT(val, 0, 64)
364 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_DA_MAC_ADDR_MASK(val) \
365 vxge_vBIT(val, 0, 48)
366 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_DA_MAC_ADDR_MODE(val) \
367 vxge_vBIT(val, 62, 2)
371 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM4_BUCKET_NUM(val) \
372 vxge_vBIT(val, 0, 8)
378 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM4_BUCKET_DATA(val) \
379 vxge_vBIT(val, 9, 7)
382 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM5_BUCKET_NUM(val) \
383 vxge_vBIT(val, 16, 8)
389 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM5_BUCKET_DATA(val) \
390 vxge_vBIT(val, 25, 7)
393 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM6_BUCKET_NUM(val) \
394 vxge_vBIT(val, 32, 8)
400 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM6_BUCKET_DATA(val) \
401 vxge_vBIT(val, 41, 7)
404 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM7_BUCKET_NUM(val) \
405 vxge_vBIT(val, 48, 8)
411 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM7_BUCKET_DATA(val) \
412 vxge_vBIT(val, 57, 7)
428 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_FW_VER_DAY(val) vxge_vBIT(val, 0, 8)
431 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_FW_VER_MONTH(val) vxge_vBIT(val, 8, 8)
434 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_FW_VER_YEAR(val) \
435 vxge_vBIT(val, 16, 16)
439 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_FW_VER_MAJOR vxge_vBIT(val, 32, 8)
442 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_FW_VER_MINOR vxge_vBIT(val, 40, 8)
445 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_FW_VER_BUILD vxge_vBIT(val, 48, 16)
449 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_FLASH_VER_DAY(val) vxge_vBIT(val, 0, 8)
452 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_FLASH_VER_MONTH(val) vxge_vBIT(val, 8, 8)
455 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_FLASH_VER_YEAR(val) \
456 vxge_vBIT(val, 16, 16)
460 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_FLASH_VER_MAJOR vxge_vBIT(val, 32, 8)
463 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_FLASH_VER_MINOR vxge_vBIT(val, 40, 8)
466 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_FLASH_VER_BUILD vxge_vBIT(val, 48, 16)
600 #define VXGE_HW_TOC_SWAPPER_FB_INITIAL_VAL(val) vxge_vBIT(val, 0, 64)
602 #define VXGE_HW_PIFM_RD_SWAP_EN_PIFM_RD_SWAP_EN(val) vxge_vBIT(val, 0, 64)
604 #define VXGE_HW_PIFM_RD_FLIP_EN_PIFM_RD_FLIP_EN(val) vxge_vBIT(val, 0, 64)
606 #define VXGE_HW_PIFM_WR_SWAP_EN_PIFM_WR_SWAP_EN(val) vxge_vBIT(val, 0, 64)
608 #define VXGE_HW_PIFM_WR_FLIP_EN_PIFM_WR_FLIP_EN(val) vxge_vBIT(val, 0, 64)
610 #define VXGE_HW_TOC_FIRST_POINTER_INITIAL_VAL(val) vxge_vBIT(val, 0, 64)
612 #define VXGE_HW_HOST_ACCESS_EN_HOST_ACCESS_EN(val) vxge_vBIT(val, 0, 64)
621 #define VXGE_HW_TOC_COMMON_POINTER_INITIAL_VAL(val) vxge_vBIT(val, 0, 64)
623 #define VXGE_HW_TOC_MEMREPAIR_POINTER_INITIAL_VAL(val) vxge_vBIT(val, 0, 64)
625 #define VXGE_HW_TOC_PCICFGMGMT_POINTER_INITIAL_VAL(val) vxge_vBIT(val, 0, 64)
629 #define VXGE_HW_TOC_MRPCIM_POINTER_INITIAL_VAL(val) vxge_vBIT(val, 0, 64)
631 #define VXGE_HW_TOC_SRPCIM_POINTER_INITIAL_VAL(val) vxge_vBIT(val, 0, 64)
635 #define VXGE_HW_TOC_VPMGMT_POINTER_INITIAL_VAL(val) vxge_vBIT(val, 0, 64)
639 #define VXGE_HW_TOC_VPATH_POINTER_INITIAL_VAL(val) vxge_vBIT(val, 0, 64)
643 #define VXGE_HW_TOC_KDFC_INITIAL_OFFSET(val) vxge_vBIT(val, 0, 61)
644 #define VXGE_HW_TOC_KDFC_INITIAL_BIR(val) vxge_vBIT(val, 61, 3)
646 #define VXGE_HW_TOC_USDC_INITIAL_OFFSET(val) vxge_vBIT(val, 0, 61)
647 #define VXGE_HW_TOC_USDC_INITIAL_BIR(val) vxge_vBIT(val, 61, 3)
649 #define VXGE_HW_TOC_KDFC_VPATH_STRIDE_INITIAL_TOC_KDFC_VPATH_STRIDE(val) \
650 vxge_vBIT(val, 0, 64)
652 #define VXGE_HW_TOC_KDFC_FIFO_STRIDE_INITIAL_TOC_KDFC_FIFO_STRIDE(val) \
653 vxge_vBIT(val, 0, 64)
702 #define VXGE_HW_MSG_RESET_IN_PROGRESS_MSG_COMPOSITE(val) vxge_vBIT(val, 0, 17)
714 #define VXGE_HW_CMN_RSTHDLR_CFG0_SW_RESET_VPATH(val) vxge_vBIT(val, 0, 17)
716 #define VXGE_HW_CMN_RSTHDLR_CFG1_CLR_VPATH_RESET(val) vxge_vBIT(val, 0, 17)
718 #define VXGE_HW_CMN_RSTHDLR_CFG2_SW_RESET_FIFO0(val) vxge_vBIT(val, 0, 17)
720 #define VXGE_HW_CMN_RSTHDLR_CFG3_SW_RESET_FIFO1(val) vxge_vBIT(val, 0, 17)
722 #define VXGE_HW_CMN_RSTHDLR_CFG4_SW_RESET_FIFO2(val) vxge_vBIT(val, 0, 17)
726 #define VXGE_HW_CMN_RSTHDLR_CFG8_INCR_VPATH_INST_NUM(val) vxge_vBIT(val, 0, 17)
728 #define VXGE_HW_STATS_CFG0_STATS_ENABLE(val) vxge_vBIT(val, 0, 17)
732 #define VXGE_HW_CLEAR_MSIX_MASK_VECT_CLEAR_MSIX_MASK_VECT(val) \
733 vxge_vBIT(val, 0, 17)
735 #define VXGE_HW_SET_MSIX_MASK_VECT_SET_MSIX_MASK_VECT(val) vxge_vBIT(val, 0, 17)
737 #define VXGE_HW_CLEAR_MSIX_MASK_ALL_VECT_CLEAR_MSIX_MASK_ALL_VECT(val) \
738 vxge_vBIT(val, 0, 17)
740 #define VXGE_HW_SET_MSIX_MASK_ALL_VECT_SET_MSIX_MASK_ALL_VECT(val) \
741 vxge_vBIT(val, 0, 17)
743 #define VXGE_HW_MASK_VECTOR_MASK_VECTOR(val) vxge_vBIT(val, 0, 17)
745 #define VXGE_HW_MSIX_PENDING_VECTOR_MSIX_PENDING_VECTOR(val) \
746 vxge_vBIT(val, 0, 17)
748 #define VXGE_HW_CLR_MSIX_ONE_SHOT_VEC_CLR_MSIX_ONE_SHOT_VEC(val) \
749 vxge_vBIT(val, 0, 17)
751 #define VXGE_HW_TITAN_ASIC_ID_INITIAL_DEVICE_ID(val) vxge_vBIT(val, 0, 16)
752 #define VXGE_HW_TITAN_ASIC_ID_INITIAL_MAJOR_REVISION(val) vxge_vBIT(val, 48, 8)
753 #define VXGE_HW_TITAN_ASIC_ID_INITIAL_MINOR_REVISION(val) vxge_vBIT(val, 56, 8)
758 #define VXGE_HW_TITAN_GENERAL_INT_STATUS_VPATH_TRAFFIC_INT(val) \
759 vxge_vBIT(val, 3, 17)
768 #define VXGE_HW_TIM_INT_STATUS0_TIM_INT_STATUS0(val) vxge_vBIT(val, 0, 64)
770 #define VXGE_HW_TIM_INT_MASK0_TIM_INT_MASK0(val) vxge_vBIT(val, 0, 64)
772 #define VXGE_HW_TIM_INT_STATUS1_TIM_INT_STATUS1(val) vxge_vBIT(val, 0, 4)
774 #define VXGE_HW_TIM_INT_MASK1_TIM_INT_MASK1(val) vxge_vBIT(val, 0, 4)
776 #define VXGE_HW_RTI_INT_STATUS_RTI_INT_STATUS(val) vxge_vBIT(val, 0, 17)
778 #define VXGE_HW_RTI_INT_MASK_RTI_INT_MASK(val) vxge_vBIT(val, 0, 17)
793 #define VXGE_HW_ADAPTER_STATUS_PCC_PCC_IDLE(val) vxge_vBIT(val, 24, 8)
794 #define VXGE_HW_ADAPTER_STATUS_ROCRC_RC_PRC_QUIESCENT(val) vxge_vBIT(val, 44, 8)
802 #define VXGE_HW_GEN_CTRL_SPI_NOT_USED(val) vxge_vBIT(val, 6, 4)
808 #define VXGE_HW_OUTSTANDING_READ_OUTSTANDING_READ(val) vxge_vBIT(val, 0, 17)
810 #define VXGE_HW_VPATH_RST_IN_PROG_VPATH_RST_IN_PROG(val) vxge_vBIT(val, 0, 17)
812 #define VXGE_HW_VPATH_REG_MODIFIED_VPATH_REG_MODIFIED(val) vxge_vBIT(val, 0, 17)
820 #define VXGE_HW_XGMAC_READY_XMACJ_READY(val) vxge_vBIT(val, 0, 17)
824 #define VXGE_HW_FBIF_READY_FAU_READY(val) vxge_vBIT(val, 0, 17)
828 #define VXGE_HW_VPLANE_ASSIGNMENTS_VPLANE_ASSIGNMENTS(val) vxge_vBIT(val, 3, 5)
830 #define VXGE_HW_VPATH_ASSIGNMENTS_VPATH_ASSIGNMENTS(val) vxge_vBIT(val, 0, 17)
832 #define VXGE_HW_RESOURCE_ASSIGNMENTS_RESOURCE_ASSIGNMENTS(val) \
833 vxge_vBIT(val, 0, 17)
835 #define VXGE_HW_HOST_TYPE_ASSIGNMENTS_HOST_TYPE_ASSIGNMENTS(val) \
836 vxge_vBIT(val, 5, 3)
840 #define VXGE_HW_MAX_RESOURCE_ASSIGNMENTS_PCI_MAX_VPLANE(val) \
841 vxge_vBIT(val, 3, 5)
842 #define VXGE_HW_MAX_RESOURCE_ASSIGNMENTS_PCI_MAX_VPATHS(val) \
843 vxge_vBIT(val, 11, 5)
845 #define VXGE_HW_PF_VPATH_ASSIGNMENTS_PF_VPATH_ASSIGNMENTS(val) \
846 vxge_vBIT(val, 0, 17)
850 #define VXGE_HW_RTS_ACCESS_ICMP_EN(val) vxge_vBIT(val, 0, 17)
852 #define VXGE_HW_RTS_ACCESS_TCPSYN_EN(val) vxge_vBIT(val, 0, 17)
854 #define VXGE_HW_RTS_ACCESS_ZL4PYLD_EN(val) vxge_vBIT(val, 0, 17)
856 #define VXGE_HW_RTS_ACCESS_L4PRTCL_TCP_EN(val) vxge_vBIT(val, 0, 17)
858 #define VXGE_HW_RTS_ACCESS_L4PRTCL_UDP_EN(val) vxge_vBIT(val, 0, 17)
860 #define VXGE_HW_RTS_ACCESS_L4PRTCL_FLEX_EN(val) vxge_vBIT(val, 0, 17)
862 #define VXGE_HW_RTS_ACCESS_IPFRAG_EN(val) vxge_vBIT(val, 0, 17)
876 #define VXGE_HW_BARGRP_PF_OR_VF_BAR0_MASK_BARGRP_PF_OR_VF_BAR0_MASK(val) \
877 vxge_vBIT(val, 2, 6)
879 #define VXGE_HW_BARGRP_PF_OR_VF_BAR1_MASK_BARGRP_PF_OR_VF_BAR1_MASK(val) \
880 vxge_vBIT(val, 2, 6)
882 #define VXGE_HW_BARGRP_PF_OR_VF_BAR2_MASK_BARGRP_PF_OR_VF_BAR2_MASK(val) \
883 vxge_vBIT(val, 2, 6)
885 #define VXGE_HW_MSIXGRP_NO_TABLE_SIZE(val) vxge_vBIT(val, 5, 11)
1033 #define VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_0(val) vxge_vBIT(val, 3, 5)
1034 #define VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_1(val) vxge_vBIT(val, 11, 5)
1035 #define VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_2(val) vxge_vBIT(val, 19, 5)
1036 #define VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_3(val) vxge_vBIT(val, 27, 5)
1037 #define VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_4(val) vxge_vBIT(val, 35, 5)
1038 #define VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_5(val) vxge_vBIT(val, 43, 5)
1039 #define VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_6(val) vxge_vBIT(val, 51, 5)
1040 #define VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_7(val) vxge_vBIT(val, 59, 5)
1042 #define VXGE_HW_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_8(val) vxge_vBIT(val, 3, 5)
1043 #define VXGE_HW_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_9(val) vxge_vBIT(val, 11, 5)
1044 #define VXGE_HW_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_10(val) \
1045 vxge_vBIT(val, 19, 5)
1046 #define VXGE_HW_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_11(val) \
1047 vxge_vBIT(val, 27, 5)
1048 #define VXGE_HW_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_12(val) \
1049 vxge_vBIT(val, 35, 5)
1050 #define VXGE_HW_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_13(val) \
1051 vxge_vBIT(val, 43, 5)
1052 #define VXGE_HW_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_14(val) \
1053 vxge_vBIT(val, 51, 5)
1054 #define VXGE_HW_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_15(val) \
1055 vxge_vBIT(val, 59, 5)
1057 #define VXGE_HW_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_16(val) vxge_vBIT(val, 3, 5)
1058 #define VXGE_HW_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_17(val) \
1059 vxge_vBIT(val, 11, 5)
1060 #define VXGE_HW_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_18(val) \
1061 vxge_vBIT(val, 19, 5)
1062 #define VXGE_HW_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_19(val) \
1063 vxge_vBIT(val, 27, 5)
1064 #define VXGE_HW_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_20(val) \
1065 vxge_vBIT(val, 35, 5)
1066 #define VXGE_HW_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_21(val) \
1067 vxge_vBIT(val, 43, 5)
1068 #define VXGE_HW_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_22(val) \
1069 vxge_vBIT(val, 51, 5)
1070 #define VXGE_HW_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_23(val) \
1071 vxge_vBIT(val, 59, 5)
1073 #define VXGE_HW_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_24(val) vxge_vBIT(val, 3, 5)
1074 #define VXGE_HW_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_25(val) \
1075 vxge_vBIT(val, 11, 5)
1076 #define VXGE_HW_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_26(val) \
1077 vxge_vBIT(val, 19, 5)
1078 #define VXGE_HW_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_27(val) \
1079 vxge_vBIT(val, 27, 5)
1080 #define VXGE_HW_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_28(val) \
1081 vxge_vBIT(val, 35, 5)
1082 #define VXGE_HW_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_29(val) \
1083 vxge_vBIT(val, 43, 5)
1084 #define VXGE_HW_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_30(val) \
1085 vxge_vBIT(val, 51, 5)
1086 #define VXGE_HW_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_31(val) \
1087 vxge_vBIT(val, 59, 5)
1089 #define VXGE_HW_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_32(val) vxge_vBIT(val, 3, 5)
1090 #define VXGE_HW_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_33(val) \
1091 vxge_vBIT(val, 11, 5)
1092 #define VXGE_HW_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_34(val) \
1093 vxge_vBIT(val, 19, 5)
1094 #define VXGE_HW_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_35(val) \
1095 vxge_vBIT(val, 27, 5)
1096 #define VXGE_HW_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_36(val) \
1097 vxge_vBIT(val, 35, 5)
1098 #define VXGE_HW_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_37(val) \
1099 vxge_vBIT(val, 43, 5)
1100 #define VXGE_HW_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_38(val) \
1101 vxge_vBIT(val, 51, 5)
1102 #define VXGE_HW_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_39(val) \
1103 vxge_vBIT(val, 59, 5)
1105 #define VXGE_HW_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_40(val) vxge_vBIT(val, 3, 5)
1106 #define VXGE_HW_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_41(val) \
1107 vxge_vBIT(val, 11, 5)
1108 #define VXGE_HW_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_42(val) \
1109 vxge_vBIT(val, 19, 5)
1110 #define VXGE_HW_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_43(val) \
1111 vxge_vBIT(val, 27, 5)
1112 #define VXGE_HW_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_44(val) \
1113 vxge_vBIT(val, 35, 5)
1114 #define VXGE_HW_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_45(val) \
1115 vxge_vBIT(val, 43, 5)
1116 #define VXGE_HW_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_46(val) \
1117 vxge_vBIT(val, 51, 5)
1118 #define VXGE_HW_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_47(val) \
1119 vxge_vBIT(val, 59, 5)
1121 #define VXGE_HW_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_48(val) vxge_vBIT(val, 3, 5)
1122 #define VXGE_HW_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_49(val) \
1123 vxge_vBIT(val, 11, 5)
1124 #define VXGE_HW_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_50(val) \
1125 vxge_vBIT(val, 19, 5)
1126 #define VXGE_HW_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_51(val) \
1127 vxge_vBIT(val, 27, 5)
1128 #define VXGE_HW_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_52(val) \
1129 vxge_vBIT(val, 35, 5)
1130 #define VXGE_HW_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_53(val) \
1131 vxge_vBIT(val, 43, 5)
1132 #define VXGE_HW_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_54(val) \
1133 vxge_vBIT(val, 51, 5)
1134 #define VXGE_HW_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_55(val) \
1135 vxge_vBIT(val, 59, 5)
1137 #define VXGE_HW_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_56(val) vxge_vBIT(val, 3, 5)
1138 #define VXGE_HW_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_57(val) \
1139 vxge_vBIT(val, 11, 5)
1140 #define VXGE_HW_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_58(val) \
1141 vxge_vBIT(val, 19, 5)
1142 #define VXGE_HW_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_59(val) \
1143 vxge_vBIT(val, 27, 5)
1144 #define VXGE_HW_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_60(val) \
1145 vxge_vBIT(val, 35, 5)
1146 #define VXGE_HW_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_61(val) \
1147 vxge_vBIT(val, 43, 5)
1148 #define VXGE_HW_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_62(val) \
1149 vxge_vBIT(val, 51, 5)
1150 #define VXGE_HW_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_63(val) \
1151 vxge_vBIT(val, 59, 5)
1153 #define VXGE_HW_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_64(val) vxge_vBIT(val, 3, 5)
1154 #define VXGE_HW_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_65(val) \
1155 vxge_vBIT(val, 11, 5)
1156 #define VXGE_HW_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_66(val) \
1157 vxge_vBIT(val, 19, 5)
1158 #define VXGE_HW_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_67(val) \
1159 vxge_vBIT(val, 27, 5)
1160 #define VXGE_HW_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_68(val) \
1161 vxge_vBIT(val, 35, 5)
1162 #define VXGE_HW_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_69(val) \
1163 vxge_vBIT(val, 43, 5)
1164 #define VXGE_HW_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_70(val) \
1165 vxge_vBIT(val, 51, 5)
1166 #define VXGE_HW_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_71(val) \
1167 vxge_vBIT(val, 59, 5)
1169 #define VXGE_HW_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_72(val) vxge_vBIT(val, 3, 5)
1170 #define VXGE_HW_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_73(val) \
1171 vxge_vBIT(val, 11, 5)
1172 #define VXGE_HW_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_74(val) \
1173 vxge_vBIT(val, 19, 5)
1174 #define VXGE_HW_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_75(val) \
1175 vxge_vBIT(val, 27, 5)
1176 #define VXGE_HW_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_76(val) \
1177 vxge_vBIT(val, 35, 5)
1178 #define VXGE_HW_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_77(val) \
1179 vxge_vBIT(val, 43, 5)
1180 #define VXGE_HW_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_78(val) \
1181 vxge_vBIT(val, 51, 5)
1182 #define VXGE_HW_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_79(val) \
1183 vxge_vBIT(val, 59, 5)
1185 #define VXGE_HW_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_80(val) \
1186 vxge_vBIT(val, 3, 5)
1187 #define VXGE_HW_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_81(val) \
1188 vxge_vBIT(val, 11, 5)
1189 #define VXGE_HW_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_82(val) \
1190 vxge_vBIT(val, 19, 5)
1191 #define VXGE_HW_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_83(val) \
1192 vxge_vBIT(val, 27, 5)
1193 #define VXGE_HW_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_84(val) \
1194 vxge_vBIT(val, 35, 5)
1195 #define VXGE_HW_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_85(val) \
1196 vxge_vBIT(val, 43, 5)
1197 #define VXGE_HW_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_86(val) \
1198 vxge_vBIT(val, 51, 5)
1199 #define VXGE_HW_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_87(val) \
1200 vxge_vBIT(val, 59, 5)
1202 #define VXGE_HW_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_88(val) \
1203 vxge_vBIT(val, 3, 5)
1204 #define VXGE_HW_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_89(val) \
1205 vxge_vBIT(val, 11, 5)
1206 #define VXGE_HW_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_90(val) \
1207 vxge_vBIT(val, 19, 5)
1208 #define VXGE_HW_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_91(val) \
1209 vxge_vBIT(val, 27, 5)
1210 #define VXGE_HW_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_92(val) \
1211 vxge_vBIT(val, 35, 5)
1212 #define VXGE_HW_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_93(val) \
1213 vxge_vBIT(val, 43, 5)
1214 #define VXGE_HW_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_94(val) \
1215 vxge_vBIT(val, 51, 5)
1216 #define VXGE_HW_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_95(val) \
1217 vxge_vBIT(val, 59, 5)
1219 #define VXGE_HW_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_96(val) \
1220 vxge_vBIT(val, 3, 5)
1221 #define VXGE_HW_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_97(val) \
1222 vxge_vBIT(val, 11, 5)
1223 #define VXGE_HW_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_98(val) \
1224 vxge_vBIT(val, 19, 5)
1225 #define VXGE_HW_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_99(val) \
1226 vxge_vBIT(val, 27, 5)
1227 #define VXGE_HW_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_100(val) \
1228 vxge_vBIT(val, 35, 5)
1229 #define VXGE_HW_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_101(val) \
1230 vxge_vBIT(val, 43, 5)
1231 #define VXGE_HW_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_102(val) \
1232 vxge_vBIT(val, 51, 5)
1233 #define VXGE_HW_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_103(val) \
1234 vxge_vBIT(val, 59, 5)
1236 #define VXGE_HW_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_104(val) \
1237 vxge_vBIT(val, 3, 5)
1238 #define VXGE_HW_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_105(val) \
1239 vxge_vBIT(val, 11, 5)
1240 #define VXGE_HW_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_106(val) \
1241 vxge_vBIT(val, 19, 5)
1242 #define VXGE_HW_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_107(val) \
1243 vxge_vBIT(val, 27, 5)
1244 #define VXGE_HW_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_108(val) \
1245 vxge_vBIT(val, 35, 5)
1246 #define VXGE_HW_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_109(val) \
1247 vxge_vBIT(val, 43, 5)
1248 #define VXGE_HW_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_110(val) \
1249 vxge_vBIT(val, 51, 5)
1250 #define VXGE_HW_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_111(val) \
1251 vxge_vBIT(val, 59, 5)
1253 #define VXGE_HW_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_112(val) \
1254 vxge_vBIT(val, 3, 5)
1255 #define VXGE_HW_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_113(val) \
1256 vxge_vBIT(val, 11, 5)
1257 #define VXGE_HW_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_114(val) \
1258 vxge_vBIT(val, 19, 5)
1259 #define VXGE_HW_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_115(val) \
1260 vxge_vBIT(val, 27, 5)
1261 #define VXGE_HW_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_116(val) \
1262 vxge_vBIT(val, 35, 5)
1263 #define VXGE_HW_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_117(val) \
1264 vxge_vBIT(val, 43, 5)
1265 #define VXGE_HW_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_118(val) \
1266 vxge_vBIT(val, 51, 5)
1267 #define VXGE_HW_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_119(val) \
1268 vxge_vBIT(val, 59, 5)
1270 #define VXGE_HW_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_120(val) \
1271 vxge_vBIT(val, 3, 5)
1272 #define VXGE_HW_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_121(val) \
1273 vxge_vBIT(val, 11, 5)
1274 #define VXGE_HW_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_122(val) \
1275 vxge_vBIT(val, 19, 5)
1276 #define VXGE_HW_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_123(val) \
1277 vxge_vBIT(val, 27, 5)
1278 #define VXGE_HW_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_124(val) \
1279 vxge_vBIT(val, 35, 5)
1280 #define VXGE_HW_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_125(val) \
1281 vxge_vBIT(val, 43, 5)
1282 #define VXGE_HW_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_126(val) \
1283 vxge_vBIT(val, 51, 5)
1284 #define VXGE_HW_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_127(val) \
1285 vxge_vBIT(val, 59, 5)
1287 #define VXGE_HW_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_128(val) \
1288 vxge_vBIT(val, 3, 5)
1289 #define VXGE_HW_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_129(val) \
1290 vxge_vBIT(val, 11, 5)
1291 #define VXGE_HW_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_130(val) \
1292 vxge_vBIT(val, 19, 5)
1293 #define VXGE_HW_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_131(val) \
1294 vxge_vBIT(val, 27, 5)
1295 #define VXGE_HW_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_132(val) \
1296 vxge_vBIT(val, 35, 5)
1297 #define VXGE_HW_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_133(val) \
1298 vxge_vBIT(val, 43, 5)
1299 #define VXGE_HW_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_134(val) \
1300 vxge_vBIT(val, 51, 5)
1301 #define VXGE_HW_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_135(val) \
1302 vxge_vBIT(val, 59, 5)
1304 #define VXGE_HW_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_136(val) \
1305 vxge_vBIT(val, 3, 5)
1306 #define VXGE_HW_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_137(val) \
1307 vxge_vBIT(val, 11, 5)
1308 #define VXGE_HW_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_138(val) \
1309 vxge_vBIT(val, 19, 5)
1310 #define VXGE_HW_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_139(val) \
1311 vxge_vBIT(val, 27, 5)
1312 #define VXGE_HW_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_140(val) \
1313 vxge_vBIT(val, 35, 5)
1314 #define VXGE_HW_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_141(val) \
1315 vxge_vBIT(val, 43, 5)
1316 #define VXGE_HW_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_142(val) \
1317 vxge_vBIT(val, 51, 5)
1318 #define VXGE_HW_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_143(val) \
1319 vxge_vBIT(val, 59, 5)
1321 #define VXGE_HW_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_144(val) \
1322 vxge_vBIT(val, 3, 5)
1323 #define VXGE_HW_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_145(val) \
1324 vxge_vBIT(val, 11, 5)
1325 #define VXGE_HW_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_146(val) \
1326 vxge_vBIT(val, 19, 5)
1327 #define VXGE_HW_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_147(val) \
1328 vxge_vBIT(val, 27, 5)
1329 #define VXGE_HW_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_148(val) \
1330 vxge_vBIT(val, 35, 5)
1331 #define VXGE_HW_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_149(val) \
1332 vxge_vBIT(val, 43, 5)
1333 #define VXGE_HW_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_150(val) \
1334 vxge_vBIT(val, 51, 5)
1335 #define VXGE_HW_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_151(val) \
1336 vxge_vBIT(val, 59, 5)
1338 #define VXGE_HW_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_152(val) \
1339 vxge_vBIT(val, 3, 5)
1340 #define VXGE_HW_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_153(val) \
1341 vxge_vBIT(val, 11, 5)
1342 #define VXGE_HW_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_154(val) \
1343 vxge_vBIT(val, 19, 5)
1344 #define VXGE_HW_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_155(val) \
1345 vxge_vBIT(val, 27, 5)
1346 #define VXGE_HW_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_156(val) \
1347 vxge_vBIT(val, 35, 5)
1348 #define VXGE_HW_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_157(val) \
1349 vxge_vBIT(val, 43, 5)
1350 #define VXGE_HW_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_158(val) \
1351 vxge_vBIT(val, 51, 5)
1352 #define VXGE_HW_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_159(val) \
1353 vxge_vBIT(val, 59, 5)
1355 #define VXGE_HW_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_160(val) \
1356 vxge_vBIT(val, 3, 5)
1357 #define VXGE_HW_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_161(val) \
1358 vxge_vBIT(val, 11, 5)
1359 #define VXGE_HW_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_162(val) \
1360 vxge_vBIT(val, 19, 5)
1361 #define VXGE_HW_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_163(val) \
1362 vxge_vBIT(val, 27, 5)
1363 #define VXGE_HW_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_164(val) \
1364 vxge_vBIT(val, 35, 5)
1365 #define VXGE_HW_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_165(val) \
1366 vxge_vBIT(val, 43, 5)
1367 #define VXGE_HW_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_166(val) \
1368 vxge_vBIT(val, 51, 5)
1369 #define VXGE_HW_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_167(val) \
1370 vxge_vBIT(val, 59, 5)
1372 #define VXGE_HW_RX_W_ROUND_ROBIN_21_RX_W_PRIORITY_SS_168(val) \
1373 vxge_vBIT(val, 3, 5)
1374 #define VXGE_HW_RX_W_ROUND_ROBIN_21_RX_W_PRIORITY_SS_169(val) \
1375 vxge_vBIT(val, 11, 5)
1376 #define VXGE_HW_RX_W_ROUND_ROBIN_21_RX_W_PRIORITY_SS_170(val) \
1377 vxge_vBIT(val, 19, 5)
1383 #define VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_0(val) vxge_vBIT(val, 3, 5)
1384 #define VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_1(val) vxge_vBIT(val, 11, 5)
1385 #define VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_2(val) vxge_vBIT(val, 19, 5)
1386 #define VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_3(val) vxge_vBIT(val, 27, 5)
1387 #define VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_4(val) vxge_vBIT(val, 35, 5)
1388 #define VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_5(val) vxge_vBIT(val, 43, 5)
1389 #define VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_6(val) vxge_vBIT(val, 51, 5)
1390 #define VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_7(val) vxge_vBIT(val, 59, 5)
1392 #define VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_8(val) vxge_vBIT(val, 3, 5)
1393 #define VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_9(val) vxge_vBIT(val, 11, 5)
1394 #define VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_10(val) vxge_vBIT(val, 19, 5)
1395 #define VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_11(val) vxge_vBIT(val, 27, 5)
1396 #define VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_12(val) vxge_vBIT(val, 35, 5)
1397 #define VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_13(val) vxge_vBIT(val, 43, 5)
1398 #define VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_14(val) vxge_vBIT(val, 51, 5)
1399 #define VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_15(val) vxge_vBIT(val, 59, 5)
1401 #define VXGE_HW_RX_QUEUE_PRIORITY_2_RX_Q_NUMBER_16(val) vxge_vBIT(val, 3, 5)
1405 #define VXGE_HW_REPLICATION_QUEUE_PRIORITY_REPLICATION_QUEUE_PRIORITY(val) \
1406 vxge_vBIT(val, 59, 5)
1418 #define VXGE_HW_RX_MULTI_CAST_CTRL_NO_RXD_TIME_OUT_CNT(val) \
1419 vxge_vBIT(val, 2, 30)
1420 #define VXGE_HW_RX_MULTI_CAST_CTRL_TIME_OUT_CNT(val) vxge_vBIT(val, 32, 32)
1422 #define VXGE_HW_WDE_PRM_CTRL_SPAV_THRESHOLD(val) vxge_vBIT(val, 2, 10)
1423 #define VXGE_HW_WDE_PRM_CTRL_SPLIT_THRESHOLD(val) vxge_vBIT(val, 18, 14)
1426 #define VXGE_HW_WDE_PRM_CTRL_FB_ROW_SIZE(val) vxge_vBIT(val, 46, 2)
1428 #define VXGE_HW_NOA_CTRL_FRM_PRTY_QUOTA(val) vxge_vBIT(val, 3, 5)
1429 #define VXGE_HW_NOA_CTRL_NON_FRM_PRTY_QUOTA(val) vxge_vBIT(val, 11, 5)
1431 #define VXGE_HW_NOA_CTRL_MAX_JOB_CNT_FOR_WDE0(val) vxge_vBIT(val, 37, 4)
1432 #define VXGE_HW_NOA_CTRL_MAX_JOB_CNT_FOR_WDE1(val) vxge_vBIT(val, 45, 4)
1433 #define VXGE_HW_NOA_CTRL_MAX_JOB_CNT_FOR_WDE2(val) vxge_vBIT(val, 53, 4)
1434 #define VXGE_HW_NOA_CTRL_MAX_JOB_CNT_FOR_WDE3(val) vxge_vBIT(val, 60, 4)
1449 #define VXGE_HW_RCQ_BYPQ_CFG_OVERFLOW_THRESHOLD(val) vxge_vBIT(val, 10, 22)
1450 #define VXGE_HW_RCQ_BYPQ_CFG_BYP_ON_THRESHOLD(val) vxge_vBIT(val, 39, 9)
1451 #define VXGE_HW_RCQ_BYPQ_CFG_BYP_OFF_THRESHOLD(val) vxge_vBIT(val, 55, 9)
1474 #define VXGE_HW_KDFC_VP_PARTITION_0_NUMBER_0(val) vxge_vBIT(val, 5, 3)
1475 #define VXGE_HW_KDFC_VP_PARTITION_0_LENGTH_0(val) vxge_vBIT(val, 17, 15)
1476 #define VXGE_HW_KDFC_VP_PARTITION_0_NUMBER_1(val) vxge_vBIT(val, 37, 3)
1477 #define VXGE_HW_KDFC_VP_PARTITION_0_LENGTH_1(val) vxge_vBIT(val, 49, 15)
1479 #define VXGE_HW_KDFC_VP_PARTITION_1_NUMBER_2(val) vxge_vBIT(val, 5, 3)
1480 #define VXGE_HW_KDFC_VP_PARTITION_1_LENGTH_2(val) vxge_vBIT(val, 17, 15)
1481 #define VXGE_HW_KDFC_VP_PARTITION_1_NUMBER_3(val) vxge_vBIT(val, 37, 3)
1482 #define VXGE_HW_KDFC_VP_PARTITION_1_LENGTH_3(val) vxge_vBIT(val, 49, 15)
1484 #define VXGE_HW_KDFC_VP_PARTITION_2_NUMBER_4(val) vxge_vBIT(val, 5, 3)
1485 #define VXGE_HW_KDFC_VP_PARTITION_2_LENGTH_4(val) vxge_vBIT(val, 17, 15)
1486 #define VXGE_HW_KDFC_VP_PARTITION_2_NUMBER_5(val) vxge_vBIT(val, 37, 3)
1487 #define VXGE_HW_KDFC_VP_PARTITION_2_LENGTH_5(val) vxge_vBIT(val, 49, 15)
1489 #define VXGE_HW_KDFC_VP_PARTITION_3_NUMBER_6(val) vxge_vBIT(val, 5, 3)
1490 #define VXGE_HW_KDFC_VP_PARTITION_3_LENGTH_6(val) vxge_vBIT(val, 17, 15)
1491 #define VXGE_HW_KDFC_VP_PARTITION_3_NUMBER_7(val) vxge_vBIT(val, 37, 3)
1492 #define VXGE_HW_KDFC_VP_PARTITION_3_LENGTH_7(val) vxge_vBIT(val, 49, 15)
1494 #define VXGE_HW_KDFC_VP_PARTITION_4_LENGTH_8(val) vxge_vBIT(val, 17, 15)
1495 #define VXGE_HW_KDFC_VP_PARTITION_4_LENGTH_9(val) vxge_vBIT(val, 49, 15)
1497 #define VXGE_HW_KDFC_VP_PARTITION_5_LENGTH_10(val) vxge_vBIT(val, 17, 15)
1498 #define VXGE_HW_KDFC_VP_PARTITION_5_LENGTH_11(val) vxge_vBIT(val, 49, 15)
1500 #define VXGE_HW_KDFC_VP_PARTITION_6_LENGTH_12(val) vxge_vBIT(val, 17, 15)
1501 #define VXGE_HW_KDFC_VP_PARTITION_6_LENGTH_13(val) vxge_vBIT(val, 49, 15)
1503 #define VXGE_HW_KDFC_VP_PARTITION_7_LENGTH_14(val) vxge_vBIT(val, 17, 15)
1504 #define VXGE_HW_KDFC_VP_PARTITION_7_LENGTH_15(val) vxge_vBIT(val, 49, 15)
1506 #define VXGE_HW_KDFC_VP_PARTITION_8_LENGTH_16(val) vxge_vBIT(val, 17, 15)
1508 #define VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_0(val) vxge_vBIT(val, 3, 5)
1509 #define VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_1(val) vxge_vBIT(val, 11, 5)
1510 #define VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_2(val) vxge_vBIT(val, 19, 5)
1511 #define VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_3(val) vxge_vBIT(val, 27, 5)
1512 #define VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_4(val) vxge_vBIT(val, 35, 5)
1513 #define VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_5(val) vxge_vBIT(val, 43, 5)
1514 #define VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_6(val) vxge_vBIT(val, 51, 5)
1515 #define VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_7(val) vxge_vBIT(val, 59, 5)
1520 #define VXGE_HW_KDFC_W_ROUND_ROBIN_20_NUMBER_0(val) vxge_vBIT(val, 3, 5)
1521 #define VXGE_HW_KDFC_W_ROUND_ROBIN_20_NUMBER_1(val) vxge_vBIT(val, 11, 5)
1522 #define VXGE_HW_KDFC_W_ROUND_ROBIN_20_NUMBER_2(val) vxge_vBIT(val, 19, 5)
1523 #define VXGE_HW_KDFC_W_ROUND_ROBIN_20_NUMBER_3(val) vxge_vBIT(val, 27, 5)
1524 #define VXGE_HW_KDFC_W_ROUND_ROBIN_20_NUMBER_4(val) vxge_vBIT(val, 35, 5)
1525 #define VXGE_HW_KDFC_W_ROUND_ROBIN_20_NUMBER_5(val) vxge_vBIT(val, 43, 5)
1526 #define VXGE_HW_KDFC_W_ROUND_ROBIN_20_NUMBER_6(val) vxge_vBIT(val, 51, 5)
1527 #define VXGE_HW_KDFC_W_ROUND_ROBIN_20_NUMBER_7(val) vxge_vBIT(val, 59, 5)
1534 #define VXGE_HW_KDFC_W_ROUND_ROBIN_40_NUMBER_0(val) vxge_vBIT(val, 3, 5)
1535 #define VXGE_HW_KDFC_W_ROUND_ROBIN_40_NUMBER_1(val) vxge_vBIT(val, 11, 5)
1536 #define VXGE_HW_KDFC_W_ROUND_ROBIN_40_NUMBER_2(val) vxge_vBIT(val, 19, 5)
1537 #define VXGE_HW_KDFC_W_ROUND_ROBIN_40_NUMBER_3(val) vxge_vBIT(val, 27, 5)
1538 #define VXGE_HW_KDFC_W_ROUND_ROBIN_40_NUMBER_4(val) vxge_vBIT(val, 35, 5)
1539 #define VXGE_HW_KDFC_W_ROUND_ROBIN_40_NUMBER_5(val) vxge_vBIT(val, 43, 5)
1540 #define VXGE_HW_KDFC_W_ROUND_ROBIN_40_NUMBER_6(val) vxge_vBIT(val, 51, 5)
1541 #define VXGE_HW_KDFC_W_ROUND_ROBIN_40_NUMBER_7(val) vxge_vBIT(val, 59, 5)
1546 #define VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_0(val) vxge_vBIT(val, 6, 2)
1547 #define VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_1(val) vxge_vBIT(val, 14, 2)
1548 #define VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_2(val) vxge_vBIT(val, 22, 2)
1549 #define VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_3(val) vxge_vBIT(val, 30, 2)
1550 #define VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_4(val) vxge_vBIT(val, 38, 2)
1551 #define VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_5(val) vxge_vBIT(val, 46, 2)
1552 #define VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_6(val) vxge_vBIT(val, 54, 2)
1553 #define VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_7(val) vxge_vBIT(val, 62, 2)
1555 #define VXGE_HW_KDFC_ENTRY_TYPE_SEL_1_NUMBER_8(val) vxge_vBIT(val, 6, 2)
1557 #define VXGE_HW_KDFC_FIFO_0_CTRL_WRR_NUMBER(val) vxge_vBIT(val, 3, 5)
1564 #define VXGE_HW_KDFC_FIFO_17_CTRL_WRR_NUMBER(val) vxge_vBIT(val, 3, 5)
1580 #define VXGE_HW_RXMAC_ECC_ERR_REG_RMAC_PORT0_RMAC_RTS_PART_SG_ERR(val) \
1581 vxge_vBIT(val, 0, 4)
1582 #define VXGE_HW_RXMAC_ECC_ERR_REG_RMAC_PORT0_RMAC_RTS_PART_DB_ERR(val) \
1583 vxge_vBIT(val, 4, 4)
1584 #define VXGE_HW_RXMAC_ECC_ERR_REG_RMAC_PORT1_RMAC_RTS_PART_SG_ERR(val) \
1585 vxge_vBIT(val, 8, 4)
1586 #define VXGE_HW_RXMAC_ECC_ERR_REG_RMAC_PORT1_RMAC_RTS_PART_DB_ERR(val) \
1587 vxge_vBIT(val, 12, 4)
1588 #define VXGE_HW_RXMAC_ECC_ERR_REG_RMAC_PORT2_RMAC_RTS_PART_SG_ERR(val) \
1589 vxge_vBIT(val, 16, 4)
1590 #define VXGE_HW_RXMAC_ECC_ERR_REG_RMAC_PORT2_RMAC_RTS_PART_DB_ERR(val) \
1591 vxge_vBIT(val, 20, 4)
1592 #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DA_LKP_PRT0_SG_ERR(val) \
1593 vxge_vBIT(val, 24, 2)
1594 #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DA_LKP_PRT0_DB_ERR(val) \
1595 vxge_vBIT(val, 26, 2)
1596 #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DA_LKP_PRT1_SG_ERR(val) \
1597 vxge_vBIT(val, 28, 2)
1598 #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DA_LKP_PRT1_DB_ERR(val) \
1599 vxge_vBIT(val, 30, 2)
1608 #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_RTH_MASK_SG_ERR(val) \
1609 vxge_vBIT(val, 40, 7)
1610 #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_RTH_MASK_DB_ERR(val) \
1611 vxge_vBIT(val, 47, 7)
1612 #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_RTH_LKP_SG_ERR(val) \
1613 vxge_vBIT(val, 54, 3)
1614 #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_RTH_LKP_DB_ERR(val) \
1615 vxge_vBIT(val, 57, 3)
1638 #define VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_CRATE_THR0(val) vxge_vBIT(val, 0, 4)
1639 #define VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_CRATE_THR1(val) vxge_vBIT(val, 4, 4)
1640 #define VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_CRATE_THR2(val) vxge_vBIT(val, 8, 4)
1641 #define VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_CRATE_THR3(val) vxge_vBIT(val, 12, 4)
1642 #define VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_FRATE_THR0(val) vxge_vBIT(val, 16, 4)
1643 #define VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_FRATE_THR1(val) vxge_vBIT(val, 20, 4)
1644 #define VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_FRATE_THR2(val) vxge_vBIT(val, 24, 4)
1645 #define VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_FRATE_THR3(val) vxge_vBIT(val, 28, 4)
1657 #define VXGE_HW_RXMAC_CFG0_PORT_MAX_PYLD_LEN(val) vxge_vBIT(val, 50, 14)
1665 #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_ACCEL_SEND(val) vxge_vBIT(val, 9, 3)
1667 #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_HIGH_PTIME(val) vxge_vBIT(val, 20, 16)
1671 #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_MAX_LIMIT(val) vxge_vBIT(val, 48, 8)
1683 #define VXGE_HW_RXMAC_LINK_UTIL_PORT_RMAC_RMAC_UTILIZATION(val) \
1684 vxge_vBIT(val, 1, 7)
1685 #define VXGE_HW_RXMAC_LINK_UTIL_PORT_RMAC_UTIL_CFG(val) vxge_vBIT(val, 8, 4)
1686 #define VXGE_HW_RXMAC_LINK_UTIL_PORT_RMAC_RMAC_FRAC_UTIL(val) \
1687 vxge_vBIT(val, 12, 4)
1688 #define VXGE_HW_RXMAC_LINK_UTIL_PORT_RMAC_PKT_WEIGHT(val) vxge_vBIT(val, 16, 4)
1722 #define VXGE_HW_RTS_MGR_CFG0_FLEX_L4PRTCL_VALUE(val) vxge_vBIT(val, 24, 8)
1734 #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_ETYPE(val) vxge_vBIT(val, 5, 3)
1735 #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_ICMP_TCPSYN(val) vxge_vBIT(val, 9, 3)
1736 #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_L4PN(val) vxge_vBIT(val, 13, 3)
1737 #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_RANGE_L4PN(val) vxge_vBIT(val, 17, 3)
1738 #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_RTH_IT(val) vxge_vBIT(val, 21, 3)
1739 #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_DS(val) vxge_vBIT(val, 25, 3)
1740 #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_QOS(val) vxge_vBIT(val, 29, 3)
1741 #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_ZL4PYLD(val) vxge_vBIT(val, 33, 3)
1742 #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_L4PRTCL(val) vxge_vBIT(val, 37, 3)
1744 #define VXGE_HW_RTS_MGR_DA_PAUSE_CFG_VPATH_VECTOR(val) vxge_vBIT(val, 0, 17)
1746 #define VXGE_HW_RTS_MGR_DA_SLOW_PROTO_CFG_VPATH_VECTOR(val) \
1747 vxge_vBIT(val, 0, 17)
1753 #define VXGE_HW_DBG_STAT_RX_ANY_FRMS_PORT0_RX_ANY_FRMS(val) vxge_vBIT(val, 0, 8)
1754 #define VXGE_HW_DBG_STAT_RX_ANY_FRMS_PORT1_RX_ANY_FRMS(val) vxge_vBIT(val, 8, 8)
1755 #define VXGE_HW_DBG_STAT_RX_ANY_FRMS_PORT2_RX_ANY_FRMS(val) \
1756 vxge_vBIT(val, 16, 8)
1760 #define VXGE_HW_RXMAC_RED_RATE_VP_CRATE_THR0(val) vxge_vBIT(val, 0, 4)
1761 #define VXGE_HW_RXMAC_RED_RATE_VP_CRATE_THR1(val) vxge_vBIT(val, 4, 4)
1762 #define VXGE_HW_RXMAC_RED_RATE_VP_CRATE_THR2(val) vxge_vBIT(val, 8, 4)
1763 #define VXGE_HW_RXMAC_RED_RATE_VP_CRATE_THR3(val) vxge_vBIT(val, 12, 4)
1764 #define VXGE_HW_RXMAC_RED_RATE_VP_FRATE_THR0(val) vxge_vBIT(val, 16, 4)
1765 #define VXGE_HW_RXMAC_RED_RATE_VP_FRATE_THR1(val) vxge_vBIT(val, 20, 4)
1766 #define VXGE_HW_RXMAC_RED_RATE_VP_FRATE_THR2(val) vxge_vBIT(val, 24, 4)
1767 #define VXGE_HW_RXMAC_RED_RATE_VP_FRATE_THR3(val) vxge_vBIT(val, 28, 4)
1792 #define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE0_SG_ERR(val) \
1793 vxge_vBIT(val, 40, 2)
1794 #define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE0_DB_ERR(val) \
1795 vxge_vBIT(val, 42, 2)
1796 #define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE1_SG_ERR(val) \
1797 vxge_vBIT(val, 44, 2)
1798 #define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE1_DB_ERR(val) \
1799 vxge_vBIT(val, 46, 2)
1800 #define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE2_SG_ERR(val) \
1801 vxge_vBIT(val, 48, 2)
1802 #define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE2_DB_ERR(val) \
1803 vxge_vBIT(val, 50, 2)
1804 #define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE3_SG_ERR(val) \
1805 vxge_vBIT(val, 52, 2)
1806 #define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE3_DB_ERR(val) \
1807 vxge_vBIT(val, 54, 2)
1808 #define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE4_SG_ERR(val) \
1809 vxge_vBIT(val, 56, 2)
1810 #define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE4_DB_ERR(val) \
1811 vxge_vBIT(val, 58, 2)
1855 #define VXGE_HW_XGMAC_GEN_FW_MEMO_STATUS_XMACJ_EVENTS_PENDING(val) \
1856 vxge_vBIT(val, 0, 17)
1858 #define VXGE_HW_XGMAC_GEN_FW_MEMO_MASK_MASK(val) vxge_vBIT(val, 0, 64)
1860 #define VXGE_HW_XGMAC_GEN_FW_VPATH_TO_VSPORT_STATUS_XMACJ_EVENTS_PENDING(val) \
1861 vxge_vBIT(val, 0, 17)
1867 #define VXGE_HW_XMAC_GEN_CFG_RATEMGMT_MAC_RATE_SEL(val) vxge_vBIT(val, 2, 2)
1870 #define VXGE_HW_XMAC_GEN_CFG_PERIOD_NTWK_UP(val) vxge_vBIT(val, 28, 4)
1871 #define VXGE_HW_XMAC_GEN_CFG_PERIOD_NTWK_DOWN(val) vxge_vBIT(val, 32, 4)
1874 #define VXGE_HW_XMAC_TIMESTAMP_USE_LINK_ID(val) vxge_vBIT(val, 6, 2)
1875 #define VXGE_HW_XMAC_TIMESTAMP_INTERVAL(val) vxge_vBIT(val, 12, 4)
1877 #define VXGE_HW_XMAC_TIMESTAMP_XMACJ_ROLLOVER_CNT(val) vxge_vBIT(val, 32, 16)
1879 #define VXGE_HW_XMAC_STATS_GEN_CFG_PRTAGGR_CUM_TIMER(val) vxge_vBIT(val, 4, 4)
1880 #define VXGE_HW_XMAC_STATS_GEN_CFG_VPATH_CUM_TIMER(val) vxge_vBIT(val, 8, 4)
1883 #define VXGE_HW_XMAC_STATS_SYS_CMD_OP(val) vxge_vBIT(val, 5, 3)
1885 #define VXGE_HW_XMAC_STATS_SYS_CMD_LOC_SEL(val) vxge_vBIT(val, 27, 5)
1886 #define VXGE_HW_XMAC_STATS_SYS_CMD_OFFSET_SEL(val) vxge_vBIT(val, 32, 8)
1888 #define VXGE_HW_XMAC_STATS_SYS_DATA_XSMGR_DATA(val) vxge_vBIT(val, 0, 64)
1905 #define VXGE_HW_XMAC_STATION_ADDR_PORT_MAC_ADDR(val) vxge_vBIT(val, 0, 48)
1910 #define VXGE_HW_LAG_CFG_MODE(val) vxge_vBIT(val, 6, 2)
1916 #define VXGE_HW_LAG_STATUS_XLCM_TIMER_VAL_COLD_FAILOVER(val) \
1917 vxge_vBIT(val, 8, 8)
1924 #define VXGE_HW_LAG_ACTIVE_PASSIVE_CFG_COLD_FAILOVER_TIMEOUT(val) \
1925 vxge_vBIT(val, 32, 16)
1934 #define VXGE_HW_LAG_TIMER_CFG_1_FAST_PER(val) vxge_vBIT(val, 0, 16)
1935 #define VXGE_HW_LAG_TIMER_CFG_1_SLOW_PER(val) vxge_vBIT(val, 16, 16)
1936 #define VXGE_HW_LAG_TIMER_CFG_1_SHORT_TIMEOUT(val) vxge_vBIT(val, 32, 16)
1937 #define VXGE_HW_LAG_TIMER_CFG_1_LONG_TIMEOUT(val) vxge_vBIT(val, 48, 16)
1939 #define VXGE_HW_LAG_TIMER_CFG_2_CHURN_DET(val) vxge_vBIT(val, 0, 16)
1940 #define VXGE_HW_LAG_TIMER_CFG_2_AGGR_WAIT(val) vxge_vBIT(val, 16, 16)
1941 #define VXGE_HW_LAG_TIMER_CFG_2_SHORT_TIMER_SCALE(val) vxge_vBIT(val, 32, 16)
1942 #define VXGE_HW_LAG_TIMER_CFG_2_LONG_TIMER_SCALE(val) vxge_vBIT(val, 48, 16)
1944 #define VXGE_HW_LAG_SYS_ID_ADDR(val) vxge_vBIT(val, 0, 48)
1948 #define VXGE_HW_LAG_SYS_CFG_SYS_PRI(val) vxge_vBIT(val, 0, 16)
1952 #define VXGE_HW_LAG_AGGR_ADDR_CFG_ADDR(val) vxge_vBIT(val, 0, 48)
1956 #define VXGE_HW_LAG_AGGR_ID_CFG_ID(val) vxge_vBIT(val, 0, 16)
1958 #define VXGE_HW_LAG_AGGR_ADMIN_KEY_KEY(val) vxge_vBIT(val, 0, 16)
1960 #define VXGE_HW_LAG_AGGR_ALT_ADMIN_KEY_KEY(val) vxge_vBIT(val, 0, 16)
1963 #define VXGE_HW_LAG_AGGR_OPER_KEY_LAGC_KEY(val) vxge_vBIT(val, 0, 16)
1965 #define VXGE_HW_LAG_AGGR_PARTNER_SYS_ID_LAGC_ADDR(val) vxge_vBIT(val, 0, 48)
1967 #define VXGE_HW_LAG_AGGR_PARTNER_INFO_LAGC_SYS_PRI(val) vxge_vBIT(val, 0, 16)
1968 #define VXGE_HW_LAG_AGGR_PARTNER_INFO_LAGC_OPER_KEY(val) \
1969 vxge_vBIT(val, 16, 16)
1983 #define VXGE_HW_LAG_PORT_ACTOR_ADMIN_CFG_PORT_NUM(val) vxge_vBIT(val, 0, 16)
1984 #define VXGE_HW_LAG_PORT_ACTOR_ADMIN_CFG_PORT_PRI(val) vxge_vBIT(val, 16, 16)
1985 #define VXGE_HW_LAG_PORT_ACTOR_ADMIN_CFG_KEY_10G(val) vxge_vBIT(val, 32, 16)
1986 #define VXGE_HW_LAG_PORT_ACTOR_ADMIN_CFG_KEY_1G(val) vxge_vBIT(val, 48, 16)
1997 #define VXGE_HW_LAG_PORT_PARTNER_ADMIN_SYS_ID_ADDR(val) vxge_vBIT(val, 0, 48)
1999 #define VXGE_HW_LAG_PORT_PARTNER_ADMIN_CFG_SYS_PRI(val) vxge_vBIT(val, 0, 16)
2000 #define VXGE_HW_LAG_PORT_PARTNER_ADMIN_CFG_KEY(val) vxge_vBIT(val, 16, 16)
2001 #define VXGE_HW_LAG_PORT_PARTNER_ADMIN_CFG_PORT_NUM(val) \
2002 vxge_vBIT(val, 32, 16)
2003 #define VXGE_HW_LAG_PORT_PARTNER_ADMIN_CFG_PORT_PRI(val) \
2004 vxge_vBIT(val, 48, 16)
2015 #define VXGE_HW_LAG_PORT_TO_AGGR_LAGC_AGGR_ID(val) vxge_vBIT(val, 0, 16)
2018 #define VXGE_HW_LAG_PORT_ACTOR_OPER_KEY_LAGC_KEY(val) vxge_vBIT(val, 0, 16)
2029 #define VXGE_HW_LAG_PORT_PARTNER_OPER_SYS_ID_LAGC_ADDR(val) \
2030 vxge_vBIT(val, 0, 48)
2032 #define VXGE_HW_LAG_PORT_PARTNER_OPER_INFO_LAGC_SYS_PRI(val) \
2033 vxge_vBIT(val, 0, 16)
2034 #define VXGE_HW_LAG_PORT_PARTNER_OPER_INFO_LAGC_KEY(val) \
2035 vxge_vBIT(val, 16, 16)
2036 #define VXGE_HW_LAG_PORT_PARTNER_OPER_INFO_LAGC_PORT_NUM(val) \
2037 vxge_vBIT(val, 32, 16)
2038 #define VXGE_HW_LAG_PORT_PARTNER_OPER_INFO_LAGC_PORT_PRI(val) \
2039 vxge_vBIT(val, 48, 16)
2052 #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_SELECTED(val) vxge_vBIT(val, 6, 2)
2066 #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_RX_FSM_STATE(val) vxge_vBIT(val, 37, 3)
2067 #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_MUX_FSM_STATE(val) \
2068 vxge_vBIT(val, 41, 3)
2069 #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_MUX_REASON(val) vxge_vBIT(val, 44, 4)
2072 #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_ACTOR_CHURN_COUNT(val) \
2073 vxge_vBIT(val, 56, 4)
2074 #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_PARTNER_CHURN_COUNT(val) \
2075 vxge_vBIT(val, 60, 4)
2077 #define VXGE_HW_LAG_PORT_TIMER_CNTR_LAGC_CURRENT_WHILE(val) vxge_vBIT(val, 0, 8)
2078 #define VXGE_HW_LAG_PORT_TIMER_CNTR_LAGC_PERIODIC_WHILE(val) \
2079 vxge_vBIT(val, 8, 8)
2080 #define VXGE_HW_LAG_PORT_TIMER_CNTR_LAGC_WAIT_WHILE(val) vxge_vBIT(val, 16, 8)
2081 #define VXGE_HW_LAG_PORT_TIMER_CNTR_LAGC_TX_LACP(val) vxge_vBIT(val, 24, 8)
2082 #define VXGE_HW_LAG_PORT_TIMER_CNTR_LAGC_ACTOR_SYNC_TRANSITION_COUNT(val) \
2083 vxge_vBIT(val, 32, 8)
2084 #define VXGE_HW_LAG_PORT_TIMER_CNTR_LAGC_PARTNER_SYNC_TRANSITION_COUNT(val) \
2085 vxge_vBIT(val, 40, 8)
2086 #define VXGE_HW_LAG_PORT_TIMER_CNTR_LAGC_ACTOR_CHANGE_COUNT(val) \
2087 vxge_vBIT(val, 48, 8)
2088 #define VXGE_HW_LAG_PORT_TIMER_CNTR_LAGC_PARTNER_CHANGE_COUNT(val) \
2089 vxge_vBIT(val, 56, 8)
2130 #define VXGE_HW_PCC_CONTROL_FE_ENABLE(val) vxge_vBIT(val, 6, 2)
2134 #define VXGE_HW_PDA_STATUS1_PDA_WRAP_0_CTR(val) vxge_vBIT(val, 4, 4)
2135 #define VXGE_HW_PDA_STATUS1_PDA_WRAP_1_CTR(val) vxge_vBIT(val, 12, 4)
2136 #define VXGE_HW_PDA_STATUS1_PDA_WRAP_2_CTR(val) vxge_vBIT(val, 20, 4)
2137 #define VXGE_HW_PDA_STATUS1_PDA_WRAP_3_CTR(val) vxge_vBIT(val, 28, 4)
2138 #define VXGE_HW_PDA_STATUS1_PDA_WRAP_4_CTR(val) vxge_vBIT(val, 36, 4)
2139 #define VXGE_HW_PDA_STATUS1_PDA_WRAP_5_CTR(val) vxge_vBIT(val, 44, 4)
2140 #define VXGE_HW_PDA_STATUS1_PDA_WRAP_6_CTR(val) vxge_vBIT(val, 52, 4)
2141 #define VXGE_HW_PDA_STATUS1_PDA_WRAP_7_CTR(val) vxge_vBIT(val, 60, 4)
2143 #define VXGE_HW_RTDMA_BW_TIMER_TIMER_CTRL(val) vxge_vBIT(val, 12, 4)
2189 #define VXGE_HW_RX_THRESH_CFG_REPL_PAUSE_LOW_THR(val) vxge_vBIT(val, 0, 8)
2190 #define VXGE_HW_RX_THRESH_CFG_REPL_PAUSE_HIGH_THR(val) vxge_vBIT(val, 8, 8)
2191 #define VXGE_HW_RX_THRESH_CFG_REPL_RED_THR_0(val) vxge_vBIT(val, 16, 8)
2192 #define VXGE_HW_RX_THRESH_CFG_REPL_RED_THR_1(val) vxge_vBIT(val, 24, 8)
2193 #define VXGE_HW_RX_THRESH_CFG_REPL_RED_THR_2(val) vxge_vBIT(val, 32, 8)
2194 #define VXGE_HW_RX_THRESH_CFG_REPL_RED_THR_3(val) vxge_vBIT(val, 40, 8)
2200 #define VXGE_HW_FBMC_ECC_CFG_ENABLE(val) vxge_vBIT(val, 3, 5)
2317 #define VXGE_HW_RC_CFG2_BUFF1_SIZE(val) vxge_vBIT(val, 0, 16)
2318 #define VXGE_HW_RC_CFG2_BUFF2_SIZE(val) vxge_vBIT(val, 16, 16)
2319 #define VXGE_HW_RC_CFG2_BUFF3_SIZE(val) vxge_vBIT(val, 32, 16)
2320 #define VXGE_HW_RC_CFG2_BUFF4_SIZE(val) vxge_vBIT(val, 48, 16)
2322 #define VXGE_HW_RC_CFG3_BUFF5_SIZE(val) vxge_vBIT(val, 0, 16)
2325 #define VXGE_HW_RX_MULTI_CAST_CTRL1_DELAY_COUNT(val) vxge_vBIT(val, 11, 5)
2327 #define VXGE_HW_RXDM_DBG_RD_ADDR(val) vxge_vBIT(val, 0, 12)
2330 #define VXGE_HW_RXDM_DBG_RD_DATA_RMC_RXDM_DBG_RD_DATA(val) vxge_vBIT(val, 0, 64)
2332 #define VXGE_HW_RQA_TOP_PRTY_FOR_VH_RQA_TOP_PRTY_FOR_VH(val) \
2333 vxge_vBIT(val, 59, 5)
2347 #define VXGE_HW_TIM_RESOURCE_ASSIGNMENT_VH_BMAP_ROOT(val) vxge_vBIT(val, 0, 32)
2349 #define VXGE_HW_TIM_BMAP_MAPPING_VP_ERR_TIM_DEST_VPATH(val) vxge_vBIT(val, 3, 5)
2358 #define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_MEM_DB_ERR(val) vxge_vBIT(val, 0, 4)
2359 #define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_MEM_SG_ERR(val) vxge_vBIT(val, 4, 4)
2413 #define VXGE_HW_PXTMC_ERR_REG_XTMC_XT_PIF_SRAM_DB_ERR(val) vxge_vBIT(val, 0, 2)
2466 #define VXGE_HW_PXTMC_ERR_REG_XTMC_XT_PIF_SRAM_SG_ERR(val) vxge_vBIT(val, 54, 2)
2472 #define VXGE_HW_CP_ERR_REG_CP_CP_DCACHE_SG_ERR(val) vxge_vBIT(val, 0, 8)
2473 #define VXGE_HW_CP_ERR_REG_CP_CP_ICACHE_SG_ERR(val) vxge_vBIT(val, 8, 2)
2480 #define VXGE_HW_CP_ERR_REG_CP_STC2CP_SG_ERR(val) vxge_vBIT(val, 16, 2)
2481 #define VXGE_HW_CP_ERR_REG_CP_CP_DCACHE_DB_ERR(val) vxge_vBIT(val, 24, 8)
2482 #define VXGE_HW_CP_ERR_REG_CP_CP_ICACHE_DB_ERR(val) vxge_vBIT(val, 32, 2)
2489 #define VXGE_HW_CP_ERR_REG_CP_STC2CP_DB_ERR(val) vxge_vBIT(val, 40, 2)
2515 #define VXGE_HW_CP_EXC_CAUSE_CP_CP_CAUSE(val) vxge_vBIT(val, 32, 32)
2609 #define VXGE_HW_MSG_EXC_CAUSE_MP_MXP(val) vxge_vBIT(val, 0, 32)
2610 #define VXGE_HW_MSG_EXC_CAUSE_UP_UXP(val) vxge_vBIT(val, 32, 32)
2733 #define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT0_FAU_MAC2F_W_SG_ERR(val) \
2734 vxge_vBIT(val, 2, 2)
2735 #define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT0_FAU_MAC2F_W_DB_ERR(val) \
2736 vxge_vBIT(val, 4, 2)
2739 #define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT1_FAU_MAC2F_W_SG_ERR(val) \
2740 vxge_vBIT(val, 8, 2)
2741 #define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT1_FAU_MAC2F_W_DB_ERR(val) \
2742 vxge_vBIT(val, 10, 2)
2745 #define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT2_FAU_MAC2F_W_SG_ERR(val) \
2746 vxge_vBIT(val, 14, 2)
2747 #define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT2_FAU_MAC2F_W_DB_ERR(val) \
2748 vxge_vBIT(val, 16, 2)
2749 #define VXGE_HW_FAU_ECC_ERR_REG_FAU_FAU_XFMD_INS_SG_ERR(val) \
2750 vxge_vBIT(val, 18, 2)
2751 #define VXGE_HW_FAU_ECC_ERR_REG_FAU_FAU_XFMD_INS_DB_ERR(val) \
2752 vxge_vBIT(val, 20, 2)
2764 #define VXGE_HW_DBG_STATS_FAU_RX_PATH_RX_PERMITTED_FRMS(val) \
2765 vxge_vBIT(val, 32, 32)
2769 #define VXGE_HW_FAU_LAG_CFG_COLL_ALG(val) vxge_vBIT(val, 2, 2)
2798 #define VXGE_HW_PTM_ALARM_REG_PTM_FRMM_ECC_DB_ERR(val) vxge_vBIT(val, 18, 2)
2799 #define VXGE_HW_PTM_ALARM_REG_PTM_FRMM_ECC_SG_ERR(val) vxge_vBIT(val, 22, 2)
2821 #define VXGE_HW_DBG_STATS_TPA_TX_PATH_TX_PERMITTED_FRMS(val) \
2822 vxge_vBIT(val, 32, 32)
2850 #define VXGE_HW_DBG_STAT_TX_ANY_FRMS_PORT0_TX_ANY_FRMS(val) vxge_vBIT(val, 0, 8)
2851 #define VXGE_HW_DBG_STAT_TX_ANY_FRMS_PORT1_TX_ANY_FRMS(val) vxge_vBIT(val, 8, 8)
2852 #define VXGE_HW_DBG_STAT_TX_ANY_FRMS_PORT2_TX_ANY_FRMS(val) \
2853 vxge_vBIT(val, 16, 8)
2857 #define VXGE_HW_TXMAC_LINK_UTIL_PORT_TMAC_TMAC_UTILIZATION(val) \
2858 vxge_vBIT(val, 1, 7)
2859 #define VXGE_HW_TXMAC_LINK_UTIL_PORT_TMAC_UTIL_CFG(val) vxge_vBIT(val, 8, 4)
2860 #define VXGE_HW_TXMAC_LINK_UTIL_PORT_TMAC_TMAC_FRAC_UTIL(val) \
2861 vxge_vBIT(val, 12, 4)
2862 #define VXGE_HW_TXMAC_LINK_UTIL_PORT_TMAC_PKT_WEIGHT(val) vxge_vBIT(val, 16, 4)
2867 #define VXGE_HW_TXMAC_CFG0_PORT_PAD_BYTE(val) vxge_vBIT(val, 8, 8)
2869 #define VXGE_HW_TXMAC_CFG1_PORT_AVG_IPG(val) vxge_vBIT(val, 40, 8)
2879 #define VXGE_HW_LAG_MARKER_CFG_RESP_TIMEOUT(val) vxge_vBIT(val, 16, 16)
2880 #define VXGE_HW_LAG_MARKER_CFG_SLOW_PROTO_MRKR_MIN_INTERVAL(val) \
2881 vxge_vBIT(val, 32, 16)
2885 #define VXGE_HW_LAG_TX_CFG_DISTRIB_ALG_SEL(val) vxge_vBIT(val, 6, 2)
2887 #define VXGE_HW_LAG_TX_CFG_COLL_MAX_DELAY(val) vxge_vBIT(val, 16, 16)
2889 #define VXGE_HW_LAG_TX_STATUS_TLAG_TIMER_VAL_EMPTIED_LINK(val) \
2890 vxge_vBIT(val, 0, 8)
2891 #define VXGE_HW_LAG_TX_STATUS_TLAG_TIMER_VAL_SLOW_PROTO_MRKR(val) \
2892 vxge_vBIT(val, 8, 8)
2893 #define VXGE_HW_LAG_TX_STATUS_TLAG_TIMER_VAL_SLOW_PROTO_MRKRRESP(val) \
2894 vxge_vBIT(val, 16, 8)
2899 VXGE_HAL_SRPCIM_TO_MRPCIM_VPLANE_RMSG_SWIF_SRPCIM_TO_MRPCIM_VPLANE_RMSG(val)\
2900 vxge_vBIT(val, 0, 64)
2904 #define VXGE_HW_MRPCIM_TO_SRPCIM_VPLANE_WMSG_MRPCIM_TO_SRPCIM_VPLANE_WMSG(val) \
2905 vxge_vBIT(val, 0, 64)
2909 #define VXGE_HW_DEBUG_STATS0_RSTDROP_MSG(val) vxge_vBIT(val, 0, 32)
2910 #define VXGE_HW_DEBUG_STATS0_RSTDROP_CPL(val) vxge_vBIT(val, 32, 32)
2912 #define VXGE_HW_DEBUG_STATS1_RSTDROP_CLIENT0(val) vxge_vBIT(val, 0, 32)
2913 #define VXGE_HW_DEBUG_STATS1_RSTDROP_CLIENT1(val) vxge_vBIT(val, 32, 32)
2915 #define VXGE_HW_DEBUG_STATS2_RSTDROP_CLIENT2(val) vxge_vBIT(val, 0, 32)
2917 #define VXGE_HW_DEBUG_STATS3_VPLANE_DEPL_PH(val) vxge_vBIT(val, 0, 16)
2918 #define VXGE_HW_DEBUG_STATS3_VPLANE_DEPL_NPH(val) vxge_vBIT(val, 16, 16)
2919 #define VXGE_HW_DEBUG_STATS3_VPLANE_DEPL_CPLH(val) vxge_vBIT(val, 32, 16)
2921 #define VXGE_HW_DEBUG_STATS4_VPLANE_DEPL_PD(val) vxge_vBIT(val, 0, 16)
2922 #define VXGE_HW_DEBUG_STATS4_VPLANE_DEPL_NPD(val) vxge_vBIT(val, 16, 16)
2923 #define VXGE_HW_DEBUG_STATS4_VPLANE_DEPL_CPLD(val) vxge_vBIT(val, 32, 16)
3165 #define VXGE_HW_SRPCIM_TO_MRPCIM_ALARM_REG_PPIF_SRPCIM_TO_MRPCIM_ALARM(val) \
3166 vxge_vBIT(val, 0, 17)
3170 #define VXGE_HW_VPATH_TO_MRPCIM_ALARM_REG_PPIF_VPATH_TO_MRPCIM_ALARM(val) \
3171 vxge_vBIT(val, 0, 17)
3221 #define VXGE_HW_DMAIF_DMADBL_PENDING_DBLGEN_IN_PROG(val) \
3222 vxge_vBIT(val, 13, 51)
3224 #define VXGE_HW_WRCRDTARB_STATUS0_VPLANE_WRCRDTARB_ABS_AVAIL_P_H(val) \
3225 vxge_vBIT(val, 0, 8)
3227 #define VXGE_HW_WRCRDTARB_STATUS1_VPLANE_WRCRDTARB_ABS_AVAIL_P_D(val) \
3228 vxge_vBIT(val, 4, 12)
3243 #define VXGE_HW_MRPCIM_GENERAL_CFG2_MRPCIM_STATS_MAP_TO_VPATH(val) \
3244 vxge_vBIT(val, 47, 5)
3255 #define VXGE_HW_MRPCIM_GENERAL_CFG3_MR_MAX_MVFS(val) vxge_vBIT(val, 20, 16)
3256 #define VXGE_HW_MRPCIM_GENERAL_CFG3_MR_MVF_TBL_SIZE(val) \
3257 vxge_vBIT(val, 36, 16)
3259 #define VXGE_HW_MRPCIM_GENERAL_CFG3_REG_MODIFIED_CFG(val) vxge_vBIT(val, 56, 2)
3263 #define VXGE_HW_MRPCIM_STATS_START_HOST_ADDR_MRPCIM_STATS_START_HOST_ADDR(val)\
3264 vxge_vBIT(val, 0, 57)
3269 #define VXGE_HW_RDCRDTARB_CFG0_RDA_MAX_OUTSTANDING_RDS(val) \
3270 vxge_vBIT(val, 18, 6)
3271 #define VXGE_HW_RDCRDTARB_CFG0_PDA_MAX_OUTSTANDING_RDS(val) \
3272 vxge_vBIT(val, 26, 6)
3273 #define VXGE_HW_RDCRDTARB_CFG0_DBLGEN_MAX_OUTSTANDING_RDS(val) \
3274 vxge_vBIT(val, 34, 6)
3275 #define VXGE_HW_RDCRDTARB_CFG0_WAIT_CNT(val) vxge_vBIT(val, 48, 4)
3276 #define VXGE_HW_RDCRDTARB_CFG0_MAX_OUTSTANDING_RDS(val) vxge_vBIT(val, 54, 6)
3281 #define VXGE_HW_BF_SW_RESET_BF_SW_RESET(val) vxge_vBIT(val, 0, 8)
3288 #define VXGE_HW_MRPCIM_DEBUG_STATS0_INI_WR_DROP(val) vxge_vBIT(val, 0, 32)
3289 #define VXGE_HW_MRPCIM_DEBUG_STATS0_INI_RD_DROP(val) vxge_vBIT(val, 32, 32)
3291 #define VXGE_HW_MRPCIM_DEBUG_STATS1_VPLANE_WRCRDTARB_PH_CRDT_DEPLETED(val) \
3292 vxge_vBIT(val, 32, 32)
3294 #define VXGE_HW_MRPCIM_DEBUG_STATS2_VPLANE_WRCRDTARB_PD_CRDT_DEPLETED(val) \
3295 vxge_vBIT(val, 32, 32)
3297 #define VXGE_HW_MRPCIM_DEBUG_STATS3_VPLANE_RDCRDTARB_NPH_CRDT_DEPLETED(val) \
3298 vxge_vBIT(val, 32, 32)
3300 #define VXGE_HW_MRPCIM_DEBUG_STATS4_INI_WR_VPIN_DROP(val) vxge_vBIT(val, 0, 32)
3301 #define VXGE_HW_MRPCIM_DEBUG_STATS4_INI_RD_VPIN_DROP(val) \
3302 vxge_vBIT(val, 32, 32)
3304 #define VXGE_HW_GENSTATS_COUNT01_GENSTATS_COUNT1(val) vxge_vBIT(val, 0, 32)
3305 #define VXGE_HW_GENSTATS_COUNT01_GENSTATS_COUNT0(val) vxge_vBIT(val, 32, 32)
3307 #define VXGE_HW_GENSTATS_COUNT23_GENSTATS_COUNT3(val) vxge_vBIT(val, 0, 32)
3308 #define VXGE_HW_GENSTATS_COUNT23_GENSTATS_COUNT2(val) vxge_vBIT(val, 32, 32)
3310 #define VXGE_HW_GENSTATS_COUNT4_GENSTATS_COUNT4(val) vxge_vBIT(val, 32, 32)
3312 #define VXGE_HW_GENSTATS_COUNT5_GENSTATS_COUNT5(val) vxge_vBIT(val, 32, 32)
3317 #define VXGE_HW_GENSTATS_CFG_DTYPE_SEL(val) vxge_vBIT(val, 3, 5)
3318 #define VXGE_HW_GENSTATS_CFG_CLIENT_NO_SEL(val) vxge_vBIT(val, 9, 3)
3319 #define VXGE_HW_GENSTATS_CFG_WR_RD_CPL_SEL(val) vxge_vBIT(val, 14, 2)
3320 #define VXGE_HW_GENSTATS_CFG_VPATH_SEL(val) vxge_vBIT(val, 31, 17)
3342 #define VXGE_HW_G3IFCMD_FB_ERR_REG_G3IF_RWDQS_DLL_LOCK(val) \
3343 vxge_vBIT(val, 24, 8)
3356 #define VXGE_HW_G3IFCMD_CMU_ERR_REG_G3IF_RWDQS_DLL_LOCK(val) \
3357 vxge_vBIT(val, 24, 8)
3370 #define VXGE_HW_G3IFCMD_CML_ERR_REG_G3IF_RWDQS_DLL_LOCK(val) \
3371 vxge_vBIT(val, 24, 8)
3378 #define VXGE_HW_VPATH_TO_VPLANE_MAP_VPATH_TO_VPLANE_MAP(val) \
3379 vxge_vBIT(val, 3, 5)
3383 #define VXGE_HW_XGXS_CFG_PORT_SIG_DETECT_FORCE_LOS(val) vxge_vBIT(val, 16, 4)
3384 #define VXGE_HW_XGXS_CFG_PORT_SIG_DETECT_FORCE_VALID(val) vxge_vBIT(val, 20, 4)
3386 #define VXGE_HW_XGXS_CFG_PORT_SEL_INFO_1(val) vxge_vBIT(val, 29, 3)
3387 #define VXGE_HW_XGXS_CFG_PORT_TX_LANE0_SKEW(val) vxge_vBIT(val, 32, 4)
3388 #define VXGE_HW_XGXS_CFG_PORT_TX_LANE1_SKEW(val) vxge_vBIT(val, 36, 4)
3389 #define VXGE_HW_XGXS_CFG_PORT_TX_LANE2_SKEW(val) vxge_vBIT(val, 40, 4)
3390 #define VXGE_HW_XGXS_CFG_PORT_TX_LANE3_SKEW(val) vxge_vBIT(val, 44, 4)
3392 #define VXGE_HW_XGXS_RXBER_CFG_PORT_INTERVAL_DUR(val) vxge_vBIT(val, 0, 4)
3393 #define VXGE_HW_XGXS_RXBER_CFG_PORT_RXGXS_INTERVAL_CNT(val) \
3394 vxge_vBIT(val, 16, 48)
3396 #define VXGE_HW_XGXS_RXBER_STATUS_PORT_RXGXS_RXGXS_LANE_A_ERR_CNT(val) \
3397 vxge_vBIT(val, 0, 16)
3398 #define VXGE_HW_XGXS_RXBER_STATUS_PORT_RXGXS_RXGXS_LANE_B_ERR_CNT(val) \
3399 vxge_vBIT(val, 16, 16)
3400 #define VXGE_HW_XGXS_RXBER_STATUS_PORT_RXGXS_RXGXS_LANE_C_ERR_CNT(val) \
3401 vxge_vBIT(val, 32, 16)
3402 #define VXGE_HW_XGXS_RXBER_STATUS_PORT_RXGXS_RXGXS_LANE_D_ERR_CNT(val) \
3403 vxge_vBIT(val, 48, 16)
3405 #define VXGE_HW_XGXS_STATUS_PORT_XMACJ_PCS_TX_ACTIVITY(val) vxge_vBIT(val, 0, 4)
3406 #define VXGE_HW_XGXS_STATUS_PORT_XMACJ_PCS_RX_ACTIVITY(val) vxge_vBIT(val, 4, 4)
3408 #define VXGE_HW_XGXS_STATUS_PORT_XMACJ_PCS_BYTE_SYNC_LOST(val) \
3409 vxge_vBIT(val, 12, 4)
3410 #define VXGE_HW_XGXS_STATUS_PORT_XMACJ_PCS_CTC_ERR(val) vxge_vBIT(val, 16, 4)
3412 #define VXGE_HW_XGXS_STATUS_PORT_XMACJ_PCS_DEC_ERR(val) vxge_vBIT(val, 24, 8)
3413 #define VXGE_HW_XGXS_STATUS_PORT_XMACJ_PCS_SKIP_INS_REQ(val) \
3414 vxge_vBIT(val, 32, 4)
3415 #define VXGE_HW_XGXS_STATUS_PORT_XMACJ_PCS_SKIP_DEL_REQ(val) \
3416 vxge_vBIT(val, 36, 4)
3418 #define VXGE_HW_XGXS_PMA_RESET_PORT_SERDES_RESET(val) vxge_vBIT(val, 0, 8)
3426 #define VXGE_HW_XGXS_INFO_PORT_XMACJ_INFO_0(val) vxge_vBIT(val, 0, 32)
3427 #define VXGE_HW_XGXS_INFO_PORT_XMACJ_INFO_1(val) vxge_vBIT(val, 32, 32)
3429 #define VXGE_HW_RATEMGMT_CFG_PORT_MODE(val) vxge_vBIT(val, 2, 2)
3446 #define VXGE_HW_RATEMGMT_ANTP_CFG_PORT_T_RETRY_PHY_QUERY(val) \
3447 vxge_vBIT(val, 16, 4)
3448 #define VXGE_HW_RATEMGMT_ANTP_CFG_PORT_T_WAIT_MDIO_RESPONSE(val) \
3449 vxge_vBIT(val, 20, 4)
3450 #define VXGE_HW_RATEMGMT_ANTP_CFG_PORT_T_LDOWN_REAUTO_RESPONSE(val) \
3451 vxge_vBIT(val, 24, 4)
3460 #define VXGE_HW_RATEMGMT_ANBE_CFG_PORT_T_SYNC_10G_KX4(val) vxge_vBIT(val, 16, 4)
3461 #define VXGE_HW_RATEMGMT_ANBE_CFG_PORT_T_SYNC_1G_KX(val) vxge_vBIT(val, 20, 4)
3462 #define VXGE_HW_RATEMGMT_ANBE_CFG_PORT_T_DME_EXCHANGE(val) vxge_vBIT(val, 24, 4)
3466 #define VXGE_HW_ANBE_CFG_PORT_RESET_CFG_REGS(val) vxge_vBIT(val, 0, 8)
3467 #define VXGE_HW_ANBE_CFG_PORT_ALIGN_10G_KX4_OVERRIDE(val) vxge_vBIT(val, 10, 2)
3468 #define VXGE_HW_ANBE_CFG_PORT_SYNC_1G_KX_OVERRIDE(val) vxge_vBIT(val, 14, 2)
3472 #define VXGE_HW_ANBE_MGR_CTRL_PORT_ADDR(val) vxge_vBIT(val, 15, 9)
3473 #define VXGE_HW_ANBE_MGR_CTRL_PORT_DATA(val) vxge_vBIT(val, 32, 32)
3488 #define VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_ANBEFSM_STATE(val) \
3489 vxge_vBIT(val, 18, 6)
3507 #define VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_COUNT_BP(val) \
3508 vxge_vBIT(val, 56, 4)
3509 #define VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_COUNT_NP(val) \
3510 vxge_vBIT(val, 60, 4)
3522 #define VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_TX_NONCE(val) \
3523 vxge_vBIT(val, 43, 5)
3530 #define VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_ECHOED_NONCE(val) \
3531 vxge_vBIT(val, 54, 5)
3532 #define VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_SELECTOR_FIELD(val) \
3533 vxge_vBIT(val, 59, 5)
3535 #define VXGE_HW_ANBE_HWFSM_NP_STATUS_PORT_RATEMGMT_NP_BITS_47_TO_32(val) \
3536 vxge_vBIT(val, 16, 16)
3537 #define VXGE_HW_ANBE_HWFSM_NP_STATUS_PORT_RATEMGMT_NP_BITS_31_TO_0(val) \
3538 vxge_vBIT(val, 32, 32)
3545 #define VXGE_HW_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_ANTPFSM_STATE(val) \
3546 vxge_vBIT(val, 10, 6)
3567 #define VXGE_HW_ANTP_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_ABILITY_FIELD(val) \
3568 vxge_vBIT(val, 4, 7)
3569 #define VXGE_HW_ANTP_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_SELECTOR_FIELD(val) \
3570 vxge_vBIT(val, 11, 5)
3577 #define VXGE_HW_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_MESSAGE_CODE(val) \
3578 vxge_vBIT(val, 5, 11)
3579 #define VXGE_HW_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_UNF_CODE_FIELD1(val) \
3580 vxge_vBIT(val, 16, 16)
3581 #define VXGE_HW_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_UNF_CODE_FIELD2(val) \
3582 vxge_vBIT(val, 32, 16)
3585 #define VXGE_HW_MDIO_MGR_ACCESS_PORT_OP_TYPE(val) vxge_vBIT(val, 5, 3)
3586 #define VXGE_HW_MDIO_MGR_ACCESS_PORT_DEVAD(val) vxge_vBIT(val, 11, 5)
3587 #define VXGE_HW_MDIO_MGR_ACCESS_PORT_ADDR(val) vxge_vBIT(val, 16, 16)
3588 #define VXGE_HW_MDIO_MGR_ACCESS_PORT_DATA(val) vxge_vBIT(val, 32, 16)
3589 #define VXGE_HW_MDIO_MGR_ACCESS_PORT_ST_PATTERN(val) vxge_vBIT(val, 49, 2)
3591 #define VXGE_HW_MDIO_MGR_ACCESS_PORT_PRTAD(val) vxge_vBIT(val, 55, 5)
3595 #define VXGE_HW_XMAC_VSPORT_CHOICES_VH_VSPORT_VECTOR(val) vxge_vBIT(val, 0, 17)
3599 #define VXGE_HW_RX_THRESH_CFG_VP_PAUSE_LOW_THR(val) vxge_vBIT(val, 0, 8)
3600 #define VXGE_HW_RX_THRESH_CFG_VP_PAUSE_HIGH_THR(val) vxge_vBIT(val, 8, 8)
3601 #define VXGE_HW_RX_THRESH_CFG_VP_RED_THR_0(val) vxge_vBIT(val, 16, 8)
3602 #define VXGE_HW_RX_THRESH_CFG_VP_RED_THR_1(val) vxge_vBIT(val, 24, 8)
3603 #define VXGE_HW_RX_THRESH_CFG_VP_RED_THR_2(val) vxge_vBIT(val, 32, 8)
3604 #define VXGE_HW_RX_THRESH_CFG_VP_RED_THR_3(val) vxge_vBIT(val, 40, 8)
3612 #define VXGE_HW_TIM_MR2SR_RESOURCE_ASSIGNMENT_VH_BMAP_ROOT(val) \
3613 vxge_vBIT(val, 0, 32)
3649 #define VXGE_HW_SRPCIM_TO_MRPCIM_WMSG_SRPCIM_TO_MRPCIM_WMSG(val) \
3650 vxge_vBIT(val, 0, 64)
3654 #define VXGE_HW_MRPCIM_TO_SRPCIM_RMSG_SWIF_MRPCIM_TO_SRPCIM_RMSG(val) \
3655 vxge_vBIT(val, 0, 64)
3657 #define VXGE_HW_VPATH_TO_SRPCIM_RMSG_SEL_VPATH_TO_SRPCIM_RMSG_SEL(val) \
3658 vxge_vBIT(val, 0, 5)
3660 #define VXGE_HW_VPATH_TO_SRPCIM_RMSG_SWIF_VPATH_TO_SRPCIM_RMSG(val) \
3661 vxge_vBIT(val, 0, 64)
3699 #define VXGE_HW_PF_SW_RESET_PF_SW_RESET(val) vxge_vBIT(val, 0, 8)
3708 #define VXGE_HW_SRPCIM_INTERRUPT_CFG1_ALARM_MAP_TO_MSG(val) vxge_vBIT(val, 1, 7)
3709 #define VXGE_HW_SRPCIM_INTERRUPT_CFG1_TRAFFIC_CLASS(val) vxge_vBIT(val, 9, 3)
3723 #define VXGE_HW_TGT_PF_ILLEGAL_ACCESS_SWIF_REGION(val) vxge_vBIT(val, 1, 7)
3743 #define VXGE_HW_XMAC_VSPORT_CHOICES_SR_CLONE_VSPORT_VECTOR(val) \
3744 vxge_vBIT(val, 0, 17)
3748 #define VXGE_HW_MR_RQA_TOP_PRTY_FOR_VH_RQA_TOP_PRTY_FOR_VH(val) \
3749 vxge_vBIT(val, 59, 5)
3773 #define VXGE_HW_WDE_CFG_ALIGNMENT_PREFERENCE(val) vxge_vBIT(val, 30, 2)
3774 #define VXGE_HW_WDE_CFG_MEM_WORD_SIZE(val) vxge_vBIT(val, 46, 2)
3784 #define VXGE_HW_VPATH_TO_FUNC_MAP_CFG1_VPATH_TO_FUNC_MAP_CFG1(val) \
3785 vxge_vBIT(val, 3, 5)
3789 #define VXGE_HW_SRPCIM_TO_VPATH_WMSG_SRPCIM_TO_VPATH_WMSG(val) \
3790 vxge_vBIT(val, 0, 64)
3797 #define VXGE_HW_TIM_VPATH_ASSIGNMENT_BMAP_ROOT(val) vxge_vBIT(val, 0, 32)
3801 #define VXGE_HW_RQA_TOP_PRTY_FOR_VP_RQA_TOP_PRTY_FOR_VP(val) \
3802 vxge_vBIT(val, 59, 5)
3830 #define VXGE_HW_RTS_MGR_CFG0_VPMGMT_CLONE_FLEX_L4PRTCL_VALUE(val) \
3831 vxge_vBIT(val, 24, 8)
3840 #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_ETYPE(val) \
3841 vxge_vBIT(val, 5, 3)
3842 #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_ICMP_TCPSYN(val) \
3843 vxge_vBIT(val, 9, 3)
3844 #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_L4PN(val) \
3845 vxge_vBIT(val, 13, 3)
3846 #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_RANGE_L4PN(val) \
3847 vxge_vBIT(val, 17, 3)
3848 #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_RTH_IT(val) \
3849 vxge_vBIT(val, 21, 3)
3850 #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_DS(val) \
3851 vxge_vBIT(val, 25, 3)
3852 #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_QOS(val) \
3853 vxge_vBIT(val, 29, 3)
3854 #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_ZL4PYLD(val) \
3855 vxge_vBIT(val, 33, 3)
3856 #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_L4PRTCL(val) \
3857 vxge_vBIT(val, 37, 3)
3867 #define VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_MAX_PYLD_LEN(val) \
3868 vxge_vBIT(val, 50, 14)
3872 #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_ACCEL_SEND(val) \
3873 vxge_vBIT(val, 9, 3)
3875 #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_HIGH_PTIME(val) \
3876 vxge_vBIT(val, 20, 16)
3882 #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_MAX_LIMIT(val) \
3883 vxge_vBIT(val, 48, 8)
3889 #define VXGE_HW_XMAC_VSPORT_CHOICES_VP_VSPORT_VECTOR(val) vxge_vBIT(val, 0, 17)
3904 #define VXGE_HW_XMAC_GEN_CFG_VPMGMT_CLONE_RATEMGMT_MAC_RATE_SEL(val) \
3905 vxge_vBIT(val, 2, 2)
3909 #define VXGE_HW_XMAC_GEN_CFG_VPMGMT_CLONE_PERIOD_NTWK_UP(val) \
3910 vxge_vBIT(val, 28, 4)
3911 #define VXGE_HW_XMAC_GEN_CFG_VPMGMT_CLONE_PERIOD_NTWK_DOWN(val) \
3912 vxge_vBIT(val, 32, 4)
3915 #define VXGE_HW_XMAC_TIMESTAMP_VPMGMT_CLONE_USE_LINK_ID(val) \
3916 vxge_vBIT(val, 6, 2)
3917 #define VXGE_HW_XMAC_TIMESTAMP_VPMGMT_CLONE_INTERVAL(val) vxge_vBIT(val, 12, 4)
3919 #define VXGE_HW_XMAC_TIMESTAMP_VPMGMT_CLONE_XMACJ_ROLLOVER_CNT(val) \
3920 vxge_vBIT(val, 32, 16)
3922 #define VXGE_HW_XMAC_STATS_GEN_CFG_VPMGMT_CLONE_PRTAGGR_CUM_TIMER(val) \
3923 vxge_vBIT(val, 4, 4)
3924 #define VXGE_HW_XMAC_STATS_GEN_CFG_VPMGMT_CLONE_VPATH_CUM_TIMER(val) \
3925 vxge_vBIT(val, 8, 4)
3940 #define VXGE_HW_TXMAC_CFG0_PORT_VPMGMT_CLONE_PAD_BYTE(val) vxge_vBIT(val, 8, 8)
3944 #define VXGE_HW_WOL_MP_CRC_CRC(val) vxge_vBIT(val, 0, 32)
3947 #define VXGE_HW_WOL_MP_MASK_A_MASK(val) vxge_vBIT(val, 0, 64)
3949 #define VXGE_HW_WOL_MP_MASK_B_MASK(val) vxge_vBIT(val, 0, 64)
3957 #define VXGE_HW_RX_DATAPATH_UTIL_VP_CLONE_FAU_RX_UTILIZATION(val) \
3958 vxge_vBIT(val, 7, 9)
3959 #define VXGE_HW_RX_DATAPATH_UTIL_VP_CLONE_RX_UTIL_CFG(val) \
3960 vxge_vBIT(val, 16, 4)
3961 #define VXGE_HW_RX_DATAPATH_UTIL_VP_CLONE_FAU_RX_FRAC_UTIL(val) \
3962 vxge_vBIT(val, 20, 4)
3963 #define VXGE_HW_RX_DATAPATH_UTIL_VP_CLONE_RX_PKT_WEIGHT(val) \
3964 vxge_vBIT(val, 24, 4)
3968 #define VXGE_HW_TX_DATAPATH_UTIL_VP_CLONE_TPA_TX_UTILIZATION(val) \
3969 vxge_vBIT(val, 7, 9)
3970 #define VXGE_HW_TX_DATAPATH_UTIL_VP_CLONE_TX_UTIL_CFG(val) \
3971 vxge_vBIT(val, 16, 4)
3972 #define VXGE_HW_TX_DATAPATH_UTIL_VP_CLONE_TPA_TX_FRAC_UTIL(val) \
3973 vxge_vBIT(val, 20, 4)
3974 #define VXGE_HW_TX_DATAPATH_UTIL_VP_CLONE_TX_PKT_WEIGHT(val) \
3975 vxge_vBIT(val, 24, 4)
3984 #define VXGE_HW_USDC_VPATH_SGRP_ASSIGN(val) vxge_vBIT(val, 0, 32)
4000 #define VXGE_HW_PRC_CFG1_RX_TIMER_VAL(val) vxge_vBIT(val, 3, 29)
4006 #define VXGE_HW_PRC_CFG1_RESET_TIMER_ON_RXD_RET(val) vxge_vBIT(val, 40, 2)
4011 #define VXGE_HW_PRC_CFG4_RING_MODE(val) vxge_vBIT(val, 14, 2)
4018 #define VXGE_HW_PRC_CFG4_BACKOFF_INTERVAL(val) vxge_vBIT(val, 40, 24)
4020 #define VXGE_HW_PRC_CFG5_RXD0_ADD(val) vxge_vBIT(val, 0, 61)
4027 #define VXGE_HW_PRC_CFG6_RXD_CRXDT(val) vxge_vBIT(val, 23, 9)
4028 #define VXGE_HW_PRC_CFG6_RXD_SPAT(val) vxge_vBIT(val, 36, 9)
4029 #define VXGE_HW_PRC_CFG6_GET_RXD_SPAT(val) vxge_bVALn(val, 36, 9)
4031 #define VXGE_HW_PRC_CFG7_SCATTER_MODE(val) vxge_vBIT(val, 6, 2)
4035 #define VXGE_HW_PRC_CFG7_RXD_BUFF_SIZE_MASK(val) vxge_vBIT(val, 20, 4)
4036 #define VXGE_HW_PRC_CFG7_BUFF_SIZE0_MASK(val) vxge_vBIT(val, 27, 5)
4038 #define VXGE_HW_TIM_DEST_ADDR_TIM_DEST_ADDR(val) vxge_vBIT(val, 0, 64)
4040 #define VXGE_HW_PRC_RXD_DOORBELL_NEW_QW_CNT(val) vxge_vBIT(val, 48, 16)
4042 #define VXGE_HW_RQA_PRTY_FOR_VP_RQA_PRTY_FOR_VP(val) vxge_vBIT(val, 59, 5)
4044 #define VXGE_HW_RXDMEM_SIZE_PRC_RXDMEM_SIZE(val) vxge_vBIT(val, 51, 13)
4046 #define VXGE_HW_FRM_IN_PROGRESS_CNT_PRC_FRM_IN_PROGRESS_CNT(val) \
4047 vxge_vBIT(val, 59, 5)
4049 #define VXGE_HW_RX_MULTI_CAST_STATS_FRAME_DISCARD(val) vxge_vBIT(val, 48, 16)
4051 #define VXGE_HW_RX_FRM_TRANSFERRED_RX_FRM_TRANSFERRED(val) \
4052 vxge_vBIT(val, 32, 32)
4054 #define VXGE_HW_RXD_RETURNED_RXD_RETURNED(val) vxge_vBIT(val, 48, 16)
4058 #define VXGE_HW_KDFC_FIFO_TRPL_PARTITION_LENGTH_0(val) vxge_vBIT(val, 17, 15)
4059 #define VXGE_HW_KDFC_FIFO_TRPL_PARTITION_LENGTH_1(val) vxge_vBIT(val, 33, 15)
4060 #define VXGE_HW_KDFC_FIFO_TRPL_PARTITION_LENGTH_2(val) vxge_vBIT(val, 49, 15)
4064 #define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE(val) vxge_vBIT(val, 14, 2)
4067 #define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_INT_CTRL(val) vxge_vBIT(val, 26, 2)
4072 #define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SELECT(val) vxge_vBIT(val, 32, 8)
4073 #define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_INT_NO(val) vxge_vBIT(val, 41, 7)
4074 #define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_BIT_MAP(val) vxge_vBIT(val, 48, 16)
4076 #define VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_MODE(val) vxge_vBIT(val, 14, 2)
4079 #define VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_INT_CTRL(val) vxge_vBIT(val, 26, 2)
4084 #define VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_SELECT(val) vxge_vBIT(val, 32, 8)
4085 #define VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_INT_NO(val) vxge_vBIT(val, 41, 7)
4086 #define VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_BIT_MAP(val) vxge_vBIT(val, 48, 16)
4090 #define VXGE_HW_KDFC_TRPL_FIFO_2_CTRL_INT_CTRL(val) vxge_vBIT(val, 26, 2)
4095 #define VXGE_HW_KDFC_TRPL_FIFO_2_CTRL_SELECT(val) vxge_vBIT(val, 32, 8)
4096 #define VXGE_HW_KDFC_TRPL_FIFO_2_CTRL_INT_NO(val) vxge_vBIT(val, 41, 7)
4097 #define VXGE_HW_KDFC_TRPL_FIFO_2_CTRL_BIT_MAP(val) vxge_vBIT(val, 48, 16)
4099 #define VXGE_HW_KDFC_TRPL_FIFO_0_WB_ADDRESS_ADD(val) vxge_vBIT(val, 0, 64)
4101 #define VXGE_HW_KDFC_TRPL_FIFO_1_WB_ADDRESS_ADD(val) vxge_vBIT(val, 0, 64)
4103 #define VXGE_HW_KDFC_TRPL_FIFO_2_WB_ADDRESS_ADD(val) vxge_vBIT(val, 0, 64)
4105 #define VXGE_HW_KDFC_TRPL_FIFO_OFFSET_KDFC_RCTR0(val) vxge_vBIT(val, 1, 15)
4106 #define VXGE_HW_KDFC_TRPL_FIFO_OFFSET_KDFC_RCTR1(val) vxge_vBIT(val, 17, 15)
4107 #define VXGE_HW_KDFC_TRPL_FIFO_OFFSET_KDFC_RCTR2(val) vxge_vBIT(val, 33, 15)
4109 #define VXGE_HW_KDFC_DRBL_TRIPLET_TOTAL_KDFC_MAX_SIZE(val) \
4110 vxge_vBIT(val, 17, 15)
4134 #define VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(val) vxge_vBIT(val, 2, 14)
4136 #define VXGE_HW_RXMAC_VCFG0_RTS_MIN_FRM_LEN(val) vxge_vBIT(val, 26, 14)
4142 #define VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_BD_MODE(val) vxge_vBIT(val, 42, 2)
4146 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION(val) vxge_vBIT(val, 1, 7)
4147 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(val) vxge_vBIT(val, 8, 4)
4152 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(val) vxge_vBIT(val, 40, 8)
4154 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_DATA(val) vxge_vBIT(val, 0, 64)
4156 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_DATA(val) vxge_vBIT(val, 0, 64)
4160 #define VXGE_HW_XMAC_VSPORT_CHOICE_VSPORT_NUMBER(val) vxge_vBIT(val, 3, 5)
4163 #define VXGE_HW_XMAC_STATS_ACCESS_CMD_OP(val) vxge_vBIT(val, 6, 2)
4165 #define VXGE_HW_XMAC_STATS_ACCESS_CMD_OFFSET_SEL(val) vxge_vBIT(val, 32, 8)
4167 #define VXGE_HW_XMAC_STATS_ACCESS_DATA_XSMGR_DATA(val) vxge_vBIT(val, 0, 64)
4194 #define VXGE_HW_RTDMA_BW_CTRL_DESIRED_BW(val) vxge_vBIT(val, 46, 18)
4197 #define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_PAD_MODE(val) vxge_vBIT(val, 6, 2)
4198 #define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_PAD_PATTERN(val) vxge_vBIT(val, 8, 8)
4201 #define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_FILL_THRESH(val) \
4202 vxge_vBIT(val, 21, 3)
4204 #define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_TXD_PYLD_WMARK(val) \
4205 vxge_vBIT(val, 29, 3)
4207 #define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY(val) \
4208 vxge_vBIT(val, 37, 3)
4210 #define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_TXD_FILL_THRESH(val) \
4211 vxge_vBIT(val, 51, 5)
4213 #define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_TXD_ADDR_BDRY(val) \
4214 vxge_vBIT(val, 61, 3)
4223 #define VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL(val) vxge_vBIT(val, 6, 26)
4229 #define VXGE_HW_TIM_CFG1_INT_NUM_URNG_A(val) vxge_vBIT(val, 41, 7)
4230 #define VXGE_HW_TIM_CFG1_INT_NUM_URNG_B(val) vxge_vBIT(val, 49, 7)
4231 #define VXGE_HW_TIM_CFG1_INT_NUM_URNG_C(val) vxge_vBIT(val, 57, 7)
4233 #define VXGE_HW_TIM_CFG2_INT_NUM_UEC_A(val) vxge_vBIT(val, 0, 16)
4234 #define VXGE_HW_TIM_CFG2_INT_NUM_UEC_B(val) vxge_vBIT(val, 16, 16)
4235 #define VXGE_HW_TIM_CFG2_INT_NUM_UEC_C(val) vxge_vBIT(val, 32, 16)
4236 #define VXGE_HW_TIM_CFG2_INT_NUM_UEC_D(val) vxge_vBIT(val, 48, 16)
4239 #define VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_EVENT_SF(val) vxge_vBIT(val, 1, 4)
4240 #define VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(val) vxge_vBIT(val, 6, 26)
4241 #define VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(val) vxge_vBIT(val, 32, 6)
4242 #define VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL(val) vxge_vBIT(val, 38, 26)
4244 #define VXGE_HW_TIM_WRKLD_CLC_WRKLD_EVAL_PRD(val) vxge_vBIT(val, 0, 32)
4245 #define VXGE_HW_TIM_WRKLD_CLC_WRKLD_EVAL_DIV(val) vxge_vBIT(val, 35, 5)
4247 #define VXGE_HW_TIM_WRKLD_CLC_CNT_RX_TX(val) vxge_vBIT(val, 41, 2)
4249 #define VXGE_HW_TIM_WRKLD_CLC_HOST_UTIL(val) vxge_vBIT(val, 57, 7)
4251 #define VXGE_HW_TIM_BITMAP_MASK(val) vxge_vBIT(val, 0, 32)
4255 #define VXGE_HW_TIM_RING_ASSN_INT_NUM(val) vxge_vBIT(val, 6, 2)
4260 #define VXGE_HW_TIM_REMAP_TO_VPATH_NUM(val) vxge_vBIT(val, 11, 5)
4262 #define VXGE_HW_TIM_VPATH_MAP_BMAP_ROOT(val) vxge_vBIT(val, 0, 32)
4271 #define VXGE_HW_SGRP_ASSIGN_SGRP_ASSIGN(val) vxge_vBIT(val, 0, 64)
4273 #define VXGE_HW_SGRP_AOA_AND_RESULT_PET_SGRP_AOA_AND_RESULT(val) \
4274 vxge_vBIT(val, 0, 64)
4303 #define VXGE_HW_PE_MR2VP_ACK_BLK_LIMIT_BLK_LIMIT(val) vxge_vBIT(val, 32, 32)
4305 #define VXGE_HW_PE_MR2VP_RIRR_LIRR_BLK_LIMIT_RIRR_BLK_LIMIT(val) \
4306 vxge_vBIT(val, 0, 32)
4307 #define VXGE_HW_PE_MR2VP_RIRR_LIRR_BLK_LIMIT_LIRR_BLK_LIMIT(val) \
4308 vxge_vBIT(val, 32, 32)
4310 #define VXGE_HW_TXPE_PCI_NCE_CFG_NCE_THRESH(val) vxge_vBIT(val, 0, 32)
4330 #define VXGE_HW_UMQDMQ_IR_INIT_HOST_WRITE_ADD(val) vxge_vBIT(val, 0, 64)
4334 #define VXGE_HW_DMQ_IR_INT_NUMBER(val) vxge_vBIT(val, 9, 7)
4335 #define VXGE_HW_DMQ_IR_INT_BITMAP(val) vxge_vBIT(val, 16, 16)
4337 #define VXGE_HW_DMQ_BWR_INIT_ADD_HOST(val) vxge_vBIT(val, 0, 64)
4339 #define VXGE_HW_DMQ_BWR_INIT_BYTE_COUNT(val) vxge_vBIT(val, 0, 32)
4341 #define VXGE_HW_DMQ_IR_POLICY(val) vxge_vBIT(val, 0, 8)
4345 #define VXGE_HW_UMQ_INT_NUMBER(val) vxge_vBIT(val, 9, 7)
4346 #define VXGE_HW_UMQ_INT_BITMAP(val) vxge_vBIT(val, 16, 16)
4348 #define VXGE_HW_UMQ_MR2VP_BWR_PFCH_INIT_NUMBER(val) vxge_vBIT(val, 0, 8)
4352 #define VXGE_HW_UMQ_MR2VP_BWR_EOL_POLL_LATENCY(val) vxge_vBIT(val, 32, 32)
4354 #define VXGE_HW_UMQ_BWR_INIT_ADD_HOST(val) vxge_vBIT(val, 0, 64)
4356 #define VXGE_HW_UMQ_BWR_INIT_BYTE_COUNT(val) vxge_vBIT(val, 0, 32)
4374 #define VXGE_HW_TX_VP_RESET_DISCARDED_FRMS_TX_VP_RESET_DISCARDED_FRMS(val) \
4375 vxge_vBIT(val, 48, 16)
4385 #define VXGE_HW_DBG_STATS_RX_MPA_CRC_FAIL_FRMS(val) vxge_vBIT(val, 0, 16)
4386 #define VXGE_HW_DBG_STATS_RX_MPA_MRK_FAIL_FRMS(val) vxge_vBIT(val, 16, 16)
4387 #define VXGE_HW_DBG_STATS_RX_MPA_LEN_FAIL_FRMS(val) vxge_vBIT(val, 32, 16)
4389 #define VXGE_HW_DBG_STATS_RX_FAU_RX_WOL_FRMS(val) vxge_vBIT(val, 0, 16)
4390 #define VXGE_HW_DBG_STATS_RX_FAU_RX_VP_RESET_DISCARDED_FRMS(val) \
4391 vxge_vBIT(val, 16, 16)
4392 #define VXGE_HW_DBG_STATS_RX_FAU_RX_PERMITTED_FRMS(val) \
4393 vxge_vBIT(val, 32, 32)
4417 #define VXGE_HW_VPATH_TO_SRPCIM_WMSG_VPATH_TO_SRPCIM_WMSG(val) \
4418 vxge_vBIT(val, 0, 64)
4484 #define VXGE_HW_SRPCIM_TO_VPATH_ALARM_REG_PPIF_SRPCIM_TO_VPATH_ALARM(val) \
4485 vxge_vBIT(val, 0, 17)
4491 #define VXGE_HW_KDFCCTL_STATUS_KDFCCTL_FIFO0_PRES(val) vxge_vBIT(val, 0, 8)
4492 #define VXGE_HW_KDFCCTL_STATUS_KDFCCTL_FIFO1_PRES(val) vxge_vBIT(val, 8, 8)
4493 #define VXGE_HW_KDFCCTL_STATUS_KDFCCTL_FIFO2_PRES(val) vxge_vBIT(val, 16, 8)
4494 #define VXGE_HW_KDFCCTL_STATUS_KDFCCTL_FIFO0_OVRWR(val) vxge_vBIT(val, 24, 8)
4495 #define VXGE_HW_KDFCCTL_STATUS_KDFCCTL_FIFO1_OVRWR(val) vxge_vBIT(val, 32, 8)
4496 #define VXGE_HW_KDFCCTL_STATUS_KDFCCTL_FIFO2_OVRWR(val) vxge_vBIT(val, 40, 8)
4499 #define VXGE_HW_RSTHDLR_STATUS_RSTHDLR_CURRENT_VPIN(val) vxge_vBIT(val, 6, 2)
4501 #define VXGE_HW_FIFO0_STATUS_DBLGEN_FIFO0_RDIDX(val) vxge_vBIT(val, 0, 12)
4503 #define VXGE_HW_FIFO1_STATUS_DBLGEN_FIFO1_RDIDX(val) vxge_vBIT(val, 0, 12)
4505 #define VXGE_HW_FIFO2_STATUS_DBLGEN_FIFO2_RDIDX(val) vxge_vBIT(val, 0, 12)
4509 #define VXGE_HW_TGT_ILLEGAL_ACCESS_SWIF_REGION(val) vxge_vBIT(val, 1, 7)
4513 #define VXGE_HW_VPATH_GENERAL_CFG1_TC_VALUE(val) vxge_vBIT(val, 1, 3)
4523 #define VXGE_HW_VPATH_GENERAL_CFG2_SIZE_QUANTUM(val) vxge_vBIT(val, 1, 3)
4563 #define VXGE_HW_STATS_CFG_START_HOST_ADDR(val) vxge_vBIT(val, 0, 57)
4565 #define VXGE_HW_INTERRUPT_CFG0_MSIX_FOR_RXTI(val) vxge_vBIT(val, 1, 7)
4566 #define VXGE_HW_INTERRUPT_CFG0_GROUP0_MSIX_FOR_TXTI(val) vxge_vBIT(val, 9, 7)
4567 #define VXGE_HW_INTERRUPT_CFG0_GROUP1_MSIX_FOR_TXTI(val) vxge_vBIT(val, 17, 7)
4568 #define VXGE_HW_INTERRUPT_CFG0_GROUP2_MSIX_FOR_TXTI(val) vxge_vBIT(val, 25, 7)
4569 #define VXGE_HW_INTERRUPT_CFG0_GROUP3_MSIX_FOR_TXTI(val) vxge_vBIT(val, 33, 7)
4573 #define VXGE_HW_INTERRUPT_CFG2_ALARM_MAP_TO_MSG(val) vxge_vBIT(val, 1, 7)
4585 #define VXGE_HW_PCI_CONFIG_ACCESS_CFG1_ADDRESS(val) vxge_vBIT(val, 0, 12)
4591 #define VXGE_HW_PCI_CONFIG_ACCESS_STATUS_DATA(val) vxge_vBIT(val, 32, 32)
4595 #define VXGE_HW_VPATH_DEBUG_STATS0_INI_NUM_MWR_SENT(val) vxge_vBIT(val, 0, 32)
4597 #define VXGE_HW_VPATH_DEBUG_STATS1_INI_NUM_MRD_SENT(val) vxge_vBIT(val, 0, 32)
4599 #define VXGE_HW_VPATH_DEBUG_STATS2_INI_NUM_CPL_RCVD(val) vxge_vBIT(val, 0, 32)
4601 #define VXGE_HW_VPATH_DEBUG_STATS3_INI_NUM_MWR_BYTE_SENT(val) \
4602 vxge_vBIT(val, 0, 64)
4604 #define VXGE_HW_VPATH_DEBUG_STATS4_INI_NUM_CPL_BYTE_RCVD(val) \
4605 vxge_vBIT(val, 0, 64)
4607 #define VXGE_HW_VPATH_DEBUG_STATS5_WRCRDTARB_XOFF(val) vxge_vBIT(val, 32, 32)
4609 #define VXGE_HW_VPATH_DEBUG_STATS6_RDCRDTARB_XOFF(val) vxge_vBIT(val, 32, 32)
4611 #define VXGE_HW_VPATH_GENSTATS_COUNT01_PPIF_VPATH_GENSTATS_COUNT1(val) \
4612 vxge_vBIT(val, 0, 32)
4613 #define VXGE_HW_VPATH_GENSTATS_COUNT01_PPIF_VPATH_GENSTATS_COUNT0(val) \
4614 vxge_vBIT(val, 32, 32)
4616 #define VXGE_HW_VPATH_GENSTATS_COUNT23_PPIF_VPATH_GENSTATS_COUNT3(val) \
4617 vxge_vBIT(val, 0, 32)
4618 #define VXGE_HW_VPATH_GENSTATS_COUNT23_PPIF_VPATH_GENSTATS_COUNT2(val) \
4619 vxge_vBIT(val, 32, 32)
4621 #define VXGE_HW_VPATH_GENSTATS_COUNT4_PPIF_VPATH_GENSTATS_COUNT4(val) \
4622 vxge_vBIT(val, 32, 32)
4624 #define VXGE_HW_VPATH_GENSTATS_COUNT5_PPIF_VPATH_GENSTATS_COUNT5(val) \
4625 vxge_vBIT(val, 32, 32)
/linux-4.1.27/include/linux/
H A Dvirtio_byteorder.h11 static inline u16 __virtio16_to_cpu(bool little_endian, __virtio16 val) __virtio16_to_cpu() argument
14 return le16_to_cpu((__force __le16)val); __virtio16_to_cpu()
16 return (__force u16)val; __virtio16_to_cpu()
19 static inline __virtio16 __cpu_to_virtio16(bool little_endian, u16 val) __cpu_to_virtio16() argument
22 return (__force __virtio16)cpu_to_le16(val); __cpu_to_virtio16()
24 return (__force __virtio16)val; __cpu_to_virtio16()
27 static inline u32 __virtio32_to_cpu(bool little_endian, __virtio32 val) __virtio32_to_cpu() argument
30 return le32_to_cpu((__force __le32)val); __virtio32_to_cpu()
32 return (__force u32)val; __virtio32_to_cpu()
35 static inline __virtio32 __cpu_to_virtio32(bool little_endian, u32 val) __cpu_to_virtio32() argument
38 return (__force __virtio32)cpu_to_le32(val); __cpu_to_virtio32()
40 return (__force __virtio32)val; __cpu_to_virtio32()
43 static inline u64 __virtio64_to_cpu(bool little_endian, __virtio64 val) __virtio64_to_cpu() argument
46 return le64_to_cpu((__force __le64)val); __virtio64_to_cpu()
48 return (__force u64)val; __virtio64_to_cpu()
51 static inline __virtio64 __cpu_to_virtio64(bool little_endian, u64 val) __cpu_to_virtio64() argument
54 return (__force __virtio64)cpu_to_le64(val); __cpu_to_virtio64()
56 return (__force __virtio64)val; __cpu_to_virtio64()
H A Dkbuild.h4 #define DEFINE(sym, val) \
5 asm volatile("\n->" #sym " %0 " #val : : "i" (val))
H A Diopoll.h29 * @val: Variable to read the value into
30 * @cond: Break condition (usually involving @val)
37 * case, the last read value at @addr is stored in @val. Must not
43 #define readx_poll_timeout(op, addr, val, cond, sleep_us, timeout_us) \
48 (val) = op(addr); \
52 (val) = op(addr); \
65 * @val: Variable to read the value into
66 * @cond: Break condition (usually involving @val)
73 * case, the last read value at @addr is stored in @val.
78 #define readx_poll_timeout_atomic(op, addr, val, cond, delay_us, timeout_us) \
82 (val) = op(addr); \
86 (val) = op(addr); \
96 #define readb_poll_timeout(addr, val, cond, delay_us, timeout_us) \
97 readx_poll_timeout(readb, addr, val, cond, delay_us, timeout_us)
99 #define readb_poll_timeout_atomic(addr, val, cond, delay_us, timeout_us) \
100 readx_poll_timeout_atomic(readb, addr, val, cond, delay_us, timeout_us)
102 #define readw_poll_timeout(addr, val, cond, delay_us, timeout_us) \
103 readx_poll_timeout(readw, addr, val, cond, delay_us, timeout_us)
105 #define readw_poll_timeout_atomic(addr, val, cond, delay_us, timeout_us) \
106 readx_poll_timeout_atomic(readw, addr, val, cond, delay_us, timeout_us)
108 #define readl_poll_timeout(addr, val, cond, delay_us, timeout_us) \
109 readx_poll_timeout(readl, addr, val, cond, delay_us, timeout_us)
111 #define readl_poll_timeout_atomic(addr, val, cond, delay_us, timeout_us) \
112 readx_poll_timeout_atomic(readl, addr, val, cond, delay_us, timeout_us)
114 #define readq_poll_timeout(addr, val, cond, delay_us, timeout_us) \
115 readx_poll_timeout(readq, addr, val, cond, delay_us, timeout_us)
117 #define readq_poll_timeout_atomic(addr, val, cond, delay_us, timeout_us) \
118 readx_poll_timeout_atomic(readq, addr, val, cond, delay_us, timeout_us)
120 #define readb_relaxed_poll_timeout(addr, val, cond, delay_us, timeout_us) \
121 readx_poll_timeout(readb_relaxed, addr, val, cond, delay_us, timeout_us)
123 #define readb_relaxed_poll_timeout_atomic(addr, val, cond, delay_us, timeout_us) \
124 readx_poll_timeout_atomic(readb_relaxed, addr, val, cond, delay_us, timeout_us)
126 #define readw_relaxed_poll_timeout(addr, val, cond, delay_us, timeout_us) \
127 readx_poll_timeout(readw_relaxed, addr, val, cond, delay_us, timeout_us)
129 #define readw_relaxed_poll_timeout_atomic(addr, val, cond, delay_us, timeout_us) \
130 readx_poll_timeout_atomic(readw_relaxed, addr, val, cond, delay_us, timeout_us)
132 #define readl_relaxed_poll_timeout(addr, val, cond, delay_us, timeout_us) \
133 readx_poll_timeout(readl_relaxed, addr, val, cond, delay_us, timeout_us)
135 #define readl_relaxed_poll_timeout_atomic(addr, val, cond, delay_us, timeout_us) \
136 readx_poll_timeout_atomic(readl_relaxed, addr, val, cond, delay_us, timeout_us)
138 #define readq_relaxed_poll_timeout(addr, val, cond, delay_us, timeout_us) \
139 readx_poll_timeout(readq_relaxed, addr, val, cond, delay_us, timeout_us)
141 #define readq_relaxed_poll_timeout_atomic(addr, val, cond, delay_us, timeout_us) \
142 readx_poll_timeout_atomic(readq_relaxed, addr, val, cond, delay_us, timeout_us)
H A Dbcd.h19 unsigned _bcd2bin(unsigned char val) __attribute_const__;
20 unsigned char _bin2bcd(unsigned val) __attribute_const__;
H A Dbtree-128.h31 void *val; btree_get_prev128() local
33 val = btree_get_prev(&head->h, &btree_geo128, btree_get_prev128()
37 return val; btree_get_prev128()
41 void *val, gfp_t gfp) btree_insert128()
45 (unsigned long *)&key, val, gfp); btree_insert128()
49 void *val) btree_update128()
53 (unsigned long *)&key, val); btree_update128()
65 void *val; btree_last128() local
67 val = btree_last(&head->h, &btree_geo128, (unsigned long *)&key[0]); btree_last128()
68 if (val) { btree_last128()
73 return val; btree_last128()
105 #define btree_for_each_safe128(head, k1, k2, val) \
106 for (val = btree_last128(head, &k1, &k2); \
107 val; \
108 val = btree_get_prev128(head, &k1, &k2))
40 btree_insert128(struct btree_head128 *head, u64 k1, u64 k2, void *val, gfp_t gfp) btree_insert128() argument
48 btree_update128(struct btree_head128 *head, u64 k1, u64 k2, void *val) btree_update128() argument
H A Dproperty.h32 u8 *val, size_t nval);
34 u16 *val, size_t nval);
36 u32 *val, size_t nval);
38 u64 *val, size_t nval);
40 const char **val, size_t nval);
42 const char **val);
46 const char *propname, u8 *val,
49 const char *propname, u16 *val,
52 const char *propname, u32 *val,
55 const char *propname, u64 *val,
58 const char *propname, const char **val,
61 const char *propname, const char **val);
81 const char *propname, u8 *val) device_property_read_u8()
83 return device_property_read_u8_array(dev, propname, val, 1); device_property_read_u8()
87 const char *propname, u16 *val) device_property_read_u16()
89 return device_property_read_u16_array(dev, propname, val, 1); device_property_read_u16()
93 const char *propname, u32 *val) device_property_read_u32()
95 return device_property_read_u32_array(dev, propname, val, 1); device_property_read_u32()
99 const char *propname, u64 *val) device_property_read_u64()
101 return device_property_read_u64_array(dev, propname, val, 1); device_property_read_u64()
111 const char *propname, u8 *val) fwnode_property_read_u8()
113 return fwnode_property_read_u8_array(fwnode, propname, val, 1); fwnode_property_read_u8()
117 const char *propname, u16 *val) fwnode_property_read_u16()
119 return fwnode_property_read_u16_array(fwnode, propname, val, 1); fwnode_property_read_u16()
123 const char *propname, u32 *val) fwnode_property_read_u32()
125 return fwnode_property_read_u32_array(fwnode, propname, val, 1); fwnode_property_read_u32()
129 const char *propname, u64 *val) fwnode_property_read_u64()
131 return fwnode_property_read_u64_array(fwnode, propname, val, 1); fwnode_property_read_u64()
80 device_property_read_u8(struct device *dev, const char *propname, u8 *val) device_property_read_u8() argument
86 device_property_read_u16(struct device *dev, const char *propname, u16 *val) device_property_read_u16() argument
92 device_property_read_u32(struct device *dev, const char *propname, u32 *val) device_property_read_u32() argument
98 device_property_read_u64(struct device *dev, const char *propname, u64 *val) device_property_read_u64() argument
110 fwnode_property_read_u8(struct fwnode_handle *fwnode, const char *propname, u8 *val) fwnode_property_read_u8() argument
116 fwnode_property_read_u16(struct fwnode_handle *fwnode, const char *propname, u16 *val) fwnode_property_read_u16() argument
122 fwnode_property_read_u32(struct fwnode_handle *fwnode, const char *propname, u32 *val) fwnode_property_read_u32() argument
128 fwnode_property_read_u64(struct fwnode_handle *fwnode, const char *propname, u64 *val) fwnode_property_read_u64() argument
H A Drange.h23 static inline resource_size_t cap_resource(u64 val) cap_resource() argument
25 if (val > MAX_RESOURCE) cap_resource()
28 return val; cap_resource()
/linux-4.1.27/arch/arm/include/asm/hardware/
H A Dcp14.h20 #define dbg_write(val, reg) WCP14_##reg(val)
22 #define etm_write(val, reg) WCP14_##reg(val)
27 u32 val; \
28 asm volatile("mrc p14, "#op1", %0, "#crn", "#crm", "#op2 : "=r" (val)); \
29 val; \
32 #define MCR14(val, op1, crn, crm, op2) \
34 asm volatile("mcr p14, "#op1", %0, "#crn", "#crm", "#op2 : : "r" (val));\
160 #define WCP14_DBGDTRTXint(val) MCR14(val, 0, c0, c5, 0)
161 #define WCP14_DBGWFAR(val) MCR14(val, 0, c0, c6, 0)
162 #define WCP14_DBGVCR(val) MCR14(val, 0, c0, c7, 0)
163 #define WCP14_DBGECR(val) MCR14(val, 0, c0, c9, 0)
164 #define WCP14_DBGDSCCR(val) MCR14(val, 0, c0, c10, 0)
165 #define WCP14_DBGDSMCR(val) MCR14(val, 0, c0, c11, 0)
166 #define WCP14_DBGDTRRXext(val) MCR14(val, 0, c0, c0, 2)
167 #define WCP14_DBGDSCRext(val) MCR14(val, 0, c0, c2, 2)
168 #define WCP14_DBGDTRTXext(val) MCR14(val, 0, c0, c3, 2)
169 #define WCP14_DBGDRCR(val) MCR14(val, 0, c0, c4, 2)
170 #define WCP14_DBGBVR0(val) MCR14(val, 0, c0, c0, 4)
171 #define WCP14_DBGBVR1(val) MCR14(val, 0, c0, c1, 4)
172 #define WCP14_DBGBVR2(val) MCR14(val, 0, c0, c2, 4)
173 #define WCP14_DBGBVR3(val) MCR14(val, 0, c0, c3, 4)
174 #define WCP14_DBGBVR4(val) MCR14(val, 0, c0, c4, 4)
175 #define WCP14_DBGBVR5(val) MCR14(val, 0, c0, c5, 4)
176 #define WCP14_DBGBVR6(val) MCR14(val, 0, c0, c6, 4)
177 #define WCP14_DBGBVR7(val) MCR14(val, 0, c0, c7, 4)
178 #define WCP14_DBGBVR8(val) MCR14(val, 0, c0, c8, 4)
179 #define WCP14_DBGBVR9(val) MCR14(val, 0, c0, c9, 4)
180 #define WCP14_DBGBVR10(val) MCR14(val, 0, c0, c10, 4)
181 #define WCP14_DBGBVR11(val) MCR14(val, 0, c0, c11, 4)
182 #define WCP14_DBGBVR12(val) MCR14(val, 0, c0, c12, 4)
183 #define WCP14_DBGBVR13(val) MCR14(val, 0, c0, c13, 4)
184 #define WCP14_DBGBVR14(val) MCR14(val, 0, c0, c14, 4)
185 #define WCP14_DBGBVR15(val) MCR14(val, 0, c0, c15, 4)
186 #define WCP14_DBGBCR0(val) MCR14(val, 0, c0, c0, 5)
187 #define WCP14_DBGBCR1(val) MCR14(val, 0, c0, c1, 5)
188 #define WCP14_DBGBCR2(val) MCR14(val, 0, c0, c2, 5)
189 #define WCP14_DBGBCR3(val) MCR14(val, 0, c0, c3, 5)
190 #define WCP14_DBGBCR4(val) MCR14(val, 0, c0, c4, 5)
191 #define WCP14_DBGBCR5(val) MCR14(val, 0, c0, c5, 5)
192 #define WCP14_DBGBCR6(val) MCR14(val, 0, c0, c6, 5)
193 #define WCP14_DBGBCR7(val) MCR14(val, 0, c0, c7, 5)
194 #define WCP14_DBGBCR8(val) MCR14(val, 0, c0, c8, 5)
195 #define WCP14_DBGBCR9(val) MCR14(val, 0, c0, c9, 5)
196 #define WCP14_DBGBCR10(val) MCR14(val, 0, c0, c10, 5)
197 #define WCP14_DBGBCR11(val) MCR14(val, 0, c0, c11, 5)
198 #define WCP14_DBGBCR12(val) MCR14(val, 0, c0, c12, 5)
199 #define WCP14_DBGBCR13(val) MCR14(val, 0, c0, c13, 5)
200 #define WCP14_DBGBCR14(val) MCR14(val, 0, c0, c14, 5)
201 #define WCP14_DBGBCR15(val) MCR14(val, 0, c0, c15, 5)
202 #define WCP14_DBGWVR0(val) MCR14(val, 0, c0, c0, 6)
203 #define WCP14_DBGWVR1(val) MCR14(val, 0, c0, c1, 6)
204 #define WCP14_DBGWVR2(val) MCR14(val, 0, c0, c2, 6)
205 #define WCP14_DBGWVR3(val) MCR14(val, 0, c0, c3, 6)
206 #define WCP14_DBGWVR4(val) MCR14(val, 0, c0, c4, 6)
207 #define WCP14_DBGWVR5(val) MCR14(val, 0, c0, c5, 6)
208 #define WCP14_DBGWVR6(val) MCR14(val, 0, c0, c6, 6)
209 #define WCP14_DBGWVR7(val) MCR14(val, 0, c0, c7, 6)
210 #define WCP14_DBGWVR8(val) MCR14(val, 0, c0, c8, 6)
211 #define WCP14_DBGWVR9(val) MCR14(val, 0, c0, c9, 6)
212 #define WCP14_DBGWVR10(val) MCR14(val, 0, c0, c10, 6)
213 #define WCP14_DBGWVR11(val) MCR14(val, 0, c0, c11, 6)
214 #define WCP14_DBGWVR12(val) MCR14(val, 0, c0, c12, 6)
215 #define WCP14_DBGWVR13(val) MCR14(val, 0, c0, c13, 6)
216 #define WCP14_DBGWVR14(val) MCR14(val, 0, c0, c14, 6)
217 #define WCP14_DBGWVR15(val) MCR14(val, 0, c0, c15, 6)
218 #define WCP14_DBGWCR0(val) MCR14(val, 0, c0, c0, 7)
219 #define WCP14_DBGWCR1(val) MCR14(val, 0, c0, c1, 7)
220 #define WCP14_DBGWCR2(val) MCR14(val, 0, c0, c2, 7)
221 #define WCP14_DBGWCR3(val) MCR14(val, 0, c0, c3, 7)
222 #define WCP14_DBGWCR4(val) MCR14(val, 0, c0, c4, 7)
223 #define WCP14_DBGWCR5(val) MCR14(val, 0, c0, c5, 7)
224 #define WCP14_DBGWCR6(val) MCR14(val, 0, c0, c6, 7)
225 #define WCP14_DBGWCR7(val) MCR14(val, 0, c0, c7, 7)
226 #define WCP14_DBGWCR8(val) MCR14(val, 0, c0, c8, 7)
227 #define WCP14_DBGWCR9(val) MCR14(val, 0, c0, c9, 7)
228 #define WCP14_DBGWCR10(val) MCR14(val, 0, c0, c10, 7)
229 #define WCP14_DBGWCR11(val) MCR14(val, 0, c0, c11, 7)
230 #define WCP14_DBGWCR12(val) MCR14(val, 0, c0, c12, 7)
231 #define WCP14_DBGWCR13(val) MCR14(val, 0, c0, c13, 7)
232 #define WCP14_DBGWCR14(val) MCR14(val, 0, c0, c14, 7)
233 #define WCP14_DBGWCR15(val) MCR14(val, 0, c0, c15, 7)
234 #define WCP14_DBGBXVR0(val) MCR14(val, 0, c1, c0, 1)
235 #define WCP14_DBGBXVR1(val) MCR14(val, 0, c1, c1, 1)
236 #define WCP14_DBGBXVR2(val) MCR14(val, 0, c1, c2, 1)
237 #define WCP14_DBGBXVR3(val) MCR14(val, 0, c1, c3, 1)
238 #define WCP14_DBGBXVR4(val) MCR14(val, 0, c1, c4, 1)
239 #define WCP14_DBGBXVR5(val) MCR14(val, 0, c1, c5, 1)
240 #define WCP14_DBGBXVR6(val) MCR14(val, 0, c1, c6, 1)
241 #define WCP14_DBGBXVR7(val) MCR14(val, 0, c1, c7, 1)
242 #define WCP14_DBGBXVR8(val) MCR14(val, 0, c1, c8, 1)
243 #define WCP14_DBGBXVR9(val) MCR14(val, 0, c1, c9, 1)
244 #define WCP14_DBGBXVR10(val) MCR14(val, 0, c1, c10, 1)
245 #define WCP14_DBGBXVR11(val) MCR14(val, 0, c1, c11, 1)
246 #define WCP14_DBGBXVR12(val) MCR14(val, 0, c1, c12, 1)
247 #define WCP14_DBGBXVR13(val) MCR14(val, 0, c1, c13, 1)
248 #define WCP14_DBGBXVR14(val) MCR14(val, 0, c1, c14, 1)
249 #define WCP14_DBGBXVR15(val) MCR14(val, 0, c1, c15, 1)
250 #define WCP14_DBGOSLAR(val) MCR14(val, 0, c1, c0, 4)
251 #define WCP14_DBGOSSRR(val) MCR14(val, 0, c1, c2, 4)
252 #define WCP14_DBGOSDLR(val) MCR14(val, 0, c1, c3, 4)
253 #define WCP14_DBGPRCR(val) MCR14(val, 0, c1, c4, 4)
254 #define WCP14_DBGITCTRL(val) MCR14(val, 0, c7, c0, 4)
255 #define WCP14_DBGCLAIMSET(val) MCR14(val, 0, c7, c8, 6)
256 #define WCP14_DBGCLAIMCLR(val) MCR14(val, 0, c7, c9, 6)
420 #define WCP14_ETMCR(val) MCR14(val, 1, c0, c0, 0)
421 #define WCP14_ETMTRIGGER(val) MCR14(val, 1, c0, c2, 0)
422 #define WCP14_ETMASICCR(val) MCR14(val, 1, c0, c3, 0)
423 #define WCP14_ETMSR(val) MCR14(val, 1, c0, c4, 0)
424 #define WCP14_ETMTSSCR(val) MCR14(val, 1, c0, c6, 0)
425 #define WCP14_ETMTECR2(val) MCR14(val, 1, c0, c7, 0)
426 #define WCP14_ETMTEEVR(val) MCR14(val, 1, c0, c8, 0)
427 #define WCP14_ETMTECR1(val) MCR14(val, 1, c0, c9, 0)
428 #define WCP14_ETMFFRR(val) MCR14(val, 1, c0, c10, 0)
429 #define WCP14_ETMFFLR(val) MCR14(val, 1, c0, c11, 0)
430 #define WCP14_ETMVDEVR(val) MCR14(val, 1, c0, c12, 0)
431 #define WCP14_ETMVDCR1(val) MCR14(val, 1, c0, c13, 0)
432 #define WCP14_ETMVDCR2(val) MCR14(val, 1, c0, c14, 0)
433 #define WCP14_ETMVDCR3(val) MCR14(val, 1, c0, c15, 0)
434 #define WCP14_ETMACVR0(val) MCR14(val, 1, c0, c0, 1)
435 #define WCP14_ETMACVR1(val) MCR14(val, 1, c0, c1, 1)
436 #define WCP14_ETMACVR2(val) MCR14(val, 1, c0, c2, 1)
437 #define WCP14_ETMACVR3(val) MCR14(val, 1, c0, c3, 1)
438 #define WCP14_ETMACVR4(val) MCR14(val, 1, c0, c4, 1)
439 #define WCP14_ETMACVR5(val) MCR14(val, 1, c0, c5, 1)
440 #define WCP14_ETMACVR6(val) MCR14(val, 1, c0, c6, 1)
441 #define WCP14_ETMACVR7(val) MCR14(val, 1, c0, c7, 1)
442 #define WCP14_ETMACVR8(val) MCR14(val, 1, c0, c8, 1)
443 #define WCP14_ETMACVR9(val) MCR14(val, 1, c0, c9, 1)
444 #define WCP14_ETMACVR10(val) MCR14(val, 1, c0, c10, 1)
445 #define WCP14_ETMACVR11(val) MCR14(val, 1, c0, c11, 1)
446 #define WCP14_ETMACVR12(val) MCR14(val, 1, c0, c12, 1)
447 #define WCP14_ETMACVR13(val) MCR14(val, 1, c0, c13, 1)
448 #define WCP14_ETMACVR14(val) MCR14(val, 1, c0, c14, 1)
449 #define WCP14_ETMACVR15(val) MCR14(val, 1, c0, c15, 1)
450 #define WCP14_ETMACTR0(val) MCR14(val, 1, c0, c0, 2)
451 #define WCP14_ETMACTR1(val) MCR14(val, 1, c0, c1, 2)
452 #define WCP14_ETMACTR2(val) MCR14(val, 1, c0, c2, 2)
453 #define WCP14_ETMACTR3(val) MCR14(val, 1, c0, c3, 2)
454 #define WCP14_ETMACTR4(val) MCR14(val, 1, c0, c4, 2)
455 #define WCP14_ETMACTR5(val) MCR14(val, 1, c0, c5, 2)
456 #define WCP14_ETMACTR6(val) MCR14(val, 1, c0, c6, 2)
457 #define WCP14_ETMACTR7(val) MCR14(val, 1, c0, c7, 2)
458 #define WCP14_ETMACTR8(val) MCR14(val, 1, c0, c8, 2)
459 #define WCP14_ETMACTR9(val) MCR14(val, 1, c0, c9, 2)
460 #define WCP14_ETMACTR10(val) MCR14(val, 1, c0, c10, 2)
461 #define WCP14_ETMACTR11(val) MCR14(val, 1, c0, c11, 2)
462 #define WCP14_ETMACTR12(val) MCR14(val, 1, c0, c12, 2)
463 #define WCP14_ETMACTR13(val) MCR14(val, 1, c0, c13, 2)
464 #define WCP14_ETMACTR14(val) MCR14(val, 1, c0, c14, 2)
465 #define WCP14_ETMACTR15(val) MCR14(val, 1, c0, c15, 2)
466 #define WCP14_ETMDCVR0(val) MCR14(val, 1, c0, c0, 3)
467 #define WCP14_ETMDCVR2(val) MCR14(val, 1, c0, c2, 3)
468 #define WCP14_ETMDCVR4(val) MCR14(val, 1, c0, c4, 3)
469 #define WCP14_ETMDCVR6(val) MCR14(val, 1, c0, c6, 3)
470 #define WCP14_ETMDCVR8(val) MCR14(val, 1, c0, c8, 3)
471 #define WCP14_ETMDCVR10(val) MCR14(val, 1, c0, c10, 3)
472 #define WCP14_ETMDCVR12(val) MCR14(val, 1, c0, c12, 3)
473 #define WCP14_ETMDCVR14(val) MCR14(val, 1, c0, c14, 3)
474 #define WCP14_ETMDCMR0(val) MCR14(val, 1, c0, c0, 4)
475 #define WCP14_ETMDCMR2(val) MCR14(val, 1, c0, c2, 4)
476 #define WCP14_ETMDCMR4(val) MCR14(val, 1, c0, c4, 4)
477 #define WCP14_ETMDCMR6(val) MCR14(val, 1, c0, c6, 4)
478 #define WCP14_ETMDCMR8(val) MCR14(val, 1, c0, c8, 4)
479 #define WCP14_ETMDCMR10(val) MCR14(val, 1, c0, c10, 4)
480 #define WCP14_ETMDCMR12(val) MCR14(val, 1, c0, c12, 4)
481 #define WCP14_ETMDCMR14(val) MCR14(val, 1, c0, c14, 4)
482 #define WCP14_ETMCNTRLDVR0(val) MCR14(val, 1, c0, c0, 5)
483 #define WCP14_ETMCNTRLDVR1(val) MCR14(val, 1, c0, c1, 5)
484 #define WCP14_ETMCNTRLDVR2(val) MCR14(val, 1, c0, c2, 5)
485 #define WCP14_ETMCNTRLDVR3(val) MCR14(val, 1, c0, c3, 5)
486 #define WCP14_ETMCNTENR0(val) MCR14(val, 1, c0, c4, 5)
487 #define WCP14_ETMCNTENR1(val) MCR14(val, 1, c0, c5, 5)
488 #define WCP14_ETMCNTENR2(val) MCR14(val, 1, c0, c6, 5)
489 #define WCP14_ETMCNTENR3(val) MCR14(val, 1, c0, c7, 5)
490 #define WCP14_ETMCNTRLDEVR0(val) MCR14(val, 1, c0, c8, 5)
491 #define WCP14_ETMCNTRLDEVR1(val) MCR14(val, 1, c0, c9, 5)
492 #define WCP14_ETMCNTRLDEVR2(val) MCR14(val, 1, c0, c10, 5)
493 #define WCP14_ETMCNTRLDEVR3(val) MCR14(val, 1, c0, c11, 5)
494 #define WCP14_ETMCNTVR0(val) MCR14(val, 1, c0, c12, 5)
495 #define WCP14_ETMCNTVR1(val) MCR14(val, 1, c0, c13, 5)
496 #define WCP14_ETMCNTVR2(val) MCR14(val, 1, c0, c14, 5)
497 #define WCP14_ETMCNTVR3(val) MCR14(val, 1, c0, c15, 5)
498 #define WCP14_ETMSQ12EVR(val) MCR14(val, 1, c0, c0, 6)
499 #define WCP14_ETMSQ21EVR(val) MCR14(val, 1, c0, c1, 6)
500 #define WCP14_ETMSQ23EVR(val) MCR14(val, 1, c0, c2, 6)
501 #define WCP14_ETMSQ31EVR(val) MCR14(val, 1, c0, c3, 6)
502 #define WCP14_ETMSQ32EVR(val) MCR14(val, 1, c0, c4, 6)
503 #define WCP14_ETMSQ13EVR(val) MCR14(val, 1, c0, c5, 6)
504 #define WCP14_ETMSQR(val) MCR14(val, 1, c0, c7, 6)
505 #define WCP14_ETMEXTOUTEVR0(val) MCR14(val, 1, c0, c8, 6)
506 #define WCP14_ETMEXTOUTEVR1(val) MCR14(val, 1, c0, c9, 6)
507 #define WCP14_ETMEXTOUTEVR2(val) MCR14(val, 1, c0, c10, 6)
508 #define WCP14_ETMEXTOUTEVR3(val) MCR14(val, 1, c0, c11, 6)
509 #define WCP14_ETMCIDCVR0(val) MCR14(val, 1, c0, c12, 6)
510 #define WCP14_ETMCIDCVR1(val) MCR14(val, 1, c0, c13, 6)
511 #define WCP14_ETMCIDCVR2(val) MCR14(val, 1, c0, c14, 6)
512 #define WCP14_ETMCIDCMR(val) MCR14(val, 1, c0, c15, 6)
513 #define WCP14_ETMIMPSPEC0(val) MCR14(val, 1, c0, c0, 7)
514 #define WCP14_ETMIMPSPEC1(val) MCR14(val, 1, c0, c1, 7)
515 #define WCP14_ETMIMPSPEC2(val) MCR14(val, 1, c0, c2, 7)
516 #define WCP14_ETMIMPSPEC3(val) MCR14(val, 1, c0, c3, 7)
517 #define WCP14_ETMIMPSPEC4(val) MCR14(val, 1, c0, c4, 7)
518 #define WCP14_ETMIMPSPEC5(val) MCR14(val, 1, c0, c5, 7)
519 #define WCP14_ETMIMPSPEC6(val) MCR14(val, 1, c0, c6, 7)
520 #define WCP14_ETMIMPSPEC7(val) MCR14(val, 1, c0, c7, 7)
522 #define WCP14_ETMSYNCFR(val) MCR14(val, 1, c0, c8, 7)
523 #define WCP14_ETMEXTINSELR(val) MCR14(val, 1, c0, c11, 7)
524 #define WCP14_ETMTESSEICR(val) MCR14(val, 1, c0, c12, 7)
525 #define WCP14_ETMEIBCR(val) MCR14(val, 1, c0, c13, 7)
526 #define WCP14_ETMTSEVR(val) MCR14(val, 1, c0, c14, 7)
527 #define WCP14_ETMAUXCR(val) MCR14(val, 1, c0, c15, 7)
528 #define WCP14_ETMTRACEIDR(val) MCR14(val, 1, c1, c0, 0)
529 #define WCP14_ETMIDR2(val) MCR14(val, 1, c1, c2, 0)
530 #define WCP14_ETMVMIDCVR(val) MCR14(val, 1, c1, c0, 1)
531 #define WCP14_ETMOSLAR(val) MCR14(val, 1, c1, c0, 4)
533 #define WCP14_ETMOSSRR(val) MCR14(val, 1, c1, c2, 4)
534 #define WCP14_ETMPDCR(val) MCR14(val, 1, c1, c4, 4)
535 #define WCP14_ETMPDSR(val) MCR14(val, 1, c1, c5, 4)
536 #define WCP14_ETMITCTRL(val) MCR14(val, 1, c7, c0, 4)
537 #define WCP14_ETMCLAIMSET(val) MCR14(val, 1, c7, c8, 6)
538 #define WCP14_ETMCLAIMCLR(val) MCR14(val, 1, c7, c9, 6)
540 #define WCP14_ETMLAR(val) MCR14(val, 1, c7, c12, 6)
/linux-4.1.27/arch/arm/mach-omap2/
H A Dclock_common_data.c23 { .div = 1, .val = 0, .flags = RATE_IN_24XX | RATE_IN_3XXX },
28 { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_3XXX },
33 { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_3XXX },
34 { .div = 2, .val = 2, .flags = RATE_IN_24XX | RATE_IN_3XXX },
35 { .div = 3, .val = 3, .flags = RATE_IN_243X | RATE_IN_3XXX },
36 { .div = 4, .val = 4, .flags = RATE_IN_243X | RATE_IN_3XXX },
41 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
42 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
43 { .div = 3, .val = 3, .flags = RATE_IN_243X },
51 { .div = 1, .val = 0, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
56 { .div = 1, .val = 0, .flags = RATE_IN_4430 },
57 { .div = 2, .val = 1, .flags = RATE_IN_4430 },
58 { .div = 4, .val = 2, .flags = RATE_IN_4430 },
63 { .div = 1, .val = 1, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
68 { .div = 1, .val = 2, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
73 { .div = 1, .val = 3, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
78 { .div = 1, .val = 4, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
83 { .div = 1, .val = 1, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
84 { .div = 2, .val = 2, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
85 { .div = 3, .val = 3, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
86 { .div = 4, .val = 4, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
87 { .div = 5, .val = 5, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
88 { .div = 6, .val = 6, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
89 { .div = 7, .val = 7, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
90 { .div = 8, .val = 8, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
91 { .div = 9, .val = 9, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
92 { .div = 10, .val = 10, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
93 { .div = 11, .val = 11, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
94 { .div = 12, .val = 12, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
95 { .div = 13, .val = 13, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
96 { .div = 14, .val = 14, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
97 { .div = 15, .val = 15, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
98 { .div = 16, .val = 16, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
99 { .div = 17, .val = 17, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
100 { .div = 18, .val = 18, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
101 { .div = 19, .val = 19, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
102 { .div = 20, .val = 20, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
103 { .div = 21, .val = 21, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
104 { .div = 22, .val = 22, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
105 { .div = 23, .val = 23, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
106 { .div = 24, .val = 24, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
107 { .div = 25, .val = 25, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
108 { .div = 26, .val = 26, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
109 { .div = 27, .val = 27, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
110 { .div = 28, .val = 28, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
111 { .div = 29, .val = 29, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
112 { .div = 30, .val = 30, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
113 { .div = 31, .val = 31, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
/linux-4.1.27/arch/x86/include/asm/
H A Dmisc.h4 int num_digits(int val);
H A Dpercpu.h89 #define percpu_to_op(op, var, val) \
94 pto_tmp__ = (val); \
101 : "qi" ((pto_T__)(val))); \
106 : "ri" ((pto_T__)(val))); \
111 : "ri" ((pto_T__)(val))); \
116 : "re" ((pto_T__)(val))); \
126 #define percpu_add_op(var, val) \
129 const int pao_ID__ = (__builtin_constant_p(val) && \
130 ((val) == 1 || (val) == -1)) ? \
131 (int)(val) : 0; \
134 pao_tmp__ = (val); \
146 : "qi" ((pao_T__)(val))); \
156 : "ri" ((pao_T__)(val))); \
166 : "ri" ((pao_T__)(val))); \
176 : "re" ((pao_T__)(val))); \
266 #define percpu_add_return_op(var, val) \
268 typeof(var) paro_ret__ = val; \
292 paro_ret__ += val; \
397 #define raw_cpu_write_1(pcp, val) percpu_to_op("mov", (pcp), val)
398 #define raw_cpu_write_2(pcp, val) percpu_to_op("mov", (pcp), val)
399 #define raw_cpu_write_4(pcp, val) percpu_to_op("mov", (pcp), val)
400 #define raw_cpu_add_1(pcp, val) percpu_add_op((pcp), val)
401 #define raw_cpu_add_2(pcp, val) percpu_add_op((pcp), val)
402 #define raw_cpu_add_4(pcp, val) percpu_add_op((pcp), val)
403 #define raw_cpu_and_1(pcp, val) percpu_to_op("and", (pcp), val)
404 #define raw_cpu_and_2(pcp, val) percpu_to_op("and", (pcp), val)
405 #define raw_cpu_and_4(pcp, val) percpu_to_op("and", (pcp), val)
406 #define raw_cpu_or_1(pcp, val) percpu_to_op("or", (pcp), val)
407 #define raw_cpu_or_2(pcp, val) percpu_to_op("or", (pcp), val)
408 #define raw_cpu_or_4(pcp, val) percpu_to_op("or", (pcp), val)
409 #define raw_cpu_xchg_1(pcp, val) percpu_xchg_op(pcp, val)
410 #define raw_cpu_xchg_2(pcp, val) percpu_xchg_op(pcp, val)
411 #define raw_cpu_xchg_4(pcp, val) percpu_xchg_op(pcp, val)
416 #define this_cpu_write_1(pcp, val) percpu_to_op("mov", (pcp), val)
417 #define this_cpu_write_2(pcp, val) percpu_to_op("mov", (pcp), val)
418 #define this_cpu_write_4(pcp, val) percpu_to_op("mov", (pcp), val)
419 #define this_cpu_add_1(pcp, val) percpu_add_op((pcp), val)
420 #define this_cpu_add_2(pcp, val) percpu_add_op((pcp), val)
421 #define this_cpu_add_4(pcp, val) percpu_add_op((pcp), val)
422 #define this_cpu_and_1(pcp, val) percpu_to_op("and", (pcp), val)
423 #define this_cpu_and_2(pcp, val) percpu_to_op("and", (pcp), val)
424 #define this_cpu_and_4(pcp, val) percpu_to_op("and", (pcp), val)
425 #define this_cpu_or_1(pcp, val) percpu_to_op("or", (pcp), val)
426 #define this_cpu_or_2(pcp, val) percpu_to_op("or", (pcp), val)
427 #define this_cpu_or_4(pcp, val) percpu_to_op("or", (pcp), val)
432 #define raw_cpu_add_return_1(pcp, val) percpu_add_return_op(pcp, val)
433 #define raw_cpu_add_return_2(pcp, val) percpu_add_return_op(pcp, val)
434 #define raw_cpu_add_return_4(pcp, val) percpu_add_return_op(pcp, val)
439 #define this_cpu_add_return_1(pcp, val) percpu_add_return_op(pcp, val)
440 #define this_cpu_add_return_2(pcp, val) percpu_add_return_op(pcp, val)
441 #define this_cpu_add_return_4(pcp, val) percpu_add_return_op(pcp, val)
468 #define raw_cpu_write_8(pcp, val) percpu_to_op("mov", (pcp), val)
469 #define raw_cpu_add_8(pcp, val) percpu_add_op((pcp), val)
470 #define raw_cpu_and_8(pcp, val) percpu_to_op("and", (pcp), val)
471 #define raw_cpu_or_8(pcp, val) percpu_to_op("or", (pcp), val)
472 #define raw_cpu_add_return_8(pcp, val) percpu_add_return_op(pcp, val)
477 #define this_cpu_write_8(pcp, val) percpu_to_op("mov", (pcp), val)
478 #define this_cpu_add_8(pcp, val) percpu_add_op((pcp), val)
479 #define this_cpu_and_8(pcp, val) percpu_to_op("and", (pcp), val)
480 #define this_cpu_or_8(pcp, val) percpu_to_op("or", (pcp), val)
481 #define this_cpu_add_return_8(pcp, val) percpu_add_return_op(pcp, val)
H A Dcmpxchg_64.h4 static inline void set_64bit(volatile u64 *ptr, u64 val) set_64bit() argument
6 *ptr = val; set_64bit()
H A Dspecial_insns.h25 unsigned long val; native_read_cr0() local
26 asm volatile("mov %%cr0,%0\n\t" : "=r" (val), "=m" (__force_order)); native_read_cr0()
27 return val; native_read_cr0()
30 static inline void native_write_cr0(unsigned long val) native_write_cr0() argument
32 asm volatile("mov %0,%%cr0": : "r" (val), "m" (__force_order)); native_write_cr0()
37 unsigned long val; native_read_cr2() local
38 asm volatile("mov %%cr2,%0\n\t" : "=r" (val), "=m" (__force_order)); native_read_cr2()
39 return val; native_read_cr2()
42 static inline void native_write_cr2(unsigned long val) native_write_cr2() argument
44 asm volatile("mov %0,%%cr2": : "r" (val), "m" (__force_order)); native_write_cr2()
49 unsigned long val; native_read_cr3() local
50 asm volatile("mov %%cr3,%0\n\t" : "=r" (val), "=m" (__force_order)); native_read_cr3()
51 return val; native_read_cr3()
54 static inline void native_write_cr3(unsigned long val) native_write_cr3() argument
56 asm volatile("mov %0,%%cr3": : "r" (val), "m" (__force_order)); native_write_cr3()
61 unsigned long val; native_read_cr4() local
62 asm volatile("mov %%cr4,%0\n\t" : "=r" (val), "=m" (__force_order)); native_read_cr4()
63 return val; native_read_cr4()
68 unsigned long val; native_read_cr4_safe() local
75 : "=r" (val), "=m" (__force_order) : "0" (0)); native_read_cr4_safe()
77 val = native_read_cr4(); native_read_cr4_safe()
79 return val; native_read_cr4_safe()
82 static inline void native_write_cr4(unsigned long val) native_write_cr4() argument
84 asm volatile("mov %0,%%cr4": : "r" (val), "m" (__force_order)); native_write_cr4()
95 static inline void native_write_cr8(unsigned long val) native_write_cr8() argument
97 asm volatile("movq %0,%%cr8" :: "r" (val) : "memory"); native_write_cr8()
H A Dmsr.h49 #define DECLARE_ARGS(val, low, high) unsigned low, high
50 #define EAX_EDX_VAL(val, low, high) ((low) | ((u64)(high) << 32))
51 #define EAX_EDX_ARGS(val, low, high) "a" (low), "d" (high)
52 #define EAX_EDX_RET(val, low, high) "=a" (low), "=d" (high)
54 #define DECLARE_ARGS(val, low, high) unsigned long long val
55 #define EAX_EDX_VAL(val, low, high) (val)
56 #define EAX_EDX_ARGS(val, low, high) "A" (val)
57 #define EAX_EDX_RET(val, low, high) "=A" (val)
62 DECLARE_ARGS(val, low, high); native_read_msr()
64 asm volatile("rdmsr" : EAX_EDX_RET(val, low, high) : "c" (msr)); native_read_msr()
65 return EAX_EDX_VAL(val, low, high); native_read_msr()
71 DECLARE_ARGS(val, low, high); native_read_msr_safe()
79 : [err] "=r" (*err), EAX_EDX_RET(val, low, high) native_read_msr_safe()
81 return EAX_EDX_VAL(val, low, high); native_read_msr_safe()
115 DECLARE_ARGS(val, low, high); __native_read_tsc()
117 asm volatile("rdtsc" : EAX_EDX_RET(val, low, high)); __native_read_tsc()
119 return EAX_EDX_VAL(val, low, high); __native_read_tsc()
124 DECLARE_ARGS(val, low, high); native_read_pmc()
126 asm volatile("rdpmc" : EAX_EDX_RET(val, low, high) : "c" (counter)); native_read_pmc()
127 return EAX_EDX_VAL(val, low, high); native_read_pmc()
152 #define rdmsrl(msr, val) \
153 ((val) = native_read_msr((msr)))
155 #define wrmsrl(msr, val) \
156 native_write_msr((msr), (u32)((u64)(val)), (u32)((u64)(val) >> 32))
185 #define rdtscll(val) \
186 ((val) = __native_read_tsc())
195 #define rdpmcl(counter, val) ((val) = native_read_pmc(counter))
204 #define rdtscpll(val, aux) (val) = native_read_tscp(&(aux))
208 #define wrmsrl_safe(msr, val) wrmsr_safe((msr), (u32)(val), \
209 (u32)((val) >> 32))
213 #define write_rdtscp_aux(val) wrmsr(MSR_TSC_AUX, (val), 0)
/linux-4.1.27/arch/x86/tools/
H A Drelocs_64.c11 #define ELF_R_SYM(val) ELF64_R_SYM(val)
12 #define ELF_R_TYPE(val) ELF64_R_TYPE(val)
H A Drelocs_32.c11 #define ELF_R_SYM(val) ELF32_R_SYM(val)
12 #define ELF_R_TYPE(val) ELF32_R_TYPE(val)
/linux-4.1.27/include/trace/events/
H A Dintel-sst.h20 TP_PROTO(unsigned int val),
22 TP_ARGS(val),
25 __field( unsigned int, val )
29 __entry->val = val;
32 TP_printk("0x%8.8x", (unsigned int)__entry->val)
37 TP_PROTO(unsigned int val),
39 TP_ARGS(val)
45 TP_PROTO(unsigned int val),
47 TP_ARGS(val)
53 TP_PROTO(unsigned int offset, unsigned int val),
55 TP_ARGS(offset, val),
59 __field( unsigned int, val )
64 __entry->val = val;
68 (unsigned int)__entry->offset, (unsigned int)__entry->val)
73 TP_PROTO(unsigned int offset, unsigned int val),
75 TP_ARGS(offset, val)
81 TP_PROTO(unsigned int offset, unsigned int val),
83 TP_ARGS(offset, val)
89 TP_PROTO(unsigned int offset, unsigned int val),
91 TP_ARGS(offset, val)
97 TP_PROTO(unsigned int offset, unsigned int val),
99 TP_ARGS(offset, val)
H A Dasoc.h20 TP_PROTO(struct snd_soc_card *card, int val),
22 TP_ARGS(card, val),
26 __field( int, val )
31 __entry->val = val;
34 TP_printk("card=%s val=%d", __get_str(name), (int)__entry->val)
39 TP_PROTO(struct snd_soc_card *card, int val),
41 TP_ARGS(card, val)
47 TP_PROTO(struct snd_soc_card *card, int val),
49 TP_ARGS(card, val)
88 TP_PROTO(struct snd_soc_dapm_widget *w, int val),
90 TP_ARGS(w, val),
94 __field( int, val )
99 __entry->val = val;
102 TP_printk("widget=%s val=%d", __get_str(name),
103 (int)__entry->val)
108 TP_PROTO(struct snd_soc_dapm_widget *w, int val),
110 TP_ARGS(w, val)
116 TP_PROTO(struct snd_soc_dapm_widget *w, int val),
118 TP_ARGS(w, val)
124 TP_PROTO(struct snd_soc_dapm_widget *w, int val),
126 TP_ARGS(w, val)
252 TP_PROTO(struct snd_soc_jack *jack, int mask, int val),
254 TP_ARGS(jack, mask, val),
259 __field( int, val )
265 __entry->val = val;
268 TP_printk("jack=%s %x/%x", __get_str(name), (int)__entry->val,
274 TP_PROTO(struct snd_soc_jack *jack, int val),
276 TP_ARGS(jack, val),
280 __field( int, val )
285 __entry->val = val;
288 TP_printk("jack=%s %x", __get_str(name), (int)__entry->val)
/linux-4.1.27/include/linux/unaligned/
H A Dbe_byteshift.h22 static inline void __put_unaligned_be16(u16 val, u8 *p) __put_unaligned_be16() argument
24 *p++ = val >> 8; __put_unaligned_be16()
25 *p++ = val; __put_unaligned_be16()
28 static inline void __put_unaligned_be32(u32 val, u8 *p) __put_unaligned_be32() argument
30 __put_unaligned_be16(val >> 16, p); __put_unaligned_be32()
31 __put_unaligned_be16(val, p + 2); __put_unaligned_be32()
34 static inline void __put_unaligned_be64(u64 val, u8 *p) __put_unaligned_be64() argument
36 __put_unaligned_be32(val >> 32, p); __put_unaligned_be64()
37 __put_unaligned_be32(val, p + 4); __put_unaligned_be64()
55 static inline void put_unaligned_be16(u16 val, void *p) put_unaligned_be16() argument
57 __put_unaligned_be16(val, p); put_unaligned_be16()
60 static inline void put_unaligned_be32(u32 val, void *p) put_unaligned_be32() argument
62 __put_unaligned_be32(val, p); put_unaligned_be32()
65 static inline void put_unaligned_be64(u64 val, void *p) put_unaligned_be64() argument
67 __put_unaligned_be64(val, p); put_unaligned_be64()
H A Dle_byteshift.h22 static inline void __put_unaligned_le16(u16 val, u8 *p) __put_unaligned_le16() argument
24 *p++ = val; __put_unaligned_le16()
25 *p++ = val >> 8; __put_unaligned_le16()
28 static inline void __put_unaligned_le32(u32 val, u8 *p) __put_unaligned_le32() argument
30 __put_unaligned_le16(val >> 16, p + 2); __put_unaligned_le32()
31 __put_unaligned_le16(val, p); __put_unaligned_le32()
34 static inline void __put_unaligned_le64(u64 val, u8 *p) __put_unaligned_le64() argument
36 __put_unaligned_le32(val >> 32, p + 4); __put_unaligned_le64()
37 __put_unaligned_le32(val, p); __put_unaligned_le64()
55 static inline void put_unaligned_le16(u16 val, void *p) put_unaligned_le16() argument
57 __put_unaligned_le16(val, p); put_unaligned_le16()
60 static inline void put_unaligned_le32(u32 val, void *p) put_unaligned_le32() argument
62 __put_unaligned_le32(val, p); put_unaligned_le32()
65 static inline void put_unaligned_le64(u64 val, void *p) put_unaligned_le64() argument
67 __put_unaligned_le64(val, p); put_unaligned_le64()
H A Daccess_ok.h37 static inline void put_unaligned_le16(u16 val, void *p) put_unaligned_le16() argument
39 *((__le16 *)p) = cpu_to_le16(val); put_unaligned_le16()
42 static inline void put_unaligned_le32(u32 val, void *p) put_unaligned_le32() argument
44 *((__le32 *)p) = cpu_to_le32(val); put_unaligned_le32()
47 static inline void put_unaligned_le64(u64 val, void *p) put_unaligned_le64() argument
49 *((__le64 *)p) = cpu_to_le64(val); put_unaligned_le64()
52 static inline void put_unaligned_be16(u16 val, void *p) put_unaligned_be16() argument
54 *((__be16 *)p) = cpu_to_be16(val); put_unaligned_be16()
57 static inline void put_unaligned_be32(u32 val, void *p) put_unaligned_be32() argument
59 *((__be32 *)p) = cpu_to_be32(val); put_unaligned_be32()
62 static inline void put_unaligned_be64(u64 val, void *p) put_unaligned_be64() argument
64 *((__be64 *)p) = cpu_to_be64(val); put_unaligned_be64()
H A Dbe_memmove.h21 static inline void put_unaligned_be16(u16 val, void *p) put_unaligned_be16() argument
23 __put_unaligned_memmove16(val, p); put_unaligned_be16()
26 static inline void put_unaligned_be32(u32 val, void *p) put_unaligned_be32() argument
28 __put_unaligned_memmove32(val, p); put_unaligned_be32()
31 static inline void put_unaligned_be64(u64 val, void *p) put_unaligned_be64() argument
33 __put_unaligned_memmove64(val, p); put_unaligned_be64()
H A Dbe_struct.h21 static inline void put_unaligned_be16(u16 val, void *p) put_unaligned_be16() argument
23 __put_unaligned_cpu16(val, p); put_unaligned_be16()
26 static inline void put_unaligned_be32(u32 val, void *p) put_unaligned_be32() argument
28 __put_unaligned_cpu32(val, p); put_unaligned_be32()
31 static inline void put_unaligned_be64(u64 val, void *p) put_unaligned_be64() argument
33 __put_unaligned_cpu64(val, p); put_unaligned_be64()
H A Dle_memmove.h21 static inline void put_unaligned_le16(u16 val, void *p) put_unaligned_le16() argument
23 __put_unaligned_memmove16(val, p); put_unaligned_le16()
26 static inline void put_unaligned_le32(u32 val, void *p) put_unaligned_le32() argument
28 __put_unaligned_memmove32(val, p); put_unaligned_le32()
31 static inline void put_unaligned_le64(u64 val, void *p) put_unaligned_le64() argument
33 __put_unaligned_memmove64(val, p); put_unaligned_le64()
H A Dle_struct.h21 static inline void put_unaligned_le16(u16 val, void *p) put_unaligned_le16() argument
23 __put_unaligned_cpu16(val, p); put_unaligned_le16()
26 static inline void put_unaligned_le32(u32 val, void *p) put_unaligned_le32() argument
28 __put_unaligned_cpu32(val, p); put_unaligned_le32()
31 static inline void put_unaligned_le64(u64 val, void *p) put_unaligned_le64() argument
33 __put_unaligned_cpu64(val, p); put_unaligned_le64()
H A Dgeneric.h26 #define __put_unaligned_le(val, ptr) ({ \
30 *(u8 *)__gu_p = (__force u8)(val); \
33 put_unaligned_le16((__force u16)(val), __gu_p); \
36 put_unaligned_le32((__force u32)(val), __gu_p); \
39 put_unaligned_le64((__force u64)(val), __gu_p); \
47 #define __put_unaligned_be(val, ptr) ({ \
51 *(u8 *)__gu_p = (__force u8)(val); \
54 put_unaligned_be16((__force u16)(val), __gu_p); \
57 put_unaligned_be32((__force u32)(val), __gu_p); \
60 put_unaligned_be64((__force u64)(val), __gu_p); \
H A Dmemmove.h30 static inline void __put_unaligned_memmove16(u16 val, void *p) __put_unaligned_memmove16() argument
32 memmove(p, &val, 2); __put_unaligned_memmove16()
35 static inline void __put_unaligned_memmove32(u32 val, void *p) __put_unaligned_memmove32() argument
37 memmove(p, &val, 4); __put_unaligned_memmove32()
40 static inline void __put_unaligned_memmove64(u64 val, void *p) __put_unaligned_memmove64() argument
42 memmove(p, &val, 8); __put_unaligned_memmove64()
H A Dpacked_struct.h28 static inline void __put_unaligned_cpu16(u16 val, void *p) __put_unaligned_cpu16() argument
31 ptr->x = val; __put_unaligned_cpu16()
34 static inline void __put_unaligned_cpu32(u32 val, void *p) __put_unaligned_cpu32() argument
37 ptr->x = val; __put_unaligned_cpu32()
40 static inline void __put_unaligned_cpu64(u64 val, void *p) __put_unaligned_cpu64() argument
43 ptr->x = val; __put_unaligned_cpu64()
/linux-4.1.27/arch/c6x/include/uapi/asm/
H A Dswab.h12 static inline __attribute_const__ __u16 __c6x_swab16(__u16 val) __c6x_swab16() argument
14 asm("swap4 .l1 %0,%0\n" : "+a"(val)); __c6x_swab16()
15 return val; __c6x_swab16()
18 static inline __attribute_const__ __u32 __c6x_swab32(__u32 val) __c6x_swab32() argument
22 : "+a"(val)); __c6x_swab32()
23 return val; __c6x_swab32()
26 static inline __attribute_const__ __u64 __c6x_swab64(__u64 val) __c6x_swab64() argument
32 : "+a"(val)); __c6x_swab64()
33 return val; __c6x_swab64()
36 static inline __attribute_const__ __u32 __c6x_swahw32(__u32 val) __c6x_swahw32() argument
38 asm("swap2 .l1 %0,%0\n" : "+a"(val)); __c6x_swahw32()
39 return val; __c6x_swahw32()
42 static inline __attribute_const__ __u32 __c6x_swahb32(__u32 val) __c6x_swahb32() argument
44 asm("swap4 .l1 %0,%0\n" : "+a"(val)); __c6x_swahb32()
45 return val; __c6x_swahb32()
/linux-4.1.27/tools/include/tools/
H A Dbe_byteshift.h22 static inline void __put_unaligned_be16(uint16_t val, uint8_t *p) __put_unaligned_be16() argument
24 *p++ = val >> 8; __put_unaligned_be16()
25 *p++ = val; __put_unaligned_be16()
28 static inline void __put_unaligned_be32(uint32_t val, uint8_t *p) __put_unaligned_be32() argument
30 __put_unaligned_be16(val >> 16, p); __put_unaligned_be32()
31 __put_unaligned_be16(val, p + 2); __put_unaligned_be32()
34 static inline void __put_unaligned_be64(uint64_t val, uint8_t *p) __put_unaligned_be64() argument
36 __put_unaligned_be32(val >> 32, p); __put_unaligned_be64()
37 __put_unaligned_be32(val, p + 4); __put_unaligned_be64()
55 static inline void put_unaligned_be16(uint16_t val, void *p) put_unaligned_be16() argument
57 __put_unaligned_be16(val, p); put_unaligned_be16()
60 static inline void put_unaligned_be32(uint32_t val, void *p) put_unaligned_be32() argument
62 __put_unaligned_be32(val, p); put_unaligned_be32()
65 static inline void put_unaligned_be64(uint64_t val, void *p) put_unaligned_be64() argument
67 __put_unaligned_be64(val, p); put_unaligned_be64()
H A Dle_byteshift.h22 static inline void __put_unaligned_le16(uint16_t val, uint8_t *p) __put_unaligned_le16() argument
24 *p++ = val; __put_unaligned_le16()
25 *p++ = val >> 8; __put_unaligned_le16()
28 static inline void __put_unaligned_le32(uint32_t val, uint8_t *p) __put_unaligned_le32() argument
30 __put_unaligned_le16(val >> 16, p + 2); __put_unaligned_le32()
31 __put_unaligned_le16(val, p); __put_unaligned_le32()
34 static inline void __put_unaligned_le64(uint64_t val, uint8_t *p) __put_unaligned_le64() argument
36 __put_unaligned_le32(val >> 32, p + 4); __put_unaligned_le64()
37 __put_unaligned_le32(val, p); __put_unaligned_le64()
55 static inline void put_unaligned_le16(uint16_t val, void *p) put_unaligned_le16() argument
57 __put_unaligned_le16(val, p); put_unaligned_le16()
60 static inline void put_unaligned_le32(uint32_t val, void *p) put_unaligned_le32() argument
62 __put_unaligned_le32(val, p); put_unaligned_le32()
65 static inline void put_unaligned_le64(uint64_t val, void *p) put_unaligned_le64() argument
67 __put_unaligned_le64(val, p); put_unaligned_le64()
/linux-4.1.27/arch/arm64/include/asm/
H A Dpercpu.h49 unsigned long val, int size) \
58 #asm_op " %w[ret], %w[ret], %w[val]\n" \
62 : [val] "Ir" (val)); \
69 #asm_op " %w[ret], %w[ret], %w[val]\n" \
73 : [val] "Ir" (val)); \
80 #asm_op " %w[ret], %w[ret], %w[val]\n" \
84 : [val] "Ir" (val)); \
91 #asm_op " %[ret], %[ret], %[val]\n" \
95 : [val] "Ir" (val)); \
134 static inline void __percpu_write(void *ptr, unsigned long val, int size) __percpu_write() argument
138 ACCESS_ONCE(*(u8 *)ptr) = (u8)val; __percpu_write()
141 ACCESS_ONCE(*(u16 *)ptr) = (u16)val; __percpu_write()
144 ACCESS_ONCE(*(u32 *)ptr) = (u32)val; __percpu_write()
147 ACCESS_ONCE(*(u64 *)ptr) = (u64)val; __percpu_write()
154 static inline unsigned long __percpu_xchg(void *ptr, unsigned long val, __percpu_xchg() argument
164 "stxrb %w[loop], %w[val], %[ptr]\n" __percpu_xchg()
167 : [val] "r" (val)); __percpu_xchg()
174 "stxrh %w[loop], %w[val], %[ptr]\n" __percpu_xchg()
177 : [val] "r" (val)); __percpu_xchg()
184 "stxr %w[loop], %w[val], %[ptr]\n" __percpu_xchg()
187 : [val] "r" (val)); __percpu_xchg()
194 "stxr %w[loop], %[val], %[ptr]\n" __percpu_xchg()
197 : [val] "r" (val)); __percpu_xchg()
217 #define _percpu_write(pcp, val) \
220 __percpu_write(raw_cpu_ptr(&(pcp)), (unsigned long)(val), \
225 #define _pcp_protect(operation, pcp, val) \
230 (val), sizeof(pcp)); \
235 #define _percpu_add(pcp, val) \
236 _pcp_protect(__percpu_add, pcp, val)
238 #define _percpu_add_return(pcp, val) _percpu_add(pcp, val)
240 #define _percpu_and(pcp, val) \
241 _pcp_protect(__percpu_and, pcp, val)
243 #define _percpu_or(pcp, val) \
244 _pcp_protect(__percpu_or, pcp, val)
246 #define _percpu_xchg(pcp, val) (typeof(pcp)) \
247 _pcp_protect(__percpu_xchg, pcp, (unsigned long)(val))
249 #define this_cpu_add_1(pcp, val) _percpu_add(pcp, val)
250 #define this_cpu_add_2(pcp, val) _percpu_add(pcp, val)
251 #define this_cpu_add_4(pcp, val) _percpu_add(pcp, val)
252 #define this_cpu_add_8(pcp, val) _percpu_add(pcp, val)
254 #define this_cpu_add_return_1(pcp, val) _percpu_add_return(pcp, val)
255 #define this_cpu_add_return_2(pcp, val) _percpu_add_return(pcp, val)
256 #define this_cpu_add_return_4(pcp, val) _percpu_add_return(pcp, val)
257 #define this_cpu_add_return_8(pcp, val) _percpu_add_return(pcp, val)
259 #define this_cpu_and_1(pcp, val) _percpu_and(pcp, val)
260 #define this_cpu_and_2(pcp, val) _percpu_and(pcp, val)
261 #define this_cpu_and_4(pcp, val) _percpu_and(pcp, val)
262 #define this_cpu_and_8(pcp, val) _percpu_and(pcp, val)
264 #define this_cpu_or_1(pcp, val) _percpu_or(pcp, val)
265 #define this_cpu_or_2(pcp, val) _percpu_or(pcp, val)
266 #define this_cpu_or_4(pcp, val) _percpu_or(pcp, val)
267 #define this_cpu_or_8(pcp, val) _percpu_or(pcp, val)
274 #define this_cpu_write_1(pcp, val) _percpu_write(pcp, val)
275 #define this_cpu_write_2(pcp, val) _percpu_write(pcp, val)
276 #define this_cpu_write_4(pcp, val) _percpu_write(pcp, val)
277 #define this_cpu_write_8(pcp, val) _percpu_write(pcp, val)
279 #define this_cpu_xchg_1(pcp, val) _percpu_xchg(pcp, val)
280 #define this_cpu_xchg_2(pcp, val) _percpu_xchg(pcp, val)
281 #define this_cpu_xchg_4(pcp, val) _percpu_xchg(pcp, val)
282 #define this_cpu_xchg_8(pcp, val) _percpu_xchg(pcp, val)
/linux-4.1.27/drivers/net/wireless/brcm80211/brcmsmac/
H A Dtypes.h133 #define CONF_HAS(config, val) ((config) & (1 << (val)))
138 #define CONF_IS(config, val) ((config) == (1 << (val)))
139 #define CONF_GE(config, val) ((config) & (0-(1 << (val))))
140 #define CONF_GT(config, val) ((config) & (0-2*(1 << (val))))
141 #define CONF_LT(config, val) ((config) & ((1 << (val))-1))
142 #define CONF_LE(config, val) ((config) & (2*(1 << (val))-1))
146 #define NCONF_HAS(val) CONF_HAS(NCONF, val)
148 #define NCONF_IS(val) CONF_IS(NCONF, val)
149 #define NCONF_GE(val) CONF_GE(NCONF, val)
150 #define NCONF_GT(val) CONF_GT(NCONF, val)
151 #define NCONF_LT(val) CONF_LT(NCONF, val)
152 #define NCONF_LE(val) CONF_LE(NCONF, val)
154 #define LCNCONF_HAS(val) CONF_HAS(LCNCONF, val)
156 #define LCNCONF_IS(val) CONF_IS(LCNCONF, val)
157 #define LCNCONF_GE(val) CONF_GE(LCNCONF, val)
158 #define LCNCONF_GT(val) CONF_GT(LCNCONF, val)
159 #define LCNCONF_LT(val) CONF_LT(LCNCONF, val)
160 #define LCNCONF_LE(val) CONF_LE(LCNCONF, val)
162 #define D11CONF_HAS(val) CONF_HAS(D11CONF, val)
164 #define D11CONF_IS(val) CONF_IS(D11CONF, val)
165 #define D11CONF_GE(val) CONF_GE(D11CONF, val)
166 #define D11CONF_GT(val) CONF_GT(D11CONF, val)
167 #define D11CONF_LT(val) CONF_LT(D11CONF, val)
168 #define D11CONF_LE(val) CONF_LE(D11CONF, val)
170 #define PHYCONF_HAS(val) CONF_HAS(PHYTYPE, val)
171 #define PHYCONF_IS(val) CONF_IS(PHYTYPE, val)
173 #define NREV_IS(var, val) \
174 (NCONF_HAS(val) && (NCONF_IS(val) || ((var) == (val))))
176 #define NREV_GE(var, val) \
177 (NCONF_GE(val) && (!NCONF_LT(val) || ((var) >= (val))))
179 #define NREV_GT(var, val) \
180 (NCONF_GT(val) && (!NCONF_LE(val) || ((var) > (val))))
182 #define NREV_LT(var, val) \
183 (NCONF_LT(val) && (!NCONF_GE(val) || ((var) < (val))))
185 #define NREV_LE(var, val) \
186 (NCONF_LE(val) && (!NCONF_GT(val) || ((var) <= (val))))
188 #define LCNREV_IS(var, val) \
189 (LCNCONF_HAS(val) && (LCNCONF_IS(val) || ((var) == (val))))
191 #define LCNREV_GE(var, val) \
192 (LCNCONF_GE(val) && (!LCNCONF_LT(val) || ((var) >= (val))))
194 #define LCNREV_GT(var, val) \
195 (LCNCONF_GT(val) && (!LCNCONF_LE(val) || ((var) > (val))))
197 #define LCNREV_LT(var, val) \
198 (LCNCONF_LT(val) && (!LCNCONF_GE(val) || ((var) < (val))))
200 #define LCNREV_LE(var, val) \
201 (LCNCONF_LE(val) && (!LCNCONF_GT(val) || ((var) <= (val))))
203 #define D11REV_IS(var, val) \
204 (D11CONF_HAS(val) && (D11CONF_IS(val) || ((var) == (val))))
206 #define D11REV_GE(var, val) \
207 (D11CONF_GE(val) && (!D11CONF_LT(val) || ((var) >= (val))))
209 #define D11REV_GT(var, val) \
210 (D11CONF_GT(val) && (!D11CONF_LE(val) || ((var) > (val))))
212 #define D11REV_LT(var, val) \
213 (D11CONF_LT(val) && (!D11CONF_GE(val) || ((var) < (val))))
215 #define D11REV_LE(var, val) \
216 (D11CONF_LE(val) && (!D11CONF_GT(val) || ((var) <= (val))))
218 #define PHYTYPE_IS(var, val)\
219 (PHYCONF_HAS(val) && (PHYCONF_IS(val) || ((var) == (val))))
273 #define mboolmaskset(mb, mask, val) ((mb) = (((mb) & ~(mask)) | (val)))
/linux-4.1.27/arch/s390/include/asm/
H A Dpercpu.h26 #define arch_this_cpu_to_op_simple(pcp, val, op) \
36 new__ = old__ op (val); \
43 #define this_cpu_add_1(pcp, val) arch_this_cpu_to_op_simple(pcp, val, +)
44 #define this_cpu_add_2(pcp, val) arch_this_cpu_to_op_simple(pcp, val, +)
45 #define this_cpu_add_return_1(pcp, val) arch_this_cpu_to_op_simple(pcp, val, +)
46 #define this_cpu_add_return_2(pcp, val) arch_this_cpu_to_op_simple(pcp, val, +)
47 #define this_cpu_and_1(pcp, val) arch_this_cpu_to_op_simple(pcp, val, &)
48 #define this_cpu_and_2(pcp, val) arch_this_cpu_to_op_simple(pcp, val, &)
49 #define this_cpu_or_1(pcp, val) arch_this_cpu_to_op_simple(pcp, val, |)
50 #define this_cpu_or_2(pcp, val) arch_this_cpu_to_op_simple(pcp, val, |)
54 #define this_cpu_add_4(pcp, val) arch_this_cpu_to_op_simple(pcp, val, +)
55 #define this_cpu_add_8(pcp, val) arch_this_cpu_to_op_simple(pcp, val, +)
56 #define this_cpu_add_return_4(pcp, val) arch_this_cpu_to_op_simple(pcp, val, +)
57 #define this_cpu_add_return_8(pcp, val) arch_this_cpu_to_op_simple(pcp, val, +)
58 #define this_cpu_and_4(pcp, val) arch_this_cpu_to_op_simple(pcp, val, &)
59 #define this_cpu_and_8(pcp, val) arch_this_cpu_to_op_simple(pcp, val, &)
60 #define this_cpu_or_4(pcp, val) arch_this_cpu_to_op_simple(pcp, val, |)
61 #define this_cpu_or_8(pcp, val) arch_this_cpu_to_op_simple(pcp, val, |)
65 #define arch_this_cpu_add(pcp, val, op1, op2, szcast) \
68 pcp_op_T__ val__ = (val); \
89 #define this_cpu_add_4(pcp, val) arch_this_cpu_add(pcp, val, "laa", "asi", int)
90 #define this_cpu_add_8(pcp, val) arch_this_cpu_add(pcp, val, "laag", "agsi", long)
92 #define arch_this_cpu_add_return(pcp, val, op) \
95 pcp_op_T__ val__ = (val); \
108 #define this_cpu_add_return_4(pcp, val) arch_this_cpu_add_return(pcp, val, "laa")
109 #define this_cpu_add_return_8(pcp, val) arch_this_cpu_add_return(pcp, val, "laag")
111 #define arch_this_cpu_to_op(pcp, val, op) \
114 pcp_op_T__ val__ = (val); \
126 #define this_cpu_and_4(pcp, val) arch_this_cpu_to_op(pcp, val, "lan")
127 #define this_cpu_and_8(pcp, val) arch_this_cpu_to_op(pcp, val, "lang")
128 #define this_cpu_or_4(pcp, val) arch_this_cpu_to_op(pcp, val, "lao")
129 #define this_cpu_or_8(pcp, val) arch_this_cpu_to_op(pcp, val, "laog")
/linux-4.1.27/arch/arm/mach-rpc/
H A Dirq.c12 unsigned int val, mask; iomd_ack_irq_a() local
15 val = iomd_readb(IOMD_IRQMASKA); iomd_ack_irq_a()
16 iomd_writeb(val & ~mask, IOMD_IRQMASKA); iomd_ack_irq_a()
22 unsigned int val, mask; iomd_mask_irq_a() local
25 val = iomd_readb(IOMD_IRQMASKA); iomd_mask_irq_a()
26 iomd_writeb(val & ~mask, IOMD_IRQMASKA); iomd_mask_irq_a()
31 unsigned int val, mask; iomd_unmask_irq_a() local
34 val = iomd_readb(IOMD_IRQMASKA); iomd_unmask_irq_a()
35 iomd_writeb(val | mask, IOMD_IRQMASKA); iomd_unmask_irq_a()
46 unsigned int val, mask; iomd_mask_irq_b() local
49 val = iomd_readb(IOMD_IRQMASKB); iomd_mask_irq_b()
50 iomd_writeb(val & ~mask, IOMD_IRQMASKB); iomd_mask_irq_b()
55 unsigned int val, mask; iomd_unmask_irq_b() local
58 val = iomd_readb(IOMD_IRQMASKB); iomd_unmask_irq_b()
59 iomd_writeb(val | mask, IOMD_IRQMASKB); iomd_unmask_irq_b()
70 unsigned int val, mask; iomd_mask_irq_dma() local
73 val = iomd_readb(IOMD_DMAMASK); iomd_mask_irq_dma()
74 iomd_writeb(val & ~mask, IOMD_DMAMASK); iomd_mask_irq_dma()
79 unsigned int val, mask; iomd_unmask_irq_dma() local
82 val = iomd_readb(IOMD_DMAMASK); iomd_unmask_irq_dma()
83 iomd_writeb(val | mask, IOMD_DMAMASK); iomd_unmask_irq_dma()
94 unsigned int val, mask; iomd_mask_irq_fiq() local
97 val = iomd_readb(IOMD_FIQMASK); iomd_mask_irq_fiq()
98 iomd_writeb(val & ~mask, IOMD_FIQMASK); iomd_mask_irq_fiq()
103 unsigned int val, mask; iomd_unmask_irq_fiq() local
106 val = iomd_readb(IOMD_FIQMASK); iomd_unmask_irq_fiq()
107 iomd_writeb(val | mask, IOMD_FIQMASK); iomd_unmask_irq_fiq()
/linux-4.1.27/include/sound/
H A Demu8000_reg.h122 #define EMU8000_CPF_WRITE(emu, chan, val) \
123 snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(0, (chan)), (val))
124 #define EMU8000_PTRX_WRITE(emu, chan, val) \
125 snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(1, (chan)), (val))
126 #define EMU8000_CVCF_WRITE(emu, chan, val) \
127 snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(2, (chan)), (val))
128 #define EMU8000_VTFT_WRITE(emu, chan, val) \
129 snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(3, (chan)), (val))
130 #define EMU8000_PSST_WRITE(emu, chan, val) \
131 snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(6, (chan)), (val))
132 #define EMU8000_CSL_WRITE(emu, chan, val) \
133 snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(7, (chan)), (val))
134 #define EMU8000_CCCA_WRITE(emu, chan, val) \
135 snd_emu8000_poke_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(0, (chan)), (val))
136 #define EMU8000_HWCF4_WRITE(emu, val) \
137 snd_emu8000_poke_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 9), (val))
138 #define EMU8000_HWCF5_WRITE(emu, val) \
139 snd_emu8000_poke_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 10), (val))
140 #define EMU8000_HWCF6_WRITE(emu, val) \
141 snd_emu8000_poke_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 13), (val))
143 #define EMU8000_HWCF7_WRITE(emu, val) \
144 snd_emu8000_poke_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 14), (val))
145 #define EMU8000_SMALR_WRITE(emu, val) \
146 snd_emu8000_poke_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 20), (val))
147 #define EMU8000_SMARR_WRITE(emu, val) \
148 snd_emu8000_poke_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 21), (val))
149 #define EMU8000_SMALW_WRITE(emu, val) \
150 snd_emu8000_poke_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 22), (val))
151 #define EMU8000_SMARW_WRITE(emu, val) \
152 snd_emu8000_poke_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 23), (val))
153 #define EMU8000_SMLD_WRITE(emu, val) \
154 snd_emu8000_poke((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 26), (val))
155 #define EMU8000_SMRD_WRITE(emu, val) \
156 snd_emu8000_poke((emu), EMU8000_DATA2(emu), EMU8000_CMD(1, 26), (val))
157 #define EMU8000_WC_WRITE(emu, val) \
158 snd_emu8000_poke((emu), EMU8000_DATA2(emu), EMU8000_CMD(1, 27), (val))
159 #define EMU8000_HWCF1_WRITE(emu, val) \
160 snd_emu8000_poke((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 29), (val))
161 #define EMU8000_HWCF2_WRITE(emu, val) \
162 snd_emu8000_poke((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 30), (val))
163 #define EMU8000_HWCF3_WRITE(emu, val) \
164 snd_emu8000_poke((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 31), (val))
165 #define EMU8000_INIT1_WRITE(emu, chan, val) \
166 snd_emu8000_poke((emu), EMU8000_DATA1(emu), EMU8000_CMD(2, (chan)), (val))
167 #define EMU8000_INIT2_WRITE(emu, chan, val) \
168 snd_emu8000_poke((emu), EMU8000_DATA2(emu), EMU8000_CMD(2, (chan)), (val))
169 #define EMU8000_INIT3_WRITE(emu, chan, val) \
170 snd_emu8000_poke((emu), EMU8000_DATA1(emu), EMU8000_CMD(3, (chan)), (val))
171 #define EMU8000_INIT4_WRITE(emu, chan, val) \
172 snd_emu8000_poke((emu), EMU8000_DATA2(emu), EMU8000_CMD(3, (chan)), (val))
173 #define EMU8000_ENVVOL_WRITE(emu, chan, val) \
174 snd_emu8000_poke((emu), EMU8000_DATA1(emu), EMU8000_CMD(4, (chan)), (val))
175 #define EMU8000_DCYSUSV_WRITE(emu, chan, val) \
176 snd_emu8000_poke((emu), EMU8000_DATA1(emu), EMU8000_CMD(5, (chan)), (val))
177 #define EMU8000_ENVVAL_WRITE(emu, chan, val) \
178 snd_emu8000_poke((emu), EMU8000_DATA1(emu), EMU8000_CMD(6, (chan)), (val))
179 #define EMU8000_DCYSUS_WRITE(emu, chan, val) \
180 snd_emu8000_poke((emu), EMU8000_DATA1(emu), EMU8000_CMD(7, (chan)), (val))
181 #define EMU8000_ATKHLDV_WRITE(emu, chan, val) \
182 snd_emu8000_poke((emu), EMU8000_DATA2(emu), EMU8000_CMD(4, (chan)), (val))
183 #define EMU8000_LFO1VAL_WRITE(emu, chan, val) \
184 snd_emu8000_poke((emu), EMU8000_DATA2(emu), EMU8000_CMD(5, (chan)), (val))
185 #define EMU8000_ATKHLD_WRITE(emu, chan, val) \
186 snd_emu8000_poke((emu), EMU8000_DATA2(emu), EMU8000_CMD(6, (chan)), (val))
187 #define EMU8000_LFO2VAL_WRITE(emu, chan, val) \
188 snd_emu8000_poke((emu), EMU8000_DATA2(emu), EMU8000_CMD(7, (chan)), (val))
189 #define EMU8000_IP_WRITE(emu, chan, val) \
190 snd_emu8000_poke((emu), EMU8000_DATA3(emu), EMU8000_CMD(0, (chan)), (val))
191 #define EMU8000_IFATN_WRITE(emu, chan, val) \
192 snd_emu8000_poke((emu), EMU8000_DATA3(emu), EMU8000_CMD(1, (chan)), (val))
193 #define EMU8000_PEFE_WRITE(emu, chan, val) \
194 snd_emu8000_poke((emu), EMU8000_DATA3(emu), EMU8000_CMD(2, (chan)), (val))
195 #define EMU8000_FMMOD_WRITE(emu, chan, val) \
196 snd_emu8000_poke((emu), EMU8000_DATA3(emu), EMU8000_CMD(3, (chan)), (val))
197 #define EMU8000_TREMFRQ_WRITE(emu, chan, val) \
198 snd_emu8000_poke((emu), EMU8000_DATA3(emu), EMU8000_CMD(4, (chan)), (val))
199 #define EMU8000_FM2FRQ2_WRITE(emu, chan, val) \
200 snd_emu8000_poke((emu), EMU8000_DATA3(emu), EMU8000_CMD(5, (chan)), (val))
202 #define EMU8000_0080_WRITE(emu, chan, val) \
203 snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(4, (chan)), (val))
204 #define EMU8000_00A0_WRITE(emu, chan, val) \
205 snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(5, (chan)), (val))
/linux-4.1.27/arch/mips/bcm63xx/
H A Dcs.c37 u32 val; bcm63xx_set_cs_base() local
49 val = (base & MPI_CSBASE_BASE_MASK); bcm63xx_set_cs_base()
51 val |= (ilog2(size) - ilog2(8 * 1024)) << MPI_CSBASE_SIZE_SHIFT; bcm63xx_set_cs_base()
54 bcm_mpi_writel(val, MPI_CSBASE_REG(cs)); bcm63xx_set_cs_base()
69 u32 val; bcm63xx_set_cs_timing() local
75 val = bcm_mpi_readl(MPI_CSCTL_REG(cs)); bcm63xx_set_cs_timing()
76 val &= ~(MPI_CSCTL_WAIT_MASK); bcm63xx_set_cs_timing()
77 val &= ~(MPI_CSCTL_SETUP_MASK); bcm63xx_set_cs_timing()
78 val &= ~(MPI_CSCTL_HOLD_MASK); bcm63xx_set_cs_timing()
79 val |= wait << MPI_CSCTL_WAIT_SHIFT; bcm63xx_set_cs_timing()
80 val |= setup << MPI_CSCTL_SETUP_SHIFT; bcm63xx_set_cs_timing()
81 val |= hold << MPI_CSCTL_HOLD_SHIFT; bcm63xx_set_cs_timing()
82 bcm_mpi_writel(val, MPI_CSCTL_REG(cs)); bcm63xx_set_cs_timing()
96 u32 val; bcm63xx_set_cs_param() local
108 val = bcm_mpi_readl(MPI_CSCTL_REG(cs)); bcm63xx_set_cs_param()
109 val &= ~(MPI_CSCTL_DATA16_MASK); bcm63xx_set_cs_param()
110 val &= ~(MPI_CSCTL_SYNCMODE_MASK); bcm63xx_set_cs_param()
111 val &= ~(MPI_CSCTL_TSIZE_MASK); bcm63xx_set_cs_param()
112 val &= ~(MPI_CSCTL_ENDIANSWAP_MASK); bcm63xx_set_cs_param()
113 val |= params; bcm63xx_set_cs_param()
114 bcm_mpi_writel(val, MPI_CSCTL_REG(cs)); bcm63xx_set_cs_param()
128 u32 val; bcm63xx_set_cs_status() local
134 val = bcm_mpi_readl(MPI_CSCTL_REG(cs)); bcm63xx_set_cs_status()
136 val |= MPI_CSCTL_ENABLE_MASK; bcm63xx_set_cs_status()
138 val &= ~MPI_CSCTL_ENABLE_MASK; bcm63xx_set_cs_status()
139 bcm_mpi_writel(val, MPI_CSCTL_REG(cs)); bcm63xx_set_cs_status()
H A Ddev-flash.c60 u32 val; bcm63xx_detect_flash_type() local
64 val = bcm_misc_readl(MISC_STRAPBUS_6328_REG); bcm63xx_detect_flash_type()
65 if (val & STRAPBUS_6328_BOOT_SEL_SERIAL) bcm63xx_detect_flash_type()
76 val = bcm_gpio_readl(GPIO_STRAPBUS_REG); bcm63xx_detect_flash_type()
77 if (val & STRAPBUS_6358_BOOT_SEL_PARALLEL) bcm63xx_detect_flash_type()
82 val = bcm_misc_readl(MISC_STRAPBUS_6362_REG); bcm63xx_detect_flash_type()
83 if (val & STRAPBUS_6362_BOOT_SEL_SERIAL) bcm63xx_detect_flash_type()
88 val = bcm_gpio_readl(GPIO_STRAPBUS_REG); bcm63xx_detect_flash_type()
89 switch (val & STRAPBUS_6368_BOOT_SEL_MASK) { bcm63xx_detect_flash_type()
105 u32 val; bcm63xx_flash_register() local
112 val = bcm_mpi_readl(MPI_CSBASE_REG(0)); bcm63xx_flash_register()
113 val &= MPI_CSBASE_BASE_MASK; bcm63xx_flash_register()
115 mtd_resources[0].start = val; bcm63xx_flash_register()
H A Dearly_printk.c14 unsigned int val; wait_xfered() local
18 val = bcm_uart0_readl(UART_IR_REG); wait_xfered()
19 if (val & UART_IR_STAT(UART_IR_TXEMPTY)) wait_xfered()
/linux-4.1.27/drivers/usb/phy/
H A Dphy-tegra-usb.c209 unsigned long val; set_pts() local
212 val = readl(base + TEGRA_USB_HOSTPC1_DEVLC); set_pts()
213 val &= ~TEGRA_USB_HOSTPC1_DEVLC_PTS(~0); set_pts()
214 val |= TEGRA_USB_HOSTPC1_DEVLC_PTS(pts_val); set_pts()
215 writel(val, base + TEGRA_USB_HOSTPC1_DEVLC); set_pts()
217 val = readl(base + TEGRA_USB_PORTSC1) & ~TEGRA_PORTSC1_RWC_BITS; set_pts()
218 val &= ~TEGRA_USB_PORTSC1_PTS(~0); set_pts()
219 val |= TEGRA_USB_PORTSC1_PTS(pts_val); set_pts()
220 writel(val, base + TEGRA_USB_PORTSC1); set_pts()
227 unsigned long val; set_phcd() local
230 val = readl(base + TEGRA_USB_HOSTPC1_DEVLC); set_phcd()
232 val |= TEGRA_USB_HOSTPC1_DEVLC_PHCD; set_phcd()
234 val &= ~TEGRA_USB_HOSTPC1_DEVLC_PHCD; set_phcd()
235 writel(val, base + TEGRA_USB_HOSTPC1_DEVLC); set_phcd()
237 val = readl(base + TEGRA_USB_PORTSC1) & ~PORT_RWC_BITS; set_phcd()
239 val |= TEGRA_USB_PORTSC1_PHCD; set_phcd()
241 val &= ~TEGRA_USB_PORTSC1_PHCD; set_phcd()
242 writel(val, base + TEGRA_USB_PORTSC1); set_phcd()
259 unsigned long val, flags; utmip_pad_power_on() local
268 val = readl(base + UTMIP_BIAS_CFG0); utmip_pad_power_on()
269 val &= ~(UTMIP_OTGPD | UTMIP_BIASPD); utmip_pad_power_on()
272 val &= ~(UTMIP_HSSQUELCH_LEVEL(~0) | utmip_pad_power_on()
276 val |= UTMIP_HSSQUELCH_LEVEL(config->hssquelch_level); utmip_pad_power_on()
277 val |= UTMIP_HSDISCON_LEVEL(config->hsdiscon_level); utmip_pad_power_on()
278 val |= UTMIP_HSDISCON_LEVEL_MSB(config->hsdiscon_level); utmip_pad_power_on()
280 writel(val, base + UTMIP_BIAS_CFG0); utmip_pad_power_on()
290 unsigned long val, flags; utmip_pad_power_off() local
303 val = readl(base + UTMIP_BIAS_CFG0); utmip_pad_power_off()
304 val |= UTMIP_OTGPD | UTMIP_BIASPD; utmip_pad_power_off()
305 writel(val, base + UTMIP_BIAS_CFG0); utmip_pad_power_off()
329 unsigned long val; utmi_phy_clk_disable() local
333 val = readl(base + USB_SUSP_CTRL); utmi_phy_clk_disable()
334 val |= USB_SUSP_SET; utmi_phy_clk_disable()
335 writel(val, base + USB_SUSP_CTRL); utmi_phy_clk_disable()
339 val = readl(base + USB_SUSP_CTRL); utmi_phy_clk_disable()
340 val &= ~USB_SUSP_SET; utmi_phy_clk_disable()
341 writel(val, base + USB_SUSP_CTRL); utmi_phy_clk_disable()
351 unsigned long val; utmi_phy_clk_enable() local
355 val = readl(base + USB_SUSP_CTRL); utmi_phy_clk_enable()
356 val |= USB_SUSP_CLR; utmi_phy_clk_enable()
357 writel(val, base + USB_SUSP_CTRL); utmi_phy_clk_enable()
361 val = readl(base + USB_SUSP_CTRL); utmi_phy_clk_enable()
362 val &= ~USB_SUSP_CLR; utmi_phy_clk_enable()
363 writel(val, base + USB_SUSP_CTRL); utmi_phy_clk_enable()
374 unsigned long val; utmi_phy_power_on() local
378 val = readl(base + USB_SUSP_CTRL); utmi_phy_power_on()
379 val |= UTMIP_RESET; utmi_phy_power_on()
380 writel(val, base + USB_SUSP_CTRL); utmi_phy_power_on()
383 val = readl(base + USB1_LEGACY_CTRL); utmi_phy_power_on()
384 val |= USB1_NO_LEGACY_MODE; utmi_phy_power_on()
385 writel(val, base + USB1_LEGACY_CTRL); utmi_phy_power_on()
388 val = readl(base + UTMIP_TX_CFG0); utmi_phy_power_on()
389 val |= UTMIP_FS_PREABMLE_J; utmi_phy_power_on()
390 writel(val, base + UTMIP_TX_CFG0); utmi_phy_power_on()
392 val = readl(base + UTMIP_HSRX_CFG0); utmi_phy_power_on()
393 val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0)); utmi_phy_power_on()
394 val |= UTMIP_IDLE_WAIT(config->idle_wait_delay); utmi_phy_power_on()
395 val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit); utmi_phy_power_on()
396 writel(val, base + UTMIP_HSRX_CFG0); utmi_phy_power_on()
398 val = readl(base + UTMIP_HSRX_CFG1); utmi_phy_power_on()
399 val &= ~UTMIP_HS_SYNC_START_DLY(~0); utmi_phy_power_on()
400 val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay); utmi_phy_power_on()
401 writel(val, base + UTMIP_HSRX_CFG1); utmi_phy_power_on()
403 val = readl(base + UTMIP_DEBOUNCE_CFG0); utmi_phy_power_on()
404 val &= ~UTMIP_BIAS_DEBOUNCE_A(~0); utmi_phy_power_on()
405 val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce); utmi_phy_power_on()
406 writel(val, base + UTMIP_DEBOUNCE_CFG0); utmi_phy_power_on()
408 val = readl(base + UTMIP_MISC_CFG0); utmi_phy_power_on()
409 val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE; utmi_phy_power_on()
410 writel(val, base + UTMIP_MISC_CFG0); utmi_phy_power_on()
413 val = readl(base + UTMIP_MISC_CFG1); utmi_phy_power_on()
414 val &= ~(UTMIP_PLL_ACTIVE_DLY_COUNT(~0) | utmi_phy_power_on()
416 val |= UTMIP_PLL_ACTIVE_DLY_COUNT(phy->freq->active_delay) | utmi_phy_power_on()
418 writel(val, base + UTMIP_MISC_CFG1); utmi_phy_power_on()
420 val = readl(base + UTMIP_PLL_CFG1); utmi_phy_power_on()
421 val &= ~(UTMIP_XTAL_FREQ_COUNT(~0) | utmi_phy_power_on()
423 val |= UTMIP_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count) | utmi_phy_power_on()
425 writel(val, base + UTMIP_PLL_CFG1); utmi_phy_power_on()
429 val = readl(base + USB_SUSP_CTRL); utmi_phy_power_on()
430 val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV); utmi_phy_power_on()
431 writel(val, base + USB_SUSP_CTRL); utmi_phy_power_on()
433 val = readl(base + UTMIP_BAT_CHRG_CFG0); utmi_phy_power_on()
434 val &= ~UTMIP_PD_CHRG; utmi_phy_power_on()
435 writel(val, base + UTMIP_BAT_CHRG_CFG0); utmi_phy_power_on()
437 val = readl(base + UTMIP_BAT_CHRG_CFG0); utmi_phy_power_on()
438 val |= UTMIP_PD_CHRG; utmi_phy_power_on()
439 writel(val, base + UTMIP_BAT_CHRG_CFG0); utmi_phy_power_on()
444 val = readl(base + UTMIP_XCVR_CFG0); utmi_phy_power_on()
445 val &= ~(UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN | utmi_phy_power_on()
451 val |= UTMIP_XCVR_SETUP(config->xcvr_setup); utmi_phy_power_on()
452 val |= UTMIP_XCVR_SETUP_MSB(config->xcvr_setup); utmi_phy_power_on()
454 val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew); utmi_phy_power_on()
455 val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew); utmi_phy_power_on()
458 val &= ~(UTMIP_XCVR_HSSLEW(~0) | UTMIP_XCVR_HSSLEW_MSB(~0)); utmi_phy_power_on()
459 val |= UTMIP_XCVR_HSSLEW(config->xcvr_hsslew); utmi_phy_power_on()
460 val |= UTMIP_XCVR_HSSLEW_MSB(config->xcvr_hsslew); utmi_phy_power_on()
462 writel(val, base + UTMIP_XCVR_CFG0); utmi_phy_power_on()
464 val = readl(base + UTMIP_XCVR_CFG1); utmi_phy_power_on()
465 val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN | utmi_phy_power_on()
467 val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj); utmi_phy_power_on()
468 writel(val, base + UTMIP_XCVR_CFG1); utmi_phy_power_on()
470 val = readl(base + UTMIP_BIAS_CFG1); utmi_phy_power_on()
471 val &= ~UTMIP_BIAS_PDTRK_COUNT(~0); utmi_phy_power_on()
472 val |= UTMIP_BIAS_PDTRK_COUNT(0x5); utmi_phy_power_on()
473 writel(val, base + UTMIP_BIAS_CFG1); utmi_phy_power_on()
475 val = readl(base + UTMIP_SPARE_CFG0); utmi_phy_power_on()
477 val |= FUSE_SETUP_SEL; utmi_phy_power_on()
479 val &= ~FUSE_SETUP_SEL; utmi_phy_power_on()
480 writel(val, base + UTMIP_SPARE_CFG0); utmi_phy_power_on()
483 val = readl(base + USB_SUSP_CTRL); utmi_phy_power_on()
484 val |= UTMIP_PHY_ENABLE; utmi_phy_power_on()
485 writel(val, base + USB_SUSP_CTRL); utmi_phy_power_on()
488 val = readl(base + USB_SUSP_CTRL); utmi_phy_power_on()
489 val &= ~UTMIP_RESET; utmi_phy_power_on()
490 writel(val, base + USB_SUSP_CTRL); utmi_phy_power_on()
493 val = readl(base + USB1_LEGACY_CTRL); utmi_phy_power_on()
494 val &= ~USB1_VBUS_SENSE_CTL_MASK; utmi_phy_power_on()
495 val |= USB1_VBUS_SENSE_CTL_A_SESS_VLD; utmi_phy_power_on()
496 writel(val, base + USB1_LEGACY_CTRL); utmi_phy_power_on()
498 val = readl(base + USB_SUSP_CTRL); utmi_phy_power_on()
499 val &= ~USB_SUSP_SET; utmi_phy_power_on()
500 writel(val, base + USB_SUSP_CTRL); utmi_phy_power_on()
506 val = readl(base + USB_USBMODE); utmi_phy_power_on()
507 val &= ~USB_USBMODE_MASK; utmi_phy_power_on()
509 val |= USB_USBMODE_HOST; utmi_phy_power_on()
511 val |= USB_USBMODE_DEVICE; utmi_phy_power_on()
512 writel(val, base + USB_USBMODE); utmi_phy_power_on()
523 unsigned long val; utmi_phy_power_off() local
529 val = readl(base + USB_SUSP_CTRL); utmi_phy_power_off()
530 val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0); utmi_phy_power_off()
531 val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5); utmi_phy_power_off()
532 writel(val, base + USB_SUSP_CTRL); utmi_phy_power_off()
535 val = readl(base + USB_SUSP_CTRL); utmi_phy_power_off()
536 val |= UTMIP_RESET; utmi_phy_power_off()
537 writel(val, base + USB_SUSP_CTRL); utmi_phy_power_off()
539 val = readl(base + UTMIP_BAT_CHRG_CFG0); utmi_phy_power_off()
540 val |= UTMIP_PD_CHRG; utmi_phy_power_off()
541 writel(val, base + UTMIP_BAT_CHRG_CFG0); utmi_phy_power_off()
543 val = readl(base + UTMIP_XCVR_CFG0); utmi_phy_power_off()
544 val |= UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN | utmi_phy_power_off()
546 writel(val, base + UTMIP_XCVR_CFG0); utmi_phy_power_off()
548 val = readl(base + UTMIP_XCVR_CFG1); utmi_phy_power_off()
549 val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN | utmi_phy_power_off()
551 writel(val, base + UTMIP_XCVR_CFG1); utmi_phy_power_off()
558 unsigned long val; utmi_phy_preresume() local
561 val = readl(base + UTMIP_TX_CFG0); utmi_phy_preresume()
562 val |= UTMIP_HS_DISCON_DISABLE; utmi_phy_preresume()
563 writel(val, base + UTMIP_TX_CFG0); utmi_phy_preresume()
568 unsigned long val; utmi_phy_postresume() local
571 val = readl(base + UTMIP_TX_CFG0); utmi_phy_postresume()
572 val &= ~UTMIP_HS_DISCON_DISABLE; utmi_phy_postresume()
573 writel(val, base + UTMIP_TX_CFG0); utmi_phy_postresume()
579 unsigned long val; utmi_phy_restore_start() local
582 val = readl(base + UTMIP_MISC_CFG0); utmi_phy_restore_start()
583 val &= ~UTMIP_DPDM_OBSERVE_SEL(~0); utmi_phy_restore_start()
585 val |= UTMIP_DPDM_OBSERVE_SEL_FS_K; utmi_phy_restore_start()
587 val |= UTMIP_DPDM_OBSERVE_SEL_FS_J; utmi_phy_restore_start()
588 writel(val, base + UTMIP_MISC_CFG0); utmi_phy_restore_start()
591 val = readl(base + UTMIP_MISC_CFG0); utmi_phy_restore_start()
592 val |= UTMIP_DPDM_OBSERVE; utmi_phy_restore_start()
593 writel(val, base + UTMIP_MISC_CFG0); utmi_phy_restore_start()
599 unsigned long val; utmi_phy_restore_end() local
602 val = readl(base + UTMIP_MISC_CFG0); utmi_phy_restore_end()
603 val &= ~UTMIP_DPDM_OBSERVE; utmi_phy_restore_end()
604 writel(val, base + UTMIP_MISC_CFG0); utmi_phy_restore_end()
611 unsigned long val; ulpi_phy_power_on() local
631 val = readl(base + USB_SUSP_CTRL); ulpi_phy_power_on()
632 val |= UHSIC_RESET; ulpi_phy_power_on()
633 writel(val, base + USB_SUSP_CTRL); ulpi_phy_power_on()
635 val = readl(base + ULPI_TIMING_CTRL_0); ulpi_phy_power_on()
636 val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP; ulpi_phy_power_on()
637 writel(val, base + ULPI_TIMING_CTRL_0); ulpi_phy_power_on()
639 val = readl(base + USB_SUSP_CTRL); ulpi_phy_power_on()
640 val |= ULPI_PHY_ENABLE; ulpi_phy_power_on()
641 writel(val, base + USB_SUSP_CTRL); ulpi_phy_power_on()
643 val = 0; ulpi_phy_power_on()
644 writel(val, base + ULPI_TIMING_CTRL_1); ulpi_phy_power_on()
646 val |= ULPI_DATA_TRIMMER_SEL(4); ulpi_phy_power_on()
647 val |= ULPI_STPDIRNXT_TRIMMER_SEL(4); ulpi_phy_power_on()
648 val |= ULPI_DIR_TRIMMER_SEL(4); ulpi_phy_power_on()
649 writel(val, base + ULPI_TIMING_CTRL_1); ulpi_phy_power_on()
652 val |= ULPI_DATA_TRIMMER_LOAD; ulpi_phy_power_on()
653 val |= ULPI_STPDIRNXT_TRIMMER_LOAD; ulpi_phy_power_on()
654 val |= ULPI_DIR_TRIMMER_LOAD; ulpi_phy_power_on()
655 writel(val, base + ULPI_TIMING_CTRL_1); ulpi_phy_power_on()
670 val = readl(base + USB_SUSP_CTRL); ulpi_phy_power_on()
671 val |= USB_SUSP_CLR; ulpi_phy_power_on()
672 writel(val, base + USB_SUSP_CTRL); ulpi_phy_power_on()
675 val = readl(base + USB_SUSP_CTRL); ulpi_phy_power_on()
676 val &= ~USB_SUSP_CLR; ulpi_phy_power_on()
677 writel(val, base + USB_SUSP_CTRL); ulpi_phy_power_on()
H A Dphy-rcar-gen2-usb.c55 u32 val; __rcar_gen2_usbhs_phy_enable() local
59 val = ioread32(base + USBHS_UGCTRL_REG); __rcar_gen2_usbhs_phy_enable()
60 val &= ~USBHS_UGCTRL_PLLRESET; __rcar_gen2_usbhs_phy_enable()
61 iowrite32(val, base + USBHS_UGCTRL_REG); __rcar_gen2_usbhs_phy_enable()
63 val = ioread16(base + USBHS_LPSTS_REG); __rcar_gen2_usbhs_phy_enable()
64 val |= USBHS_LPSTS_SUSPM; __rcar_gen2_usbhs_phy_enable()
65 iowrite16(val, base + USBHS_LPSTS_REG); __rcar_gen2_usbhs_phy_enable()
68 val = ioread32(base + USBHS_UGSTS_REG); __rcar_gen2_usbhs_phy_enable()
69 if ((val & USBHS_UGSTS_LOCK) == USBHS_UGSTS_LOCK) { __rcar_gen2_usbhs_phy_enable()
70 val = ioread32(base + USBHS_UGCTRL_REG); __rcar_gen2_usbhs_phy_enable()
71 val |= USBHS_UGCTRL_CONNECT; __rcar_gen2_usbhs_phy_enable()
72 iowrite32(val, base + USBHS_UGCTRL_REG); __rcar_gen2_usbhs_phy_enable()
85 u32 val; __rcar_gen2_usbhs_phy_disable() local
88 val = ioread32(base + USBHS_UGCTRL_REG); __rcar_gen2_usbhs_phy_disable()
89 val &= ~USBHS_UGCTRL_CONNECT; __rcar_gen2_usbhs_phy_disable()
90 iowrite32(val, base + USBHS_UGCTRL_REG); __rcar_gen2_usbhs_phy_disable()
92 val = ioread16(base + USBHS_LPSTS_REG); __rcar_gen2_usbhs_phy_disable()
93 val &= ~USBHS_LPSTS_SUSPM; __rcar_gen2_usbhs_phy_disable()
94 iowrite16(val, base + USBHS_LPSTS_REG); __rcar_gen2_usbhs_phy_disable()
96 val = ioread32(base + USBHS_UGCTRL_REG); __rcar_gen2_usbhs_phy_disable()
97 val |= USBHS_UGCTRL_PLLRESET; __rcar_gen2_usbhs_phy_disable()
98 iowrite32(val, base + USBHS_UGCTRL_REG); __rcar_gen2_usbhs_phy_disable()
105 u32 val; __rcar_gen2_usb_phy_init() local
110 val = ioread32(priv->base + USBHS_UGCTRL2_REG); __rcar_gen2_usb_phy_init()
111 val &= ~(USBHS_UGCTRL2_USB0_HS | USBHS_UGCTRL2_USB2_SS); __rcar_gen2_usb_phy_init()
112 val |= priv->ugctrl2; __rcar_gen2_usb_phy_init()
113 iowrite32(val, priv->base + USBHS_UGCTRL2_REG); __rcar_gen2_usb_phy_init()
/linux-4.1.27/arch/mips/boot/dts/include/dt-bindings/pinctrl/
H A Domap.h58 #define OMAP2420_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0030) (val)
59 #define OMAP2430_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val)
60 #define OMAP3_CORE1_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val)
61 #define OMAP3430_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25d8) (val)
62 #define OMAP3630_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25a0) (val)
63 #define OMAP3_WKUP_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2a00) (val)
64 #define DM816X_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
65 #define AM33XX_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
66 #define AM4372_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
67 #define DRA7XX_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x3400) (val)
75 #define OMAP4_IOPAD(offset, val) OMAP_PADCONF_OFFSET((offset), 0x0040) (val)
76 #define OMAP5_IOPAD(offset, val) OMAP_PADCONF_OFFSET((offset), 0x0040) (val)
/linux-4.1.27/arch/powerpc/boot/dts/include/dt-bindings/pinctrl/
H A Domap.h58 #define OMAP2420_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0030) (val)
59 #define OMAP2430_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val)
60 #define OMAP3_CORE1_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val)
61 #define OMAP3430_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25d8) (val)
62 #define OMAP3630_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25a0) (val)
63 #define OMAP3_WKUP_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2a00) (val)
64 #define DM816X_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
65 #define AM33XX_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
66 #define AM4372_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
67 #define DRA7XX_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x3400) (val)
75 #define OMAP4_IOPAD(offset, val) OMAP_PADCONF_OFFSET((offset), 0x0040) (val)
76 #define OMAP5_IOPAD(offset, val) OMAP_PADCONF_OFFSET((offset), 0x0040) (val)
/linux-4.1.27/arch/arm64/boot/dts/include/dt-bindings/pinctrl/
H A Domap.h58 #define OMAP2420_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0030) (val)
59 #define OMAP2430_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val)
60 #define OMAP3_CORE1_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val)
61 #define OMAP3430_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25d8) (val)
62 #define OMAP3630_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25a0) (val)
63 #define OMAP3_WKUP_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2a00) (val)
64 #define DM816X_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
65 #define AM33XX_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
66 #define AM4372_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
67 #define DRA7XX_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x3400) (val)
75 #define OMAP4_IOPAD(offset, val) OMAP_PADCONF_OFFSET((offset), 0x0040) (val)
76 #define OMAP5_IOPAD(offset, val) OMAP_PADCONF_OFFSET((offset), 0x0040) (val)
/linux-4.1.27/arch/metag/boot/dts/include/dt-bindings/pinctrl/
H A Domap.h58 #define OMAP2420_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0030) (val)
59 #define OMAP2430_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val)
60 #define OMAP3_CORE1_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val)
61 #define OMAP3430_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25d8) (val)
62 #define OMAP3630_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25a0) (val)
63 #define OMAP3_WKUP_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2a00) (val)
64 #define DM816X_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
65 #define AM33XX_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
66 #define AM4372_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
67 #define DRA7XX_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x3400) (val)
75 #define OMAP4_IOPAD(offset, val) OMAP_PADCONF_OFFSET((offset), 0x0040) (val)
76 #define OMAP5_IOPAD(offset, val) OMAP_PADCONF_OFFSET((offset), 0x0040) (val)
/linux-4.1.27/arch/arm/boot/dts/include/dt-bindings/pinctrl/
H A Domap.h58 #define OMAP2420_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0030) (val)
59 #define OMAP2430_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val)
60 #define OMAP3_CORE1_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val)
61 #define OMAP3430_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25d8) (val)
62 #define OMAP3630_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25a0) (val)
63 #define OMAP3_WKUP_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2a00) (val)
64 #define DM816X_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
65 #define AM33XX_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
66 #define AM4372_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
67 #define DRA7XX_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x3400) (val)
75 #define OMAP4_IOPAD(offset, val) OMAP_PADCONF_OFFSET((offset), 0x0040) (val)
76 #define OMAP5_IOPAD(offset, val) OMAP_PADCONF_OFFSET((offset), 0x0040) (val)
/linux-4.1.27/include/dt-bindings/pinctrl/
H A Domap.h58 #define OMAP2420_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0030) (val)
59 #define OMAP2430_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val)
60 #define OMAP3_CORE1_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val)
61 #define OMAP3430_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25d8) (val)
62 #define OMAP3630_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25a0) (val)
63 #define OMAP3_WKUP_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2a00) (val)
64 #define DM816X_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
65 #define AM33XX_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
66 #define AM4372_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
67 #define DRA7XX_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x3400) (val)
75 #define OMAP4_IOPAD(offset, val) OMAP_PADCONF_OFFSET((offset), 0x0040) (val)
76 #define OMAP5_IOPAD(offset, val) OMAP_PADCONF_OFFSET((offset), 0x0040) (val)
/linux-4.1.27/drivers/gpu/drm/msm/adreno/
H A Da2xx.xml.h262 static inline uint32_t A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR() argument
264 return ((val) << A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK; A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR()
268 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR() argument
270 return ((val) << A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK; A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR()
274 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR() argument
276 return ((val) << A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK; A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR()
280 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR() argument
282 return ((val) << A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK; A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR()
286 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR() argument
288 return ((val) << A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK; A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR()
292 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR() argument
294 return ((val) << A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK; A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR()
298 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR() argument
300 return ((val) << A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK; A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR()
304 static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR() argument
306 return ((val) << A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK; A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR()
310 static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR() argument
312 return ((val) << A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK; A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR()
316 static inline uint32_t A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR() argument
318 return ((val) << A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK; A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR()
322 static inline uint32_t A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR() argument
324 return ((val) << A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK; A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR()
384 static inline uint32_t A2XX_RBBM_STATUS_CMDFIFO_AVAIL(uint32_t val) A2XX_RBBM_STATUS_CMDFIFO_AVAIL() argument
386 return ((val) << A2XX_RBBM_STATUS_CMDFIFO_AVAIL__SHIFT) & A2XX_RBBM_STATUS_CMDFIFO_AVAIL__MASK; A2XX_RBBM_STATUS_CMDFIFO_AVAIL()
411 static inline uint32_t A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT(uint32_t val) A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT() argument
413 return ((val) << A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__SHIFT) & A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__MASK; A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT()
421 static inline uint32_t A2XX_MH_ARBITER_CONFIG_PAGE_SIZE(uint32_t val) A2XX_MH_ARBITER_CONFIG_PAGE_SIZE() argument
423 return ((val) << A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__SHIFT) & A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__MASK; A2XX_MH_ARBITER_CONFIG_PAGE_SIZE()
430 static inline uint32_t A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT(uint32_t val) A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT() argument
432 return ((val) << A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__SHIFT) & A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__MASK; A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT()
443 static inline uint32_t A2XX_A220_VSC_BIN_SIZE_WIDTH(uint32_t val) A2XX_A220_VSC_BIN_SIZE_WIDTH() argument
445 return ((val >> 5) << A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT) & A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK; A2XX_A220_VSC_BIN_SIZE_WIDTH()
449 static inline uint32_t A2XX_A220_VSC_BIN_SIZE_HEIGHT(uint32_t val) A2XX_A220_VSC_BIN_SIZE_HEIGHT() argument
451 return ((val >> 5) << A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT) & A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK; A2XX_A220_VSC_BIN_SIZE_HEIGHT()
541 static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT(uint32_t val) A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT() argument
543 return ((val) << A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__MASK; A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT()
552 static inline uint32_t A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT(uint32_t val) A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT() argument
554 return ((val) << A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__SHIFT) & A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__MASK; A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT()
562 static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK(uint32_t val) A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK() argument
564 return ((val) << A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__MASK; A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK()
569 static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT(uint32_t val) A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT() argument
571 return ((val) << A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__MASK; A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT()
575 static inline uint32_t A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT(uint32_t val) A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT() argument
577 return ((val) << A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__SHIFT) & A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__MASK; A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT()
594 static inline uint32_t A2XX_RB_COLOR_INFO_FORMAT(enum a2xx_colorformatx val) A2XX_RB_COLOR_INFO_FORMAT() argument
596 return ((val) << A2XX_RB_COLOR_INFO_FORMAT__SHIFT) & A2XX_RB_COLOR_INFO_FORMAT__MASK; A2XX_RB_COLOR_INFO_FORMAT()
600 static inline uint32_t A2XX_RB_COLOR_INFO_ROUND_MODE(uint32_t val) A2XX_RB_COLOR_INFO_ROUND_MODE() argument
602 return ((val) << A2XX_RB_COLOR_INFO_ROUND_MODE__SHIFT) & A2XX_RB_COLOR_INFO_ROUND_MODE__MASK; A2XX_RB_COLOR_INFO_ROUND_MODE()
607 static inline uint32_t A2XX_RB_COLOR_INFO_ENDIAN(uint32_t val) A2XX_RB_COLOR_INFO_ENDIAN() argument
609 return ((val) << A2XX_RB_COLOR_INFO_ENDIAN__SHIFT) & A2XX_RB_COLOR_INFO_ENDIAN__MASK; A2XX_RB_COLOR_INFO_ENDIAN()
613 static inline uint32_t A2XX_RB_COLOR_INFO_SWAP(uint32_t val) A2XX_RB_COLOR_INFO_SWAP() argument
615 return ((val) << A2XX_RB_COLOR_INFO_SWAP__SHIFT) & A2XX_RB_COLOR_INFO_SWAP__MASK; A2XX_RB_COLOR_INFO_SWAP()
619 static inline uint32_t A2XX_RB_COLOR_INFO_BASE(uint32_t val) A2XX_RB_COLOR_INFO_BASE() argument
621 return ((val >> 10) << A2XX_RB_COLOR_INFO_BASE__SHIFT) & A2XX_RB_COLOR_INFO_BASE__MASK; A2XX_RB_COLOR_INFO_BASE()
627 static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_format val) A2XX_RB_DEPTH_INFO_DEPTH_FORMAT() argument
629 return ((val) << A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK; A2XX_RB_DEPTH_INFO_DEPTH_FORMAT()
633 static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) A2XX_RB_DEPTH_INFO_DEPTH_BASE() argument
635 return ((val >> 10) << A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK; A2XX_RB_DEPTH_INFO_DEPTH_BASE()
646 static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_TL_X(uint32_t val) A2XX_PA_SC_SCREEN_SCISSOR_TL_X() argument
648 return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_TL_X__MASK; A2XX_PA_SC_SCREEN_SCISSOR_TL_X()
652 static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) A2XX_PA_SC_SCREEN_SCISSOR_TL_Y() argument
654 return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__MASK; A2XX_PA_SC_SCREEN_SCISSOR_TL_Y()
661 static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_BR_X(uint32_t val) A2XX_PA_SC_SCREEN_SCISSOR_BR_X() argument
663 return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_BR_X__MASK; A2XX_PA_SC_SCREEN_SCISSOR_BR_X()
667 static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) A2XX_PA_SC_SCREEN_SCISSOR_BR_Y() argument
669 return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__MASK; A2XX_PA_SC_SCREEN_SCISSOR_BR_Y()
675 static inline uint32_t A2XX_PA_SC_WINDOW_OFFSET_X(int32_t val) A2XX_PA_SC_WINDOW_OFFSET_X() argument
677 return ((val) << A2XX_PA_SC_WINDOW_OFFSET_X__SHIFT) & A2XX_PA_SC_WINDOW_OFFSET_X__MASK; A2XX_PA_SC_WINDOW_OFFSET_X()
681 static inline uint32_t A2XX_PA_SC_WINDOW_OFFSET_Y(int32_t val) A2XX_PA_SC_WINDOW_OFFSET_Y() argument
683 return ((val) << A2XX_PA_SC_WINDOW_OFFSET_Y__SHIFT) & A2XX_PA_SC_WINDOW_OFFSET_Y__MASK; A2XX_PA_SC_WINDOW_OFFSET_Y()
691 static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_TL_X(uint32_t val) A2XX_PA_SC_WINDOW_SCISSOR_TL_X() argument
693 return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_TL_X__MASK; A2XX_PA_SC_WINDOW_SCISSOR_TL_X()
697 static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) A2XX_PA_SC_WINDOW_SCISSOR_TL_Y() argument
699 return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__MASK; A2XX_PA_SC_WINDOW_SCISSOR_TL_Y()
706 static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_X(uint32_t val) A2XX_PA_SC_WINDOW_SCISSOR_BR_X() argument
708 return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_BR_X__MASK; A2XX_PA_SC_WINDOW_SCISSOR_BR_X()
712 static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) A2XX_PA_SC_WINDOW_SCISSOR_BR_Y() argument
714 return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__MASK; A2XX_PA_SC_WINDOW_SCISSOR_BR_Y()
746 static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) A2XX_RB_STENCILREFMASK_BF_STENCILREF() argument
748 return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILREF__MASK; A2XX_RB_STENCILREFMASK_BF_STENCILREF()
752 static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) A2XX_RB_STENCILREFMASK_BF_STENCILMASK() argument
754 return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK; A2XX_RB_STENCILREFMASK_BF_STENCILMASK()
758 static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK() argument
760 return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK; A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK()
766 static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) A2XX_RB_STENCILREFMASK_STENCILREF() argument
768 return ((val) << A2XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILREF__MASK; A2XX_RB_STENCILREFMASK_STENCILREF()
772 static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) A2XX_RB_STENCILREFMASK_STENCILMASK() argument
774 return ((val) << A2XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILMASK__MASK; A2XX_RB_STENCILREFMASK_STENCILMASK()
778 static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) A2XX_RB_STENCILREFMASK_STENCILWRITEMASK() argument
780 return ((val) << A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK; A2XX_RB_STENCILREFMASK_STENCILWRITEMASK()
788 static inline uint32_t A2XX_PA_CL_VPORT_XSCALE(float val) A2XX_PA_CL_VPORT_XSCALE() argument
790 return ((fui(val)) << A2XX_PA_CL_VPORT_XSCALE__SHIFT) & A2XX_PA_CL_VPORT_XSCALE__MASK; A2XX_PA_CL_VPORT_XSCALE()
796 static inline uint32_t A2XX_PA_CL_VPORT_XOFFSET(float val) A2XX_PA_CL_VPORT_XOFFSET() argument
798 return ((fui(val)) << A2XX_PA_CL_VPORT_XOFFSET__SHIFT) & A2XX_PA_CL_VPORT_XOFFSET__MASK; A2XX_PA_CL_VPORT_XOFFSET()
804 static inline uint32_t A2XX_PA_CL_VPORT_YSCALE(float val) A2XX_PA_CL_VPORT_YSCALE() argument
806 return ((fui(val)) << A2XX_PA_CL_VPORT_YSCALE__SHIFT) & A2XX_PA_CL_VPORT_YSCALE__MASK; A2XX_PA_CL_VPORT_YSCALE()
812 static inline uint32_t A2XX_PA_CL_VPORT_YOFFSET(float val) A2XX_PA_CL_VPORT_YOFFSET() argument
814 return ((fui(val)) << A2XX_PA_CL_VPORT_YOFFSET__SHIFT) & A2XX_PA_CL_VPORT_YOFFSET__MASK; A2XX_PA_CL_VPORT_YOFFSET()
820 static inline uint32_t A2XX_PA_CL_VPORT_ZSCALE(float val) A2XX_PA_CL_VPORT_ZSCALE() argument
822 return ((fui(val)) << A2XX_PA_CL_VPORT_ZSCALE__SHIFT) & A2XX_PA_CL_VPORT_ZSCALE__MASK; A2XX_PA_CL_VPORT_ZSCALE()
828 static inline uint32_t A2XX_PA_CL_VPORT_ZOFFSET(float val) A2XX_PA_CL_VPORT_ZOFFSET() argument
830 return ((fui(val)) << A2XX_PA_CL_VPORT_ZOFFSET__SHIFT) & A2XX_PA_CL_VPORT_ZOFFSET__MASK; A2XX_PA_CL_VPORT_ZOFFSET()
836 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_REGS(uint32_t val) A2XX_SQ_PROGRAM_CNTL_VS_REGS() argument
838 return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_REGS__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_REGS__MASK; A2XX_SQ_PROGRAM_CNTL_VS_REGS()
842 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_PS_REGS(uint32_t val) A2XX_SQ_PROGRAM_CNTL_PS_REGS() argument
844 return ((val) << A2XX_SQ_PROGRAM_CNTL_PS_REGS__SHIFT) & A2XX_SQ_PROGRAM_CNTL_PS_REGS__MASK; A2XX_SQ_PROGRAM_CNTL_PS_REGS()
852 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT(uint32_t val) A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT() argument
854 return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__MASK; A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT()
858 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE(enum a2xx_sq_ps_vtx_mode val) A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE() argument
860 return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__MASK; A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE()
864 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE(uint32_t val) A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE() argument
866 return ((val) << A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__SHIFT) & A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__MASK; A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE()
875 static inline uint32_t A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL(enum a2xx_sq_sample_cntl val) A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL() argument
877 return ((val) << A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__SHIFT) & A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__MASK; A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL()
881 static inline uint32_t A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS(uint32_t val) A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS() argument
883 return ((val) << A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__SHIFT) & A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__MASK; A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS()
904 static inline uint32_t A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val) A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE() argument
906 return ((val) << A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK; A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE()
910 static inline uint32_t A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val) A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT() argument
912 return ((val) << A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK; A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT()
916 static inline uint32_t A2XX_VGT_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val) A2XX_VGT_DRAW_INITIATOR_VIS_CULL() argument
918 return ((val) << A2XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT) & A2XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK; A2XX_VGT_DRAW_INITIATOR_VIS_CULL()
922 static inline uint32_t A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE(enum pc_di_index_size val) A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE() argument
924 return ((val) << A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK; A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE()
931 static inline uint32_t A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES(uint32_t val) A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES() argument
933 return ((val) << A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT) & A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK; A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES()
945 static inline uint32_t A2XX_RB_DEPTHCONTROL_ZFUNC(enum adreno_compare_func val) A2XX_RB_DEPTHCONTROL_ZFUNC() argument
947 return ((val) << A2XX_RB_DEPTHCONTROL_ZFUNC__SHIFT) & A2XX_RB_DEPTHCONTROL_ZFUNC__MASK; A2XX_RB_DEPTHCONTROL_ZFUNC()
952 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFUNC(enum adreno_compare_func val) A2XX_RB_DEPTHCONTROL_STENCILFUNC() argument
954 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFUNC__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFUNC__MASK; A2XX_RB_DEPTHCONTROL_STENCILFUNC()
958 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFAIL(enum adreno_stencil_op val) A2XX_RB_DEPTHCONTROL_STENCILFAIL() argument
960 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFAIL__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFAIL__MASK; A2XX_RB_DEPTHCONTROL_STENCILFAIL()
964 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZPASS(enum adreno_stencil_op val) A2XX_RB_DEPTHCONTROL_STENCILZPASS() argument
966 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZPASS__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZPASS__MASK; A2XX_RB_DEPTHCONTROL_STENCILZPASS()
970 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZFAIL(enum adreno_stencil_op val) A2XX_RB_DEPTHCONTROL_STENCILZFAIL() argument
972 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZFAIL__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZFAIL__MASK; A2XX_RB_DEPTHCONTROL_STENCILZFAIL()
976 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF(enum adreno_compare_func val) A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF() argument
978 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__MASK; A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF()
982 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF(enum adreno_stencil_op val) A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF() argument
984 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__MASK; A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF()
988 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF(enum adreno_stencil_op val) A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF() argument
990 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__MASK; A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF()
994 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF(enum adreno_stencil_op val) A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF() argument
996 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__MASK; A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF()
1002 static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND(enum adreno_rb_blend_factor val) A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND() argument
1004 return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__MASK; A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND()
1008 static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN(enum a2xx_rb_blend_opcode val) A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN() argument
1010 return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK; A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN()
1014 static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND(enum adreno_rb_blend_factor val) A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND() argument
1016 return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__MASK; A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND()
1020 static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND(enum adreno_rb_blend_factor val) A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND() argument
1022 return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__MASK; A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND()
1026 static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN(enum a2xx_rb_blend_opcode val) A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN() argument
1028 return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK; A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN()
1032 static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND(enum adreno_rb_blend_factor val) A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND() argument
1034 return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__MASK; A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND()
1042 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_FUNC(enum adreno_compare_func val) A2XX_RB_COLORCONTROL_ALPHA_FUNC() argument
1044 return ((val) << A2XX_RB_COLORCONTROL_ALPHA_FUNC__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_FUNC__MASK; A2XX_RB_COLORCONTROL_ALPHA_FUNC()
1053 static inline uint32_t A2XX_RB_COLORCONTROL_ROP_CODE(uint32_t val) A2XX_RB_COLORCONTROL_ROP_CODE() argument
1055 return ((val) << A2XX_RB_COLORCONTROL_ROP_CODE__SHIFT) & A2XX_RB_COLORCONTROL_ROP_CODE__MASK; A2XX_RB_COLORCONTROL_ROP_CODE()
1059 static inline uint32_t A2XX_RB_COLORCONTROL_DITHER_MODE(enum adreno_rb_dither_mode val) A2XX_RB_COLORCONTROL_DITHER_MODE() argument
1061 return ((val) << A2XX_RB_COLORCONTROL_DITHER_MODE__SHIFT) & A2XX_RB_COLORCONTROL_DITHER_MODE__MASK; A2XX_RB_COLORCONTROL_DITHER_MODE()
1065 static inline uint32_t A2XX_RB_COLORCONTROL_DITHER_TYPE(enum a2xx_rb_dither_type val) A2XX_RB_COLORCONTROL_DITHER_TYPE() argument
1067 return ((val) << A2XX_RB_COLORCONTROL_DITHER_TYPE__SHIFT) & A2XX_RB_COLORCONTROL_DITHER_TYPE__MASK; A2XX_RB_COLORCONTROL_DITHER_TYPE()
1072 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0(uint32_t val) A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0() argument
1074 return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__MASK; A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0()
1078 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1(uint32_t val) A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1() argument
1080 return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__MASK; A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1()
1084 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2(uint32_t val) A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2() argument
1086 return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__MASK; A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2()
1090 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3(uint32_t val) A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3() argument
1092 return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__MASK; A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3()
1098 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN(uint32_t val) A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN() argument
1100 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__MASK; A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN()
1104 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_ROW(uint32_t val) A2XX_VGT_CURRENT_BIN_ID_MAX_ROW() argument
1106 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__MASK; A2XX_VGT_CURRENT_BIN_ID_MAX_ROW()
1110 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK(uint32_t val) A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK() argument
1112 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__MASK; A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK()
1120 static inline uint32_t A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF(enum a2xx_dx_clip_space val) A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF() argument
1122 return ((val) << A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__SHIFT) & A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__MASK; A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF()
1136 static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_POLYMODE(enum a2xx_pa_su_sc_polymode val) A2XX_PA_SU_SC_MODE_CNTL_POLYMODE() argument
1138 return ((val) << A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__MASK; A2XX_PA_SU_SC_MODE_CNTL_POLYMODE()
1142 static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(enum adreno_pa_su_sc_draw val) A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE() argument
1144 return ((val) << A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__MASK; A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE()
1148 static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(enum adreno_pa_su_sc_draw val) A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE() argument
1150 return ((val) << A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__MASK; A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE()
1184 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN(uint32_t val) A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN() argument
1186 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__MASK; A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN()
1190 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_ROW(uint32_t val) A2XX_VGT_CURRENT_BIN_ID_MIN_ROW() argument
1192 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__MASK; A2XX_VGT_CURRENT_BIN_ID_MIN_ROW()
1196 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK(uint32_t val) A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK() argument
1198 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__MASK; A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK()
1204 static inline uint32_t A2XX_RB_MODECONTROL_EDRAM_MODE(enum a2xx_rb_edram_mode val) A2XX_RB_MODECONTROL_EDRAM_MODE() argument
1206 return ((val) << A2XX_RB_MODECONTROL_EDRAM_MODE__SHIFT) & A2XX_RB_MODECONTROL_EDRAM_MODE__MASK; A2XX_RB_MODECONTROL_EDRAM_MODE()
1216 static inline uint32_t A2XX_CLEAR_COLOR_RED(uint32_t val) A2XX_CLEAR_COLOR_RED() argument
1218 return ((val) << A2XX_CLEAR_COLOR_RED__SHIFT) & A2XX_CLEAR_COLOR_RED__MASK; A2XX_CLEAR_COLOR_RED()
1222 static inline uint32_t A2XX_CLEAR_COLOR_GREEN(uint32_t val) A2XX_CLEAR_COLOR_GREEN() argument
1224 return ((val) << A2XX_CLEAR_COLOR_GREEN__SHIFT) & A2XX_CLEAR_COLOR_GREEN__MASK; A2XX_CLEAR_COLOR_GREEN()
1228 static inline uint32_t A2XX_CLEAR_COLOR_BLUE(uint32_t val) A2XX_CLEAR_COLOR_BLUE() argument
1230 return ((val) << A2XX_CLEAR_COLOR_BLUE__SHIFT) & A2XX_CLEAR_COLOR_BLUE__MASK; A2XX_CLEAR_COLOR_BLUE()
1234 static inline uint32_t A2XX_CLEAR_COLOR_ALPHA(uint32_t val) A2XX_CLEAR_COLOR_ALPHA() argument
1236 return ((val) << A2XX_CLEAR_COLOR_ALPHA__SHIFT) & A2XX_CLEAR_COLOR_ALPHA__MASK; A2XX_CLEAR_COLOR_ALPHA()
1244 static inline uint32_t A2XX_PA_SU_POINT_SIZE_HEIGHT(float val) A2XX_PA_SU_POINT_SIZE_HEIGHT() argument
1246 return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_SIZE_HEIGHT__SHIFT) & A2XX_PA_SU_POINT_SIZE_HEIGHT__MASK; A2XX_PA_SU_POINT_SIZE_HEIGHT()
1250 static inline uint32_t A2XX_PA_SU_POINT_SIZE_WIDTH(float val) A2XX_PA_SU_POINT_SIZE_WIDTH() argument
1252 return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_SIZE_WIDTH__SHIFT) & A2XX_PA_SU_POINT_SIZE_WIDTH__MASK; A2XX_PA_SU_POINT_SIZE_WIDTH()
1258 static inline uint32_t A2XX_PA_SU_POINT_MINMAX_MIN(float val) A2XX_PA_SU_POINT_MINMAX_MIN() argument
1260 return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_MINMAX_MIN__SHIFT) & A2XX_PA_SU_POINT_MINMAX_MIN__MASK; A2XX_PA_SU_POINT_MINMAX_MIN()
1264 static inline uint32_t A2XX_PA_SU_POINT_MINMAX_MAX(float val) A2XX_PA_SU_POINT_MINMAX_MAX() argument
1266 return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_MINMAX_MAX__SHIFT) & A2XX_PA_SU_POINT_MINMAX_MAX__MASK; A2XX_PA_SU_POINT_MINMAX_MAX()
1272 static inline uint32_t A2XX_PA_SU_LINE_CNTL_WIDTH(float val) A2XX_PA_SU_LINE_CNTL_WIDTH() argument
1274 return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_LINE_CNTL_WIDTH__SHIFT) & A2XX_PA_SU_LINE_CNTL_WIDTH__MASK; A2XX_PA_SU_LINE_CNTL_WIDTH()
1280 static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN(uint32_t val) A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN() argument
1282 return ((val) << A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__MASK; A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN()
1286 static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT(uint32_t val) A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT() argument
1288 return ((val) << A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__MASK; A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT()
1292 static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER(enum a2xx_pa_sc_pattern_bit_order val) A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER() argument
1294 return ((val) << A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__MASK; A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER()
1298 static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL(enum a2xx_pa_sc_auto_reset_cntl val) A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL() argument
1300 return ((val) << A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__MASK; A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL()
1310 static inline uint32_t A2XX_PA_SC_LINE_CNTL_BRES_CNTL(uint32_t val) A2XX_PA_SC_LINE_CNTL_BRES_CNTL() argument
1312 return ((val) << A2XX_PA_SC_LINE_CNTL_BRES_CNTL__SHIFT) & A2XX_PA_SC_LINE_CNTL_BRES_CNTL__MASK; A2XX_PA_SC_LINE_CNTL_BRES_CNTL()
1323 static inline uint32_t A2XX_PA_SU_VTX_CNTL_PIX_CENTER(enum a2xx_pa_pixcenter val) A2XX_PA_SU_VTX_CNTL_PIX_CENTER() argument
1325 return ((val) << A2XX_PA_SU_VTX_CNTL_PIX_CENTER__SHIFT) & A2XX_PA_SU_VTX_CNTL_PIX_CENTER__MASK; A2XX_PA_SU_VTX_CNTL_PIX_CENTER()
1329 static inline uint32_t A2XX_PA_SU_VTX_CNTL_ROUND_MODE(enum a2xx_pa_roundmode val) A2XX_PA_SU_VTX_CNTL_ROUND_MODE() argument
1331 return ((val) << A2XX_PA_SU_VTX_CNTL_ROUND_MODE__SHIFT) & A2XX_PA_SU_VTX_CNTL_ROUND_MODE__MASK; A2XX_PA_SU_VTX_CNTL_ROUND_MODE()
1335 static inline uint32_t A2XX_PA_SU_VTX_CNTL_QUANT_MODE(enum a2xx_pa_quantmode val) A2XX_PA_SU_VTX_CNTL_QUANT_MODE() argument
1337 return ((val) << A2XX_PA_SU_VTX_CNTL_QUANT_MODE__SHIFT) & A2XX_PA_SU_VTX_CNTL_QUANT_MODE__MASK; A2XX_PA_SU_VTX_CNTL_QUANT_MODE()
1343 static inline uint32_t A2XX_PA_CL_GB_VERT_CLIP_ADJ(float val) A2XX_PA_CL_GB_VERT_CLIP_ADJ() argument
1345 return ((fui(val)) << A2XX_PA_CL_GB_VERT_CLIP_ADJ__SHIFT) & A2XX_PA_CL_GB_VERT_CLIP_ADJ__MASK; A2XX_PA_CL_GB_VERT_CLIP_ADJ()
1351 static inline uint32_t A2XX_PA_CL_GB_VERT_DISC_ADJ(float val) A2XX_PA_CL_GB_VERT_DISC_ADJ() argument
1353 return ((fui(val)) << A2XX_PA_CL_GB_VERT_DISC_ADJ__SHIFT) & A2XX_PA_CL_GB_VERT_DISC_ADJ__MASK; A2XX_PA_CL_GB_VERT_DISC_ADJ()
1359 static inline uint32_t A2XX_PA_CL_GB_HORZ_CLIP_ADJ(float val) A2XX_PA_CL_GB_HORZ_CLIP_ADJ() argument
1361 return ((fui(val)) << A2XX_PA_CL_GB_HORZ_CLIP_ADJ__SHIFT) & A2XX_PA_CL_GB_HORZ_CLIP_ADJ__MASK; A2XX_PA_CL_GB_HORZ_CLIP_ADJ()
1367 static inline uint32_t A2XX_PA_CL_GB_HORZ_DISC_ADJ(float val) A2XX_PA_CL_GB_HORZ_DISC_ADJ() argument
1369 return ((fui(val)) << A2XX_PA_CL_GB_HORZ_DISC_ADJ__SHIFT) & A2XX_PA_CL_GB_HORZ_DISC_ADJ__MASK; A2XX_PA_CL_GB_HORZ_DISC_ADJ()
1375 static inline uint32_t A2XX_SQ_VS_CONST_BASE(uint32_t val) A2XX_SQ_VS_CONST_BASE() argument
1377 return ((val) << A2XX_SQ_VS_CONST_BASE__SHIFT) & A2XX_SQ_VS_CONST_BASE__MASK; A2XX_SQ_VS_CONST_BASE()
1381 static inline uint32_t A2XX_SQ_VS_CONST_SIZE(uint32_t val) A2XX_SQ_VS_CONST_SIZE() argument
1383 return ((val) << A2XX_SQ_VS_CONST_SIZE__SHIFT) & A2XX_SQ_VS_CONST_SIZE__MASK; A2XX_SQ_VS_CONST_SIZE()
1389 static inline uint32_t A2XX_SQ_PS_CONST_BASE(uint32_t val) A2XX_SQ_PS_CONST_BASE() argument
1391 return ((val) << A2XX_SQ_PS_CONST_BASE__SHIFT) & A2XX_SQ_PS_CONST_BASE__MASK; A2XX_SQ_PS_CONST_BASE()
1395 static inline uint32_t A2XX_SQ_PS_CONST_SIZE(uint32_t val) A2XX_SQ_PS_CONST_SIZE() argument
1397 return ((val) << A2XX_SQ_PS_CONST_SIZE__SHIFT) & A2XX_SQ_PS_CONST_SIZE__MASK; A2XX_SQ_PS_CONST_SIZE()
1413 static inline uint32_t A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT(enum a2xx_rb_copy_sample_select val) A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT() argument
1415 return ((val) << A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__SHIFT) & A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__MASK; A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT()
1420 static inline uint32_t A2XX_RB_COPY_CONTROL_CLEAR_MASK(uint32_t val) A2XX_RB_COPY_CONTROL_CLEAR_MASK() argument
1422 return ((val) << A2XX_RB_COPY_CONTROL_CLEAR_MASK__SHIFT) & A2XX_RB_COPY_CONTROL_CLEAR_MASK__MASK; A2XX_RB_COPY_CONTROL_CLEAR_MASK()
1430 static inline uint32_t A2XX_RB_COPY_DEST_PITCH(uint32_t val) A2XX_RB_COPY_DEST_PITCH() argument
1432 return ((val >> 5) << A2XX_RB_COPY_DEST_PITCH__SHIFT) & A2XX_RB_COPY_DEST_PITCH__MASK; A2XX_RB_COPY_DEST_PITCH()
1438 static inline uint32_t A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN(enum adreno_rb_surface_endian val) A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN() argument
1440 return ((val) << A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__SHIFT) & A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__MASK; A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN()
1445 static inline uint32_t A2XX_RB_COPY_DEST_INFO_FORMAT(enum a2xx_colorformatx val) A2XX_RB_COPY_DEST_INFO_FORMAT() argument
1447 return ((val) << A2XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A2XX_RB_COPY_DEST_INFO_FORMAT__MASK; A2XX_RB_COPY_DEST_INFO_FORMAT()
1451 static inline uint32_t A2XX_RB_COPY_DEST_INFO_SWAP(uint32_t val) A2XX_RB_COPY_DEST_INFO_SWAP() argument
1453 return ((val) << A2XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A2XX_RB_COPY_DEST_INFO_SWAP__MASK; A2XX_RB_COPY_DEST_INFO_SWAP()
1457 static inline uint32_t A2XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) A2XX_RB_COPY_DEST_INFO_DITHER_MODE() argument
1459 return ((val) << A2XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A2XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK; A2XX_RB_COPY_DEST_INFO_DITHER_MODE()
1463 static inline uint32_t A2XX_RB_COPY_DEST_INFO_DITHER_TYPE(enum a2xx_rb_dither_type val) A2XX_RB_COPY_DEST_INFO_DITHER_TYPE() argument
1465 return ((val) << A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__SHIFT) & A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__MASK; A2XX_RB_COPY_DEST_INFO_DITHER_TYPE()
1475 static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_X(uint32_t val) A2XX_RB_COPY_DEST_OFFSET_X() argument
1477 return ((val) << A2XX_RB_COPY_DEST_OFFSET_X__SHIFT) & A2XX_RB_COPY_DEST_OFFSET_X__MASK; A2XX_RB_COPY_DEST_OFFSET_X()
1481 static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_Y(uint32_t val) A2XX_RB_COPY_DEST_OFFSET_Y() argument
1483 return ((val) << A2XX_RB_COPY_DEST_OFFSET_Y__SHIFT) & A2XX_RB_COPY_DEST_OFFSET_Y__MASK; A2XX_RB_COPY_DEST_OFFSET_Y()
1519 static inline uint32_t A2XX_SQ_TEX_0_CLAMP_X(enum sq_tex_clamp val) A2XX_SQ_TEX_0_CLAMP_X() argument
1521 return ((val) << A2XX_SQ_TEX_0_CLAMP_X__SHIFT) & A2XX_SQ_TEX_0_CLAMP_X__MASK; A2XX_SQ_TEX_0_CLAMP_X()
1525 static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Y(enum sq_tex_clamp val) A2XX_SQ_TEX_0_CLAMP_Y() argument
1527 return ((val) << A2XX_SQ_TEX_0_CLAMP_Y__SHIFT) & A2XX_SQ_TEX_0_CLAMP_Y__MASK; A2XX_SQ_TEX_0_CLAMP_Y()
1531 static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Z(enum sq_tex_clamp val) A2XX_SQ_TEX_0_CLAMP_Z() argument
1533 return ((val) << A2XX_SQ_TEX_0_CLAMP_Z__SHIFT) & A2XX_SQ_TEX_0_CLAMP_Z__MASK; A2XX_SQ_TEX_0_CLAMP_Z()
1537 static inline uint32_t A2XX_SQ_TEX_0_PITCH(uint32_t val) A2XX_SQ_TEX_0_PITCH() argument
1539 return ((val >> 5) << A2XX_SQ_TEX_0_PITCH__SHIFT) & A2XX_SQ_TEX_0_PITCH__MASK; A2XX_SQ_TEX_0_PITCH()
1547 static inline uint32_t A2XX_SQ_TEX_2_WIDTH(uint32_t val) A2XX_SQ_TEX_2_WIDTH() argument
1549 return ((val) << A2XX_SQ_TEX_2_WIDTH__SHIFT) & A2XX_SQ_TEX_2_WIDTH__MASK; A2XX_SQ_TEX_2_WIDTH()
1553 static inline uint32_t A2XX_SQ_TEX_2_HEIGHT(uint32_t val) A2XX_SQ_TEX_2_HEIGHT() argument
1555 return ((val) << A2XX_SQ_TEX_2_HEIGHT__SHIFT) & A2XX_SQ_TEX_2_HEIGHT__MASK; A2XX_SQ_TEX_2_HEIGHT()
1561 static inline uint32_t A2XX_SQ_TEX_3_SWIZ_X(enum sq_tex_swiz val) A2XX_SQ_TEX_3_SWIZ_X() argument
1563 return ((val) << A2XX_SQ_TEX_3_SWIZ_X__SHIFT) & A2XX_SQ_TEX_3_SWIZ_X__MASK; A2XX_SQ_TEX_3_SWIZ_X()
1567 static inline uint32_t A2XX_SQ_TEX_3_SWIZ_Y(enum sq_tex_swiz val) A2XX_SQ_TEX_3_SWIZ_Y() argument
1569 return ((val) << A2XX_SQ_TEX_3_SWIZ_Y__SHIFT) & A2XX_SQ_TEX_3_SWIZ_Y__MASK; A2XX_SQ_TEX_3_SWIZ_Y()
1573 static inline uint32_t A2XX_SQ_TEX_3_SWIZ_Z(enum sq_tex_swiz val) A2XX_SQ_TEX_3_SWIZ_Z() argument
1575 return ((val) << A2XX_SQ_TEX_3_SWIZ_Z__SHIFT) & A2XX_SQ_TEX_3_SWIZ_Z__MASK; A2XX_SQ_TEX_3_SWIZ_Z()
1579 static inline uint32_t A2XX_SQ_TEX_3_SWIZ_W(enum sq_tex_swiz val) A2XX_SQ_TEX_3_SWIZ_W() argument
1581 return ((val) << A2XX_SQ_TEX_3_SWIZ_W__SHIFT) & A2XX_SQ_TEX_3_SWIZ_W__MASK; A2XX_SQ_TEX_3_SWIZ_W()
1585 static inline uint32_t A2XX_SQ_TEX_3_XY_MAG_FILTER(enum sq_tex_filter val) A2XX_SQ_TEX_3_XY_MAG_FILTER() argument
1587 return ((val) << A2XX_SQ_TEX_3_XY_MAG_FILTER__SHIFT) & A2XX_SQ_TEX_3_XY_MAG_FILTER__MASK; A2XX_SQ_TEX_3_XY_MAG_FILTER()
1591 static inline uint32_t A2XX_SQ_TEX_3_XY_MIN_FILTER(enum sq_tex_filter val) A2XX_SQ_TEX_3_XY_MIN_FILTER() argument
1593 return ((val) << A2XX_SQ_TEX_3_XY_MIN_FILTER__SHIFT) & A2XX_SQ_TEX_3_XY_MIN_FILTER__MASK; A2XX_SQ_TEX_3_XY_MIN_FILTER()
H A Da3xx.xml.h660 static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val) A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ() argument
662 return ((val) << A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT) & A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK; A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ()
666 static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val) A3XX_GRAS_CL_GB_CLIP_ADJ_VERT() argument
668 return ((val) << A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT) & A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK; A3XX_GRAS_CL_GB_CLIP_ADJ_VERT()
674 static inline uint32_t A3XX_GRAS_CL_VPORT_XOFFSET(float val) A3XX_GRAS_CL_VPORT_XOFFSET() argument
676 return ((fui(val)) << A3XX_GRAS_CL_VPORT_XOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_XOFFSET__MASK; A3XX_GRAS_CL_VPORT_XOFFSET()
682 static inline uint32_t A3XX_GRAS_CL_VPORT_XSCALE(float val) A3XX_GRAS_CL_VPORT_XSCALE() argument
684 return ((fui(val)) << A3XX_GRAS_CL_VPORT_XSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_XSCALE__MASK; A3XX_GRAS_CL_VPORT_XSCALE()
690 static inline uint32_t A3XX_GRAS_CL_VPORT_YOFFSET(float val) A3XX_GRAS_CL_VPORT_YOFFSET() argument
692 return ((fui(val)) << A3XX_GRAS_CL_VPORT_YOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_YOFFSET__MASK; A3XX_GRAS_CL_VPORT_YOFFSET()
698 static inline uint32_t A3XX_GRAS_CL_VPORT_YSCALE(float val) A3XX_GRAS_CL_VPORT_YSCALE() argument
700 return ((fui(val)) << A3XX_GRAS_CL_VPORT_YSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_YSCALE__MASK; A3XX_GRAS_CL_VPORT_YSCALE()
706 static inline uint32_t A3XX_GRAS_CL_VPORT_ZOFFSET(float val) A3XX_GRAS_CL_VPORT_ZOFFSET() argument
708 return ((fui(val)) << A3XX_GRAS_CL_VPORT_ZOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_ZOFFSET__MASK; A3XX_GRAS_CL_VPORT_ZOFFSET()
714 static inline uint32_t A3XX_GRAS_CL_VPORT_ZSCALE(float val) A3XX_GRAS_CL_VPORT_ZSCALE() argument
716 return ((fui(val)) << A3XX_GRAS_CL_VPORT_ZSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_ZSCALE__MASK; A3XX_GRAS_CL_VPORT_ZSCALE()
722 static inline uint32_t A3XX_GRAS_SU_POINT_MINMAX_MIN(float val) A3XX_GRAS_SU_POINT_MINMAX_MIN() argument
724 return ((((uint32_t)(val * 16.0))) << A3XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A3XX_GRAS_SU_POINT_MINMAX_MIN__MASK; A3XX_GRAS_SU_POINT_MINMAX_MIN()
728 static inline uint32_t A3XX_GRAS_SU_POINT_MINMAX_MAX(float val) A3XX_GRAS_SU_POINT_MINMAX_MAX() argument
730 return ((((uint32_t)(val * 16.0))) << A3XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A3XX_GRAS_SU_POINT_MINMAX_MAX__MASK; A3XX_GRAS_SU_POINT_MINMAX_MAX()
736 static inline uint32_t A3XX_GRAS_SU_POINT_SIZE(float val) A3XX_GRAS_SU_POINT_SIZE() argument
738 return ((((int32_t)(val * 16.0))) << A3XX_GRAS_SU_POINT_SIZE__SHIFT) & A3XX_GRAS_SU_POINT_SIZE__MASK; A3XX_GRAS_SU_POINT_SIZE()
744 static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL(float val) A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL() argument
746 return ((((int32_t)(val * 16384.0))) << A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__SHIFT) & A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__MASK; A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL()
752 static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) A3XX_GRAS_SU_POLY_OFFSET_OFFSET() argument
754 return ((((int32_t)(val * 16384.0))) << A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A3XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK; A3XX_GRAS_SU_POLY_OFFSET_OFFSET()
763 static inline uint32_t A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val) A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH() argument
765 return ((((int32_t)(val * 4.0))) << A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT) & A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK; A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH()
772 static inline uint32_t A3XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val) A3XX_GRAS_SC_CONTROL_RENDER_MODE() argument
774 return ((val) << A3XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT) & A3XX_GRAS_SC_CONTROL_RENDER_MODE__MASK; A3XX_GRAS_SC_CONTROL_RENDER_MODE()
778 static inline uint32_t A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(enum a3xx_msaa_samples val) A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES() argument
780 return ((val) << A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT) & A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK; A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES()
784 static inline uint32_t A3XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val) A3XX_GRAS_SC_CONTROL_RASTER_MODE() argument
786 return ((val) << A3XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT) & A3XX_GRAS_SC_CONTROL_RASTER_MODE__MASK; A3XX_GRAS_SC_CONTROL_RASTER_MODE()
793 static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val) A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X() argument
795 return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK; A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X()
799 static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y() argument
801 return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK; A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y()
808 static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val) A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X() argument
810 return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK; A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X()
814 static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y() argument
816 return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK; A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y()
823 static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val) A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X() argument
825 return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK; A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X()
829 static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y() argument
831 return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK; A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y()
838 static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val) A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X() argument
840 return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK; A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X()
844 static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y() argument
846 return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK; A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y()
853 static inline uint32_t A3XX_RB_MODE_CONTROL_RENDER_MODE(enum a3xx_render_mode val) A3XX_RB_MODE_CONTROL_RENDER_MODE() argument
855 return ((val) << A3XX_RB_MODE_CONTROL_RENDER_MODE__SHIFT) & A3XX_RB_MODE_CONTROL_RENDER_MODE__MASK; A3XX_RB_MODE_CONTROL_RENDER_MODE()
864 static inline uint32_t A3XX_RB_RENDER_CONTROL_BIN_WIDTH(uint32_t val) A3XX_RB_RENDER_CONTROL_BIN_WIDTH() argument
866 return ((val >> 5) << A3XX_RB_RENDER_CONTROL_BIN_WIDTH__SHIFT) & A3XX_RB_RENDER_CONTROL_BIN_WIDTH__MASK; A3XX_RB_RENDER_CONTROL_BIN_WIDTH()
877 static inline uint32_t A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val) A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC() argument
879 return ((val) << A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__MASK; A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC()
886 static inline uint32_t A3XX_RB_MSAA_CONTROL_SAMPLES(enum a3xx_msaa_samples val) A3XX_RB_MSAA_CONTROL_SAMPLES() argument
888 return ((val) << A3XX_RB_MSAA_CONTROL_SAMPLES__SHIFT) & A3XX_RB_MSAA_CONTROL_SAMPLES__MASK; A3XX_RB_MSAA_CONTROL_SAMPLES()
892 static inline uint32_t A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(uint32_t val) A3XX_RB_MSAA_CONTROL_SAMPLE_MASK() argument
894 return ((val) << A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__SHIFT) & A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__MASK; A3XX_RB_MSAA_CONTROL_SAMPLE_MASK()
900 static inline uint32_t A3XX_RB_ALPHA_REF_UINT(uint32_t val) A3XX_RB_ALPHA_REF_UINT() argument
902 return ((val) << A3XX_RB_ALPHA_REF_UINT__SHIFT) & A3XX_RB_ALPHA_REF_UINT__MASK; A3XX_RB_ALPHA_REF_UINT()
906 static inline uint32_t A3XX_RB_ALPHA_REF_FLOAT(float val) A3XX_RB_ALPHA_REF_FLOAT() argument
908 return ((util_float_to_half(val)) << A3XX_RB_ALPHA_REF_FLOAT__SHIFT) & A3XX_RB_ALPHA_REF_FLOAT__MASK; A3XX_RB_ALPHA_REF_FLOAT()
919 static inline uint32_t A3XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val) A3XX_RB_MRT_CONTROL_ROP_CODE() argument
921 return ((val) << A3XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A3XX_RB_MRT_CONTROL_ROP_CODE__MASK; A3XX_RB_MRT_CONTROL_ROP_CODE()
925 static inline uint32_t A3XX_RB_MRT_CONTROL_DITHER_MODE(enum adreno_rb_dither_mode val) A3XX_RB_MRT_CONTROL_DITHER_MODE() argument
927 return ((val) << A3XX_RB_MRT_CONTROL_DITHER_MODE__SHIFT) & A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK; A3XX_RB_MRT_CONTROL_DITHER_MODE()
931 static inline uint32_t A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE() argument
933 return ((val) << A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK; A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE()
939 static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a3xx_color_fmt val) A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT() argument
941 return ((val) << A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK; A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT()
945 static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a3xx_tile_mode val) A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE() argument
947 return ((val) << A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK; A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE()
951 static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) A3XX_RB_MRT_BUF_INFO_COLOR_SWAP() argument
953 return ((val) << A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK; A3XX_RB_MRT_BUF_INFO_COLOR_SWAP()
958 static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val) A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH() argument
960 return ((val >> 5) << A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK; A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH()
966 static inline uint32_t A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE(uint32_t val) A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE() argument
968 return ((val >> 5) << A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__SHIFT) & A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__MASK; A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE()
974 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val) A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR() argument
976 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK; A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR()
980 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE() argument
982 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK; A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE()
986 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val) A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR() argument
988 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK; A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR()
992 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val) A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR() argument
994 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK; A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR()
998 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE() argument
1000 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK; A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE()
1004 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val) A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR() argument
1006 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK; A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR()
1013 static inline uint32_t A3XX_RB_BLEND_RED_UINT(uint32_t val) A3XX_RB_BLEND_RED_UINT() argument
1015 return ((val) << A3XX_RB_BLEND_RED_UINT__SHIFT) & A3XX_RB_BLEND_RED_UINT__MASK; A3XX_RB_BLEND_RED_UINT()
1019 static inline uint32_t A3XX_RB_BLEND_RED_FLOAT(float val) A3XX_RB_BLEND_RED_FLOAT() argument
1021 return ((util_float_to_half(val)) << A3XX_RB_BLEND_RED_FLOAT__SHIFT) & A3XX_RB_BLEND_RED_FLOAT__MASK; A3XX_RB_BLEND_RED_FLOAT()
1027 static inline uint32_t A3XX_RB_BLEND_GREEN_UINT(uint32_t val) A3XX_RB_BLEND_GREEN_UINT() argument
1029 return ((val) << A3XX_RB_BLEND_GREEN_UINT__SHIFT) & A3XX_RB_BLEND_GREEN_UINT__MASK; A3XX_RB_BLEND_GREEN_UINT()
1033 static inline uint32_t A3XX_RB_BLEND_GREEN_FLOAT(float val) A3XX_RB_BLEND_GREEN_FLOAT() argument
1035 return ((util_float_to_half(val)) << A3XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A3XX_RB_BLEND_GREEN_FLOAT__MASK; A3XX_RB_BLEND_GREEN_FLOAT()
1041 static inline uint32_t A3XX_RB_BLEND_BLUE_UINT(uint32_t val) A3XX_RB_BLEND_BLUE_UINT() argument
1043 return ((val) << A3XX_RB_BLEND_BLUE_UINT__SHIFT) & A3XX_RB_BLEND_BLUE_UINT__MASK; A3XX_RB_BLEND_BLUE_UINT()
1047 static inline uint32_t A3XX_RB_BLEND_BLUE_FLOAT(float val) A3XX_RB_BLEND_BLUE_FLOAT() argument
1049 return ((util_float_to_half(val)) << A3XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A3XX_RB_BLEND_BLUE_FLOAT__MASK; A3XX_RB_BLEND_BLUE_FLOAT()
1055 static inline uint32_t A3XX_RB_BLEND_ALPHA_UINT(uint32_t val) A3XX_RB_BLEND_ALPHA_UINT() argument
1057 return ((val) << A3XX_RB_BLEND_ALPHA_UINT__SHIFT) & A3XX_RB_BLEND_ALPHA_UINT__MASK; A3XX_RB_BLEND_ALPHA_UINT()
1061 static inline uint32_t A3XX_RB_BLEND_ALPHA_FLOAT(float val) A3XX_RB_BLEND_ALPHA_FLOAT() argument
1063 return ((util_float_to_half(val)) << A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A3XX_RB_BLEND_ALPHA_FLOAT__MASK; A3XX_RB_BLEND_ALPHA_FLOAT()
1077 static inline uint32_t A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(enum a3xx_msaa_samples val) A3XX_RB_COPY_CONTROL_MSAA_RESOLVE() argument
1079 return ((val) << A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT) & A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK; A3XX_RB_COPY_CONTROL_MSAA_RESOLVE()
1084 static inline uint32_t A3XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val) A3XX_RB_COPY_CONTROL_MODE() argument
1086 return ((val) << A3XX_RB_COPY_CONTROL_MODE__SHIFT) & A3XX_RB_COPY_CONTROL_MODE__MASK; A3XX_RB_COPY_CONTROL_MODE()
1090 static inline uint32_t A3XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val) A3XX_RB_COPY_CONTROL_FASTCLEAR() argument
1092 return ((val) << A3XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT) & A3XX_RB_COPY_CONTROL_FASTCLEAR__MASK; A3XX_RB_COPY_CONTROL_FASTCLEAR()
1097 static inline uint32_t A3XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val) A3XX_RB_COPY_CONTROL_GMEM_BASE() argument
1099 return ((val >> 14) << A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT) & A3XX_RB_COPY_CONTROL_GMEM_BASE__MASK; A3XX_RB_COPY_CONTROL_GMEM_BASE()
1105 static inline uint32_t A3XX_RB_COPY_DEST_BASE_BASE(uint32_t val) A3XX_RB_COPY_DEST_BASE_BASE() argument
1107 return ((val >> 5) << A3XX_RB_COPY_DEST_BASE_BASE__SHIFT) & A3XX_RB_COPY_DEST_BASE_BASE__MASK; A3XX_RB_COPY_DEST_BASE_BASE()
1113 static inline uint32_t A3XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val) A3XX_RB_COPY_DEST_PITCH_PITCH() argument
1115 return ((val >> 5) << A3XX_RB_COPY_DEST_PITCH_PITCH__SHIFT) & A3XX_RB_COPY_DEST_PITCH_PITCH__MASK; A3XX_RB_COPY_DEST_PITCH_PITCH()
1121 static inline uint32_t A3XX_RB_COPY_DEST_INFO_TILE(enum a3xx_tile_mode val) A3XX_RB_COPY_DEST_INFO_TILE() argument
1123 return ((val) << A3XX_RB_COPY_DEST_INFO_TILE__SHIFT) & A3XX_RB_COPY_DEST_INFO_TILE__MASK; A3XX_RB_COPY_DEST_INFO_TILE()
1127 static inline uint32_t A3XX_RB_COPY_DEST_INFO_FORMAT(enum a3xx_color_fmt val) A3XX_RB_COPY_DEST_INFO_FORMAT() argument
1129 return ((val) << A3XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A3XX_RB_COPY_DEST_INFO_FORMAT__MASK; A3XX_RB_COPY_DEST_INFO_FORMAT()
1133 static inline uint32_t A3XX_RB_COPY_DEST_INFO_SWAP(enum a3xx_color_swap val) A3XX_RB_COPY_DEST_INFO_SWAP() argument
1135 return ((val) << A3XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A3XX_RB_COPY_DEST_INFO_SWAP__MASK; A3XX_RB_COPY_DEST_INFO_SWAP()
1139 static inline uint32_t A3XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) A3XX_RB_COPY_DEST_INFO_DITHER_MODE() argument
1141 return ((val) << A3XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A3XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK; A3XX_RB_COPY_DEST_INFO_DITHER_MODE()
1145 static inline uint32_t A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val) A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE() argument
1147 return ((val) << A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT) & A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK; A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE()
1151 static inline uint32_t A3XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endian val) A3XX_RB_COPY_DEST_INFO_ENDIAN() argument
1153 return ((val) << A3XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT) & A3XX_RB_COPY_DEST_INFO_ENDIAN__MASK; A3XX_RB_COPY_DEST_INFO_ENDIAN()
1163 static inline uint32_t A3XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val) A3XX_RB_DEPTH_CONTROL_ZFUNC() argument
1165 return ((val) << A3XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT) & A3XX_RB_DEPTH_CONTROL_ZFUNC__MASK; A3XX_RB_DEPTH_CONTROL_ZFUNC()
1175 static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_format val) A3XX_RB_DEPTH_INFO_DEPTH_FORMAT() argument
1177 return ((val) << A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK; A3XX_RB_DEPTH_INFO_DEPTH_FORMAT()
1181 static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) A3XX_RB_DEPTH_INFO_DEPTH_BASE() argument
1183 return ((val >> 12) << A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A3XX_RB_DEPTH_INFO_DEPTH_BASE__MASK; A3XX_RB_DEPTH_INFO_DEPTH_BASE()
1189 static inline uint32_t A3XX_RB_DEPTH_PITCH(uint32_t val) A3XX_RB_DEPTH_PITCH() argument
1191 return ((val >> 3) << A3XX_RB_DEPTH_PITCH__SHIFT) & A3XX_RB_DEPTH_PITCH__MASK; A3XX_RB_DEPTH_PITCH()
1200 static inline uint32_t A3XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val) A3XX_RB_STENCIL_CONTROL_FUNC() argument
1202 return ((val) << A3XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A3XX_RB_STENCIL_CONTROL_FUNC__MASK; A3XX_RB_STENCIL_CONTROL_FUNC()
1206 static inline uint32_t A3XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val) A3XX_RB_STENCIL_CONTROL_FAIL() argument
1208 return ((val) << A3XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A3XX_RB_STENCIL_CONTROL_FAIL__MASK; A3XX_RB_STENCIL_CONTROL_FAIL()
1212 static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val) A3XX_RB_STENCIL_CONTROL_ZPASS() argument
1214 return ((val) << A3XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZPASS__MASK; A3XX_RB_STENCIL_CONTROL_ZPASS()
1218 static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val) A3XX_RB_STENCIL_CONTROL_ZFAIL() argument
1220 return ((val) << A3XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZFAIL__MASK; A3XX_RB_STENCIL_CONTROL_ZFAIL()
1224 static inline uint32_t A3XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val) A3XX_RB_STENCIL_CONTROL_FUNC_BF() argument
1226 return ((val) << A3XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_FUNC_BF__MASK; A3XX_RB_STENCIL_CONTROL_FUNC_BF()
1230 static inline uint32_t A3XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val) A3XX_RB_STENCIL_CONTROL_FAIL_BF() argument
1232 return ((val) << A3XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_FAIL_BF__MASK; A3XX_RB_STENCIL_CONTROL_FAIL_BF()
1236 static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val) A3XX_RB_STENCIL_CONTROL_ZPASS_BF() argument
1238 return ((val) << A3XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK; A3XX_RB_STENCIL_CONTROL_ZPASS_BF()
1242 static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val) A3XX_RB_STENCIL_CONTROL_ZFAIL_BF() argument
1244 return ((val) << A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK; A3XX_RB_STENCIL_CONTROL_ZFAIL_BF()
1256 static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) A3XX_RB_STENCILREFMASK_STENCILREF() argument
1258 return ((val) << A3XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A3XX_RB_STENCILREFMASK_STENCILREF__MASK; A3XX_RB_STENCILREFMASK_STENCILREF()
1262 static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) A3XX_RB_STENCILREFMASK_STENCILMASK() argument
1264 return ((val) << A3XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A3XX_RB_STENCILREFMASK_STENCILMASK__MASK; A3XX_RB_STENCILREFMASK_STENCILMASK()
1268 static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) A3XX_RB_STENCILREFMASK_STENCILWRITEMASK() argument
1270 return ((val) << A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK; A3XX_RB_STENCILREFMASK_STENCILWRITEMASK()
1276 static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) A3XX_RB_STENCILREFMASK_BF_STENCILREF() argument
1278 return ((val) << A3XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A3XX_RB_STENCILREFMASK_BF_STENCILREF__MASK; A3XX_RB_STENCILREFMASK_BF_STENCILREF()
1282 static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) A3XX_RB_STENCILREFMASK_BF_STENCILMASK() argument
1284 return ((val) << A3XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A3XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK; A3XX_RB_STENCILREFMASK_BF_STENCILMASK()
1288 static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK() argument
1290 return ((val) << A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK; A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK()
1299 static inline uint32_t A3XX_RB_WINDOW_OFFSET_X(uint32_t val) A3XX_RB_WINDOW_OFFSET_X() argument
1301 return ((val) << A3XX_RB_WINDOW_OFFSET_X__SHIFT) & A3XX_RB_WINDOW_OFFSET_X__MASK; A3XX_RB_WINDOW_OFFSET_X()
1305 static inline uint32_t A3XX_RB_WINDOW_OFFSET_Y(uint32_t val) A3XX_RB_WINDOW_OFFSET_Y() argument
1307 return ((val) << A3XX_RB_WINDOW_OFFSET_Y__SHIFT) & A3XX_RB_WINDOW_OFFSET_Y__MASK; A3XX_RB_WINDOW_OFFSET_Y()
1327 static inline uint32_t A3XX_PC_VSTREAM_CONTROL_SIZE(uint32_t val) A3XX_PC_VSTREAM_CONTROL_SIZE() argument
1329 return ((val) << A3XX_PC_VSTREAM_CONTROL_SIZE__SHIFT) & A3XX_PC_VSTREAM_CONTROL_SIZE__MASK; A3XX_PC_VSTREAM_CONTROL_SIZE()
1333 static inline uint32_t A3XX_PC_VSTREAM_CONTROL_N(uint32_t val) A3XX_PC_VSTREAM_CONTROL_N() argument
1335 return ((val) << A3XX_PC_VSTREAM_CONTROL_N__SHIFT) & A3XX_PC_VSTREAM_CONTROL_N__MASK; A3XX_PC_VSTREAM_CONTROL_N()
1343 static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(uint32_t val) A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC() argument
1345 return ((val) << A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__SHIFT) & A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__MASK; A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC()
1349 static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val) A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE() argument
1351 return ((val) << A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__SHIFT) & A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__MASK; A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE()
1355 static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val) A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE() argument
1357 return ((val) << A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__SHIFT) & A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__MASK; A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE()
1368 static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val) A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE() argument
1370 return ((val) << A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK; A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE()
1378 static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_CONSTMODE(uint32_t val) A3XX_HLSQ_CONTROL_0_REG_CONSTMODE() argument
1380 return ((val) << A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT) & A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK; A3XX_HLSQ_CONTROL_0_REG_CONSTMODE()
1390 static inline uint32_t A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val) A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE() argument
1392 return ((val) << A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT) & A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK; A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE()
1401 static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val) A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD() argument
1403 return ((val) << A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT) & A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK; A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD()
1409 static inline uint32_t A3XX_HLSQ_CONTROL_3_REG_REGID(uint32_t val) A3XX_HLSQ_CONTROL_3_REG_REGID() argument
1411 return ((val) << A3XX_HLSQ_CONTROL_3_REG_REGID__SHIFT) & A3XX_HLSQ_CONTROL_3_REG_REGID__MASK; A3XX_HLSQ_CONTROL_3_REG_REGID()
1417 static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val) A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH() argument
1419 return ((val) << A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK; A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH()
1423 static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val) A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET() argument
1425 return ((val) << A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__MASK; A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET()
1429 static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val) A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH() argument
1431 return ((val) << A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK; A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH()
1437 static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val) A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH() argument
1439 return ((val) << A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK; A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH()
1443 static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val) A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET() argument
1445 return ((val) << A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__MASK; A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET()
1449 static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val) A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH() argument
1451 return ((val) << A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK; A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH()
1457 static inline uint32_t A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(uint32_t val) A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY() argument
1459 return ((val) << A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__SHIFT) & A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__MASK; A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY()
1463 static inline uint32_t A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(uint32_t val) A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY() argument
1465 return ((val) << A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__SHIFT) & A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__MASK; A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY()
1471 static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(uint32_t val) A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY() argument
1473 return ((val) << A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__SHIFT) & A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__MASK; A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY()
1477 static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(uint32_t val) A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY() argument
1479 return ((val) << A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__SHIFT) & A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__MASK; A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY()
1485 static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM(uint32_t val) A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM() argument
1487 return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__MASK; A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM()
1491 static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0(uint32_t val) A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0() argument
1493 return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__MASK; A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0()
1497 static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1(uint32_t val) A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1() argument
1499 return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__MASK; A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1()
1503 static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2(uint32_t val) A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2() argument
1505 return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__MASK; A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2()
1533 static inline uint32_t A3XX_VFD_CONTROL_0_TOTALATTRTOVS(uint32_t val) A3XX_VFD_CONTROL_0_TOTALATTRTOVS() argument
1535 return ((val) << A3XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT) & A3XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK; A3XX_VFD_CONTROL_0_TOTALATTRTOVS()
1539 static inline uint32_t A3XX_VFD_CONTROL_0_PACKETSIZE(uint32_t val) A3XX_VFD_CONTROL_0_PACKETSIZE() argument
1541 return ((val) << A3XX_VFD_CONTROL_0_PACKETSIZE__SHIFT) & A3XX_VFD_CONTROL_0_PACKETSIZE__MASK; A3XX_VFD_CONTROL_0_PACKETSIZE()
1545 static inline uint32_t A3XX_VFD_CONTROL_0_STRMDECINSTRCNT(uint32_t val) A3XX_VFD_CONTROL_0_STRMDECINSTRCNT() argument
1547 return ((val) << A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT) & A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK; A3XX_VFD_CONTROL_0_STRMDECINSTRCNT()
1551 static inline uint32_t A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val) A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT() argument
1553 return ((val) << A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT) & A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK; A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT()
1559 static inline uint32_t A3XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val) A3XX_VFD_CONTROL_1_MAXSTORAGE() argument
1561 return ((val) << A3XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT) & A3XX_VFD_CONTROL_1_MAXSTORAGE__MASK; A3XX_VFD_CONTROL_1_MAXSTORAGE()
1565 static inline uint32_t A3XX_VFD_CONTROL_1_REGID4VTX(uint32_t val) A3XX_VFD_CONTROL_1_REGID4VTX() argument
1567 return ((val) << A3XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A3XX_VFD_CONTROL_1_REGID4VTX__MASK; A3XX_VFD_CONTROL_1_REGID4VTX()
1571 static inline uint32_t A3XX_VFD_CONTROL_1_REGID4INST(uint32_t val) A3XX_VFD_CONTROL_1_REGID4INST() argument
1573 return ((val) << A3XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A3XX_VFD_CONTROL_1_REGID4INST__MASK; A3XX_VFD_CONTROL_1_REGID4INST()
1591 static inline uint32_t A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(uint32_t val) A3XX_VFD_FETCH_INSTR_0_FETCHSIZE() argument
1593 return ((val) << A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK; A3XX_VFD_FETCH_INSTR_0_FETCHSIZE()
1597 static inline uint32_t A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val) A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE() argument
1599 return ((val) << A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK; A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE()
1605 static inline uint32_t A3XX_VFD_FETCH_INSTR_0_INDEXCODE(uint32_t val) A3XX_VFD_FETCH_INSTR_0_INDEXCODE() argument
1607 return ((val) << A3XX_VFD_FETCH_INSTR_0_INDEXCODE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_INDEXCODE__MASK; A3XX_VFD_FETCH_INSTR_0_INDEXCODE()
1611 static inline uint32_t A3XX_VFD_FETCH_INSTR_0_STEPRATE(uint32_t val) A3XX_VFD_FETCH_INSTR_0_STEPRATE() argument
1613 return ((val) << A3XX_VFD_FETCH_INSTR_0_STEPRATE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_STEPRATE__MASK; A3XX_VFD_FETCH_INSTR_0_STEPRATE()
1623 static inline uint32_t A3XX_VFD_DECODE_INSTR_WRITEMASK(uint32_t val) A3XX_VFD_DECODE_INSTR_WRITEMASK() argument
1625 return ((val) << A3XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT) & A3XX_VFD_DECODE_INSTR_WRITEMASK__MASK; A3XX_VFD_DECODE_INSTR_WRITEMASK()
1630 static inline uint32_t A3XX_VFD_DECODE_INSTR_FORMAT(enum a3xx_vtx_fmt val) A3XX_VFD_DECODE_INSTR_FORMAT() argument
1632 return ((val) << A3XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A3XX_VFD_DECODE_INSTR_FORMAT__MASK; A3XX_VFD_DECODE_INSTR_FORMAT()
1636 static inline uint32_t A3XX_VFD_DECODE_INSTR_REGID(uint32_t val) A3XX_VFD_DECODE_INSTR_REGID() argument
1638 return ((val) << A3XX_VFD_DECODE_INSTR_REGID__SHIFT) & A3XX_VFD_DECODE_INSTR_REGID__MASK; A3XX_VFD_DECODE_INSTR_REGID()
1643 static inline uint32_t A3XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val) A3XX_VFD_DECODE_INSTR_SWAP() argument
1645 return ((val) << A3XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A3XX_VFD_DECODE_INSTR_SWAP__MASK; A3XX_VFD_DECODE_INSTR_SWAP()
1649 static inline uint32_t A3XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val) A3XX_VFD_DECODE_INSTR_SHIFTCNT() argument
1651 return ((val) << A3XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT) & A3XX_VFD_DECODE_INSTR_SHIFTCNT__MASK; A3XX_VFD_DECODE_INSTR_SHIFTCNT()
1659 static inline uint32_t A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD(uint32_t val) A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD() argument
1661 return ((val) << A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__SHIFT) & A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__MASK; A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD()
1665 static inline uint32_t A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT(uint32_t val) A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT() argument
1667 return ((val) << A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__SHIFT) & A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__MASK; A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT()
1673 static inline uint32_t A3XX_VPC_ATTR_TOTALATTR(uint32_t val) A3XX_VPC_ATTR_TOTALATTR() argument
1675 return ((val) << A3XX_VPC_ATTR_TOTALATTR__SHIFT) & A3XX_VPC_ATTR_TOTALATTR__MASK; A3XX_VPC_ATTR_TOTALATTR()
1680 static inline uint32_t A3XX_VPC_ATTR_THRDASSIGN(uint32_t val) A3XX_VPC_ATTR_THRDASSIGN() argument
1682 return ((val) << A3XX_VPC_ATTR_THRDASSIGN__SHIFT) & A3XX_VPC_ATTR_THRDASSIGN__MASK; A3XX_VPC_ATTR_THRDASSIGN()
1686 static inline uint32_t A3XX_VPC_ATTR_LMSIZE(uint32_t val) A3XX_VPC_ATTR_LMSIZE() argument
1688 return ((val) << A3XX_VPC_ATTR_LMSIZE__SHIFT) & A3XX_VPC_ATTR_LMSIZE__MASK; A3XX_VPC_ATTR_LMSIZE()
1694 static inline uint32_t A3XX_VPC_PACK_NUMFPNONPOSVAR(uint32_t val) A3XX_VPC_PACK_NUMFPNONPOSVAR() argument
1696 return ((val) << A3XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT) & A3XX_VPC_PACK_NUMFPNONPOSVAR__MASK; A3XX_VPC_PACK_NUMFPNONPOSVAR()
1700 static inline uint32_t A3XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val) A3XX_VPC_PACK_NUMNONPOSVSVAR() argument
1702 return ((val) << A3XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT) & A3XX_VPC_PACK_NUMNONPOSVSVAR__MASK; A3XX_VPC_PACK_NUMNONPOSVSVAR()
1710 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C0(enum a3xx_intp_mode val) A3XX_VPC_VARYING_INTERP_MODE_C0() argument
1712 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C0__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C0__MASK; A3XX_VPC_VARYING_INTERP_MODE_C0()
1716 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C1(enum a3xx_intp_mode val) A3XX_VPC_VARYING_INTERP_MODE_C1() argument
1718 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C1__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C1__MASK; A3XX_VPC_VARYING_INTERP_MODE_C1()
1722 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C2(enum a3xx_intp_mode val) A3XX_VPC_VARYING_INTERP_MODE_C2() argument
1724 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C2__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C2__MASK; A3XX_VPC_VARYING_INTERP_MODE_C2()
1728 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C3(enum a3xx_intp_mode val) A3XX_VPC_VARYING_INTERP_MODE_C3() argument
1730 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C3__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C3__MASK; A3XX_VPC_VARYING_INTERP_MODE_C3()
1734 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C4(enum a3xx_intp_mode val) A3XX_VPC_VARYING_INTERP_MODE_C4() argument
1736 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C4__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C4__MASK; A3XX_VPC_VARYING_INTERP_MODE_C4()
1740 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C5(enum a3xx_intp_mode val) A3XX_VPC_VARYING_INTERP_MODE_C5() argument
1742 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C5__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C5__MASK; A3XX_VPC_VARYING_INTERP_MODE_C5()
1746 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C6(enum a3xx_intp_mode val) A3XX_VPC_VARYING_INTERP_MODE_C6() argument
1748 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C6__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C6__MASK; A3XX_VPC_VARYING_INTERP_MODE_C6()
1752 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C7(enum a3xx_intp_mode val) A3XX_VPC_VARYING_INTERP_MODE_C7() argument
1754 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C7__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C7__MASK; A3XX_VPC_VARYING_INTERP_MODE_C7()
1758 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C8(enum a3xx_intp_mode val) A3XX_VPC_VARYING_INTERP_MODE_C8() argument
1760 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C8__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C8__MASK; A3XX_VPC_VARYING_INTERP_MODE_C8()
1764 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C9(enum a3xx_intp_mode val) A3XX_VPC_VARYING_INTERP_MODE_C9() argument
1766 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C9__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C9__MASK; A3XX_VPC_VARYING_INTERP_MODE_C9()
1770 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CA(enum a3xx_intp_mode val) A3XX_VPC_VARYING_INTERP_MODE_CA() argument
1772 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CA__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CA__MASK; A3XX_VPC_VARYING_INTERP_MODE_CA()
1776 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CB(enum a3xx_intp_mode val) A3XX_VPC_VARYING_INTERP_MODE_CB() argument
1778 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CB__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CB__MASK; A3XX_VPC_VARYING_INTERP_MODE_CB()
1782 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CC(enum a3xx_intp_mode val) A3XX_VPC_VARYING_INTERP_MODE_CC() argument
1784 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CC__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CC__MASK; A3XX_VPC_VARYING_INTERP_MODE_CC()
1788 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CD(enum a3xx_intp_mode val) A3XX_VPC_VARYING_INTERP_MODE_CD() argument
1790 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CD__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CD__MASK; A3XX_VPC_VARYING_INTERP_MODE_CD()
1794 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CE(enum a3xx_intp_mode val) A3XX_VPC_VARYING_INTERP_MODE_CE() argument
1796 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CE__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CE__MASK; A3XX_VPC_VARYING_INTERP_MODE_CE()
1800 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CF(enum a3xx_intp_mode val) A3XX_VPC_VARYING_INTERP_MODE_CF() argument
1802 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CF__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CF__MASK; A3XX_VPC_VARYING_INTERP_MODE_CF()
1817 static inline uint32_t A3XX_SP_SP_CTRL_REG_CONSTMODE(uint32_t val) A3XX_SP_SP_CTRL_REG_CONSTMODE() argument
1819 return ((val) << A3XX_SP_SP_CTRL_REG_CONSTMODE__SHIFT) & A3XX_SP_SP_CTRL_REG_CONSTMODE__MASK; A3XX_SP_SP_CTRL_REG_CONSTMODE()
1824 static inline uint32_t A3XX_SP_SP_CTRL_REG_SLEEPMODE(uint32_t val) A3XX_SP_SP_CTRL_REG_SLEEPMODE() argument
1826 return ((val) << A3XX_SP_SP_CTRL_REG_SLEEPMODE__SHIFT) & A3XX_SP_SP_CTRL_REG_SLEEPMODE__MASK; A3XX_SP_SP_CTRL_REG_SLEEPMODE()
1830 static inline uint32_t A3XX_SP_SP_CTRL_REG_L0MODE(uint32_t val) A3XX_SP_SP_CTRL_REG_L0MODE() argument
1832 return ((val) << A3XX_SP_SP_CTRL_REG_L0MODE__SHIFT) & A3XX_SP_SP_CTRL_REG_L0MODE__MASK; A3XX_SP_SP_CTRL_REG_L0MODE()
1838 static inline uint32_t A3XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) A3XX_SP_VS_CTRL_REG0_THREADMODE() argument
1840 return ((val) << A3XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A3XX_SP_VS_CTRL_REG0_THREADMODE__MASK; A3XX_SP_VS_CTRL_REG0_THREADMODE()
1844 static inline uint32_t A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffermode val) A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE() argument
1846 return ((val) << A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__SHIFT) & A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__MASK; A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE()
1851 static inline uint32_t A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT() argument
1853 return ((val) << A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK; A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT()
1857 static inline uint32_t A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT() argument
1859 return ((val) << A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK; A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT()
1863 static inline uint32_t A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val) A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP() argument
1865 return ((val) << A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK; A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP()
1869 static inline uint32_t A3XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) A3XX_SP_VS_CTRL_REG0_THREADSIZE() argument
1871 return ((val) << A3XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A3XX_SP_VS_CTRL_REG0_THREADSIZE__MASK; A3XX_SP_VS_CTRL_REG0_THREADSIZE()
1878 static inline uint32_t A3XX_SP_VS_CTRL_REG0_LENGTH(uint32_t val) A3XX_SP_VS_CTRL_REG0_LENGTH() argument
1880 return ((val) << A3XX_SP_VS_CTRL_REG0_LENGTH__SHIFT) & A3XX_SP_VS_CTRL_REG0_LENGTH__MASK; A3XX_SP_VS_CTRL_REG0_LENGTH()
1886 static inline uint32_t A3XX_SP_VS_CTRL_REG1_CONSTLENGTH(uint32_t val) A3XX_SP_VS_CTRL_REG1_CONSTLENGTH() argument
1888 return ((val) << A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT) & A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK; A3XX_SP_VS_CTRL_REG1_CONSTLENGTH()
1892 static inline uint32_t A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT(uint32_t val) A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT() argument
1894 return ((val) << A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__MASK; A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT()
1898 static inline uint32_t A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val) A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING() argument
1900 return ((val) << A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK; A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING()
1906 static inline uint32_t A3XX_SP_VS_PARAM_REG_POSREGID(uint32_t val) A3XX_SP_VS_PARAM_REG_POSREGID() argument
1908 return ((val) << A3XX_SP_VS_PARAM_REG_POSREGID__SHIFT) & A3XX_SP_VS_PARAM_REG_POSREGID__MASK; A3XX_SP_VS_PARAM_REG_POSREGID()
1912 static inline uint32_t A3XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val) A3XX_SP_VS_PARAM_REG_PSIZEREGID() argument
1914 return ((val) << A3XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT) & A3XX_SP_VS_PARAM_REG_PSIZEREGID__MASK; A3XX_SP_VS_PARAM_REG_PSIZEREGID()
1918 static inline uint32_t A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val) A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR() argument
1920 return ((val) << A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT) & A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK; A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR()
1928 static inline uint32_t A3XX_SP_VS_OUT_REG_A_REGID(uint32_t val) A3XX_SP_VS_OUT_REG_A_REGID() argument
1930 return ((val) << A3XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A3XX_SP_VS_OUT_REG_A_REGID__MASK; A3XX_SP_VS_OUT_REG_A_REGID()
1934 static inline uint32_t A3XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val) A3XX_SP_VS_OUT_REG_A_COMPMASK() argument
1936 return ((val) << A3XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A3XX_SP_VS_OUT_REG_A_COMPMASK__MASK; A3XX_SP_VS_OUT_REG_A_COMPMASK()
1940 static inline uint32_t A3XX_SP_VS_OUT_REG_B_REGID(uint32_t val) A3XX_SP_VS_OUT_REG_B_REGID() argument
1942 return ((val) << A3XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A3XX_SP_VS_OUT_REG_B_REGID__MASK; A3XX_SP_VS_OUT_REG_B_REGID()
1946 static inline uint32_t A3XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) A3XX_SP_VS_OUT_REG_B_COMPMASK() argument
1948 return ((val) << A3XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A3XX_SP_VS_OUT_REG_B_COMPMASK__MASK; A3XX_SP_VS_OUT_REG_B_COMPMASK()
1956 static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val) A3XX_SP_VS_VPC_DST_REG_OUTLOC0() argument
1958 return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK; A3XX_SP_VS_VPC_DST_REG_OUTLOC0()
1962 static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val) A3XX_SP_VS_VPC_DST_REG_OUTLOC1() argument
1964 return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK; A3XX_SP_VS_VPC_DST_REG_OUTLOC1()
1968 static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val) A3XX_SP_VS_VPC_DST_REG_OUTLOC2() argument
1970 return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK; A3XX_SP_VS_VPC_DST_REG_OUTLOC2()
1974 static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) A3XX_SP_VS_VPC_DST_REG_OUTLOC3() argument
1976 return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK; A3XX_SP_VS_VPC_DST_REG_OUTLOC3()
1982 static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET() argument
1984 return ((val) << A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET()
1988 static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET() argument
1990 return ((val) << A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET()
2004 static inline uint32_t A3XX_SP_VS_LENGTH_REG_SHADERLENGTH(uint32_t val) A3XX_SP_VS_LENGTH_REG_SHADERLENGTH() argument
2006 return ((val) << A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__SHIFT) & A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__MASK; A3XX_SP_VS_LENGTH_REG_SHADERLENGTH()
2012 static inline uint32_t A3XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) A3XX_SP_FS_CTRL_REG0_THREADMODE() argument
2014 return ((val) << A3XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A3XX_SP_FS_CTRL_REG0_THREADMODE__MASK; A3XX_SP_FS_CTRL_REG0_THREADMODE()
2018 static inline uint32_t A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffermode val) A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE() argument
2020 return ((val) << A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__SHIFT) & A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__MASK; A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE()
2025 static inline uint32_t A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT() argument
2027 return ((val) << A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK; A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT()
2031 static inline uint32_t A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT() argument
2033 return ((val) << A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK; A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT()
2037 static inline uint32_t A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val) A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP() argument
2039 return ((val) << A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK; A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP()
2043 static inline uint32_t A3XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) A3XX_SP_FS_CTRL_REG0_THREADSIZE() argument
2045 return ((val) << A3XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A3XX_SP_FS_CTRL_REG0_THREADSIZE__MASK; A3XX_SP_FS_CTRL_REG0_THREADSIZE()
2052 static inline uint32_t A3XX_SP_FS_CTRL_REG0_LENGTH(uint32_t val) A3XX_SP_FS_CTRL_REG0_LENGTH() argument
2054 return ((val) << A3XX_SP_FS_CTRL_REG0_LENGTH__SHIFT) & A3XX_SP_FS_CTRL_REG0_LENGTH__MASK; A3XX_SP_FS_CTRL_REG0_LENGTH()
2060 static inline uint32_t A3XX_SP_FS_CTRL_REG1_CONSTLENGTH(uint32_t val) A3XX_SP_FS_CTRL_REG1_CONSTLENGTH() argument
2062 return ((val) << A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT) & A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK; A3XX_SP_FS_CTRL_REG1_CONSTLENGTH()
2066 static inline uint32_t A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT(uint32_t val) A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT() argument
2068 return ((val) << A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__MASK; A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT()
2072 static inline uint32_t A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val) A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING() argument
2074 return ((val) << A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__MASK; A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING()
2078 static inline uint32_t A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET(uint32_t val) A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET() argument
2080 return ((val) << A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__SHIFT) & A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__MASK; A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET()
2086 static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET() argument
2088 return ((val) << A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET()
2092 static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET() argument
2094 return ((val) << A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET()
2113 static inline uint32_t A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID(uint32_t val) A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID() argument
2115 return ((val) << A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT) & A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK; A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID()
2123 static inline uint32_t A3XX_SP_FS_MRT_REG_REGID(uint32_t val) A3XX_SP_FS_MRT_REG_REGID() argument
2125 return ((val) << A3XX_SP_FS_MRT_REG_REGID__SHIFT) & A3XX_SP_FS_MRT_REG_REGID__MASK; A3XX_SP_FS_MRT_REG_REGID()
2136 static inline uint32_t A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT(enum a3xx_color_fmt val) A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT() argument
2138 return ((val) << A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__SHIFT) & A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__MASK; A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT()
2144 static inline uint32_t A3XX_SP_FS_LENGTH_REG_SHADERLENGTH(uint32_t val) A3XX_SP_FS_LENGTH_REG_SHADERLENGTH() argument
2146 return ((val) << A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__SHIFT) & A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__MASK; A3XX_SP_FS_LENGTH_REG_SHADERLENGTH()
2154 static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET(uint32_t val) A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET() argument
2156 return ((val) << A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__SHIFT) & A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__MASK; A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET()
2160 static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET(uint32_t val) A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET() argument
2162 return ((val) << A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__SHIFT) & A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__MASK; A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET()
2166 static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR(uint32_t val) A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR() argument
2168 return ((val) << A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__SHIFT) & A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__MASK; A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR()
2176 static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET(uint32_t val) A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET() argument
2178 return ((val) << A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__SHIFT) & A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__MASK; A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET()
2182 static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET(uint32_t val) A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET() argument
2184 return ((val) << A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__SHIFT) & A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__MASK; A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET()
2188 static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR(uint32_t val) A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR() argument
2190 return ((val) << A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__SHIFT) & A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__MASK; A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR()
2272 static inline uint32_t A3XX_VSC_BIN_SIZE_WIDTH(uint32_t val) A3XX_VSC_BIN_SIZE_WIDTH() argument
2274 return ((val >> 5) << A3XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A3XX_VSC_BIN_SIZE_WIDTH__MASK; A3XX_VSC_BIN_SIZE_WIDTH()
2278 static inline uint32_t A3XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) A3XX_VSC_BIN_SIZE_HEIGHT() argument
2280 return ((val >> 5) << A3XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A3XX_VSC_BIN_SIZE_HEIGHT__MASK; A3XX_VSC_BIN_SIZE_HEIGHT()
2290 static inline uint32_t A3XX_VSC_PIPE_CONFIG_X(uint32_t val) A3XX_VSC_PIPE_CONFIG_X() argument
2292 return ((val) << A3XX_VSC_PIPE_CONFIG_X__SHIFT) & A3XX_VSC_PIPE_CONFIG_X__MASK; A3XX_VSC_PIPE_CONFIG_X()
2296 static inline uint32_t A3XX_VSC_PIPE_CONFIG_Y(uint32_t val) A3XX_VSC_PIPE_CONFIG_Y() argument
2298 return ((val) << A3XX_VSC_PIPE_CONFIG_Y__SHIFT) & A3XX_VSC_PIPE_CONFIG_Y__MASK; A3XX_VSC_PIPE_CONFIG_Y()
2302 static inline uint32_t A3XX_VSC_PIPE_CONFIG_W(uint32_t val) A3XX_VSC_PIPE_CONFIG_W() argument
2304 return ((val) << A3XX_VSC_PIPE_CONFIG_W__SHIFT) & A3XX_VSC_PIPE_CONFIG_W__MASK; A3XX_VSC_PIPE_CONFIG_W()
2308 static inline uint32_t A3XX_VSC_PIPE_CONFIG_H(uint32_t val) A3XX_VSC_PIPE_CONFIG_H() argument
2310 return ((val) << A3XX_VSC_PIPE_CONFIG_H__SHIFT) & A3XX_VSC_PIPE_CONFIG_H__MASK; A3XX_VSC_PIPE_CONFIG_H()
2361 static inline uint32_t A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val) A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH() argument
2363 return ((val) << A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT) & A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK; A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH()
2367 static inline uint32_t A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val) A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT() argument
2369 return ((val) << A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT) & A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK; A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT()
2415 static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR(uint32_t val) A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR() argument
2417 return ((val) << A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__SHIFT) & A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__MASK; A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR()
2423 static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR(uint32_t val) A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR() argument
2425 return ((val) << A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__SHIFT) & A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__MASK; A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR()
2429 static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE(enum a3xx_cache_opcode val) A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE() argument
2431 return ((val) << A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__SHIFT) & A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__MASK; A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE()
2476 static inline uint32_t A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val) A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE() argument
2478 return ((val) << A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK; A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE()
2482 static inline uint32_t A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val) A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT() argument
2484 return ((val) << A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK; A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT()
2488 static inline uint32_t A3XX_VGT_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val) A3XX_VGT_DRAW_INITIATOR_VIS_CULL() argument
2490 return ((val) << A3XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT) & A3XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK; A3XX_VGT_DRAW_INITIATOR_VIS_CULL()
2494 static inline uint32_t A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE(enum pc_di_index_size val) A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE() argument
2496 return ((val) << A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK; A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE()
2503 static inline uint32_t A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES(uint32_t val) A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES() argument
2505 return ((val) << A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT) & A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK; A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES()
2514 static inline uint32_t A3XX_TEX_SAMP_0_XY_MAG(enum a3xx_tex_filter val) A3XX_TEX_SAMP_0_XY_MAG() argument
2516 return ((val) << A3XX_TEX_SAMP_0_XY_MAG__SHIFT) & A3XX_TEX_SAMP_0_XY_MAG__MASK; A3XX_TEX_SAMP_0_XY_MAG()
2520 static inline uint32_t A3XX_TEX_SAMP_0_XY_MIN(enum a3xx_tex_filter val) A3XX_TEX_SAMP_0_XY_MIN() argument
2522 return ((val) << A3XX_TEX_SAMP_0_XY_MIN__SHIFT) & A3XX_TEX_SAMP_0_XY_MIN__MASK; A3XX_TEX_SAMP_0_XY_MIN()
2526 static inline uint32_t A3XX_TEX_SAMP_0_WRAP_S(enum a3xx_tex_clamp val) A3XX_TEX_SAMP_0_WRAP_S() argument
2528 return ((val) << A3XX_TEX_SAMP_0_WRAP_S__SHIFT) & A3XX_TEX_SAMP_0_WRAP_S__MASK; A3XX_TEX_SAMP_0_WRAP_S()
2532 static inline uint32_t A3XX_TEX_SAMP_0_WRAP_T(enum a3xx_tex_clamp val) A3XX_TEX_SAMP_0_WRAP_T() argument
2534 return ((val) << A3XX_TEX_SAMP_0_WRAP_T__SHIFT) & A3XX_TEX_SAMP_0_WRAP_T__MASK; A3XX_TEX_SAMP_0_WRAP_T()
2538 static inline uint32_t A3XX_TEX_SAMP_0_WRAP_R(enum a3xx_tex_clamp val) A3XX_TEX_SAMP_0_WRAP_R() argument
2540 return ((val) << A3XX_TEX_SAMP_0_WRAP_R__SHIFT) & A3XX_TEX_SAMP_0_WRAP_R__MASK; A3XX_TEX_SAMP_0_WRAP_R()
2544 static inline uint32_t A3XX_TEX_SAMP_0_ANISO(enum a3xx_tex_aniso val) A3XX_TEX_SAMP_0_ANISO() argument
2546 return ((val) << A3XX_TEX_SAMP_0_ANISO__SHIFT) & A3XX_TEX_SAMP_0_ANISO__MASK; A3XX_TEX_SAMP_0_ANISO()
2550 static inline uint32_t A3XX_TEX_SAMP_0_COMPARE_FUNC(enum adreno_compare_func val) A3XX_TEX_SAMP_0_COMPARE_FUNC() argument
2552 return ((val) << A3XX_TEX_SAMP_0_COMPARE_FUNC__SHIFT) & A3XX_TEX_SAMP_0_COMPARE_FUNC__MASK; A3XX_TEX_SAMP_0_COMPARE_FUNC()
2559 static inline uint32_t A3XX_TEX_SAMP_1_LOD_BIAS(float val) A3XX_TEX_SAMP_1_LOD_BIAS() argument
2561 return ((((int32_t)(val * 64.0))) << A3XX_TEX_SAMP_1_LOD_BIAS__SHIFT) & A3XX_TEX_SAMP_1_LOD_BIAS__MASK; A3XX_TEX_SAMP_1_LOD_BIAS()
2565 static inline uint32_t A3XX_TEX_SAMP_1_MAX_LOD(float val) A3XX_TEX_SAMP_1_MAX_LOD() argument
2567 return ((((uint32_t)(val * 64.0))) << A3XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A3XX_TEX_SAMP_1_MAX_LOD__MASK; A3XX_TEX_SAMP_1_MAX_LOD()
2571 static inline uint32_t A3XX_TEX_SAMP_1_MIN_LOD(float val) A3XX_TEX_SAMP_1_MIN_LOD() argument
2573 return ((((uint32_t)(val * 64.0))) << A3XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A3XX_TEX_SAMP_1_MIN_LOD__MASK; A3XX_TEX_SAMP_1_MIN_LOD()
2581 static inline uint32_t A3XX_TEX_CONST_0_SWIZ_X(enum a3xx_tex_swiz val) A3XX_TEX_CONST_0_SWIZ_X() argument
2583 return ((val) << A3XX_TEX_CONST_0_SWIZ_X__SHIFT) & A3XX_TEX_CONST_0_SWIZ_X__MASK; A3XX_TEX_CONST_0_SWIZ_X()
2587 static inline uint32_t A3XX_TEX_CONST_0_SWIZ_Y(enum a3xx_tex_swiz val) A3XX_TEX_CONST_0_SWIZ_Y() argument
2589 return ((val) << A3XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A3XX_TEX_CONST_0_SWIZ_Y__MASK; A3XX_TEX_CONST_0_SWIZ_Y()
2593 static inline uint32_t A3XX_TEX_CONST_0_SWIZ_Z(enum a3xx_tex_swiz val) A3XX_TEX_CONST_0_SWIZ_Z() argument
2595 return ((val) << A3XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A3XX_TEX_CONST_0_SWIZ_Z__MASK; A3XX_TEX_CONST_0_SWIZ_Z()
2599 static inline uint32_t A3XX_TEX_CONST_0_SWIZ_W(enum a3xx_tex_swiz val) A3XX_TEX_CONST_0_SWIZ_W() argument
2601 return ((val) << A3XX_TEX_CONST_0_SWIZ_W__SHIFT) & A3XX_TEX_CONST_0_SWIZ_W__MASK; A3XX_TEX_CONST_0_SWIZ_W()
2605 static inline uint32_t A3XX_TEX_CONST_0_MIPLVLS(uint32_t val) A3XX_TEX_CONST_0_MIPLVLS() argument
2607 return ((val) << A3XX_TEX_CONST_0_MIPLVLS__SHIFT) & A3XX_TEX_CONST_0_MIPLVLS__MASK; A3XX_TEX_CONST_0_MIPLVLS()
2611 static inline uint32_t A3XX_TEX_CONST_0_FMT(enum a3xx_tex_fmt val) A3XX_TEX_CONST_0_FMT() argument
2613 return ((val) << A3XX_TEX_CONST_0_FMT__SHIFT) & A3XX_TEX_CONST_0_FMT__MASK; A3XX_TEX_CONST_0_FMT()
2618 static inline uint32_t A3XX_TEX_CONST_0_TYPE(enum a3xx_tex_type val) A3XX_TEX_CONST_0_TYPE() argument
2620 return ((val) << A3XX_TEX_CONST_0_TYPE__SHIFT) & A3XX_TEX_CONST_0_TYPE__MASK; A3XX_TEX_CONST_0_TYPE()
2626 static inline uint32_t A3XX_TEX_CONST_1_HEIGHT(uint32_t val) A3XX_TEX_CONST_1_HEIGHT() argument
2628 return ((val) << A3XX_TEX_CONST_1_HEIGHT__SHIFT) & A3XX_TEX_CONST_1_HEIGHT__MASK; A3XX_TEX_CONST_1_HEIGHT()
2632 static inline uint32_t A3XX_TEX_CONST_1_WIDTH(uint32_t val) A3XX_TEX_CONST_1_WIDTH() argument
2634 return ((val) << A3XX_TEX_CONST_1_WIDTH__SHIFT) & A3XX_TEX_CONST_1_WIDTH__MASK; A3XX_TEX_CONST_1_WIDTH()
2638 static inline uint32_t A3XX_TEX_CONST_1_FETCHSIZE(enum a3xx_tex_fetchsize val) A3XX_TEX_CONST_1_FETCHSIZE() argument
2640 return ((val) << A3XX_TEX_CONST_1_FETCHSIZE__SHIFT) & A3XX_TEX_CONST_1_FETCHSIZE__MASK; A3XX_TEX_CONST_1_FETCHSIZE()
2646 static inline uint32_t A3XX_TEX_CONST_2_INDX(uint32_t val) A3XX_TEX_CONST_2_INDX() argument
2648 return ((val) << A3XX_TEX_CONST_2_INDX__SHIFT) & A3XX_TEX_CONST_2_INDX__MASK; A3XX_TEX_CONST_2_INDX()
2652 static inline uint32_t A3XX_TEX_CONST_2_PITCH(uint32_t val) A3XX_TEX_CONST_2_PITCH() argument
2654 return ((val) << A3XX_TEX_CONST_2_PITCH__SHIFT) & A3XX_TEX_CONST_2_PITCH__MASK; A3XX_TEX_CONST_2_PITCH()
2658 static inline uint32_t A3XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val) A3XX_TEX_CONST_2_SWAP() argument
2660 return ((val) << A3XX_TEX_CONST_2_SWAP__SHIFT) & A3XX_TEX_CONST_2_SWAP__MASK; A3XX_TEX_CONST_2_SWAP()
2666 static inline uint32_t A3XX_TEX_CONST_3_LAYERSZ1(uint32_t val) A3XX_TEX_CONST_3_LAYERSZ1() argument
2668 return ((val >> 12) << A3XX_TEX_CONST_3_LAYERSZ1__SHIFT) & A3XX_TEX_CONST_3_LAYERSZ1__MASK; A3XX_TEX_CONST_3_LAYERSZ1()
2672 static inline uint32_t A3XX_TEX_CONST_3_DEPTH(uint32_t val) A3XX_TEX_CONST_3_DEPTH() argument
2674 return ((val) << A3XX_TEX_CONST_3_DEPTH__SHIFT) & A3XX_TEX_CONST_3_DEPTH__MASK; A3XX_TEX_CONST_3_DEPTH()
2678 static inline uint32_t A3XX_TEX_CONST_3_LAYERSZ2(uint32_t val) A3XX_TEX_CONST_3_LAYERSZ2() argument
2680 return ((val >> 12) << A3XX_TEX_CONST_3_LAYERSZ2__SHIFT) & A3XX_TEX_CONST_3_LAYERSZ2__MASK; A3XX_TEX_CONST_3_LAYERSZ2()
H A Da4xx.xml.h180 static inline uint32_t A4XX_CGC_HLSQ_EARLY_CYC(uint32_t val) A4XX_CGC_HLSQ_EARLY_CYC() argument
182 return ((val) << A4XX_CGC_HLSQ_EARLY_CYC__SHIFT) & A4XX_CGC_HLSQ_EARLY_CYC__MASK; A4XX_CGC_HLSQ_EARLY_CYC()
231 static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val) A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH() argument
233 return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK; A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH()
237 static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val) A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT() argument
239 return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK; A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT()
253 static inline uint32_t A4XX_RB_MODE_CONTROL_WIDTH(uint32_t val) A4XX_RB_MODE_CONTROL_WIDTH() argument
255 return ((val >> 5) << A4XX_RB_MODE_CONTROL_WIDTH__SHIFT) & A4XX_RB_MODE_CONTROL_WIDTH__MASK; A4XX_RB_MODE_CONTROL_WIDTH()
259 static inline uint32_t A4XX_RB_MODE_CONTROL_HEIGHT(uint32_t val) A4XX_RB_MODE_CONTROL_HEIGHT() argument
261 return ((val >> 5) << A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT) & A4XX_RB_MODE_CONTROL_HEIGHT__MASK; A4XX_RB_MODE_CONTROL_HEIGHT()
272 static inline uint32_t A4XX_RB_MSAA_CONTROL_SAMPLES(uint32_t val) A4XX_RB_MSAA_CONTROL_SAMPLES() argument
274 return ((val) << A4XX_RB_MSAA_CONTROL_SAMPLES__SHIFT) & A4XX_RB_MSAA_CONTROL_SAMPLES__MASK; A4XX_RB_MSAA_CONTROL_SAMPLES()
285 static inline uint32_t A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES(uint32_t val) A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES() argument
287 return ((val) << A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT) & A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK; A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES()
301 static inline uint32_t A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE() argument
303 return ((val) << A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK; A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE()
309 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a4xx_color_fmt val) A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT() argument
311 return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK; A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT()
315 static inline uint32_t A4XX_RB_MRT_BUF_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) A4XX_RB_MRT_BUF_INFO_DITHER_MODE() argument
317 return ((val) << A4XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT) & A4XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK; A4XX_RB_MRT_BUF_INFO_DITHER_MODE()
321 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) A4XX_RB_MRT_BUF_INFO_COLOR_SWAP() argument
323 return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK; A4XX_RB_MRT_BUF_INFO_COLOR_SWAP()
327 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val) A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH() argument
329 return ((val >> 4) << A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK; A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH()
337 static inline uint32_t A4XX_RB_MRT_CONTROL3_STRIDE(uint32_t val) A4XX_RB_MRT_CONTROL3_STRIDE() argument
339 return ((val) << A4XX_RB_MRT_CONTROL3_STRIDE__SHIFT) & A4XX_RB_MRT_CONTROL3_STRIDE__MASK; A4XX_RB_MRT_CONTROL3_STRIDE()
345 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val) A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR() argument
347 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK; A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR()
351 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a4xx_rb_blend_opcode val) A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE() argument
353 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK; A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE()
357 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val) A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR() argument
359 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK; A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR()
363 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val) A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR() argument
365 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK; A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR()
369 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a4xx_rb_blend_opcode val) A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE() argument
371 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK; A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE()
375 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val) A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR() argument
377 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK; A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR()
383 static inline uint32_t A4XX_RB_BLEND_RED_UINT(uint32_t val) A4XX_RB_BLEND_RED_UINT() argument
385 return ((val) << A4XX_RB_BLEND_RED_UINT__SHIFT) & A4XX_RB_BLEND_RED_UINT__MASK; A4XX_RB_BLEND_RED_UINT()
389 static inline uint32_t A4XX_RB_BLEND_RED_FLOAT(float val) A4XX_RB_BLEND_RED_FLOAT() argument
391 return ((util_float_to_half(val)) << A4XX_RB_BLEND_RED_FLOAT__SHIFT) & A4XX_RB_BLEND_RED_FLOAT__MASK; A4XX_RB_BLEND_RED_FLOAT()
397 static inline uint32_t A4XX_RB_BLEND_GREEN_UINT(uint32_t val) A4XX_RB_BLEND_GREEN_UINT() argument
399 return ((val) << A4XX_RB_BLEND_GREEN_UINT__SHIFT) & A4XX_RB_BLEND_GREEN_UINT__MASK; A4XX_RB_BLEND_GREEN_UINT()
403 static inline uint32_t A4XX_RB_BLEND_GREEN_FLOAT(float val) A4XX_RB_BLEND_GREEN_FLOAT() argument
405 return ((util_float_to_half(val)) << A4XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A4XX_RB_BLEND_GREEN_FLOAT__MASK; A4XX_RB_BLEND_GREEN_FLOAT()
411 static inline uint32_t A4XX_RB_BLEND_BLUE_UINT(uint32_t val) A4XX_RB_BLEND_BLUE_UINT() argument
413 return ((val) << A4XX_RB_BLEND_BLUE_UINT__SHIFT) & A4XX_RB_BLEND_BLUE_UINT__MASK; A4XX_RB_BLEND_BLUE_UINT()
417 static inline uint32_t A4XX_RB_BLEND_BLUE_FLOAT(float val) A4XX_RB_BLEND_BLUE_FLOAT() argument
419 return ((util_float_to_half(val)) << A4XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A4XX_RB_BLEND_BLUE_FLOAT__MASK; A4XX_RB_BLEND_BLUE_FLOAT()
425 static inline uint32_t A4XX_RB_BLEND_ALPHA_UINT(uint32_t val) A4XX_RB_BLEND_ALPHA_UINT() argument
427 return ((val) << A4XX_RB_BLEND_ALPHA_UINT__SHIFT) & A4XX_RB_BLEND_ALPHA_UINT__MASK; A4XX_RB_BLEND_ALPHA_UINT()
431 static inline uint32_t A4XX_RB_BLEND_ALPHA_FLOAT(float val) A4XX_RB_BLEND_ALPHA_FLOAT() argument
433 return ((util_float_to_half(val)) << A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A4XX_RB_BLEND_ALPHA_FLOAT__MASK; A4XX_RB_BLEND_ALPHA_FLOAT()
439 static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val) A4XX_RB_ALPHA_CONTROL_ALPHA_REF() argument
441 return ((val) << A4XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A4XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK; A4XX_RB_ALPHA_CONTROL_ALPHA_REF()
446 static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val) A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC() argument
448 return ((val) << A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK; A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC()
456 static inline uint32_t A4XX_RB_FS_OUTPUT_SAMPLE_MASK(uint32_t val) A4XX_RB_FS_OUTPUT_SAMPLE_MASK() argument
458 return ((val) << A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT) & A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK; A4XX_RB_FS_OUTPUT_SAMPLE_MASK()
464 static inline uint32_t A4XX_RB_RENDER_CONTROL3_COMPONENT_ENABLE(uint32_t val) A4XX_RB_RENDER_CONTROL3_COMPONENT_ENABLE() argument
466 return ((val) << A4XX_RB_RENDER_CONTROL3_COMPONENT_ENABLE__SHIFT) & A4XX_RB_RENDER_CONTROL3_COMPONENT_ENABLE__MASK; A4XX_RB_RENDER_CONTROL3_COMPONENT_ENABLE()
472 static inline uint32_t A4XX_RB_COPY_CONTROL_MSAA_RESOLVE(enum a3xx_msaa_samples val) A4XX_RB_COPY_CONTROL_MSAA_RESOLVE() argument
474 return ((val) << A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT) & A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK; A4XX_RB_COPY_CONTROL_MSAA_RESOLVE()
478 static inline uint32_t A4XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val) A4XX_RB_COPY_CONTROL_MODE() argument
480 return ((val) << A4XX_RB_COPY_CONTROL_MODE__SHIFT) & A4XX_RB_COPY_CONTROL_MODE__MASK; A4XX_RB_COPY_CONTROL_MODE()
484 static inline uint32_t A4XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val) A4XX_RB_COPY_CONTROL_FASTCLEAR() argument
486 return ((val) << A4XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT) & A4XX_RB_COPY_CONTROL_FASTCLEAR__MASK; A4XX_RB_COPY_CONTROL_FASTCLEAR()
490 static inline uint32_t A4XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val) A4XX_RB_COPY_CONTROL_GMEM_BASE() argument
492 return ((val >> 14) << A4XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT) & A4XX_RB_COPY_CONTROL_GMEM_BASE__MASK; A4XX_RB_COPY_CONTROL_GMEM_BASE()
498 static inline uint32_t A4XX_RB_COPY_DEST_BASE_BASE(uint32_t val) A4XX_RB_COPY_DEST_BASE_BASE() argument
500 return ((val >> 5) << A4XX_RB_COPY_DEST_BASE_BASE__SHIFT) & A4XX_RB_COPY_DEST_BASE_BASE__MASK; A4XX_RB_COPY_DEST_BASE_BASE()
506 static inline uint32_t A4XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val) A4XX_RB_COPY_DEST_PITCH_PITCH() argument
508 return ((val >> 5) << A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT) & A4XX_RB_COPY_DEST_PITCH_PITCH__MASK; A4XX_RB_COPY_DEST_PITCH_PITCH()
514 static inline uint32_t A4XX_RB_COPY_DEST_INFO_FORMAT(enum a4xx_color_fmt val) A4XX_RB_COPY_DEST_INFO_FORMAT() argument
516 return ((val) << A4XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A4XX_RB_COPY_DEST_INFO_FORMAT__MASK; A4XX_RB_COPY_DEST_INFO_FORMAT()
520 static inline uint32_t A4XX_RB_COPY_DEST_INFO_SWAP(enum a3xx_color_swap val) A4XX_RB_COPY_DEST_INFO_SWAP() argument
522 return ((val) << A4XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A4XX_RB_COPY_DEST_INFO_SWAP__MASK; A4XX_RB_COPY_DEST_INFO_SWAP()
526 static inline uint32_t A4XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) A4XX_RB_COPY_DEST_INFO_DITHER_MODE() argument
528 return ((val) << A4XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A4XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK; A4XX_RB_COPY_DEST_INFO_DITHER_MODE()
532 static inline uint32_t A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val) A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE() argument
534 return ((val) << A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT) & A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK; A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE()
538 static inline uint32_t A4XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endian val) A4XX_RB_COPY_DEST_INFO_ENDIAN() argument
540 return ((val) << A4XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT) & A4XX_RB_COPY_DEST_INFO_ENDIAN__MASK; A4XX_RB_COPY_DEST_INFO_ENDIAN()
544 static inline uint32_t A4XX_RB_COPY_DEST_INFO_TILE(enum a4xx_tile_mode val) A4XX_RB_COPY_DEST_INFO_TILE() argument
546 return ((val) << A4XX_RB_COPY_DEST_INFO_TILE__SHIFT) & A4XX_RB_COPY_DEST_INFO_TILE__MASK; A4XX_RB_COPY_DEST_INFO_TILE()
559 static inline uint32_t A4XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val) A4XX_RB_DEPTH_CONTROL_ZFUNC() argument
561 return ((val) << A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT) & A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK; A4XX_RB_DEPTH_CONTROL_ZFUNC()
572 static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum a4xx_depth_format val) A4XX_RB_DEPTH_INFO_DEPTH_FORMAT() argument
574 return ((val) << A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK; A4XX_RB_DEPTH_INFO_DEPTH_FORMAT()
578 static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) A4XX_RB_DEPTH_INFO_DEPTH_BASE() argument
580 return ((val >> 12) << A4XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A4XX_RB_DEPTH_INFO_DEPTH_BASE__MASK; A4XX_RB_DEPTH_INFO_DEPTH_BASE()
586 static inline uint32_t A4XX_RB_DEPTH_PITCH(uint32_t val) A4XX_RB_DEPTH_PITCH() argument
588 return ((val >> 5) << A4XX_RB_DEPTH_PITCH__SHIFT) & A4XX_RB_DEPTH_PITCH__MASK; A4XX_RB_DEPTH_PITCH()
594 static inline uint32_t A4XX_RB_DEPTH_PITCH2(uint32_t val) A4XX_RB_DEPTH_PITCH2() argument
596 return ((val >> 5) << A4XX_RB_DEPTH_PITCH2__SHIFT) & A4XX_RB_DEPTH_PITCH2__MASK; A4XX_RB_DEPTH_PITCH2()
605 static inline uint32_t A4XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val) A4XX_RB_STENCIL_CONTROL_FUNC() argument
607 return ((val) << A4XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A4XX_RB_STENCIL_CONTROL_FUNC__MASK; A4XX_RB_STENCIL_CONTROL_FUNC()
611 static inline uint32_t A4XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val) A4XX_RB_STENCIL_CONTROL_FAIL() argument
613 return ((val) << A4XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A4XX_RB_STENCIL_CONTROL_FAIL__MASK; A4XX_RB_STENCIL_CONTROL_FAIL()
617 static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val) A4XX_RB_STENCIL_CONTROL_ZPASS() argument
619 return ((val) << A4XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZPASS__MASK; A4XX_RB_STENCIL_CONTROL_ZPASS()
623 static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val) A4XX_RB_STENCIL_CONTROL_ZFAIL() argument
625 return ((val) << A4XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZFAIL__MASK; A4XX_RB_STENCIL_CONTROL_ZFAIL()
629 static inline uint32_t A4XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val) A4XX_RB_STENCIL_CONTROL_FUNC_BF() argument
631 return ((val) << A4XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_FUNC_BF__MASK; A4XX_RB_STENCIL_CONTROL_FUNC_BF()
635 static inline uint32_t A4XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val) A4XX_RB_STENCIL_CONTROL_FAIL_BF() argument
637 return ((val) << A4XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_FAIL_BF__MASK; A4XX_RB_STENCIL_CONTROL_FAIL_BF()
641 static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val) A4XX_RB_STENCIL_CONTROL_ZPASS_BF() argument
643 return ((val) << A4XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK; A4XX_RB_STENCIL_CONTROL_ZPASS_BF()
647 static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val) A4XX_RB_STENCIL_CONTROL_ZFAIL_BF() argument
649 return ((val) << A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK; A4XX_RB_STENCIL_CONTROL_ZFAIL_BF()
658 static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) A4XX_RB_STENCILREFMASK_STENCILREF() argument
660 return ((val) << A4XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILREF__MASK; A4XX_RB_STENCILREFMASK_STENCILREF()
664 static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) A4XX_RB_STENCILREFMASK_STENCILMASK() argument
666 return ((val) << A4XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILMASK__MASK; A4XX_RB_STENCILREFMASK_STENCILMASK()
670 static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) A4XX_RB_STENCILREFMASK_STENCILWRITEMASK() argument
672 return ((val) << A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK; A4XX_RB_STENCILREFMASK_STENCILWRITEMASK()
678 static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) A4XX_RB_STENCILREFMASK_BF_STENCILREF() argument
680 return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILREF__MASK; A4XX_RB_STENCILREFMASK_BF_STENCILREF()
684 static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) A4XX_RB_STENCILREFMASK_BF_STENCILMASK() argument
686 return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK; A4XX_RB_STENCILREFMASK_BF_STENCILMASK()
690 static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK() argument
692 return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK; A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK()
699 static inline uint32_t A4XX_RB_BIN_OFFSET_X(uint32_t val) A4XX_RB_BIN_OFFSET_X() argument
701 return ((val) << A4XX_RB_BIN_OFFSET_X__SHIFT) & A4XX_RB_BIN_OFFSET_X__MASK; A4XX_RB_BIN_OFFSET_X()
705 static inline uint32_t A4XX_RB_BIN_OFFSET_Y(uint32_t val) A4XX_RB_BIN_OFFSET_Y() argument
707 return ((val) << A4XX_RB_BIN_OFFSET_Y__SHIFT) & A4XX_RB_BIN_OFFSET_Y__MASK; A4XX_RB_BIN_OFFSET_Y()
1017 static inline uint32_t A4XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) A4XX_SP_VS_CTRL_REG0_THREADMODE() argument
1019 return ((val) << A4XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A4XX_SP_VS_CTRL_REG0_THREADMODE__MASK; A4XX_SP_VS_CTRL_REG0_THREADMODE()
1025 static inline uint32_t A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT() argument
1027 return ((val) << A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK; A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT()
1031 static inline uint32_t A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT() argument
1033 return ((val) << A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK; A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT()
1037 static inline uint32_t A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val) A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP() argument
1039 return ((val) << A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK; A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP()
1043 static inline uint32_t A4XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) A4XX_SP_VS_CTRL_REG0_THREADSIZE() argument
1045 return ((val) << A4XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A4XX_SP_VS_CTRL_REG0_THREADSIZE__MASK; A4XX_SP_VS_CTRL_REG0_THREADSIZE()
1053 static inline uint32_t A4XX_SP_VS_CTRL_REG1_CONSTLENGTH(uint32_t val) A4XX_SP_VS_CTRL_REG1_CONSTLENGTH() argument
1055 return ((val) << A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT) & A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK; A4XX_SP_VS_CTRL_REG1_CONSTLENGTH()
1059 static inline uint32_t A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val) A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING() argument
1061 return ((val) << A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK; A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING()
1067 static inline uint32_t A4XX_SP_VS_PARAM_REG_POSREGID(uint32_t val) A4XX_SP_VS_PARAM_REG_POSREGID() argument
1069 return ((val) << A4XX_SP_VS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_VS_PARAM_REG_POSREGID__MASK; A4XX_SP_VS_PARAM_REG_POSREGID()
1073 static inline uint32_t A4XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val) A4XX_SP_VS_PARAM_REG_PSIZEREGID() argument
1075 return ((val) << A4XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT) & A4XX_SP_VS_PARAM_REG_PSIZEREGID__MASK; A4XX_SP_VS_PARAM_REG_PSIZEREGID()
1079 static inline uint32_t A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val) A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR() argument
1081 return ((val) << A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT) & A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK; A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR()
1089 static inline uint32_t A4XX_SP_VS_OUT_REG_A_REGID(uint32_t val) A4XX_SP_VS_OUT_REG_A_REGID() argument
1091 return ((val) << A4XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_VS_OUT_REG_A_REGID__MASK; A4XX_SP_VS_OUT_REG_A_REGID()
1095 static inline uint32_t A4XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val) A4XX_SP_VS_OUT_REG_A_COMPMASK() argument
1097 return ((val) << A4XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_VS_OUT_REG_A_COMPMASK__MASK; A4XX_SP_VS_OUT_REG_A_COMPMASK()
1101 static inline uint32_t A4XX_SP_VS_OUT_REG_B_REGID(uint32_t val) A4XX_SP_VS_OUT_REG_B_REGID() argument
1103 return ((val) << A4XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_VS_OUT_REG_B_REGID__MASK; A4XX_SP_VS_OUT_REG_B_REGID()
1107 static inline uint32_t A4XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) A4XX_SP_VS_OUT_REG_B_COMPMASK() argument
1109 return ((val) << A4XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_VS_OUT_REG_B_COMPMASK__MASK; A4XX_SP_VS_OUT_REG_B_COMPMASK()
1117 static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val) A4XX_SP_VS_VPC_DST_REG_OUTLOC0() argument
1119 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK; A4XX_SP_VS_VPC_DST_REG_OUTLOC0()
1123 static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val) A4XX_SP_VS_VPC_DST_REG_OUTLOC1() argument
1125 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK; A4XX_SP_VS_VPC_DST_REG_OUTLOC1()
1129 static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val) A4XX_SP_VS_VPC_DST_REG_OUTLOC2() argument
1131 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK; A4XX_SP_VS_VPC_DST_REG_OUTLOC2()
1135 static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) A4XX_SP_VS_VPC_DST_REG_OUTLOC3() argument
1137 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK; A4XX_SP_VS_VPC_DST_REG_OUTLOC3()
1143 static inline uint32_t A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET() argument
1145 return ((val) << A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET()
1149 static inline uint32_t A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET() argument
1151 return ((val) << A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET()
1165 static inline uint32_t A4XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) A4XX_SP_FS_CTRL_REG0_THREADMODE() argument
1167 return ((val) << A4XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A4XX_SP_FS_CTRL_REG0_THREADMODE__MASK; A4XX_SP_FS_CTRL_REG0_THREADMODE()
1173 static inline uint32_t A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT() argument
1175 return ((val) << A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK; A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT()
1179 static inline uint32_t A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT() argument
1181 return ((val) << A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK; A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT()
1185 static inline uint32_t A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val) A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP() argument
1187 return ((val) << A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK; A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP()
1191 static inline uint32_t A4XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) A4XX_SP_FS_CTRL_REG0_THREADSIZE() argument
1193 return ((val) << A4XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A4XX_SP_FS_CTRL_REG0_THREADSIZE__MASK; A4XX_SP_FS_CTRL_REG0_THREADSIZE()
1201 static inline uint32_t A4XX_SP_FS_CTRL_REG1_CONSTLENGTH(uint32_t val) A4XX_SP_FS_CTRL_REG1_CONSTLENGTH() argument
1203 return ((val) << A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT) & A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK; A4XX_SP_FS_CTRL_REG1_CONSTLENGTH()
1212 static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET() argument
1214 return ((val) << A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET()
1218 static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET() argument
1220 return ((val) << A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET()
1235 static inline uint32_t A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID(uint32_t val) A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID() argument
1237 return ((val) << A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT) & A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK; A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID()
1245 static inline uint32_t A4XX_SP_FS_MRT_REG_REGID(uint32_t val) A4XX_SP_FS_MRT_REG_REGID() argument
1247 return ((val) << A4XX_SP_FS_MRT_REG_REGID__SHIFT) & A4XX_SP_FS_MRT_REG_REGID__MASK; A4XX_SP_FS_MRT_REG_REGID()
1252 static inline uint32_t A4XX_SP_FS_MRT_REG_MRTFORMAT(enum a4xx_color_fmt val) A4XX_SP_FS_MRT_REG_MRTFORMAT() argument
1254 return ((val) << A4XX_SP_FS_MRT_REG_MRTFORMAT__SHIFT) & A4XX_SP_FS_MRT_REG_MRTFORMAT__MASK; A4XX_SP_FS_MRT_REG_MRTFORMAT()
1260 static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET() argument
1262 return ((val) << A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET()
1266 static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET() argument
1268 return ((val) << A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET()
1274 static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET() argument
1276 return ((val) << A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET()
1280 static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET() argument
1282 return ((val) << A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET()
1288 static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET() argument
1290 return ((val) << A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET()
1294 static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET() argument
1296 return ((val) << A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET()
1312 static inline uint32_t A4XX_VPC_ATTR_TOTALATTR(uint32_t val) A4XX_VPC_ATTR_TOTALATTR() argument
1314 return ((val) << A4XX_VPC_ATTR_TOTALATTR__SHIFT) & A4XX_VPC_ATTR_TOTALATTR__MASK; A4XX_VPC_ATTR_TOTALATTR()
1319 static inline uint32_t A4XX_VPC_ATTR_THRDASSIGN(uint32_t val) A4XX_VPC_ATTR_THRDASSIGN() argument
1321 return ((val) << A4XX_VPC_ATTR_THRDASSIGN__SHIFT) & A4XX_VPC_ATTR_THRDASSIGN__MASK; A4XX_VPC_ATTR_THRDASSIGN()
1328 static inline uint32_t A4XX_VPC_PACK_NUMBYPASSVAR(uint32_t val) A4XX_VPC_PACK_NUMBYPASSVAR() argument
1330 return ((val) << A4XX_VPC_PACK_NUMBYPASSVAR__SHIFT) & A4XX_VPC_PACK_NUMBYPASSVAR__MASK; A4XX_VPC_PACK_NUMBYPASSVAR()
1334 static inline uint32_t A4XX_VPC_PACK_NUMFPNONPOSVAR(uint32_t val) A4XX_VPC_PACK_NUMFPNONPOSVAR() argument
1336 return ((val) << A4XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT) & A4XX_VPC_PACK_NUMFPNONPOSVAR__MASK; A4XX_VPC_PACK_NUMFPNONPOSVAR()
1340 static inline uint32_t A4XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val) A4XX_VPC_PACK_NUMNONPOSVSVAR() argument
1342 return ((val) << A4XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT) & A4XX_VPC_PACK_NUMNONPOSVSVAR__MASK; A4XX_VPC_PACK_NUMNONPOSVSVAR()
1358 static inline uint32_t A4XX_VSC_BIN_SIZE_WIDTH(uint32_t val) A4XX_VSC_BIN_SIZE_WIDTH() argument
1360 return ((val >> 5) << A4XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A4XX_VSC_BIN_SIZE_WIDTH__MASK; A4XX_VSC_BIN_SIZE_WIDTH()
1364 static inline uint32_t A4XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) A4XX_VSC_BIN_SIZE_HEIGHT() argument
1366 return ((val >> 5) << A4XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A4XX_VSC_BIN_SIZE_HEIGHT__MASK; A4XX_VSC_BIN_SIZE_HEIGHT()
1380 static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_X(uint32_t val) A4XX_VSC_PIPE_CONFIG_REG_X() argument
1382 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_X__MASK; A4XX_VSC_PIPE_CONFIG_REG_X()
1386 static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val) A4XX_VSC_PIPE_CONFIG_REG_Y() argument
1388 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_Y__MASK; A4XX_VSC_PIPE_CONFIG_REG_Y()
1392 static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_W(uint32_t val) A4XX_VSC_PIPE_CONFIG_REG_W() argument
1394 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_W__MASK; A4XX_VSC_PIPE_CONFIG_REG_W()
1398 static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_H(uint32_t val) A4XX_VSC_PIPE_CONFIG_REG_H() argument
1400 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_H__MASK; A4XX_VSC_PIPE_CONFIG_REG_H()
1424 static inline uint32_t A4XX_VFD_CONTROL_0_TOTALATTRTOVS(uint32_t val) A4XX_VFD_CONTROL_0_TOTALATTRTOVS() argument
1426 return ((val) << A4XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT) & A4XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK; A4XX_VFD_CONTROL_0_TOTALATTRTOVS()
1430 static inline uint32_t A4XX_VFD_CONTROL_0_BYPASSATTROVS(uint32_t val) A4XX_VFD_CONTROL_0_BYPASSATTROVS() argument
1432 return ((val) << A4XX_VFD_CONTROL_0_BYPASSATTROVS__SHIFT) & A4XX_VFD_CONTROL_0_BYPASSATTROVS__MASK; A4XX_VFD_CONTROL_0_BYPASSATTROVS()
1436 static inline uint32_t A4XX_VFD_CONTROL_0_STRMDECINSTRCNT(uint32_t val) A4XX_VFD_CONTROL_0_STRMDECINSTRCNT() argument
1438 return ((val) << A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT) & A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK; A4XX_VFD_CONTROL_0_STRMDECINSTRCNT()
1442 static inline uint32_t A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val) A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT() argument
1444 return ((val) << A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT) & A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK; A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT()
1450 static inline uint32_t A4XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val) A4XX_VFD_CONTROL_1_MAXSTORAGE() argument
1452 return ((val) << A4XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT) & A4XX_VFD_CONTROL_1_MAXSTORAGE__MASK; A4XX_VFD_CONTROL_1_MAXSTORAGE()
1456 static inline uint32_t A4XX_VFD_CONTROL_1_REGID4VTX(uint32_t val) A4XX_VFD_CONTROL_1_REGID4VTX() argument
1458 return ((val) << A4XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A4XX_VFD_CONTROL_1_REGID4VTX__MASK; A4XX_VFD_CONTROL_1_REGID4VTX()
1462 static inline uint32_t A4XX_VFD_CONTROL_1_REGID4INST(uint32_t val) A4XX_VFD_CONTROL_1_REGID4INST() argument
1464 return ((val) << A4XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A4XX_VFD_CONTROL_1_REGID4INST__MASK; A4XX_VFD_CONTROL_1_REGID4INST()
1472 static inline uint32_t A4XX_VFD_CONTROL_3_REGID_VTXCNT(uint32_t val) A4XX_VFD_CONTROL_3_REGID_VTXCNT() argument
1474 return ((val) << A4XX_VFD_CONTROL_3_REGID_VTXCNT__SHIFT) & A4XX_VFD_CONTROL_3_REGID_VTXCNT__MASK; A4XX_VFD_CONTROL_3_REGID_VTXCNT()
1486 static inline uint32_t A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(uint32_t val) A4XX_VFD_FETCH_INSTR_0_FETCHSIZE() argument
1488 return ((val) << A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT) & A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK; A4XX_VFD_FETCH_INSTR_0_FETCHSIZE()
1492 static inline uint32_t A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val) A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE() argument
1494 return ((val) << A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT) & A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK; A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE()
1504 static inline uint32_t A4XX_VFD_FETCH_INSTR_2_SIZE(uint32_t val) A4XX_VFD_FETCH_INSTR_2_SIZE() argument
1506 return ((val >> 4) << A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT) & A4XX_VFD_FETCH_INSTR_2_SIZE__MASK; A4XX_VFD_FETCH_INSTR_2_SIZE()
1512 static inline uint32_t A4XX_VFD_FETCH_INSTR_3_STEPRATE(uint32_t val) A4XX_VFD_FETCH_INSTR_3_STEPRATE() argument
1514 return ((val) << A4XX_VFD_FETCH_INSTR_3_STEPRATE__SHIFT) & A4XX_VFD_FETCH_INSTR_3_STEPRATE__MASK; A4XX_VFD_FETCH_INSTR_3_STEPRATE()
1522 static inline uint32_t A4XX_VFD_DECODE_INSTR_WRITEMASK(uint32_t val) A4XX_VFD_DECODE_INSTR_WRITEMASK() argument
1524 return ((val) << A4XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT) & A4XX_VFD_DECODE_INSTR_WRITEMASK__MASK; A4XX_VFD_DECODE_INSTR_WRITEMASK()
1529 static inline uint32_t A4XX_VFD_DECODE_INSTR_FORMAT(enum a4xx_vtx_fmt val) A4XX_VFD_DECODE_INSTR_FORMAT() argument
1531 return ((val) << A4XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A4XX_VFD_DECODE_INSTR_FORMAT__MASK; A4XX_VFD_DECODE_INSTR_FORMAT()
1535 static inline uint32_t A4XX_VFD_DECODE_INSTR_REGID(uint32_t val) A4XX_VFD_DECODE_INSTR_REGID() argument
1537 return ((val) << A4XX_VFD_DECODE_INSTR_REGID__SHIFT) & A4XX_VFD_DECODE_INSTR_REGID__MASK; A4XX_VFD_DECODE_INSTR_REGID()
1542 static inline uint32_t A4XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val) A4XX_VFD_DECODE_INSTR_SWAP() argument
1544 return ((val) << A4XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A4XX_VFD_DECODE_INSTR_SWAP__MASK; A4XX_VFD_DECODE_INSTR_SWAP()
1548 static inline uint32_t A4XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val) A4XX_VFD_DECODE_INSTR_SHIFTCNT() argument
1550 return ((val) << A4XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT) & A4XX_VFD_DECODE_INSTR_SHIFTCNT__MASK; A4XX_VFD_DECODE_INSTR_SHIFTCNT()
1579 static inline uint32_t A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val) A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ() argument
1581 return ((val) << A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT) & A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK; A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ()
1585 static inline uint32_t A4XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val) A4XX_GRAS_CL_GB_CLIP_ADJ_VERT() argument
1587 return ((val) << A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT) & A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK; A4XX_GRAS_CL_GB_CLIP_ADJ_VERT()
1593 static inline uint32_t A4XX_GRAS_CL_VPORT_XOFFSET_0(float val) A4XX_GRAS_CL_VPORT_XOFFSET_0() argument
1595 return ((fui(val)) << A4XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_XOFFSET_0__MASK; A4XX_GRAS_CL_VPORT_XOFFSET_0()
1601 static inline uint32_t A4XX_GRAS_CL_VPORT_XSCALE_0(float val) A4XX_GRAS_CL_VPORT_XSCALE_0() argument
1603 return ((fui(val)) << A4XX_GRAS_CL_VPORT_XSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_XSCALE_0__MASK; A4XX_GRAS_CL_VPORT_XSCALE_0()
1609 static inline uint32_t A4XX_GRAS_CL_VPORT_YOFFSET_0(float val) A4XX_GRAS_CL_VPORT_YOFFSET_0() argument
1611 return ((fui(val)) << A4XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_YOFFSET_0__MASK; A4XX_GRAS_CL_VPORT_YOFFSET_0()
1617 static inline uint32_t A4XX_GRAS_CL_VPORT_YSCALE_0(float val) A4XX_GRAS_CL_VPORT_YSCALE_0() argument
1619 return ((fui(val)) << A4XX_GRAS_CL_VPORT_YSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_YSCALE_0__MASK; A4XX_GRAS_CL_VPORT_YSCALE_0()
1625 static inline uint32_t A4XX_GRAS_CL_VPORT_ZOFFSET_0(float val) A4XX_GRAS_CL_VPORT_ZOFFSET_0() argument
1627 return ((fui(val)) << A4XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_ZOFFSET_0__MASK; A4XX_GRAS_CL_VPORT_ZOFFSET_0()
1633 static inline uint32_t A4XX_GRAS_CL_VPORT_ZSCALE_0(float val) A4XX_GRAS_CL_VPORT_ZSCALE_0() argument
1635 return ((fui(val)) << A4XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_ZSCALE_0__MASK; A4XX_GRAS_CL_VPORT_ZSCALE_0()
1641 static inline uint32_t A4XX_GRAS_SU_POINT_MINMAX_MIN(float val) A4XX_GRAS_SU_POINT_MINMAX_MIN() argument
1643 return ((((uint32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A4XX_GRAS_SU_POINT_MINMAX_MIN__MASK; A4XX_GRAS_SU_POINT_MINMAX_MIN()
1647 static inline uint32_t A4XX_GRAS_SU_POINT_MINMAX_MAX(float val) A4XX_GRAS_SU_POINT_MINMAX_MAX() argument
1649 return ((((uint32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A4XX_GRAS_SU_POINT_MINMAX_MAX__MASK; A4XX_GRAS_SU_POINT_MINMAX_MAX()
1655 static inline uint32_t A4XX_GRAS_SU_POINT_SIZE(float val) A4XX_GRAS_SU_POINT_SIZE() argument
1657 return ((((int32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_SIZE__SHIFT) & A4XX_GRAS_SU_POINT_SIZE__MASK; A4XX_GRAS_SU_POINT_SIZE()
1666 static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_SCALE(float val) A4XX_GRAS_SU_POLY_OFFSET_SCALE() argument
1668 return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_SCALE__MASK; A4XX_GRAS_SU_POLY_OFFSET_SCALE()
1674 static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) A4XX_GRAS_SU_POLY_OFFSET_OFFSET() argument
1676 return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK; A4XX_GRAS_SU_POLY_OFFSET_OFFSET()
1682 static inline uint32_t A4XX_GRAS_DEPTH_CONTROL_FORMAT(enum a4xx_depth_format val) A4XX_GRAS_DEPTH_CONTROL_FORMAT() argument
1684 return ((val) << A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT) & A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK; A4XX_GRAS_DEPTH_CONTROL_FORMAT()
1693 static inline uint32_t A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val) A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH() argument
1695 return ((((int32_t)(val * 4.0))) << A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT) & A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK; A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH()
1703 static inline uint32_t A4XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val) A4XX_GRAS_SC_CONTROL_RENDER_MODE() argument
1705 return ((val) << A4XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT) & A4XX_GRAS_SC_CONTROL_RENDER_MODE__MASK; A4XX_GRAS_SC_CONTROL_RENDER_MODE()
1709 static inline uint32_t A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(uint32_t val) A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES() argument
1711 return ((val) << A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT) & A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK; A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES()
1716 static inline uint32_t A4XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val) A4XX_GRAS_SC_CONTROL_RASTER_MODE() argument
1718 return ((val) << A4XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT) & A4XX_GRAS_SC_CONTROL_RASTER_MODE__MASK; A4XX_GRAS_SC_CONTROL_RASTER_MODE()
1725 static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val) A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X() argument
1727 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK; A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X()
1731 static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y() argument
1733 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK; A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y()
1740 static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val) A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X() argument
1742 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK; A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X()
1746 static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y() argument
1748 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK; A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y()
1755 static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val) A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X() argument
1757 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK; A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X()
1761 static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y() argument
1763 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK; A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y()
1770 static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val) A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X() argument
1772 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK; A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X()
1776 static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y() argument
1778 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK; A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y()
1785 static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_BR_X(uint32_t val) A4XX_GRAS_SC_EXTENT_WINDOW_BR_X() argument
1787 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__MASK; A4XX_GRAS_SC_EXTENT_WINDOW_BR_X()
1791 static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y(uint32_t val) A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y() argument
1793 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__MASK; A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y()
1800 static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_X(uint32_t val) A4XX_GRAS_SC_EXTENT_WINDOW_TL_X() argument
1802 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__MASK; A4XX_GRAS_SC_EXTENT_WINDOW_TL_X()
1806 static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y(uint32_t val) A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y() argument
1808 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__MASK; A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y()
1836 static inline uint32_t A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val) A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE() argument
1838 return ((val) << A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK; A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE()
1846 static inline uint32_t A4XX_HLSQ_CONTROL_0_REG_CONSTMODE(uint32_t val) A4XX_HLSQ_CONTROL_0_REG_CONSTMODE() argument
1848 return ((val) << A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT) & A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK; A4XX_HLSQ_CONTROL_0_REG_CONSTMODE()
1858 static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val) A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE() argument
1860 return ((val) << A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK; A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE()
1866 static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_COORDREGID(uint32_t val) A4XX_HLSQ_CONTROL_1_REG_COORDREGID() argument
1868 return ((val) << A4XX_HLSQ_CONTROL_1_REG_COORDREGID__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_COORDREGID__MASK; A4XX_HLSQ_CONTROL_1_REG_COORDREGID()
1875 static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val) A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD() argument
1877 return ((val) << A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK; A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD()
1881 static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val) A4XX_HLSQ_CONTROL_2_REG_FACEREGID() argument
1883 return ((val) << A4XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK; A4XX_HLSQ_CONTROL_2_REG_FACEREGID()
1889 static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_REGID(uint32_t val) A4XX_HLSQ_CONTROL_3_REG_REGID() argument
1891 return ((val) << A4XX_HLSQ_CONTROL_3_REG_REGID__SHIFT) & A4XX_HLSQ_CONTROL_3_REG_REGID__MASK; A4XX_HLSQ_CONTROL_3_REG_REGID()
1897 static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val) A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH() argument
1899 return ((val) << A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK; A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH()
1903 static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET() argument
1905 return ((val) << A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET()
1909 static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET() argument
1911 return ((val) << A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK; A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET()
1915 static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val) A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH() argument
1917 return ((val) << A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK; A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH()
1923 static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val) A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH() argument
1925 return ((val) << A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK; A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH()
1929 static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET() argument
1931 return ((val) << A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET()
1935 static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET() argument
1937 return ((val) << A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK; A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET()
1941 static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val) A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH() argument
1943 return ((val) << A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK; A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH()
1949 static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH(uint32_t val) A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH() argument
1951 return ((val) << A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__MASK; A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH()
1955 static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET() argument
1957 return ((val) << A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET()
1961 static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET() argument
1963 return ((val) << A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK; A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET()
1967 static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH(uint32_t val) A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH() argument
1969 return ((val) << A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__MASK; A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH()
1975 static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH(uint32_t val) A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH() argument
1977 return ((val) << A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__MASK; A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH()
1981 static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET() argument
1983 return ((val) << A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET()
1987 static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET() argument
1989 return ((val) << A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK; A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET()
1993 static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH(uint32_t val) A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH() argument
1995 return ((val) << A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__MASK; A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH()
2001 static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH(uint32_t val) A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH() argument
2003 return ((val) << A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__MASK; A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH()
2007 static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET() argument
2009 return ((val) << A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET()
2013 static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET() argument
2015 return ((val) << A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK; A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET()
2019 static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(uint32_t val) A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH() argument
2021 return ((val) << A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__MASK; A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH()
2102 static inline uint32_t A4XX_UNKNOWN_20F7(float val) A4XX_UNKNOWN_20F7() argument
2104 return ((fui(val)) << A4XX_UNKNOWN_20F7__SHIFT) & A4XX_UNKNOWN_20F7__MASK; A4XX_UNKNOWN_20F7()
2135 static inline uint32_t A4XX_TEX_SAMP_0_XY_MAG(enum a4xx_tex_filter val) A4XX_TEX_SAMP_0_XY_MAG() argument
2137 return ((val) << A4XX_TEX_SAMP_0_XY_MAG__SHIFT) & A4XX_TEX_SAMP_0_XY_MAG__MASK; A4XX_TEX_SAMP_0_XY_MAG()
2141 static inline uint32_t A4XX_TEX_SAMP_0_XY_MIN(enum a4xx_tex_filter val) A4XX_TEX_SAMP_0_XY_MIN() argument
2143 return ((val) << A4XX_TEX_SAMP_0_XY_MIN__SHIFT) & A4XX_TEX_SAMP_0_XY_MIN__MASK; A4XX_TEX_SAMP_0_XY_MIN()
2147 static inline uint32_t A4XX_TEX_SAMP_0_WRAP_S(enum a4xx_tex_clamp val) A4XX_TEX_SAMP_0_WRAP_S() argument
2149 return ((val) << A4XX_TEX_SAMP_0_WRAP_S__SHIFT) & A4XX_TEX_SAMP_0_WRAP_S__MASK; A4XX_TEX_SAMP_0_WRAP_S()
2153 static inline uint32_t A4XX_TEX_SAMP_0_WRAP_T(enum a4xx_tex_clamp val) A4XX_TEX_SAMP_0_WRAP_T() argument
2155 return ((val) << A4XX_TEX_SAMP_0_WRAP_T__SHIFT) & A4XX_TEX_SAMP_0_WRAP_T__MASK; A4XX_TEX_SAMP_0_WRAP_T()
2159 static inline uint32_t A4XX_TEX_SAMP_0_WRAP_R(enum a4xx_tex_clamp val) A4XX_TEX_SAMP_0_WRAP_R() argument
2161 return ((val) << A4XX_TEX_SAMP_0_WRAP_R__SHIFT) & A4XX_TEX_SAMP_0_WRAP_R__MASK; A4XX_TEX_SAMP_0_WRAP_R()
2167 static inline uint32_t A4XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val) A4XX_TEX_SAMP_1_COMPARE_FUNC() argument
2169 return ((val) << A4XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK; A4XX_TEX_SAMP_1_COMPARE_FUNC()
2175 static inline uint32_t A4XX_TEX_SAMP_1_MAX_LOD(float val) A4XX_TEX_SAMP_1_MAX_LOD() argument
2177 return ((((uint32_t)(val * 256.0))) << A4XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A4XX_TEX_SAMP_1_MAX_LOD__MASK; A4XX_TEX_SAMP_1_MAX_LOD()
2181 static inline uint32_t A4XX_TEX_SAMP_1_MIN_LOD(float val) A4XX_TEX_SAMP_1_MIN_LOD() argument
2183 return ((((uint32_t)(val * 256.0))) << A4XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A4XX_TEX_SAMP_1_MIN_LOD__MASK; A4XX_TEX_SAMP_1_MIN_LOD()
2190 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_X(enum a4xx_tex_swiz val) A4XX_TEX_CONST_0_SWIZ_X() argument
2192 return ((val) << A4XX_TEX_CONST_0_SWIZ_X__SHIFT) & A4XX_TEX_CONST_0_SWIZ_X__MASK; A4XX_TEX_CONST_0_SWIZ_X()
2196 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_Y(enum a4xx_tex_swiz val) A4XX_TEX_CONST_0_SWIZ_Y() argument
2198 return ((val) << A4XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A4XX_TEX_CONST_0_SWIZ_Y__MASK; A4XX_TEX_CONST_0_SWIZ_Y()
2202 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_Z(enum a4xx_tex_swiz val) A4XX_TEX_CONST_0_SWIZ_Z() argument
2204 return ((val) << A4XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A4XX_TEX_CONST_0_SWIZ_Z__MASK; A4XX_TEX_CONST_0_SWIZ_Z()
2208 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_W(enum a4xx_tex_swiz val) A4XX_TEX_CONST_0_SWIZ_W() argument
2210 return ((val) << A4XX_TEX_CONST_0_SWIZ_W__SHIFT) & A4XX_TEX_CONST_0_SWIZ_W__MASK; A4XX_TEX_CONST_0_SWIZ_W()
2214 static inline uint32_t A4XX_TEX_CONST_0_MIPLVLS(uint32_t val) A4XX_TEX_CONST_0_MIPLVLS() argument
2216 return ((val) << A4XX_TEX_CONST_0_MIPLVLS__SHIFT) & A4XX_TEX_CONST_0_MIPLVLS__MASK; A4XX_TEX_CONST_0_MIPLVLS()
2220 static inline uint32_t A4XX_TEX_CONST_0_FMT(enum a4xx_tex_fmt val) A4XX_TEX_CONST_0_FMT() argument
2222 return ((val) << A4XX_TEX_CONST_0_FMT__SHIFT) & A4XX_TEX_CONST_0_FMT__MASK; A4XX_TEX_CONST_0_FMT()
2226 static inline uint32_t A4XX_TEX_CONST_0_TYPE(enum a4xx_tex_type val) A4XX_TEX_CONST_0_TYPE() argument
2228 return ((val) << A4XX_TEX_CONST_0_TYPE__SHIFT) & A4XX_TEX_CONST_0_TYPE__MASK; A4XX_TEX_CONST_0_TYPE()
2234 static inline uint32_t A4XX_TEX_CONST_1_HEIGHT(uint32_t val) A4XX_TEX_CONST_1_HEIGHT() argument
2236 return ((val) << A4XX_TEX_CONST_1_HEIGHT__SHIFT) & A4XX_TEX_CONST_1_HEIGHT__MASK; A4XX_TEX_CONST_1_HEIGHT()
2240 static inline uint32_t A4XX_TEX_CONST_1_WIDTH(uint32_t val) A4XX_TEX_CONST_1_WIDTH() argument
2242 return ((val) << A4XX_TEX_CONST_1_WIDTH__SHIFT) & A4XX_TEX_CONST_1_WIDTH__MASK; A4XX_TEX_CONST_1_WIDTH()
2248 static inline uint32_t A4XX_TEX_CONST_2_FETCHSIZE(enum a4xx_tex_fetchsize val) A4XX_TEX_CONST_2_FETCHSIZE() argument
2250 return ((val) << A4XX_TEX_CONST_2_FETCHSIZE__SHIFT) & A4XX_TEX_CONST_2_FETCHSIZE__MASK; A4XX_TEX_CONST_2_FETCHSIZE()
2254 static inline uint32_t A4XX_TEX_CONST_2_PITCH(uint32_t val) A4XX_TEX_CONST_2_PITCH() argument
2256 return ((val) << A4XX_TEX_CONST_2_PITCH__SHIFT) & A4XX_TEX_CONST_2_PITCH__MASK; A4XX_TEX_CONST_2_PITCH()
2260 static inline uint32_t A4XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val) A4XX_TEX_CONST_2_SWAP() argument
2262 return ((val) << A4XX_TEX_CONST_2_SWAP__SHIFT) & A4XX_TEX_CONST_2_SWAP__MASK; A4XX_TEX_CONST_2_SWAP()
2268 static inline uint32_t A4XX_TEX_CONST_3_LAYERSZ(uint32_t val) A4XX_TEX_CONST_3_LAYERSZ() argument
2270 return ((val >> 12) << A4XX_TEX_CONST_3_LAYERSZ__SHIFT) & A4XX_TEX_CONST_3_LAYERSZ__MASK; A4XX_TEX_CONST_3_LAYERSZ()
2274 static inline uint32_t A4XX_TEX_CONST_3_DEPTH(uint32_t val) A4XX_TEX_CONST_3_DEPTH() argument
2276 return ((val) << A4XX_TEX_CONST_3_DEPTH__SHIFT) & A4XX_TEX_CONST_3_DEPTH__MASK; A4XX_TEX_CONST_3_DEPTH()
2282 static inline uint32_t A4XX_TEX_CONST_4_LAYERSZ(uint32_t val) A4XX_TEX_CONST_4_LAYERSZ() argument
2284 return ((val >> 12) << A4XX_TEX_CONST_4_LAYERSZ__SHIFT) & A4XX_TEX_CONST_4_LAYERSZ__MASK; A4XX_TEX_CONST_4_LAYERSZ()
2288 static inline uint32_t A4XX_TEX_CONST_4_BASE(uint32_t val) A4XX_TEX_CONST_4_BASE() argument
2290 return ((val >> 5) << A4XX_TEX_CONST_4_BASE__SHIFT) & A4XX_TEX_CONST_4_BASE__MASK; A4XX_TEX_CONST_4_BASE()
H A Dadreno_pm4.xml.h217 static inline uint32_t CP_LOAD_STATE_0_DST_OFF(uint32_t val) CP_LOAD_STATE_0_DST_OFF() argument
219 return ((val) << CP_LOAD_STATE_0_DST_OFF__SHIFT) & CP_LOAD_STATE_0_DST_OFF__MASK; CP_LOAD_STATE_0_DST_OFF()
223 static inline uint32_t CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val) CP_LOAD_STATE_0_STATE_SRC() argument
225 return ((val) << CP_LOAD_STATE_0_STATE_SRC__SHIFT) & CP_LOAD_STATE_0_STATE_SRC__MASK; CP_LOAD_STATE_0_STATE_SRC()
229 static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val) CP_LOAD_STATE_0_STATE_BLOCK() argument
231 return ((val) << CP_LOAD_STATE_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE_0_STATE_BLOCK__MASK; CP_LOAD_STATE_0_STATE_BLOCK()
235 static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val) CP_LOAD_STATE_0_NUM_UNIT() argument
237 return ((val) << CP_LOAD_STATE_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE_0_NUM_UNIT__MASK; CP_LOAD_STATE_0_NUM_UNIT()
243 static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val) CP_LOAD_STATE_1_STATE_TYPE() argument
245 return ((val) << CP_LOAD_STATE_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE_1_STATE_TYPE__MASK; CP_LOAD_STATE_1_STATE_TYPE()
249 static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val) CP_LOAD_STATE_1_EXT_SRC_ADDR() argument
251 return ((val >> 2) << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK; CP_LOAD_STATE_1_EXT_SRC_ADDR()
257 static inline uint32_t CP_DRAW_INDX_0_VIZ_QUERY(uint32_t val) CP_DRAW_INDX_0_VIZ_QUERY() argument
259 return ((val) << CP_DRAW_INDX_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_0_VIZ_QUERY__MASK; CP_DRAW_INDX_0_VIZ_QUERY()
265 static inline uint32_t CP_DRAW_INDX_1_PRIM_TYPE(enum pc_di_primtype val) CP_DRAW_INDX_1_PRIM_TYPE() argument
267 return ((val) << CP_DRAW_INDX_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_1_PRIM_TYPE__MASK; CP_DRAW_INDX_1_PRIM_TYPE()
271 static inline uint32_t CP_DRAW_INDX_1_SOURCE_SELECT(enum pc_di_src_sel val) CP_DRAW_INDX_1_SOURCE_SELECT() argument
273 return ((val) << CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_1_SOURCE_SELECT__MASK; CP_DRAW_INDX_1_SOURCE_SELECT()
277 static inline uint32_t CP_DRAW_INDX_1_VIS_CULL(enum pc_di_vis_cull_mode val) CP_DRAW_INDX_1_VIS_CULL() argument
279 return ((val) << CP_DRAW_INDX_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_1_VIS_CULL__MASK; CP_DRAW_INDX_1_VIS_CULL()
283 static inline uint32_t CP_DRAW_INDX_1_INDEX_SIZE(enum pc_di_index_size val) CP_DRAW_INDX_1_INDEX_SIZE() argument
285 return ((val) << CP_DRAW_INDX_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_1_INDEX_SIZE__MASK; CP_DRAW_INDX_1_INDEX_SIZE()
292 static inline uint32_t CP_DRAW_INDX_1_NUM_INSTANCES(uint32_t val) CP_DRAW_INDX_1_NUM_INSTANCES() argument
294 return ((val) << CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_1_NUM_INSTANCES__MASK; CP_DRAW_INDX_1_NUM_INSTANCES()
300 static inline uint32_t CP_DRAW_INDX_2_NUM_INDICES(uint32_t val) CP_DRAW_INDX_2_NUM_INDICES() argument
302 return ((val) << CP_DRAW_INDX_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_NUM_INDICES__MASK; CP_DRAW_INDX_2_NUM_INDICES()
308 static inline uint32_t CP_DRAW_INDX_3_INDX_BASE(uint32_t val) CP_DRAW_INDX_3_INDX_BASE() argument
310 return ((val) << CP_DRAW_INDX_3_INDX_BASE__SHIFT) & CP_DRAW_INDX_3_INDX_BASE__MASK; CP_DRAW_INDX_3_INDX_BASE()
316 static inline uint32_t CP_DRAW_INDX_4_INDX_SIZE(uint32_t val) CP_DRAW_INDX_4_INDX_SIZE() argument
318 return ((val) << CP_DRAW_INDX_4_INDX_SIZE__SHIFT) & CP_DRAW_INDX_4_INDX_SIZE__MASK; CP_DRAW_INDX_4_INDX_SIZE()
324 static inline uint32_t CP_DRAW_INDX_2_0_VIZ_QUERY(uint32_t val) CP_DRAW_INDX_2_0_VIZ_QUERY() argument
326 return ((val) << CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_2_0_VIZ_QUERY__MASK; CP_DRAW_INDX_2_0_VIZ_QUERY()
332 static inline uint32_t CP_DRAW_INDX_2_1_PRIM_TYPE(enum pc_di_primtype val) CP_DRAW_INDX_2_1_PRIM_TYPE() argument
334 return ((val) << CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_2_1_PRIM_TYPE__MASK; CP_DRAW_INDX_2_1_PRIM_TYPE()
338 static inline uint32_t CP_DRAW_INDX_2_1_SOURCE_SELECT(enum pc_di_src_sel val) CP_DRAW_INDX_2_1_SOURCE_SELECT() argument
340 return ((val) << CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK; CP_DRAW_INDX_2_1_SOURCE_SELECT()
344 static inline uint32_t CP_DRAW_INDX_2_1_VIS_CULL(enum pc_di_vis_cull_mode val) CP_DRAW_INDX_2_1_VIS_CULL() argument
346 return ((val) << CP_DRAW_INDX_2_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_2_1_VIS_CULL__MASK; CP_DRAW_INDX_2_1_VIS_CULL()
350 static inline uint32_t CP_DRAW_INDX_2_1_INDEX_SIZE(enum pc_di_index_size val) CP_DRAW_INDX_2_1_INDEX_SIZE() argument
352 return ((val) << CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_2_1_INDEX_SIZE__MASK; CP_DRAW_INDX_2_1_INDEX_SIZE()
359 static inline uint32_t CP_DRAW_INDX_2_1_NUM_INSTANCES(uint32_t val) CP_DRAW_INDX_2_1_NUM_INSTANCES() argument
361 return ((val) << CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK; CP_DRAW_INDX_2_1_NUM_INSTANCES()
367 static inline uint32_t CP_DRAW_INDX_2_2_NUM_INDICES(uint32_t val) CP_DRAW_INDX_2_2_NUM_INDICES() argument
369 return ((val) << CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_2_NUM_INDICES__MASK; CP_DRAW_INDX_2_2_NUM_INDICES()
375 static inline uint32_t CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(enum pc_di_primtype val) CP_DRAW_INDX_OFFSET_0_PRIM_TYPE() argument
377 return ((val) << CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK; CP_DRAW_INDX_OFFSET_0_PRIM_TYPE()
381 static inline uint32_t CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel val) CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT() argument
383 return ((val) << CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK; CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT()
387 static inline uint32_t CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum a4xx_index_size val) CP_DRAW_INDX_OFFSET_0_INDEX_SIZE() argument
389 return ((val) << CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK; CP_DRAW_INDX_OFFSET_0_INDEX_SIZE()
395 static inline uint32_t CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES(uint32_t val) CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES() argument
397 return ((val) << CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK; CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES()
403 static inline uint32_t CP_DRAW_INDX_OFFSET_2_NUM_INDICES(uint32_t val) CP_DRAW_INDX_OFFSET_2_NUM_INDICES() argument
405 return ((val) << CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK; CP_DRAW_INDX_OFFSET_2_NUM_INDICES()
413 static inline uint32_t CP_DRAW_INDX_OFFSET_4_INDX_BASE(uint32_t val) CP_DRAW_INDX_OFFSET_4_INDX_BASE() argument
415 return ((val) << CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT) & CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK; CP_DRAW_INDX_OFFSET_4_INDX_BASE()
421 static inline uint32_t CP_DRAW_INDX_OFFSET_5_INDX_SIZE(uint32_t val) CP_DRAW_INDX_OFFSET_5_INDX_SIZE() argument
423 return ((val) << CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK; CP_DRAW_INDX_OFFSET_5_INDX_SIZE()
429 static inline uint32_t CP_SET_DRAW_STATE_0_COUNT(uint32_t val) CP_SET_DRAW_STATE_0_COUNT() argument
431 return ((val) << CP_SET_DRAW_STATE_0_COUNT__SHIFT) & CP_SET_DRAW_STATE_0_COUNT__MASK; CP_SET_DRAW_STATE_0_COUNT()
439 static inline uint32_t CP_SET_DRAW_STATE_0_GROUP_ID(uint32_t val) CP_SET_DRAW_STATE_0_GROUP_ID() argument
441 return ((val) << CP_SET_DRAW_STATE_0_GROUP_ID__SHIFT) & CP_SET_DRAW_STATE_0_GROUP_ID__MASK; CP_SET_DRAW_STATE_0_GROUP_ID()
447 static inline uint32_t CP_SET_DRAW_STATE_1_ADDR(uint32_t val) CP_SET_DRAW_STATE_1_ADDR() argument
449 return ((val) << CP_SET_DRAW_STATE_1_ADDR__SHIFT) & CP_SET_DRAW_STATE_1_ADDR__MASK; CP_SET_DRAW_STATE_1_ADDR()
457 static inline uint32_t CP_SET_BIN_1_X1(uint32_t val) CP_SET_BIN_1_X1() argument
459 return ((val) << CP_SET_BIN_1_X1__SHIFT) & CP_SET_BIN_1_X1__MASK; CP_SET_BIN_1_X1()
463 static inline uint32_t CP_SET_BIN_1_Y1(uint32_t val) CP_SET_BIN_1_Y1() argument
465 return ((val) << CP_SET_BIN_1_Y1__SHIFT) & CP_SET_BIN_1_Y1__MASK; CP_SET_BIN_1_Y1()
471 static inline uint32_t CP_SET_BIN_2_X2(uint32_t val) CP_SET_BIN_2_X2() argument
473 return ((val) << CP_SET_BIN_2_X2__SHIFT) & CP_SET_BIN_2_X2__MASK; CP_SET_BIN_2_X2()
477 static inline uint32_t CP_SET_BIN_2_Y2(uint32_t val) CP_SET_BIN_2_Y2() argument
479 return ((val) << CP_SET_BIN_2_Y2__SHIFT) & CP_SET_BIN_2_Y2__MASK; CP_SET_BIN_2_Y2()
485 static inline uint32_t CP_SET_BIN_DATA_0_BIN_DATA_ADDR(uint32_t val) CP_SET_BIN_DATA_0_BIN_DATA_ADDR() argument
487 return ((val) << CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT) & CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK; CP_SET_BIN_DATA_0_BIN_DATA_ADDR()
493 static inline uint32_t CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(uint32_t val) CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS() argument
495 return ((val) << CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT) & CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK; CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS()
H A Dadreno_common.xml.h157 static inline uint32_t AXXX_CP_RB_CNTL_BUFSZ(uint32_t val) AXXX_CP_RB_CNTL_BUFSZ() argument
159 return ((val) << AXXX_CP_RB_CNTL_BUFSZ__SHIFT) & AXXX_CP_RB_CNTL_BUFSZ__MASK; AXXX_CP_RB_CNTL_BUFSZ()
163 static inline uint32_t AXXX_CP_RB_CNTL_BLKSZ(uint32_t val) AXXX_CP_RB_CNTL_BLKSZ() argument
165 return ((val) << AXXX_CP_RB_CNTL_BLKSZ__SHIFT) & AXXX_CP_RB_CNTL_BLKSZ__MASK; AXXX_CP_RB_CNTL_BLKSZ()
169 static inline uint32_t AXXX_CP_RB_CNTL_BUF_SWAP(uint32_t val) AXXX_CP_RB_CNTL_BUF_SWAP() argument
171 return ((val) << AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT) & AXXX_CP_RB_CNTL_BUF_SWAP__MASK; AXXX_CP_RB_CNTL_BUF_SWAP()
180 static inline uint32_t AXXX_CP_RB_RPTR_ADDR_SWAP(uint32_t val) AXXX_CP_RB_RPTR_ADDR_SWAP() argument
182 return ((val) << AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT) & AXXX_CP_RB_RPTR_ADDR_SWAP__MASK; AXXX_CP_RB_RPTR_ADDR_SWAP()
186 static inline uint32_t AXXX_CP_RB_RPTR_ADDR_ADDR(uint32_t val) AXXX_CP_RB_RPTR_ADDR_ADDR() argument
188 return ((val >> 2) << AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT) & AXXX_CP_RB_RPTR_ADDR_ADDR__MASK; AXXX_CP_RB_RPTR_ADDR_ADDR()
204 static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(uint32_t val) AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START() argument
206 return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK; AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START()
210 static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(uint32_t val) AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START() argument
212 return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK; AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START()
216 static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START(uint32_t val) AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START() argument
218 return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK; AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START()
224 static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_MEQ_END(uint32_t val) AXXX_CP_MEQ_THRESHOLDS_MEQ_END() argument
226 return ((val) << AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT) & AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK; AXXX_CP_MEQ_THRESHOLDS_MEQ_END()
230 static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_ROQ_END(uint32_t val) AXXX_CP_MEQ_THRESHOLDS_ROQ_END() argument
232 return ((val) << AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT) & AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK; AXXX_CP_MEQ_THRESHOLDS_ROQ_END()
238 static inline uint32_t AXXX_CP_CSQ_AVAIL_RING(uint32_t val) AXXX_CP_CSQ_AVAIL_RING() argument
240 return ((val) << AXXX_CP_CSQ_AVAIL_RING__SHIFT) & AXXX_CP_CSQ_AVAIL_RING__MASK; AXXX_CP_CSQ_AVAIL_RING()
244 static inline uint32_t AXXX_CP_CSQ_AVAIL_IB1(uint32_t val) AXXX_CP_CSQ_AVAIL_IB1() argument
246 return ((val) << AXXX_CP_CSQ_AVAIL_IB1__SHIFT) & AXXX_CP_CSQ_AVAIL_IB1__MASK; AXXX_CP_CSQ_AVAIL_IB1()
250 static inline uint32_t AXXX_CP_CSQ_AVAIL_IB2(uint32_t val) AXXX_CP_CSQ_AVAIL_IB2() argument
252 return ((val) << AXXX_CP_CSQ_AVAIL_IB2__SHIFT) & AXXX_CP_CSQ_AVAIL_IB2__MASK; AXXX_CP_CSQ_AVAIL_IB2()
258 static inline uint32_t AXXX_CP_STQ_AVAIL_ST(uint32_t val) AXXX_CP_STQ_AVAIL_ST() argument
260 return ((val) << AXXX_CP_STQ_AVAIL_ST__SHIFT) & AXXX_CP_STQ_AVAIL_ST__MASK; AXXX_CP_STQ_AVAIL_ST()
266 static inline uint32_t AXXX_CP_MEQ_AVAIL_MEQ(uint32_t val) AXXX_CP_MEQ_AVAIL_MEQ() argument
268 return ((val) << AXXX_CP_MEQ_AVAIL_MEQ__SHIFT) & AXXX_CP_MEQ_AVAIL_MEQ__MASK; AXXX_CP_MEQ_AVAIL_MEQ()
274 static inline uint32_t AXXX_SCRATCH_UMSK_UMSK(uint32_t val) AXXX_SCRATCH_UMSK_UMSK() argument
276 return ((val) << AXXX_SCRATCH_UMSK_UMSK__SHIFT) & AXXX_SCRATCH_UMSK_UMSK__MASK; AXXX_SCRATCH_UMSK_UMSK()
280 static inline uint32_t AXXX_SCRATCH_UMSK_SWAP(uint32_t val) AXXX_SCRATCH_UMSK_SWAP() argument
282 return ((val) << AXXX_SCRATCH_UMSK_SWAP__SHIFT) & AXXX_SCRATCH_UMSK_SWAP__MASK; AXXX_SCRATCH_UMSK_SWAP()
324 static inline uint32_t AXXX_CP_CSQ_RB_STAT_RPTR(uint32_t val) AXXX_CP_CSQ_RB_STAT_RPTR() argument
326 return ((val) << AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_RPTR__MASK; AXXX_CP_CSQ_RB_STAT_RPTR()
330 static inline uint32_t AXXX_CP_CSQ_RB_STAT_WPTR(uint32_t val) AXXX_CP_CSQ_RB_STAT_WPTR() argument
332 return ((val) << AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_WPTR__MASK; AXXX_CP_CSQ_RB_STAT_WPTR()
338 static inline uint32_t AXXX_CP_CSQ_IB1_STAT_RPTR(uint32_t val) AXXX_CP_CSQ_IB1_STAT_RPTR() argument
340 return ((val) << AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_RPTR__MASK; AXXX_CP_CSQ_IB1_STAT_RPTR()
344 static inline uint32_t AXXX_CP_CSQ_IB1_STAT_WPTR(uint32_t val) AXXX_CP_CSQ_IB1_STAT_WPTR() argument
346 return ((val) << AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_WPTR__MASK; AXXX_CP_CSQ_IB1_STAT_WPTR()
352 static inline uint32_t AXXX_CP_CSQ_IB2_STAT_RPTR(uint32_t val) AXXX_CP_CSQ_IB2_STAT_RPTR() argument
354 return ((val) << AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_RPTR__MASK; AXXX_CP_CSQ_IB2_STAT_RPTR()
358 static inline uint32_t AXXX_CP_CSQ_IB2_STAT_WPTR(uint32_t val) AXXX_CP_CSQ_IB2_STAT_WPTR() argument
360 return ((val) << AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_WPTR__MASK; AXXX_CP_CSQ_IB2_STAT_WPTR()
/linux-4.1.27/arch/alpha/include/uapi/asm/
H A Dcompiler.h13 # define __kernel_insbl(val, shift) __builtin_alpha_insbl(val, shift)
14 # define __kernel_inswl(val, shift) __builtin_alpha_inswl(val, shift)
15 # define __kernel_insql(val, shift) __builtin_alpha_insql(val, shift)
16 # define __kernel_inslh(val, shift) __builtin_alpha_inslh(val, shift)
17 # define __kernel_extbl(val, shift) __builtin_alpha_extbl(val, shift)
18 # define __kernel_extwl(val, shift) __builtin_alpha_extwl(val, shift)
21 # define __kernel_insbl(val, shift) \
23 __asm__("insbl %2,%1,%0" : "=r"(__kir) : "rI"(shift), "r"(val)); \
25 # define __kernel_inswl(val, shift) \
27 __asm__("inswl %2,%1,%0" : "=r"(__kir) : "rI"(shift), "r"(val)); \
29 # define __kernel_insql(val, shift) \
31 __asm__("insql %2,%1,%0" : "=r"(__kir) : "rI"(shift), "r"(val)); \
33 # define __kernel_inslh(val, shift) \
35 __asm__("inslh %2,%1,%0" : "=r"(__kir) : "rI"(shift), "r"(val)); \
37 # define __kernel_extbl(val, shift) \
39 __asm__("extbl %2,%1,%0" : "=r"(__kir) : "rI"(shift), "r"(val)); \
41 # define __kernel_extwl(val, shift) \
43 __asm__("extwl %2,%1,%0" : "=r"(__kir) : "rI"(shift), "r"(val)); \
95 #define __kernel_stb(val,mem) ((mem) = (val))
96 #define __kernel_stw(val,mem) ((mem) = (val))
108 #define __kernel_stb(val,mem) \
110 stb %1,%0" : "=m"(mem) : "r"(val))
111 #define __kernel_stw(val,mem) \
113 stw %1,%0" : "=m"(mem) : "r"(val))
/linux-4.1.27/arch/arm/mach-iop13xx/include/mach/
H A Dtime.h73 u32 val; read_tmr0() local
74 asm volatile("mrc p6, 0, %0, c0, c9, 0" : "=r" (val)); read_tmr0()
75 return val; read_tmr0()
78 static inline void write_tmr0(u32 val) write_tmr0() argument
80 asm volatile("mcr p6, 0, %0, c0, c9, 0" : : "r" (val)); write_tmr0()
83 static inline void write_tmr1(u32 val) write_tmr1() argument
85 asm volatile("mcr p6, 0, %0, c1, c9, 0" : : "r" (val)); write_tmr1()
90 u32 val; read_tcr0() local
91 asm volatile("mrc p6, 0, %0, c2, c9, 0" : "=r" (val)); read_tcr0()
92 return val; read_tcr0()
95 static inline void write_tcr0(u32 val) write_tcr0() argument
97 asm volatile("mcr p6, 0, %0, c2, c9, 0" : : "r" (val)); write_tcr0()
102 u32 val; read_tcr1() local
103 asm volatile("mrc p6, 0, %0, c3, c9, 0" : "=r" (val)); read_tcr1()
104 return val; read_tcr1()
107 static inline void write_tcr1(u32 val) write_tcr1() argument
109 asm volatile("mcr p6, 0, %0, c3, c9, 0" : : "r" (val)); write_tcr1()
112 static inline void write_trr0(u32 val) write_trr0() argument
114 asm volatile("mcr p6, 0, %0, c4, c9, 0" : : "r" (val)); write_trr0()
117 static inline void write_trr1(u32 val) write_trr1() argument
119 asm volatile("mcr p6, 0, %0, c5, c9, 0" : : "r" (val)); write_trr1()
122 static inline void write_tisr(u32 val) write_tisr() argument
124 asm volatile("mcr p6, 0, %0, c6, c9, 0" : : "r" (val)); write_tisr()
/linux-4.1.27/arch/mips/pci/
H A Dpci-bcm63xx.c109 static void bcm63xx_int_cfg_writel(u32 val, u32 reg) bcm63xx_int_cfg_writel() argument
116 bcm_mpi_writel(val, MPI_PCICFGDATA_REG); bcm63xx_int_cfg_writel()
123 u32 val; bcm63xx_reset_pcie() local
132 val = bcm_misc_readl(reg); bcm63xx_reset_pcie()
133 val |= SERDES_PCIE_EN | SERDES_PCIE_EXD_EN; bcm63xx_reset_pcie()
134 bcm_misc_writel(val, reg); bcm63xx_reset_pcie()
152 u32 val; bcm63xx_register_pcie() local
164 val = bcm_pcie_readl(PCIE_BRIDGE_OPT1_REG); bcm63xx_register_pcie()
165 val |= OPT1_RD_BE_OPT_EN; bcm63xx_register_pcie()
166 val |= OPT1_RD_REPLY_BE_FIX_EN; bcm63xx_register_pcie()
167 val |= OPT1_PCIE_BRIDGE_HOLE_DET_EN; bcm63xx_register_pcie()
168 val |= OPT1_L1_INT_STATUS_MASK_POL; bcm63xx_register_pcie()
169 bcm_pcie_writel(val, PCIE_BRIDGE_OPT1_REG); bcm63xx_register_pcie()
172 val = bcm_pcie_readl(PCIE_BRIDGE_RC_INT_MASK_REG); bcm63xx_register_pcie()
173 val |= PCIE_RC_INT_A | PCIE_RC_INT_B | PCIE_RC_INT_C | PCIE_RC_INT_D; bcm63xx_register_pcie()
174 bcm_pcie_writel(val, PCIE_BRIDGE_RC_INT_MASK_REG); bcm63xx_register_pcie()
176 val = bcm_pcie_readl(PCIE_BRIDGE_OPT2_REG); bcm63xx_register_pcie()
178 val |= OPT2_TX_CREDIT_CHK_EN; bcm63xx_register_pcie()
179 val |= OPT2_UBUS_UR_DECODE_DIS; bcm63xx_register_pcie()
182 val |= (PCIE_BUS_DEVICE << OPT2_CFG_TYPE1_BUS_NO_SHIFT); bcm63xx_register_pcie()
183 val |= OPT2_CFG_TYPE1_BD_SEL; bcm63xx_register_pcie()
184 bcm_pcie_writel(val, PCIE_BRIDGE_OPT2_REG); bcm63xx_register_pcie()
187 val = bcm_pcie_readl(PCIE_IDVAL3_REG); bcm63xx_register_pcie()
188 val &= ~IDVAL3_CLASS_CODE_MASK; bcm63xx_register_pcie()
189 val |= (PCI_CLASS_BRIDGE_PCI << IDVAL3_SUBCLASS_SHIFT); bcm63xx_register_pcie()
190 bcm_pcie_writel(val, PCIE_IDVAL3_REG); bcm63xx_register_pcie()
193 val = bcm_pcie_readl(PCIE_CONFIG2_REG); bcm63xx_register_pcie()
194 val &= ~CONFIG2_BAR1_SIZE_MASK; bcm63xx_register_pcie()
195 bcm_pcie_writel(val, PCIE_CONFIG2_REG); bcm63xx_register_pcie()
198 val = (BCM_PCIE_MEM_BASE_PA >> 20) << BASEMASK_BASE_SHIFT; bcm63xx_register_pcie()
199 val |= (BCM_PCIE_MEM_BASE_PA >> 20) << BASEMASK_MASK_SHIFT; bcm63xx_register_pcie()
200 val |= BASEMASK_REMAP_EN; bcm63xx_register_pcie()
201 bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_BASEMASK_REG); bcm63xx_register_pcie()
203 val = (BCM_PCIE_MEM_BASE_PA >> 20) << REBASE_ADDR_BASE_SHIFT; bcm63xx_register_pcie()
204 bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_REBASE_ADDR_REG); bcm63xx_register_pcie()
214 u32 val; bcm63xx_register_pci() local
229 val = BCM_PCI_MEM_BASE_PA & MPI_L2P_BASE_MASK; bcm63xx_register_pci()
230 bcm_mpi_writel(val, MPI_L2PMEMBASE1_REG); bcm63xx_register_pci()
232 bcm_mpi_writel(val | MPI_L2PREMAP_ENABLED_MASK, MPI_L2PMEMREMAP1_REG); bcm63xx_register_pci()
236 val = bcm_pcmcia_readl(PCMCIA_C1_REG); bcm63xx_register_pci()
237 val &= ~PCMCIA_C1_CBIDSEL_MASK; bcm63xx_register_pci()
238 val |= (CARDBUS_PCI_IDSEL << PCMCIA_C1_CBIDSEL_SHIFT); bcm63xx_register_pci()
239 bcm_pcmcia_writel(val, PCMCIA_C1_REG); bcm63xx_register_pci()
243 val = BCM_CB_MEM_BASE_PA & MPI_L2P_BASE_MASK; bcm63xx_register_pci()
244 bcm_mpi_writel(val, MPI_L2PMEMBASE2_REG); bcm63xx_register_pci()
246 val |= MPI_L2PREMAP_ENABLED_MASK | MPI_L2PREMAP_IS_CARDBUS_MASK; bcm63xx_register_pci()
247 bcm_mpi_writel(val, MPI_L2PMEMREMAP2_REG); bcm63xx_register_pci()
258 val = BCM_PCI_IO_BASE_PA & MPI_L2P_BASE_MASK; bcm63xx_register_pci()
259 bcm_mpi_writel(val, MPI_L2PIOBASE_REG); bcm63xx_register_pci()
261 bcm_mpi_writel(val | MPI_L2PREMAP_ENABLED_MASK, MPI_L2PIOREMAP_REG); bcm63xx_register_pci()
270 val = MPI_SP0_REMAP_ENABLE_MASK; bcm63xx_register_pci()
272 val = 0; bcm63xx_register_pci()
273 bcm_mpi_writel(val, MPI_SP0_REMAP_REG); bcm63xx_register_pci()
296 val = bcm63xx_int_cfg_readl(BCMPCI_REG_TIMERS); bcm63xx_register_pci()
297 val &= ~REG_TIMER_RETRY_MASK; bcm63xx_register_pci()
298 bcm63xx_int_cfg_writel(val, BCMPCI_REG_TIMERS); bcm63xx_register_pci()
301 val = bcm63xx_int_cfg_readl(PCI_COMMAND); bcm63xx_register_pci()
302 val |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); bcm63xx_register_pci()
303 bcm63xx_int_cfg_writel(val, PCI_COMMAND); bcm63xx_register_pci()
307 val = bcm_mpi_readl(MPI_PCIMODESEL_REG); bcm63xx_register_pci()
308 val &= ~MPI_PCIMODESEL_BAR1_NOSWAP_MASK; bcm63xx_register_pci()
309 val &= ~MPI_PCIMODESEL_BAR2_NOSWAP_MASK; bcm63xx_register_pci()
310 val &= ~MPI_PCIMODESEL_PREFETCH_MASK; bcm63xx_register_pci()
311 val |= (8 << MPI_PCIMODESEL_PREFETCH_SHIFT); bcm63xx_register_pci()
312 bcm_mpi_writel(val, MPI_PCIMODESEL_REG); bcm63xx_register_pci()
315 val = bcm_mpi_readl(MPI_LOCINT_REG); bcm63xx_register_pci()
316 val |= MPI_LOCINT_MASK(MPI_LOCINT_EXT_PCI_INT); bcm63xx_register_pci()
317 bcm_mpi_writel(val, MPI_LOCINT_REG); bcm63xx_register_pci()
H A Dpci-vr41xx.c118 uint32_t val; vr41xx_pciu_init() local
166 val = IBA(master->bus_base_address) | vr41xx_pciu_init()
170 pciu_write(PCIMMAW1REG, val); vr41xx_pciu_init()
172 val = pciu_read(PCIMMAW1REG); vr41xx_pciu_init()
173 val &= ~WINEN; vr41xx_pciu_init()
174 pciu_write(PCIMMAW1REG, val); vr41xx_pciu_init()
179 val = IBA(master->bus_base_address) | vr41xx_pciu_init()
183 pciu_write(PCIMMAW2REG, val); vr41xx_pciu_init()
185 val = pciu_read(PCIMMAW2REG); vr41xx_pciu_init()
186 val &= ~WINEN; vr41xx_pciu_init()
187 pciu_write(PCIMMAW2REG, val); vr41xx_pciu_init()
192 val = TARGET_MSK(target->address_mask) | vr41xx_pciu_init()
195 pciu_write(PCITAW1REG, val); vr41xx_pciu_init()
197 val = pciu_read(PCITAW1REG); vr41xx_pciu_init()
198 val &= ~WINEN; vr41xx_pciu_init()
199 pciu_write(PCITAW1REG, val); vr41xx_pciu_init()
204 val = TARGET_MSK(target->address_mask) | vr41xx_pciu_init()
207 pciu_write(PCITAW2REG, val); vr41xx_pciu_init()
209 val = pciu_read(PCITAW2REG); vr41xx_pciu_init()
210 val &= ~WINEN; vr41xx_pciu_init()
211 pciu_write(PCITAW2REG, val); vr41xx_pciu_init()
216 val = IBA(master->bus_base_address) | vr41xx_pciu_init()
220 pciu_write(PCIMIOAWREG, val); vr41xx_pciu_init()
222 val = pciu_read(PCIMIOAWREG); vr41xx_pciu_init()
223 val &= ~WINEN; vr41xx_pciu_init()
224 pciu_write(PCIMIOAWREG, val); vr41xx_pciu_init()
239 val = MBADD(mailbox->base_address) | TYPE_32BITSPACE | vr41xx_pciu_init()
241 pciu_write(MAILBAREG, val); vr41xx_pciu_init()
246 val = PMBA(window->base_address) | TYPE_32BITSPACE | vr41xx_pciu_init()
248 pciu_write(PCIMBA1REG, val); vr41xx_pciu_init()
253 val = PMBA(window->base_address) | TYPE_32BITSPACE | vr41xx_pciu_init()
255 pciu_write(PCIMBA2REG, val); vr41xx_pciu_init()
258 val = pciu_read(RETVALREG); vr41xx_pciu_init()
259 val &= ~RTYVAL_MASK; vr41xx_pciu_init()
260 val |= RTYVAL(setup->retry_limit); vr41xx_pciu_init()
261 pciu_write(RETVALREG, val); vr41xx_pciu_init()
263 val = pciu_read(PCIAPCNTREG); vr41xx_pciu_init()
264 val &= ~(TKYGNT | PAPC); vr41xx_pciu_init()
268 val |= PAPC_ALTERNATE_0; vr41xx_pciu_init()
271 val |= PAPC_ALTERNATE_B; vr41xx_pciu_init()
274 val |= PAPC_FAIR; vr41xx_pciu_init()
279 val |= TKYGNT_ENABLE; vr41xx_pciu_init()
281 pciu_write(PCIAPCNTREG, val); vr41xx_pciu_init()
H A Dops-mace.c42 int reg, int size, u32 *val) mace_pci_read_config()
51 *val = mace->pci.config_data.b[(reg & 3) ^ 3]; mace_pci_read_config()
54 *val = mace->pci.config_data.w[((reg >> 1) & 1) ^ 1]; mace_pci_read_config()
57 *val = mace->pci.config_data.l; mace_pci_read_config()
69 *val |= 0x1000; mace_pci_read_config()
71 DPRINTK("read%d: reg=%08x,val=%02x\n", size * 8, reg, *val); mace_pci_read_config()
78 int reg, int size, u32 val) mace_pci_write_config()
83 mace->pci.config_data.b[(reg & 3) ^ 3] = val; mace_pci_write_config()
86 mace->pci.config_data.w[((reg >> 1) & 1) ^ 1] = val; mace_pci_write_config()
89 mace->pci.config_data.l = val; mace_pci_write_config()
93 DPRINTK("write%d: reg=%08x,val=%02x\n", size * 8, reg, val); mace_pci_write_config()
41 mace_pci_read_config(struct pci_bus *bus, unsigned int devfn, int reg, int size, u32 *val) mace_pci_read_config() argument
77 mace_pci_write_config(struct pci_bus *bus, unsigned int devfn, int reg, int size, u32 val) mace_pci_write_config() argument
H A Dops-nile4.c17 struct pci_bus *bus, unsigned int devfn, int where, u32 *val) nile4_pcibios_config_access()
31 vrc_pciregs[(0x200 + where) >> 2] = *val; nile4_pcibios_config_access()
33 *val = vrc_pciregs[(0x200 + where) >> 2]; nile4_pcibios_config_access()
58 *(u32 *) adr = *val; nile4_pcibios_config_access()
60 *val = *(u32 *) adr; nile4_pcibios_config_access()
75 int where, int size, u32 *val) nile4_pcibios_read()
91 *val = (data >> ((where & 3) << 3)) & 0xff; nile4_pcibios_read()
93 *val = (data >> ((where & 3) << 3)) & 0xffff; nile4_pcibios_read()
95 *val = data; nile4_pcibios_read()
101 int where, int size, u32 val) nile4_pcibios_write()
118 (val << ((where & 3) << 3)); nile4_pcibios_write()
121 (val << ((where & 3) << 3)); nile4_pcibios_write()
123 data = val; nile4_pcibios_write()
16 nile4_pcibios_config_access(unsigned char access_type, struct pci_bus *bus, unsigned int devfn, int where, u32 *val) nile4_pcibios_config_access() argument
74 nile4_pcibios_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val) nile4_pcibios_read() argument
100 nile4_pcibios_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val) nile4_pcibios_write() argument
/linux-4.1.27/drivers/net/wireless/iwlwifi/
H A Diwl-devtrace-io.h36 TP_PROTO(const struct device *dev, u32 offs, u32 val),
37 TP_ARGS(dev, offs, val),
41 __field(u32, val)
46 __entry->val = val;
49 __get_str(dev), __entry->offs, __entry->val)
53 TP_PROTO(const struct device *dev, u32 offs, u8 val),
54 TP_ARGS(dev, offs, val),
58 __field(u8, val)
63 __entry->val = val;
66 __get_str(dev), __entry->offs, __entry->val)
70 TP_PROTO(const struct device *dev, u32 offs, u32 val),
71 TP_ARGS(dev, offs, val),
75 __field(u32, val)
80 __entry->val = val;
83 __get_str(dev), __entry->offs, __entry->val)
87 TP_PROTO(const struct device *dev, u32 offs, u32 val),
88 TP_ARGS(dev, offs, val),
92 __field(u32, val)
97 __entry->val = val;
100 __get_str(dev), __entry->offs, __entry->val)
104 TP_PROTO(const struct device *dev, u32 offs, u32 val),
105 TP_ARGS(dev, offs, val),
109 __field(u32, val)
114 __entry->val = val;
117 __get_str(dev), __entry->offs, __entry->val)
/linux-4.1.27/include/asm-generic/
H A Dpercpu.h68 #define raw_cpu_generic_to_op(pcp, val, op) \
70 *raw_cpu_ptr(&(pcp)) op val; \
73 #define raw_cpu_generic_add_return(pcp, val) \
75 raw_cpu_add(pcp, val); \
117 #define this_cpu_generic_to_op(pcp, val, op) \
121 *raw_cpu_ptr(&(pcp)) op val; \
125 #define this_cpu_generic_add_return(pcp, val) \
130 raw_cpu_add(pcp, val); \
184 #define raw_cpu_write_1(pcp, val) raw_cpu_generic_to_op(pcp, val, =)
187 #define raw_cpu_write_2(pcp, val) raw_cpu_generic_to_op(pcp, val, =)
190 #define raw_cpu_write_4(pcp, val) raw_cpu_generic_to_op(pcp, val, =)
193 #define raw_cpu_write_8(pcp, val) raw_cpu_generic_to_op(pcp, val, =)
197 #define raw_cpu_add_1(pcp, val) raw_cpu_generic_to_op(pcp, val, +=)
200 #define raw_cpu_add_2(pcp, val) raw_cpu_generic_to_op(pcp, val, +=)
203 #define raw_cpu_add_4(pcp, val) raw_cpu_generic_to_op(pcp, val, +=)
206 #define raw_cpu_add_8(pcp, val) raw_cpu_generic_to_op(pcp, val, +=)
210 #define raw_cpu_and_1(pcp, val) raw_cpu_generic_to_op(pcp, val, &=)
213 #define raw_cpu_and_2(pcp, val) raw_cpu_generic_to_op(pcp, val, &=)
216 #define raw_cpu_and_4(pcp, val) raw_cpu_generic_to_op(pcp, val, &=)
219 #define raw_cpu_and_8(pcp, val) raw_cpu_generic_to_op(pcp, val, &=)
223 #define raw_cpu_or_1(pcp, val) raw_cpu_generic_to_op(pcp, val, |=)
226 #define raw_cpu_or_2(pcp, val) raw_cpu_generic_to_op(pcp, val, |=)
229 #define raw_cpu_or_4(pcp, val) raw_cpu_generic_to_op(pcp, val, |=)
232 #define raw_cpu_or_8(pcp, val) raw_cpu_generic_to_op(pcp, val, |=)
236 #define raw_cpu_add_return_1(pcp, val) raw_cpu_generic_add_return(pcp, val)
239 #define raw_cpu_add_return_2(pcp, val) raw_cpu_generic_add_return(pcp, val)
242 #define raw_cpu_add_return_4(pcp, val) raw_cpu_generic_add_return(pcp, val)
245 #define raw_cpu_add_return_8(pcp, val) raw_cpu_generic_add_return(pcp, val)
309 #define this_cpu_write_1(pcp, val) this_cpu_generic_to_op(pcp, val, =)
312 #define this_cpu_write_2(pcp, val) this_cpu_generic_to_op(pcp, val, =)
315 #define this_cpu_write_4(pcp, val) this_cpu_generic_to_op(pcp, val, =)
318 #define this_cpu_write_8(pcp, val) this_cpu_generic_to_op(pcp, val, =)
322 #define this_cpu_add_1(pcp, val) this_cpu_generic_to_op(pcp, val, +=)
325 #define this_cpu_add_2(pcp, val) this_cpu_generic_to_op(pcp, val, +=)
328 #define this_cpu_add_4(pcp, val) this_cpu_generic_to_op(pcp, val, +=)
331 #define this_cpu_add_8(pcp, val) this_cpu_generic_to_op(pcp, val, +=)
335 #define this_cpu_and_1(pcp, val) this_cpu_generic_to_op(pcp, val, &=)
338 #define this_cpu_and_2(pcp, val) this_cpu_generic_to_op(pcp, val, &=)
341 #define this_cpu_and_4(pcp, val) this_cpu_generic_to_op(pcp, val, &=)
344 #define this_cpu_and_8(pcp, val) this_cpu_generic_to_op(pcp, val, &=)
348 #define this_cpu_or_1(pcp, val) this_cpu_generic_to_op(pcp, val, |=)
351 #define this_cpu_or_2(pcp, val) this_cpu_generic_to_op(pcp, val, |=)
354 #define this_cpu_or_4(pcp, val) this_cpu_generic_to_op(pcp, val, |=)
357 #define this_cpu_or_8(pcp, val) this_cpu_generic_to_op(pcp, val, |=)
361 #define this_cpu_add_return_1(pcp, val) this_cpu_generic_add_return(pcp, val)
364 #define this_cpu_add_return_2(pcp, val) this_cpu_generic_add_return(pcp, val)
367 #define this_cpu_add_return_4(pcp, val) this_cpu_generic_add_return(pcp, val)
370 #define this_cpu_add_return_8(pcp, val) this_cpu_generic_add_return(pcp, val)
H A Dptrace.h19 #define SET_IP(regs, val) (GET_IP(regs) = (val))
27 unsigned long val) instruction_pointer_set()
29 SET_IP(regs, val); instruction_pointer_set()
41 #define SET_USP(regs, val) (GET_USP(regs) = (val))
49 unsigned long val) user_stack_pointer_set()
51 SET_USP(regs, val); user_stack_pointer_set()
59 #define SET_FP(regs, val) (GET_FP(regs) = (val))
67 unsigned long val) frame_pointer_set()
69 SET_FP(regs, val); frame_pointer_set()
26 instruction_pointer_set(struct pt_regs *regs, unsigned long val) instruction_pointer_set() argument
48 user_stack_pointer_set(struct pt_regs *regs, unsigned long val) user_stack_pointer_set() argument
66 frame_pointer_set(struct pt_regs *regs, unsigned long val) frame_pointer_set() argument
H A Dcputime_nsecs.h76 static inline cputime_t timespec_to_cputime(const struct timespec *val) timespec_to_cputime() argument
78 u64 ret = (u64)val->tv_sec * NSEC_PER_SEC + val->tv_nsec; timespec_to_cputime()
81 static inline void cputime_to_timespec(const cputime_t ct, struct timespec *val) cputime_to_timespec() argument
85 val->tv_sec = cputime_div_rem(ct, NSEC_PER_SEC, &rem); cputime_to_timespec()
86 val->tv_nsec = rem; cputime_to_timespec()
92 static inline cputime_t timeval_to_cputime(const struct timeval *val) timeval_to_cputime() argument
94 u64 ret = (u64)val->tv_sec * NSEC_PER_SEC + timeval_to_cputime()
95 val->tv_usec * NSEC_PER_USEC; timeval_to_cputime()
98 static inline void cputime_to_timeval(const cputime_t ct, struct timeval *val) cputime_to_timeval() argument
102 val->tv_sec = cputime_div_rem(ct, NSEC_PER_SEC, &rem); cputime_to_timeval()
103 val->tv_usec = rem / NSEC_PER_USEC; cputime_to_timeval()
H A Dio-64-nonatomic-hi-lo.h18 static inline void hi_lo_writeq(__u64 val, volatile void __iomem *addr) hi_lo_writeq() argument
20 writel(val >> 32, addr + 4); hi_lo_writeq()
21 writel(val, addr); hi_lo_writeq()
H A Dio-64-nonatomic-lo-hi.h18 static inline void lo_hi_writeq(__u64 val, volatile void __iomem *addr) lo_hi_writeq() argument
20 writel(val, addr); lo_hi_writeq()
21 writel(val >> 32, addr + 4); lo_hi_writeq()
/linux-4.1.27/drivers/phy/
H A Dphy-xgene.c566 u32 val; sds_wr() local
576 val = readl(csr_base + indirect_cmd_reg); sds_wr()
577 } while (!(val & CFG_IND_CMD_DONE_MASK) && sds_wr()
579 if (!(val & CFG_IND_CMD_DONE_MASK)) sds_wr()
588 u32 val; sds_rd() local
596 val = readl(csr_base + indirect_cmd_reg); sds_rd()
597 } while (!(val & CFG_IND_CMD_DONE_MASK) && sds_rd()
600 if (!(val & CFG_IND_CMD_DONE_MASK)) sds_rd()
609 u32 val; cmu_wr() local
618 SATA_ENET_SDS_IND_RDATA_REG, reg, &val); cmu_wr()
619 pr_debug("CMU WR addr 0x%X value 0x%08X <-> 0x%08X\n", reg, data, val); cmu_wr()
639 u32 val; cmu_toggle1to0() local
641 cmu_rd(ctx, cmu_type, reg, &val); cmu_toggle1to0()
642 val |= bits; cmu_toggle1to0()
643 cmu_wr(ctx, cmu_type, reg, val); cmu_toggle1to0()
644 cmu_rd(ctx, cmu_type, reg, &val); cmu_toggle1to0()
645 val &= ~bits; cmu_toggle1to0()
646 cmu_wr(ctx, cmu_type, reg, val); cmu_toggle1to0()
652 u32 val; cmu_clrbits() local
654 cmu_rd(ctx, cmu_type, reg, &val); cmu_clrbits()
655 val &= ~bits; cmu_clrbits()
656 cmu_wr(ctx, cmu_type, reg, val); cmu_clrbits()
662 u32 val; cmu_setbits() local
664 cmu_rd(ctx, cmu_type, reg, &val); cmu_setbits()
665 val |= bits; cmu_setbits()
666 cmu_wr(ctx, cmu_type, reg, val); cmu_setbits()
672 u32 val; serdes_wr() local
679 SATA_ENET_SDS_IND_RDATA_REG, reg, &val); serdes_wr()
681 val); serdes_wr()
698 u32 val; serdes_clrbits() local
700 serdes_rd(ctx, lane, reg, &val); serdes_clrbits()
701 val &= ~bits; serdes_clrbits()
702 serdes_wr(ctx, lane, reg, val); serdes_clrbits()
708 u32 val; serdes_setbits() local
710 serdes_rd(ctx, lane, reg, &val); serdes_setbits()
711 val |= bits; serdes_setbits()
712 serdes_wr(ctx, lane, reg, val); serdes_setbits()
719 u32 val; xgene_phy_cfg_cmu_clk_type() local
722 cmu_rd(ctx, cmu_type, CMU_REG12, &val); xgene_phy_cfg_cmu_clk_type()
723 val = CMU_REG12_STATE_DELAY9_SET(val, 0x1); xgene_phy_cfg_cmu_clk_type()
724 cmu_wr(ctx, cmu_type, CMU_REG12, val); xgene_phy_cfg_cmu_clk_type()
732 cmu_rd(ctx, cmu_type, CMU_REG0, &val); xgene_phy_cfg_cmu_clk_type()
733 val = CMU_REG0_PLL_REF_SEL_SET(val, 0x0); xgene_phy_cfg_cmu_clk_type()
734 cmu_wr(ctx, cmu_type, CMU_REG0, val); xgene_phy_cfg_cmu_clk_type()
736 cmu_rd(ctx, cmu_type, CMU_REG1, &val); xgene_phy_cfg_cmu_clk_type()
737 val = CMU_REG1_REFCLK_CMOS_SEL_SET(val, 0x0); xgene_phy_cfg_cmu_clk_type()
738 cmu_wr(ctx, cmu_type, CMU_REG1, val); xgene_phy_cfg_cmu_clk_type()
742 cmu_rd(ctx, cmu_type, CMU_REG0, &val); xgene_phy_cfg_cmu_clk_type()
743 val = CMU_REG0_PLL_REF_SEL_SET(val, 0x1); xgene_phy_cfg_cmu_clk_type()
744 cmu_wr(ctx, cmu_type, CMU_REG0, val); xgene_phy_cfg_cmu_clk_type()
746 cmu_rd(ctx, cmu_type, CMU_REG1, &val); xgene_phy_cfg_cmu_clk_type()
747 val = CMU_REG1_REFCLK_CMOS_SEL_SET(val, 0x1); xgene_phy_cfg_cmu_clk_type()
748 cmu_wr(ctx, cmu_type, CMU_REG1, val); xgene_phy_cfg_cmu_clk_type()
757 cmu_rd(ctx, cmu_type, CMU_REG1, &val); xgene_phy_cfg_cmu_clk_type()
758 val = CMU_REG1_REFCLK_CMOS_SEL_SET(val, 0x1); xgene_phy_cfg_cmu_clk_type()
759 cmu_wr(ctx, cmu_type, CMU_REG1, val); xgene_phy_cfg_cmu_clk_type()
761 cmu_rd(ctx, cmu_type, CMU_REG1, &val); xgene_phy_cfg_cmu_clk_type()
762 val = CMU_REG1_REFCLK_CMOS_SEL_SET(val, 0x0); xgene_phy_cfg_cmu_clk_type()
763 cmu_wr(ctx, cmu_type, CMU_REG1, val); xgene_phy_cfg_cmu_clk_type()
773 u32 val; xgene_phy_sata_cfg_cmu_core() local
778 cmu_rd(ctx, cmu_type, CMU_REG34, &val); xgene_phy_sata_cfg_cmu_core()
779 val = CMU_REG34_VCO_CAL_VTH_LO_MAX_SET(val, 0x7); xgene_phy_sata_cfg_cmu_core()
780 val = CMU_REG34_VCO_CAL_VTH_HI_MAX_SET(val, 0xc); xgene_phy_sata_cfg_cmu_core()
781 val = CMU_REG34_VCO_CAL_VTH_LO_MIN_SET(val, 0x3); xgene_phy_sata_cfg_cmu_core()
782 val = CMU_REG34_VCO_CAL_VTH_HI_MIN_SET(val, 0x8); xgene_phy_sata_cfg_cmu_core()
783 cmu_wr(ctx, cmu_type, CMU_REG34, val); xgene_phy_sata_cfg_cmu_core()
787 cmu_rd(ctx, cmu_type, CMU_REG0, &val); xgene_phy_sata_cfg_cmu_core()
789 val = CMU_REG0_CAL_COUNT_RESOL_SET(val, 0x4); xgene_phy_sata_cfg_cmu_core()
791 val = CMU_REG0_CAL_COUNT_RESOL_SET(val, 0x7); xgene_phy_sata_cfg_cmu_core()
792 cmu_wr(ctx, cmu_type, CMU_REG0, val); xgene_phy_sata_cfg_cmu_core()
795 cmu_rd(ctx, cmu_type, CMU_REG1, &val); xgene_phy_sata_cfg_cmu_core()
796 val = CMU_REG1_PLL_CP_SET(val, 0x1); xgene_phy_sata_cfg_cmu_core()
798 val = CMU_REG1_PLL_CP_SEL_SET(val, 0x5); xgene_phy_sata_cfg_cmu_core()
800 val = CMU_REG1_PLL_CP_SEL_SET(val, 0x3); xgene_phy_sata_cfg_cmu_core()
802 val = CMU_REG1_PLL_MANUALCAL_SET(val, 0x0); xgene_phy_sata_cfg_cmu_core()
804 val = CMU_REG1_PLL_MANUALCAL_SET(val, 0x1); xgene_phy_sata_cfg_cmu_core()
805 cmu_wr(ctx, cmu_type, CMU_REG1, val); xgene_phy_sata_cfg_cmu_core()
811 cmu_rd(ctx, cmu_type, CMU_REG2, &val); xgene_phy_sata_cfg_cmu_core()
813 val = CMU_REG2_PLL_LFRES_SET(val, 0xa); xgene_phy_sata_cfg_cmu_core()
816 val = CMU_REG2_PLL_LFRES_SET(val, 0x3); xgene_phy_sata_cfg_cmu_core()
823 val = CMU_REG2_PLL_FBDIV_SET(val, FBDIV_VAL_100M); xgene_phy_sata_cfg_cmu_core()
824 val = CMU_REG2_PLL_REFDIV_SET(val, REFDIV_VAL_100M); xgene_phy_sata_cfg_cmu_core()
826 val = CMU_REG2_PLL_FBDIV_SET(val, FBDIV_VAL_50M); xgene_phy_sata_cfg_cmu_core()
827 val = CMU_REG2_PLL_REFDIV_SET(val, REFDIV_VAL_50M); xgene_phy_sata_cfg_cmu_core()
829 cmu_wr(ctx, cmu_type, CMU_REG2, val); xgene_phy_sata_cfg_cmu_core()
832 cmu_rd(ctx, cmu_type, CMU_REG3, &val); xgene_phy_sata_cfg_cmu_core()
834 val = CMU_REG3_VCOVARSEL_SET(val, 0x3); xgene_phy_sata_cfg_cmu_core()
835 val = CMU_REG3_VCO_MOMSEL_INIT_SET(val, 0x10); xgene_phy_sata_cfg_cmu_core()
837 val = CMU_REG3_VCOVARSEL_SET(val, 0xF); xgene_phy_sata_cfg_cmu_core()
839 val = CMU_REG3_VCO_MOMSEL_INIT_SET(val, 0x15); xgene_phy_sata_cfg_cmu_core()
841 val = CMU_REG3_VCO_MOMSEL_INIT_SET(val, 0x1a); xgene_phy_sata_cfg_cmu_core()
842 val = CMU_REG3_VCO_MANMOMSEL_SET(val, 0x15); xgene_phy_sata_cfg_cmu_core()
844 cmu_wr(ctx, cmu_type, CMU_REG3, val); xgene_phy_sata_cfg_cmu_core()
847 cmu_rd(ctx, cmu_type, CMU_REG26, &val); xgene_phy_sata_cfg_cmu_core()
848 val = CMU_REG26_FORCE_PLL_LOCK_SET(val, 0x0); xgene_phy_sata_cfg_cmu_core()
849 cmu_wr(ctx, cmu_type, CMU_REG26, val); xgene_phy_sata_cfg_cmu_core()
852 cmu_rd(ctx, cmu_type, CMU_REG5, &val); xgene_phy_sata_cfg_cmu_core()
853 val = CMU_REG5_PLL_LFSMCAP_SET(val, 0x3); xgene_phy_sata_cfg_cmu_core()
854 val = CMU_REG5_PLL_LFCAP_SET(val, 0x3); xgene_phy_sata_cfg_cmu_core()
856 val = CMU_REG5_PLL_LOCK_RESOLUTION_SET(val, 0x7); xgene_phy_sata_cfg_cmu_core()
858 val = CMU_REG5_PLL_LOCK_RESOLUTION_SET(val, 0x4); xgene_phy_sata_cfg_cmu_core()
859 cmu_wr(ctx, cmu_type, CMU_REG5, val); xgene_phy_sata_cfg_cmu_core()
862 cmu_rd(ctx, cmu_type, CMU_REG6, &val); xgene_phy_sata_cfg_cmu_core()
863 val = CMU_REG6_PLL_VREGTRIM_SET(val, preA3Chip ? 0x0 : 0x2); xgene_phy_sata_cfg_cmu_core()
864 val = CMU_REG6_MAN_PVT_CAL_SET(val, preA3Chip ? 0x1 : 0x0); xgene_phy_sata_cfg_cmu_core()
865 cmu_wr(ctx, cmu_type, CMU_REG6, val); xgene_phy_sata_cfg_cmu_core()
869 cmu_rd(ctx, cmu_type, CMU_REG9, &val); xgene_phy_sata_cfg_cmu_core()
870 val = CMU_REG9_TX_WORD_MODE_CH1_SET(val, xgene_phy_sata_cfg_cmu_core()
872 val = CMU_REG9_TX_WORD_MODE_CH0_SET(val, xgene_phy_sata_cfg_cmu_core()
874 val = CMU_REG9_PLL_POST_DIVBY2_SET(val, 0x1); xgene_phy_sata_cfg_cmu_core()
876 val = CMU_REG9_VBG_BYPASSB_SET(val, 0x0); xgene_phy_sata_cfg_cmu_core()
877 val = CMU_REG9_IGEN_BYPASS_SET(val , 0x0); xgene_phy_sata_cfg_cmu_core()
879 cmu_wr(ctx, cmu_type, CMU_REG9, val); xgene_phy_sata_cfg_cmu_core()
882 cmu_rd(ctx, cmu_type, CMU_REG10, &val); xgene_phy_sata_cfg_cmu_core()
883 val = CMU_REG10_VREG_REFSEL_SET(val, 0x1); xgene_phy_sata_cfg_cmu_core()
884 cmu_wr(ctx, cmu_type, CMU_REG10, val); xgene_phy_sata_cfg_cmu_core()
888 cmu_rd(ctx, cmu_type, CMU_REG16, &val); xgene_phy_sata_cfg_cmu_core()
889 val = CMU_REG16_CALIBRATION_DONE_OVERRIDE_SET(val, 0x1); xgene_phy_sata_cfg_cmu_core()
890 val = CMU_REG16_BYPASS_PLL_LOCK_SET(val, 0x1); xgene_phy_sata_cfg_cmu_core()
892 val = CMU_REG16_VCOCAL_WAIT_BTW_CODE_SET(val, 0x4); xgene_phy_sata_cfg_cmu_core()
894 val = CMU_REG16_VCOCAL_WAIT_BTW_CODE_SET(val, 0x7); xgene_phy_sata_cfg_cmu_core()
895 cmu_wr(ctx, cmu_type, CMU_REG16, val); xgene_phy_sata_cfg_cmu_core()
898 cmu_rd(ctx, cmu_type, CMU_REG30, &val); xgene_phy_sata_cfg_cmu_core()
899 val = CMU_REG30_PCIE_MODE_SET(val, 0x0); xgene_phy_sata_cfg_cmu_core()
900 val = CMU_REG30_LOCK_COUNT_SET(val, 0x3); xgene_phy_sata_cfg_cmu_core()
901 cmu_wr(ctx, cmu_type, CMU_REG30, val); xgene_phy_sata_cfg_cmu_core()
906 cmu_rd(ctx, cmu_type, CMU_REG32, &val); xgene_phy_sata_cfg_cmu_core()
907 val = CMU_REG32_PVT_CAL_WAIT_SEL_SET(val, 0x3); xgene_phy_sata_cfg_cmu_core()
909 val = CMU_REG32_IREF_ADJ_SET(val, 0x3); xgene_phy_sata_cfg_cmu_core()
911 val = CMU_REG32_IREF_ADJ_SET(val, 0x1); xgene_phy_sata_cfg_cmu_core()
912 cmu_wr(ctx, cmu_type, CMU_REG32, val); xgene_phy_sata_cfg_cmu_core()
927 u32 val; xgene_phy_ssc_enable() local
930 cmu_rd(ctx, cmu_type, CMU_REG35, &val); xgene_phy_ssc_enable()
931 val = CMU_REG35_PLL_SSC_MOD_SET(val, 98); xgene_phy_ssc_enable()
932 cmu_wr(ctx, cmu_type, CMU_REG35, val); xgene_phy_ssc_enable()
935 cmu_rd(ctx, cmu_type, CMU_REG36, &val); xgene_phy_ssc_enable()
936 val = CMU_REG36_PLL_SSC_VSTEP_SET(val, 30); xgene_phy_ssc_enable()
937 val = CMU_REG36_PLL_SSC_EN_SET(val, 1); xgene_phy_ssc_enable()
938 val = CMU_REG36_PLL_SSC_DSMSEL_SET(val, 1); xgene_phy_ssc_enable()
939 cmu_wr(ctx, cmu_type, CMU_REG36, val); xgene_phy_ssc_enable()
952 u32 val; xgene_phy_sata_cfg_lanes() local
961 serdes_rd(ctx, lane, RXTX_REG0, &val); xgene_phy_sata_cfg_lanes()
962 val = RXTX_REG0_CTLE_EQ_HR_SET(val, 0x10); xgene_phy_sata_cfg_lanes()
963 val = RXTX_REG0_CTLE_EQ_QR_SET(val, 0x10); xgene_phy_sata_cfg_lanes()
964 val = RXTX_REG0_CTLE_EQ_FR_SET(val, 0x10); xgene_phy_sata_cfg_lanes()
965 serdes_wr(ctx, lane, RXTX_REG0, val); xgene_phy_sata_cfg_lanes()
968 serdes_rd(ctx, lane, RXTX_REG1, &val); xgene_phy_sata_cfg_lanes()
969 val = RXTX_REG1_RXACVCM_SET(val, 0x7); xgene_phy_sata_cfg_lanes()
970 val = RXTX_REG1_CTLE_EQ_SET(val, xgene_phy_sata_cfg_lanes()
973 serdes_wr(ctx, lane, RXTX_REG1, val); xgene_phy_sata_cfg_lanes()
977 serdes_rd(ctx, lane, RXTX_REG2, &val); xgene_phy_sata_cfg_lanes()
978 val = RXTX_REG2_VTT_ENA_SET(val, 0x1); xgene_phy_sata_cfg_lanes()
979 val = RXTX_REG2_VTT_SEL_SET(val, 0x1); xgene_phy_sata_cfg_lanes()
980 val = RXTX_REG2_TX_FIFO_ENA_SET(val, 0x1); xgene_phy_sata_cfg_lanes()
981 serdes_wr(ctx, lane, RXTX_REG2, val); xgene_phy_sata_cfg_lanes()
984 serdes_rd(ctx, lane, RXTX_REG4, &val); xgene_phy_sata_cfg_lanes()
985 val = RXTX_REG4_TX_WORD_MODE_SET(val, CMU_REG9_WORD_LEN_20BIT); xgene_phy_sata_cfg_lanes()
986 serdes_wr(ctx, lane, RXTX_REG4, val); xgene_phy_sata_cfg_lanes()
989 serdes_rd(ctx, lane, RXTX_REG1, &val); xgene_phy_sata_cfg_lanes()
990 val = RXTX_REG1_RXVREG1_SET(val, 0x2); xgene_phy_sata_cfg_lanes()
991 val = RXTX_REG1_RXIREF_ADJ_SET(val, 0x2); xgene_phy_sata_cfg_lanes()
992 serdes_wr(ctx, lane, RXTX_REG1, val); xgene_phy_sata_cfg_lanes()
996 serdes_rd(ctx, lane, RXTX_REG5, &val); xgene_phy_sata_cfg_lanes()
997 val = RXTX_REG5_TX_CN1_SET(val, xgene_phy_sata_cfg_lanes()
1000 val = RXTX_REG5_TX_CP1_SET(val, xgene_phy_sata_cfg_lanes()
1003 val = RXTX_REG5_TX_CN2_SET(val, xgene_phy_sata_cfg_lanes()
1006 serdes_wr(ctx, lane, RXTX_REG5, val); xgene_phy_sata_cfg_lanes()
1009 serdes_rd(ctx, lane, RXTX_REG6, &val); xgene_phy_sata_cfg_lanes()
1010 val = RXTX_REG6_TXAMP_CNTL_SET(val, xgene_phy_sata_cfg_lanes()
1013 val = RXTX_REG6_TXAMP_ENA_SET(val, 0x1); xgene_phy_sata_cfg_lanes()
1014 val = RXTX_REG6_TX_IDLE_SET(val, 0x0); xgene_phy_sata_cfg_lanes()
1015 val = RXTX_REG6_RX_BIST_RESYNC_SET(val, 0x0); xgene_phy_sata_cfg_lanes()
1016 val = RXTX_REG6_RX_BIST_ERRCNT_RD_SET(val, 0x0); xgene_phy_sata_cfg_lanes()
1017 serdes_wr(ctx, lane, RXTX_REG6, val); xgene_phy_sata_cfg_lanes()
1020 serdes_rd(ctx, lane, RXTX_REG7, &val); xgene_phy_sata_cfg_lanes()
1021 val = RXTX_REG7_BIST_ENA_RX_SET(val, 0x0); xgene_phy_sata_cfg_lanes()
1022 val = RXTX_REG7_RX_WORD_MODE_SET(val, CMU_REG9_WORD_LEN_20BIT); xgene_phy_sata_cfg_lanes()
1023 serdes_wr(ctx, lane, RXTX_REG7, val); xgene_phy_sata_cfg_lanes()
1026 serdes_rd(ctx, lane, RXTX_REG8, &val); xgene_phy_sata_cfg_lanes()
1027 val = RXTX_REG8_CDR_LOOP_ENA_SET(val, 0x1); xgene_phy_sata_cfg_lanes()
1028 val = RXTX_REG8_CDR_BYPASS_RXLOS_SET(val, 0x0); xgene_phy_sata_cfg_lanes()
1029 val = RXTX_REG8_SSC_ENABLE_SET(val, 0x1); xgene_phy_sata_cfg_lanes()
1030 val = RXTX_REG8_SD_DISABLE_SET(val, 0x0); xgene_phy_sata_cfg_lanes()
1031 val = RXTX_REG8_SD_VREF_SET(val, 0x4); xgene_phy_sata_cfg_lanes()
1032 serdes_wr(ctx, lane, RXTX_REG8, val); xgene_phy_sata_cfg_lanes()
1035 serdes_rd(ctx, lane, RXTX_REG11, &val); xgene_phy_sata_cfg_lanes()
1036 val = RXTX_REG11_PHASE_ADJUST_LIMIT_SET(val, 0x0); xgene_phy_sata_cfg_lanes()
1037 serdes_wr(ctx, lane, RXTX_REG11, val); xgene_phy_sata_cfg_lanes()
1040 serdes_rd(ctx, lane, RXTX_REG12, &val); xgene_phy_sata_cfg_lanes()
1041 val = RXTX_REG12_LATCH_OFF_ENA_SET(val, 0x1); xgene_phy_sata_cfg_lanes()
1042 val = RXTX_REG12_SUMOS_ENABLE_SET(val, 0x0); xgene_phy_sata_cfg_lanes()
1043 val = RXTX_REG12_RX_DET_TERM_ENABLE_SET(val, 0x0); xgene_phy_sata_cfg_lanes()
1044 serdes_wr(ctx, lane, RXTX_REG12, val); xgene_phy_sata_cfg_lanes()
1047 serdes_rd(ctx, lane, RXTX_REG26, &val); xgene_phy_sata_cfg_lanes()
1048 val = RXTX_REG26_PERIOD_ERROR_LATCH_SET(val, 0x0); xgene_phy_sata_cfg_lanes()
1049 val = RXTX_REG26_BLWC_ENA_SET(val, 0x1); xgene_phy_sata_cfg_lanes()
1050 serdes_wr(ctx, lane, RXTX_REG26, val); xgene_phy_sata_cfg_lanes()
1058 serdes_rd(ctx, lane, RXTX_REG61, &val); xgene_phy_sata_cfg_lanes()
1059 val = RXTX_REG61_ISCAN_INBERT_SET(val, 0x1); xgene_phy_sata_cfg_lanes()
1060 val = RXTX_REG61_LOADFREQ_SHIFT_SET(val, 0x0); xgene_phy_sata_cfg_lanes()
1061 val = RXTX_REG61_EYE_COUNT_WIDTH_SEL_SET(val, 0x0); xgene_phy_sata_cfg_lanes()
1062 serdes_wr(ctx, lane, RXTX_REG61, val); xgene_phy_sata_cfg_lanes()
1064 serdes_rd(ctx, lane, RXTX_REG62, &val); xgene_phy_sata_cfg_lanes()
1065 val = RXTX_REG62_PERIOD_H1_QLATCH_SET(val, 0x0); xgene_phy_sata_cfg_lanes()
1066 serdes_wr(ctx, lane, RXTX_REG62, val); xgene_phy_sata_cfg_lanes()
1071 serdes_rd(ctx, lane, reg, &val); xgene_phy_sata_cfg_lanes()
1072 val = RXTX_REG89_MU_TH7_SET(val, 0xe); xgene_phy_sata_cfg_lanes()
1073 val = RXTX_REG89_MU_TH8_SET(val, 0xe); xgene_phy_sata_cfg_lanes()
1074 val = RXTX_REG89_MU_TH9_SET(val, 0xe); xgene_phy_sata_cfg_lanes()
1075 serdes_wr(ctx, lane, reg, val); xgene_phy_sata_cfg_lanes()
1081 serdes_rd(ctx, lane, reg, &val); xgene_phy_sata_cfg_lanes()
1082 val = RXTX_REG96_MU_FREQ1_SET(val, 0x10); xgene_phy_sata_cfg_lanes()
1083 val = RXTX_REG96_MU_FREQ2_SET(val, 0x10); xgene_phy_sata_cfg_lanes()
1084 val = RXTX_REG96_MU_FREQ3_SET(val, 0x10); xgene_phy_sata_cfg_lanes()
1085 serdes_wr(ctx, lane, reg, val); xgene_phy_sata_cfg_lanes()
1091 serdes_rd(ctx, lane, reg, &val); xgene_phy_sata_cfg_lanes()
1092 val = RXTX_REG99_MU_PHASE1_SET(val, 0x7); xgene_phy_sata_cfg_lanes()
1093 val = RXTX_REG99_MU_PHASE2_SET(val, 0x7); xgene_phy_sata_cfg_lanes()
1094 val = RXTX_REG99_MU_PHASE3_SET(val, 0x7); xgene_phy_sata_cfg_lanes()
1095 serdes_wr(ctx, lane, reg, val); xgene_phy_sata_cfg_lanes()
1098 serdes_rd(ctx, lane, RXTX_REG102, &val); xgene_phy_sata_cfg_lanes()
1099 val = RXTX_REG102_FREQLOOP_LIMIT_SET(val, 0x0); xgene_phy_sata_cfg_lanes()
1100 serdes_wr(ctx, lane, RXTX_REG102, val); xgene_phy_sata_cfg_lanes()
1104 serdes_rd(ctx, lane, RXTX_REG125, &val); xgene_phy_sata_cfg_lanes()
1105 val = RXTX_REG125_SIGN_PQ_SET(val, xgene_phy_sata_cfg_lanes()
1108 val = RXTX_REG125_PQ_REG_SET(val, xgene_phy_sata_cfg_lanes()
1111 val = RXTX_REG125_PHZ_MANUAL_SET(val, 0x1); xgene_phy_sata_cfg_lanes()
1112 serdes_wr(ctx, lane, RXTX_REG125, val); xgene_phy_sata_cfg_lanes()
1114 serdes_rd(ctx, lane, RXTX_REG127, &val); xgene_phy_sata_cfg_lanes()
1115 val = RXTX_REG127_LATCH_MAN_CAL_ENA_SET(val, 0x0); xgene_phy_sata_cfg_lanes()
1116 serdes_wr(ctx, lane, RXTX_REG127, val); xgene_phy_sata_cfg_lanes()
1118 serdes_rd(ctx, lane, RXTX_REG128, &val); xgene_phy_sata_cfg_lanes()
1119 val = RXTX_REG128_LATCH_CAL_WAIT_SEL_SET(val, 0x3); xgene_phy_sata_cfg_lanes()
1120 serdes_wr(ctx, lane, RXTX_REG128, val); xgene_phy_sata_cfg_lanes()
1122 serdes_rd(ctx, lane, RXTX_REG145, &val); xgene_phy_sata_cfg_lanes()
1123 val = RXTX_REG145_RXDFE_CONFIG_SET(val, 0x3); xgene_phy_sata_cfg_lanes()
1124 val = RXTX_REG145_TX_IDLE_SATA_SET(val, 0x0); xgene_phy_sata_cfg_lanes()
1126 val = RXTX_REG145_RXES_ENA_SET(val, 0x1); xgene_phy_sata_cfg_lanes()
1127 val = RXTX_REG145_RXVWES_LATENA_SET(val, 0x1); xgene_phy_sata_cfg_lanes()
1129 val = RXTX_REG145_RXES_ENA_SET(val, 0x0); xgene_phy_sata_cfg_lanes()
1130 val = RXTX_REG145_RXVWES_LATENA_SET(val, 0x0); xgene_phy_sata_cfg_lanes()
1132 serdes_wr(ctx, lane, RXTX_REG145, val); xgene_phy_sata_cfg_lanes()
1151 u32 val; xgene_phy_cal_rdy_chk() local
1165 cmu_rd(ctx, cmu_type, CMU_REG1, &val); xgene_phy_cal_rdy_chk()
1166 val = CMU_REG1_PLL_MANUALCAL_SET(val, 0x0); xgene_phy_cal_rdy_chk()
1167 cmu_wr(ctx, cmu_type, CMU_REG1, val); xgene_phy_cal_rdy_chk()
1191 cmu_rd(ctx, cmu_type, CMU_REG17, &val); xgene_phy_cal_rdy_chk()
1192 val = CMU_REG17_PVT_CODE_R2A_SET(val, 0x12); xgene_phy_cal_rdy_chk()
1193 val = CMU_REG17_RESERVED_7_SET(val, 0x0); xgene_phy_cal_rdy_chk()
1194 cmu_wr(ctx, cmu_type, CMU_REG17, val); xgene_phy_cal_rdy_chk()
1202 cmu_rd(ctx, cmu_type, CMU_REG17, &val); xgene_phy_cal_rdy_chk()
1203 val = CMU_REG17_PVT_CODE_R2A_SET(val, 0x29); xgene_phy_cal_rdy_chk()
1204 val = CMU_REG17_RESERVED_7_SET(val, 0x0); xgene_phy_cal_rdy_chk()
1205 cmu_wr(ctx, cmu_type, CMU_REG17, val); xgene_phy_cal_rdy_chk()
1209 cmu_rd(ctx, cmu_type, CMU_REG17, &val); xgene_phy_cal_rdy_chk()
1210 val = CMU_REG17_PVT_CODE_R2A_SET(val, 0x28); xgene_phy_cal_rdy_chk()
1211 val = CMU_REG17_RESERVED_7_SET(val, 0x0); xgene_phy_cal_rdy_chk()
1212 cmu_wr(ctx, cmu_type, CMU_REG17, val); xgene_phy_cal_rdy_chk()
1220 cmu_rd(ctx, cmu_type, CMU_REG7, &val); xgene_phy_cal_rdy_chk()
1221 if (CMU_REG7_PLL_CALIB_DONE_RD(val)) xgene_phy_cal_rdy_chk()
1230 cmu_rd(ctx, cmu_type, CMU_REG7, &val); xgene_phy_cal_rdy_chk()
1232 CMU_REG7_PLL_CALIB_DONE_RD(val) ? "done" : "failed"); xgene_phy_cal_rdy_chk()
1233 if (CMU_REG7_VCO_CAL_FAIL_RD(val)) { xgene_phy_cal_rdy_chk()
1240 cmu_rd(ctx, cmu_type, CMU_REG15, &val); xgene_phy_cal_rdy_chk()
1241 dev_dbg(ctx->dev, "PHY Tx is %sready\n", val & 0x300 ? "" : "not "); xgene_phy_cal_rdy_chk()
1249 u32 val; xgene_phy_pdwn_force_vco() local
1253 cmu_rd(ctx, cmu_type, CMU_REG16, &val); xgene_phy_pdwn_force_vco()
1254 val = CMU_REG16_VCOCAL_WAIT_BTW_CODE_SET(val, 0x7); xgene_phy_pdwn_force_vco()
1255 cmu_wr(ctx, cmu_type, CMU_REG16, val); xgene_phy_pdwn_force_vco()
1267 u32 val; xgene_phy_hw_init_sata() local
1274 val = readl(sds_base + SATA_ENET_SDS_RST_CTL); /* Force a barrier */ xgene_phy_hw_init_sata()
1283 val = readl(sds_base + SATA_ENET_SDS_CTL1); xgene_phy_hw_init_sata()
1284 val = CFG_I_SPD_SEL_CDR_OVR1_SET(val, xgene_phy_hw_init_sata()
1286 writel(val, sds_base + SATA_ENET_SDS_CTL1); xgene_phy_hw_init_sata()
1289 val = readl(sds_base + SATA_ENET_SDS_CTL0); xgene_phy_hw_init_sata()
1290 val = REGSPEC_CFG_I_CUSTOMER_PIN_MODE0_SET(val, 0x4421); xgene_phy_hw_init_sata()
1291 writel(val, sds_base + SATA_ENET_SDS_CTL0); xgene_phy_hw_init_sata()
1307 val = readl(sds_base + SATA_ENET_SDS_PCS_CTL0); xgene_phy_hw_init_sata()
1308 val = REGSPEC_CFG_I_RX_WORDMODE0_SET(val, 0x3); xgene_phy_hw_init_sata()
1309 val = REGSPEC_CFG_I_TX_WORDMODE0_SET(val, 0x3); xgene_phy_hw_init_sata()
1310 writel(val, sds_base + SATA_ENET_SDS_PCS_CTL0); xgene_phy_hw_init_sata()
1359 u32 val; xgene_phy_force_lat_summer_cal() member in struct:__anon8272
1417 serdes_reg[i].val); xgene_phy_force_lat_summer_cal()
1446 u32 val; xgene_phy_gen_avg_val() local
1470 serdes_rd(ctx, lane, RXTX_REG21, &val); xgene_phy_gen_avg_val()
1471 lat_do_itr = RXTX_REG21_DO_LATCH_CALOUT_RD(val); xgene_phy_gen_avg_val()
1472 lat_xo_itr = RXTX_REG21_XO_LATCH_CALOUT_RD(val); xgene_phy_gen_avg_val()
1473 fail_odd = RXTX_REG21_LATCH_CAL_FAIL_ODD_RD(val); xgene_phy_gen_avg_val()
1475 serdes_rd(ctx, lane, RXTX_REG22, &val); xgene_phy_gen_avg_val()
1476 lat_eo_itr = RXTX_REG22_EO_LATCH_CALOUT_RD(val); xgene_phy_gen_avg_val()
1477 lat_so_itr = RXTX_REG22_SO_LATCH_CALOUT_RD(val); xgene_phy_gen_avg_val()
1478 fail_even = RXTX_REG22_LATCH_CAL_FAIL_EVEN_RD(val); xgene_phy_gen_avg_val()
1480 serdes_rd(ctx, lane, RXTX_REG23, &val); xgene_phy_gen_avg_val()
1481 lat_de_itr = RXTX_REG23_DE_LATCH_CALOUT_RD(val); xgene_phy_gen_avg_val()
1482 lat_xe_itr = RXTX_REG23_XE_LATCH_CALOUT_RD(val); xgene_phy_gen_avg_val()
1484 serdes_rd(ctx, lane, RXTX_REG24, &val); xgene_phy_gen_avg_val()
1485 lat_ee_itr = RXTX_REG24_EE_LATCH_CALOUT_RD(val); xgene_phy_gen_avg_val()
1486 lat_se_itr = RXTX_REG24_SE_LATCH_CALOUT_RD(val); xgene_phy_gen_avg_val()
1488 serdes_rd(ctx, lane, RXTX_REG121, &val); xgene_phy_gen_avg_val()
1489 sum_cal_itr = RXTX_REG121_SUMOS_CAL_CODE_RD(val); xgene_phy_gen_avg_val()
1522 serdes_rd(ctx, lane, RXTX_REG127, &val); xgene_phy_gen_avg_val()
1523 val = RXTX_REG127_DO_LATCH_MANCAL_SET(val, xgene_phy_gen_avg_val()
1525 val = RXTX_REG127_XO_LATCH_MANCAL_SET(val, xgene_phy_gen_avg_val()
1527 serdes_wr(ctx, lane, RXTX_REG127, val); xgene_phy_gen_avg_val()
1529 serdes_rd(ctx, lane, RXTX_REG128, &val); xgene_phy_gen_avg_val()
1530 val = RXTX_REG128_EO_LATCH_MANCAL_SET(val, xgene_phy_gen_avg_val()
1532 val = RXTX_REG128_SO_LATCH_MANCAL_SET(val, xgene_phy_gen_avg_val()
1534 serdes_wr(ctx, lane, RXTX_REG128, val); xgene_phy_gen_avg_val()
1536 serdes_rd(ctx, lane, RXTX_REG129, &val); xgene_phy_gen_avg_val()
1537 val = RXTX_REG129_DE_LATCH_MANCAL_SET(val, xgene_phy_gen_avg_val()
1539 val = RXTX_REG129_XE_LATCH_MANCAL_SET(val, xgene_phy_gen_avg_val()
1541 serdes_wr(ctx, lane, RXTX_REG129, val); xgene_phy_gen_avg_val()
1543 serdes_rd(ctx, lane, RXTX_REG130, &val); xgene_phy_gen_avg_val()
1544 val = RXTX_REG130_EE_LATCH_MANCAL_SET(val, xgene_phy_gen_avg_val()
1546 val = RXTX_REG130_SE_LATCH_MANCAL_SET(val, xgene_phy_gen_avg_val()
1548 serdes_wr(ctx, lane, RXTX_REG130, val); xgene_phy_gen_avg_val()
1551 serdes_rd(ctx, lane, RXTX_REG14, &val); xgene_phy_gen_avg_val()
1552 val = RXTX_REG14_CLTE_LATCAL_MAN_PROG_SET(val, xgene_phy_gen_avg_val()
1554 serdes_wr(ctx, lane, RXTX_REG14, val); xgene_phy_gen_avg_val()
1570 serdes_rd(ctx, lane, RXTX_REG14, &val); xgene_phy_gen_avg_val()
1571 val = RXTX_REG14_CTLE_LATCAL_MAN_ENA_SET(val, 0x1); xgene_phy_gen_avg_val()
1572 serdes_wr(ctx, lane, RXTX_REG14, val); xgene_phy_gen_avg_val()
1575 serdes_rd(ctx, lane, RXTX_REG127, &val); xgene_phy_gen_avg_val()
1576 val = RXTX_REG127_LATCH_MAN_CAL_ENA_SET(val, 0x1); xgene_phy_gen_avg_val()
1578 serdes_wr(ctx, lane, RXTX_REG127, val); xgene_phy_gen_avg_val()
1581 serdes_rd(ctx, lane, RXTX_REG12, &val); xgene_phy_gen_avg_val()
1582 val = RXTX_REG12_RX_DET_TERM_ENABLE_SET(val, 0); xgene_phy_gen_avg_val()
1583 serdes_wr(ctx, lane, RXTX_REG12, val); xgene_phy_gen_avg_val()
H A Dphy-hix5hd2-sata.c68 u32 val, data[2]; hix5hd2_sata_phy_init() local
85 val = readl_relaxed(priv->base + SATA_PHY0_CTLL); hix5hd2_sata_phy_init()
86 val &= ~(MPLL_MULTIPLIER_MASK | REF_USE_PAD); hix5hd2_sata_phy_init()
87 val |= MPLL_MULTIPLIER_50M << MPLL_MULTIPLIER_SHIFT | hix5hd2_sata_phy_init()
89 writel_relaxed(val, priv->base + SATA_PHY0_CTLL); hix5hd2_sata_phy_init()
91 val &= ~PHY_RESET; hix5hd2_sata_phy_init()
92 writel_relaxed(val, priv->base + SATA_PHY0_CTLL); hix5hd2_sata_phy_init()
94 val = readl_relaxed(priv->base + SATA_PORT_PHYCTL1); hix5hd2_sata_phy_init()
95 val &= ~AMPLITUDE_MASK; hix5hd2_sata_phy_init()
96 val |= AMPLITUDE_GEN3 << AMPLITUDE_GEN3_SHIFT | hix5hd2_sata_phy_init()
99 writel_relaxed(val, priv->base + SATA_PORT_PHYCTL1); hix5hd2_sata_phy_init()
101 val = readl_relaxed(priv->base + SATA_PORT_PHYCTL2); hix5hd2_sata_phy_init()
102 val &= ~PREEMPH_MASK; hix5hd2_sata_phy_init()
103 val |= PREEMPH_GEN3 << PREEMPH_GEN3_SHIFT | hix5hd2_sata_phy_init()
106 writel_relaxed(val, priv->base + SATA_PORT_PHYCTL2); hix5hd2_sata_phy_init()
109 val = readl_relaxed(priv->base + SATA_PORT_PHYCTL); hix5hd2_sata_phy_init()
110 val &= ~SPEED_MODE_MASK; hix5hd2_sata_phy_init()
111 val |= SPEED_MODE_GEN1 << HALF_RATE_SHIFT | hix5hd2_sata_phy_init()
114 writel_relaxed(val, priv->base + SATA_PORT_PHYCTL); hix5hd2_sata_phy_init()
117 val &= ~SPEED_MODE_MASK; hix5hd2_sata_phy_init()
118 val |= SPEED_MODE_GEN3 << HALF_RATE_SHIFT | hix5hd2_sata_phy_init()
121 writel_relaxed(val, priv->base + SATA_PORT_PHYCTL); hix5hd2_sata_phy_init()
123 val &= ~(SPEED_MODE_MASK | SPEED_CTRL); hix5hd2_sata_phy_init()
124 val |= SPEED_MODE_GEN2 << HALF_RATE_SHIFT | hix5hd2_sata_phy_init()
127 writel_relaxed(val, priv->base + SATA_PORT_PHYCTL); hix5hd2_sata_phy_init()
/linux-4.1.27/sound/pci/ac97/
H A Dac97_proc.c110 unsigned short val, tmp, ext, mext; snd_ac97_proc_read_main() local
130 val = snd_ac97_read(ac97, AC97_INT_PAGING); snd_ac97_proc_read_main()
141 AC97_PAGE_MASK, val & AC97_PAGE_MASK); snd_ac97_proc_read_main()
144 // val = snd_ac97_read(ac97, AC97_RESET); snd_ac97_proc_read_main()
145 val = ac97->caps; snd_ac97_proc_read_main()
147 val & AC97_BC_DEDICATED_MIC ? " -dedicated MIC PCM IN channel-" : "", snd_ac97_proc_read_main()
148 val & AC97_BC_RESERVED1 ? " -reserved1-" : "", snd_ac97_proc_read_main()
149 val & AC97_BC_BASS_TREBLE ? " -bass & treble-" : "", snd_ac97_proc_read_main()
150 val & AC97_BC_SIM_STEREO ? " -simulated stereo-" : "", snd_ac97_proc_read_main()
151 val & AC97_BC_HEADPHONE ? " -headphone out-" : "", snd_ac97_proc_read_main()
152 val & AC97_BC_LOUDNESS ? " -loudness-" : ""); snd_ac97_proc_read_main()
166 snd_ac97_stereo_enhancements[(val >> 10) & 0x1f]); snd_ac97_proc_read_main()
168 val = snd_ac97_read(ac97, AC97_MIC); snd_ac97_proc_read_main()
169 snd_iprintf(buffer, "Mic gain : %s [%s]\n", val & 0x0040 ? "+20dB" : "+0dB", ac97->regs[AC97_MIC] & 0x0040 ? "+20dB" : "+0dB"); snd_ac97_proc_read_main()
170 val = snd_ac97_read(ac97, AC97_GENERAL_PURPOSE); snd_ac97_proc_read_main()
178 val & 0x8000 ? "post" : "pre", snd_ac97_proc_read_main()
179 val & 0x4000 ? "on" : "off", snd_ac97_proc_read_main()
180 val & 0x2000 ? "on" : "off", snd_ac97_proc_read_main()
181 val & 0x1000 ? "on" : "off", snd_ac97_proc_read_main()
182 val & 0x0200 ? "Mic" : "MIX", snd_ac97_proc_read_main()
183 val & 0x0100 ? "Mic2" : "Mic1", snd_ac97_proc_read_main()
184 val & 0x0080 ? "on" : "off"); snd_ac97_proc_read_main()
187 double_rate_slots[(val >> 10) & 3]); snd_ac97_proc_read_main()
205 val = snd_ac97_read(ac97, AC97_EXTENDED_STATUS); snd_ac97_proc_read_main()
207 val & AC97_EA_PRL ? " PRL" : "", snd_ac97_proc_read_main()
208 val & AC97_EA_PRK ? " PRK" : "", snd_ac97_proc_read_main()
209 val & AC97_EA_PRJ ? " PRJ" : "", snd_ac97_proc_read_main()
210 val & AC97_EA_PRI ? " PRI" : "", snd_ac97_proc_read_main()
211 val & AC97_EA_SPCV ? " SPCV" : "", snd_ac97_proc_read_main()
212 val & AC97_EA_MDAC ? " MADC" : "", snd_ac97_proc_read_main()
213 val & AC97_EA_LDAC ? " LDAC" : "", snd_ac97_proc_read_main()
214 val & AC97_EA_SDAC ? " SDAC" : "", snd_ac97_proc_read_main()
215 val & AC97_EA_CDAC ? " CDAC" : "", snd_ac97_proc_read_main()
216 ext & AC97_EI_SPDIF ? spdif_slots[(val & AC97_EA_SPSA_SLOT_MASK) >> AC97_EA_SPSA_SLOT_SHIFT] : "", snd_ac97_proc_read_main()
217 val & AC97_EA_VRM ? " VRM" : "", snd_ac97_proc_read_main()
218 val & AC97_EA_SPDIF ? " SPDIF" : "", snd_ac97_proc_read_main()
219 val & AC97_EA_DRA ? " DRA" : "", snd_ac97_proc_read_main()
220 val & AC97_EA_VRA ? " VRA" : ""); snd_ac97_proc_read_main()
222 val = snd_ac97_read(ac97, AC97_PCM_FRONT_DAC_RATE); snd_ac97_proc_read_main()
223 snd_iprintf(buffer, "PCM front DAC : %iHz\n", val); snd_ac97_proc_read_main()
225 val = snd_ac97_read(ac97, AC97_PCM_SURR_DAC_RATE); snd_ac97_proc_read_main()
226 snd_iprintf(buffer, "PCM Surr DAC : %iHz\n", val); snd_ac97_proc_read_main()
229 val = snd_ac97_read(ac97, AC97_PCM_LFE_DAC_RATE); snd_ac97_proc_read_main()
230 snd_iprintf(buffer, "PCM LFE DAC : %iHz\n", val); snd_ac97_proc_read_main()
232 val = snd_ac97_read(ac97, AC97_PCM_LR_ADC_RATE); snd_ac97_proc_read_main()
233 snd_iprintf(buffer, "PCM ADC : %iHz\n", val); snd_ac97_proc_read_main()
236 val = snd_ac97_read(ac97, AC97_PCM_MIC_ADC_RATE); snd_ac97_proc_read_main()
237 snd_iprintf(buffer, "PCM MIC ADC : %iHz\n", val); snd_ac97_proc_read_main()
242 val = snd_ac97_read(ac97, AC97_CSR_SPDIF); snd_ac97_proc_read_main()
244 val = snd_ac97_read(ac97, AC97_YMF7X3_DIT_CTRL); snd_ac97_proc_read_main()
245 val = 0x2000 | (val & 0xff00) >> 4 | (val & 0x38) >> 2; snd_ac97_proc_read_main()
247 val = snd_ac97_read(ac97, AC97_SPDIF); snd_ac97_proc_read_main()
250 val & AC97_SC_PRO ? " PRO" : " Consumer", snd_ac97_proc_read_main()
251 val & AC97_SC_NAUDIO ? " Non-audio" : " PCM", snd_ac97_proc_read_main()
252 val & AC97_SC_COPY ? "" : " Copyright", snd_ac97_proc_read_main()
253 val & AC97_SC_PRE ? " Preemph50/15" : "", snd_ac97_proc_read_main()
254 (val & AC97_SC_CC_MASK) >> AC97_SC_CC_SHIFT, snd_ac97_proc_read_main()
255 (val & AC97_SC_L) >> 11, snd_ac97_proc_read_main()
257 spdif_rates_cs4205[(val & AC97_SC_SPSR_MASK) >> AC97_SC_SPSR_SHIFT] : snd_ac97_proc_read_main()
258 spdif_rates[(val & AC97_SC_SPSR_MASK) >> AC97_SC_SPSR_SHIFT], snd_ac97_proc_read_main()
260 (val & AC97_SC_DRS ? " Validity" : "") : snd_ac97_proc_read_main()
261 (val & AC97_SC_DRS ? " DRS" : ""), snd_ac97_proc_read_main()
263 (val & AC97_SC_V ? " Enabled" : "") : snd_ac97_proc_read_main()
264 (val & AC97_SC_V ? " Validity" : "")); snd_ac97_proc_read_main()
268 val = snd_ac97_read(ac97, AC97_ALC650_SPDIF_INPUT_STATUS2); snd_ac97_proc_read_main()
269 if (val & AC97_ALC650_CLOCK_LOCK) { snd_ac97_proc_read_main()
270 val = snd_ac97_read(ac97, AC97_ALC650_SPDIF_INPUT_STATUS1); snd_ac97_proc_read_main()
272 val & AC97_ALC650_PRO ? " PRO" : " Consumer", snd_ac97_proc_read_main()
273 val & AC97_ALC650_NAUDIO ? " Non-audio" : " PCM", snd_ac97_proc_read_main()
274 val & AC97_ALC650_COPY ? "" : " Copyright", snd_ac97_proc_read_main()
275 val & AC97_ALC650_PRE ? " Preemph50/15" : "", snd_ac97_proc_read_main()
276 (val & AC97_ALC650_CC_MASK) >> AC97_ALC650_CC_SHIFT, snd_ac97_proc_read_main()
277 (val & AC97_ALC650_L) >> 15); snd_ac97_proc_read_main()
278 val = snd_ac97_read(ac97, AC97_ALC650_SPDIF_INPUT_STATUS2); snd_ac97_proc_read_main()
280 spdif_rates[(val & AC97_ALC650_SPSR_MASK) >> AC97_ALC650_SPSR_SHIFT], snd_ac97_proc_read_main()
281 (val & AC97_ALC650_CLOCK_ACCURACY) >> AC97_ALC650_CLOCK_SHIFT, snd_ac97_proc_read_main()
282 (val & AC97_ALC650_CLOCK_LOCK ? " Locked" : " Unlocked"), snd_ac97_proc_read_main()
283 (val & AC97_ALC650_V ? " Validity?" : "")); snd_ac97_proc_read_main()
290 val = snd_ac97_read(ac97, AC97_INT_PAGING); snd_ac97_proc_read_main()
295 AC97_PAGE_MASK, val & AC97_PAGE_MASK); snd_ac97_proc_read_main()
311 val = snd_ac97_read(ac97, AC97_EXTENDED_MSTATUS); snd_ac97_proc_read_main()
313 val & AC97_MEA_GPIO ? " GPIO" : "", snd_ac97_proc_read_main()
314 val & AC97_MEA_MREF ? " MREF" : "", snd_ac97_proc_read_main()
315 val & AC97_MEA_ADC1 ? " ADC1" : "", snd_ac97_proc_read_main()
316 val & AC97_MEA_DAC1 ? " DAC1" : "", snd_ac97_proc_read_main()
317 val & AC97_MEA_ADC2 ? " ADC2" : "", snd_ac97_proc_read_main()
318 val & AC97_MEA_DAC2 ? " DAC2" : "", snd_ac97_proc_read_main()
319 val & AC97_MEA_HADC ? " HADC" : "", snd_ac97_proc_read_main()
320 val & AC97_MEA_HDAC ? " HDAC" : "", snd_ac97_proc_read_main()
321 val & AC97_MEA_PRA ? " PRA(GPIO)" : "", snd_ac97_proc_read_main()
322 val & AC97_MEA_PRB ? " PRB(res)" : "", snd_ac97_proc_read_main()
323 val & AC97_MEA_PRC ? " PRC(ADC1)" : "", snd_ac97_proc_read_main()
324 val & AC97_MEA_PRD ? " PRD(DAC1)" : "", snd_ac97_proc_read_main()
325 val & AC97_MEA_PRE ? " PRE(ADC2)" : "", snd_ac97_proc_read_main()
326 val & AC97_MEA_PRF ? " PRF(DAC2)" : "", snd_ac97_proc_read_main()
327 val & AC97_MEA_PRG ? " PRG(HADC)" : "", snd_ac97_proc_read_main()
328 val & AC97_MEA_PRH ? " PRH(HDAC)" : ""); snd_ac97_proc_read_main()
330 val = snd_ac97_read(ac97, AC97_LINE1_RATE); snd_ac97_proc_read_main()
331 snd_iprintf(buffer, "Line1 rate : %iHz\n", val); snd_ac97_proc_read_main()
334 val = snd_ac97_read(ac97, AC97_LINE2_RATE); snd_ac97_proc_read_main()
335 snd_iprintf(buffer, "Line2 rate : %iHz\n", val); snd_ac97_proc_read_main()
338 val = snd_ac97_read(ac97, AC97_HANDSET_RATE); snd_ac97_proc_read_main()
339 snd_iprintf(buffer, "Headset rate : %iHz\n", val); snd_ac97_proc_read_main()
382 unsigned int reg, val; snd_ac97_proc_regs_write() local
385 if (sscanf(line, "%x %x", &reg, &val) != 2) snd_ac97_proc_regs_write()
388 if (reg < 0x80 && (reg & 1) == 0 && val <= 0xffff) snd_ac97_proc_regs_write()
389 snd_ac97_write_cache(ac97, reg, val); snd_ac97_proc_regs_write()
397 int reg, val; snd_ac97_proc_regs_read_main() local
400 val = snd_ac97_read(ac97, reg); snd_ac97_proc_regs_read_main()
401 snd_iprintf(buffer, "%i:%02x = %04x\n", subidx, reg, val); snd_ac97_proc_regs_read_main()
/linux-4.1.27/drivers/net/wireless/ath/ath5k/
H A Deeprom.c43 u16 val; ath5k_eeprom_bin2freq() local
50 val = (5 * bin) + 4800; ath5k_eeprom_bin2freq()
52 val = bin > 62 ? (10 * 62) + (5 * (bin - 62)) + 5100 : ath5k_eeprom_bin2freq()
56 val = bin + 2300; ath5k_eeprom_bin2freq()
58 val = bin + 2400; ath5k_eeprom_bin2freq()
61 return val; ath5k_eeprom_bin2freq()
76 u16 val; ath5k_eeprom_init_header() local
96 AR5K_EEPROM_READ(AR5K_EEPROM_SIZE_UPPER, val); ath5k_eeprom_init_header()
97 if (val) { ath5k_eeprom_init_header()
98 eep_max = (val & AR5K_EEPROM_SIZE_UPPER_MASK) << ath5k_eeprom_init_header()
100 AR5K_EEPROM_READ(AR5K_EEPROM_SIZE_LOWER, val); ath5k_eeprom_init_header()
101 eep_max = (eep_max | val) - AR5K_EEPROM_INFO_BASE; ath5k_eeprom_init_header()
119 AR5K_EEPROM_READ(AR5K_EEPROM_INFO(offset), val); ath5k_eeprom_init_header() local
120 cksum ^= val; ath5k_eeprom_init_header()
152 AR5K_EEPROM_READ(AR5K_EEPROM_OBDB0_2GHZ, val); ath5k_eeprom_init_header()
153 ee->ee_ob[AR5K_EEPROM_MODE_11B][0] = val & 0x7; ath5k_eeprom_init_header()
154 ee->ee_db[AR5K_EEPROM_MODE_11B][0] = (val >> 3) & 0x7; ath5k_eeprom_init_header()
156 AR5K_EEPROM_READ(AR5K_EEPROM_OBDB1_2GHZ, val); ath5k_eeprom_init_header()
157 ee->ee_ob[AR5K_EEPROM_MODE_11G][0] = val & 0x7; ath5k_eeprom_init_header()
158 ee->ee_db[AR5K_EEPROM_MODE_11G][0] = (val >> 3) & 0x7; ath5k_eeprom_init_header()
161 AR5K_EEPROM_READ(AR5K_EEPROM_IS_HB63, val); ath5k_eeprom_init_header()
163 if ((ah->ah_mac_version == (AR5K_SREV_AR2425 >> 4)) && val) ath5k_eeprom_init_header()
168 AR5K_EEPROM_READ(AR5K_EEPROM_RFKILL, val); ath5k_eeprom_init_header()
169 ee->ee_rfkill_pin = (u8) AR5K_REG_MS(val, AR5K_EEPROM_RFKILL_GPIO_SEL); ath5k_eeprom_init_header()
170 ee->ee_rfkill_pol = val & AR5K_EEPROM_RFKILL_POLARITY ? true : false; ath5k_eeprom_init_header()
178 AR5K_EEPROM_READ(AR5K_EEPROM_PCIE_OFFSET, val); ath5k_eeprom_init_header()
179 ee->ee_serdes = (val == AR5K_EEPROM_PCIE_SERDES_SECTION) ? ath5k_eeprom_init_header()
194 u16 val; ath5k_eeprom_read_ants() local
197 AR5K_EEPROM_READ(o++, val); ath5k_eeprom_read_ants()
198 ee->ee_switch_settling[mode] = (val >> 8) & 0x7f; ath5k_eeprom_read_ants()
199 ee->ee_atn_tx_rx[mode] = (val >> 2) & 0x3f; ath5k_eeprom_read_ants()
200 ee->ee_ant_control[mode][i] = (val << 4) & 0x3f; ath5k_eeprom_read_ants()
202 AR5K_EEPROM_READ(o++, val); ath5k_eeprom_read_ants()
203 ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf; ath5k_eeprom_read_ants()
204 ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f; ath5k_eeprom_read_ants()
205 ee->ee_ant_control[mode][i++] = val & 0x3f; ath5k_eeprom_read_ants()
207 AR5K_EEPROM_READ(o++, val); ath5k_eeprom_read_ants()
208 ee->ee_ant_control[mode][i++] = (val >> 10) & 0x3f; ath5k_eeprom_read_ants()
209 ee->ee_ant_control[mode][i++] = (val >> 4) & 0x3f; ath5k_eeprom_read_ants()
210 ee->ee_ant_control[mode][i] = (val << 2) & 0x3f; ath5k_eeprom_read_ants()
212 AR5K_EEPROM_READ(o++, val); ath5k_eeprom_read_ants()
213 ee->ee_ant_control[mode][i++] |= (val >> 14) & 0x3; ath5k_eeprom_read_ants()
214 ee->ee_ant_control[mode][i++] = (val >> 8) & 0x3f; ath5k_eeprom_read_ants()
215 ee->ee_ant_control[mode][i++] = (val >> 2) & 0x3f; ath5k_eeprom_read_ants()
216 ee->ee_ant_control[mode][i] = (val << 4) & 0x3f; ath5k_eeprom_read_ants()
218 AR5K_EEPROM_READ(o++, val); ath5k_eeprom_read_ants()
219 ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf; ath5k_eeprom_read_ants()
220 ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f; ath5k_eeprom_read_ants()
221 ee->ee_ant_control[mode][i++] = val & 0x3f; ath5k_eeprom_read_ants()
254 u16 val; ath5k_eeprom_read_modes() local
257 AR5K_EEPROM_READ(o++, val); ath5k_eeprom_read_modes()
258 ee->ee_adc_desired_size[mode] = (s8)((val >> 8) & 0xff); ath5k_eeprom_read_modes()
261 ee->ee_ob[mode][3] = (val >> 5) & 0x7; ath5k_eeprom_read_modes()
262 ee->ee_db[mode][3] = (val >> 2) & 0x7; ath5k_eeprom_read_modes()
263 ee->ee_ob[mode][2] = (val << 1) & 0x7; ath5k_eeprom_read_modes()
265 AR5K_EEPROM_READ(o++, val); ath5k_eeprom_read_modes()
266 ee->ee_ob[mode][2] |= (val >> 15) & 0x1; ath5k_eeprom_read_modes()
267 ee->ee_db[mode][2] = (val >> 12) & 0x7; ath5k_eeprom_read_modes()
268 ee->ee_ob[mode][1] = (val >> 9) & 0x7; ath5k_eeprom_read_modes()
269 ee->ee_db[mode][1] = (val >> 6) & 0x7; ath5k_eeprom_read_modes()
270 ee->ee_ob[mode][0] = (val >> 3) & 0x7; ath5k_eeprom_read_modes()
271 ee->ee_db[mode][0] = val & 0x7; ath5k_eeprom_read_modes()
275 ee->ee_ob[mode][1] = (val >> 4) & 0x7; ath5k_eeprom_read_modes()
276 ee->ee_db[mode][1] = val & 0x7; ath5k_eeprom_read_modes()
280 AR5K_EEPROM_READ(o++, val); ath5k_eeprom_read_modes()
281 ee->ee_tx_end2xlna_enable[mode] = (val >> 8) & 0xff; ath5k_eeprom_read_modes()
282 ee->ee_thr_62[mode] = val & 0xff; ath5k_eeprom_read_modes()
287 AR5K_EEPROM_READ(o++, val); ath5k_eeprom_read_modes()
288 ee->ee_tx_end2xpa_disable[mode] = (val >> 8) & 0xff; ath5k_eeprom_read_modes()
289 ee->ee_tx_frm2xpa_enable[mode] = val & 0xff; ath5k_eeprom_read_modes()
291 AR5K_EEPROM_READ(o++, val); ath5k_eeprom_read_modes()
292 ee->ee_pga_desired_size[mode] = (val >> 8) & 0xff; ath5k_eeprom_read_modes()
294 if ((val & 0xff) & 0x80) ath5k_eeprom_read_modes()
295 ee->ee_noise_floor_thr[mode] = -((((val & 0xff) ^ 0xff)) + 1); ath5k_eeprom_read_modes()
297 ee->ee_noise_floor_thr[mode] = val & 0xff; ath5k_eeprom_read_modes()
303 AR5K_EEPROM_READ(o++, val); ath5k_eeprom_read_modes()
304 ee->ee_xlna_gain[mode] = (val >> 5) & 0xff; ath5k_eeprom_read_modes()
305 ee->ee_x_gain[mode] = (val >> 1) & 0xf; ath5k_eeprom_read_modes()
306 ee->ee_xpd[mode] = val & 0x1; ath5k_eeprom_read_modes()
310 ee->ee_fixed_bias[mode] = (val >> 13) & 0x1; ath5k_eeprom_read_modes()
313 AR5K_EEPROM_READ(o++, val); ath5k_eeprom_read_modes()
314 ee->ee_false_detect[mode] = (val >> 6) & 0x7f; ath5k_eeprom_read_modes()
317 ee->ee_xr_power[mode] = val & 0x3f; ath5k_eeprom_read_modes()
320 ee->ee_ob[mode][0] = val & 0x7; ath5k_eeprom_read_modes()
321 ee->ee_db[mode][0] = (val >> 3) & 0x7; ath5k_eeprom_read_modes()
329 ee->ee_i_gain[mode] = (val >> 13) & 0x7; ath5k_eeprom_read_modes()
331 AR5K_EEPROM_READ(o++, val); ath5k_eeprom_read_modes()
332 ee->ee_i_gain[mode] |= (val << 3) & 0x38; ath5k_eeprom_read_modes()
335 ee->ee_cck_ofdm_power_delta = (val >> 3) & 0xff; ath5k_eeprom_read_modes()
337 ee->ee_scaled_cck_delta = (val >> 11) & 0x1f; ath5k_eeprom_read_modes()
343 ee->ee_i_cal[mode] = (val >> 8) & 0x3f; ath5k_eeprom_read_modes()
344 ee->ee_q_cal[mode] = (val >> 3) & 0x1f; ath5k_eeprom_read_modes()
358 AR5K_EEPROM_READ(o++, val); ath5k_eeprom_read_modes()
359 ee->ee_margin_tx_rx[mode] = val & 0x3f; ath5k_eeprom_read_modes()
362 AR5K_EEPROM_READ(o++, val); ath5k_eeprom_read_modes()
365 ath5k_eeprom_bin2freq(ee, val & 0xff, mode); ath5k_eeprom_read_modes()
370 ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff, mode); ath5k_eeprom_read_modes()
374 AR5K_EEPROM_READ(o++, val); ath5k_eeprom_read_modes()
376 ath5k_eeprom_bin2freq(ee, val & 0xff, mode); ath5k_eeprom_read_modes()
381 ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f; ath5k_eeprom_read_modes()
384 AR5K_EEPROM_READ(o++, val); ath5k_eeprom_read_modes()
387 ath5k_eeprom_bin2freq(ee, val & 0xff, mode); ath5k_eeprom_read_modes()
392 ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff, mode); ath5k_eeprom_read_modes()
396 AR5K_EEPROM_READ(o++, val); ath5k_eeprom_read_modes()
397 ee->ee_turbo_max_power[mode] = val & 0x7f; ath5k_eeprom_read_modes()
398 ee->ee_xr_power[mode] = (val >> 7) & 0x3f; ath5k_eeprom_read_modes()
400 AR5K_EEPROM_READ(o++, val); ath5k_eeprom_read_modes()
402 ath5k_eeprom_bin2freq(ee, val & 0xff, mode); ath5k_eeprom_read_modes()
407 ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f; ath5k_eeprom_read_modes()
409 AR5K_EEPROM_READ(o++, val); ath5k_eeprom_read_modes()
410 ee->ee_i_cal[mode] = (val >> 5) & 0x3f; ath5k_eeprom_read_modes()
411 ee->ee_q_cal[mode] = val & 0x1f; ath5k_eeprom_read_modes()
414 AR5K_EEPROM_READ(o++, val); ath5k_eeprom_read_modes()
415 ee->ee_cck_ofdm_gain_delta = val & 0xff; ath5k_eeprom_read_modes()
428 ee->ee_switch_settling_turbo[mode] = (val >> 6) & 0x7f; ath5k_eeprom_read_modes()
430 ee->ee_atn_tx_rx_turbo[mode] = (val >> 13) & 0x7; ath5k_eeprom_read_modes()
431 AR5K_EEPROM_READ(o++, val); ath5k_eeprom_read_modes()
432 ee->ee_atn_tx_rx_turbo[mode] |= (val & 0x7) << 3; ath5k_eeprom_read_modes()
433 ee->ee_margin_tx_rx_turbo[mode] = (val >> 3) & 0x3f; ath5k_eeprom_read_modes()
435 ee->ee_adc_desired_size_turbo[mode] = (val >> 9) & 0x7f; ath5k_eeprom_read_modes()
436 AR5K_EEPROM_READ(o++, val); ath5k_eeprom_read_modes()
437 ee->ee_adc_desired_size_turbo[mode] |= (val & 0x1) << 7; ath5k_eeprom_read_modes()
438 ee->ee_pga_desired_size_turbo[mode] = (val >> 1) & 0xff; ath5k_eeprom_read_modes()
441 ee->ee_pd_gain_overlap = (val >> 9) & 0xf; ath5k_eeprom_read_modes()
444 ee->ee_switch_settling_turbo[mode] = (val >> 8) & 0x7f; ath5k_eeprom_read_modes()
446 ee->ee_atn_tx_rx_turbo[mode] = (val >> 15) & 0x7; ath5k_eeprom_read_modes()
447 AR5K_EEPROM_READ(o++, val); ath5k_eeprom_read_modes()
448 ee->ee_atn_tx_rx_turbo[mode] |= (val & 0x1f) << 1; ath5k_eeprom_read_modes()
449 ee->ee_margin_tx_rx_turbo[mode] = (val >> 5) & 0x3f; ath5k_eeprom_read_modes()
451 ee->ee_adc_desired_size_turbo[mode] = (val >> 11) & 0x7f; ath5k_eeprom_read_modes()
452 AR5K_EEPROM_READ(o++, val); ath5k_eeprom_read_modes()
453 ee->ee_adc_desired_size_turbo[mode] |= (val & 0x7) << 5; ath5k_eeprom_read_modes()
454 ee->ee_pga_desired_size_turbo[mode] = (val >> 3) & 0xff; ath5k_eeprom_read_modes()
517 u16 val; ath5k_eeprom_read_freq_list() local
521 AR5K_EEPROM_READ(o++, val); ath5k_eeprom_read_freq_list()
523 freq1 = val & 0xff; ath5k_eeprom_read_freq_list()
531 freq2 = (val >> 8) & 0xff; ath5k_eeprom_read_freq_list()
553 u16 val; ath5k_eeprom_init_11a_pcal_freq() local
563 AR5K_EEPROM_READ(offset++, val); ath5k_eeprom_init_11a_pcal_freq()
564 pcal[0].freq = (val >> 9) & mask; ath5k_eeprom_init_11a_pcal_freq()
565 pcal[1].freq = (val >> 2) & mask; ath5k_eeprom_init_11a_pcal_freq()
566 pcal[2].freq = (val << 5) & mask; ath5k_eeprom_init_11a_pcal_freq()
568 AR5K_EEPROM_READ(offset++, val); ath5k_eeprom_init_11a_pcal_freq()
569 pcal[2].freq |= (val >> 11) & 0x1f; ath5k_eeprom_init_11a_pcal_freq()
570 pcal[3].freq = (val >> 4) & mask; ath5k_eeprom_init_11a_pcal_freq()
571 pcal[4].freq = (val << 3) & mask; ath5k_eeprom_init_11a_pcal_freq()
573 AR5K_EEPROM_READ(offset++, val); ath5k_eeprom_init_11a_pcal_freq()
574 pcal[4].freq |= (val >> 13) & 0x7; ath5k_eeprom_init_11a_pcal_freq()
575 pcal[5].freq = (val >> 6) & mask; ath5k_eeprom_init_11a_pcal_freq()
576 pcal[6].freq = (val << 1) & mask; ath5k_eeprom_init_11a_pcal_freq()
578 AR5K_EEPROM_READ(offset++, val); ath5k_eeprom_init_11a_pcal_freq()
579 pcal[6].freq |= (val >> 15) & 0x1; ath5k_eeprom_init_11a_pcal_freq()
580 pcal[7].freq = (val >> 8) & mask; ath5k_eeprom_init_11a_pcal_freq()
581 pcal[8].freq = (val >> 1) & mask; ath5k_eeprom_init_11a_pcal_freq()
582 pcal[9].freq = (val << 6) & mask; ath5k_eeprom_init_11a_pcal_freq()
584 AR5K_EEPROM_READ(offset++, val); ath5k_eeprom_init_11a_pcal_freq()
585 pcal[9].freq |= (val >> 10) & 0x3f; ath5k_eeprom_init_11a_pcal_freq()
799 u16 val; ath5k_eeprom_read_pcal_info_5111() local
850 AR5K_EEPROM_READ(offset++, val); ath5k_eeprom_read_pcal_info_5111()
851 cdata->pcdac_max = ((val >> 10) & AR5K_EEPROM_PCDAC_M); ath5k_eeprom_read_pcal_info_5111()
852 cdata->pcdac_min = ((val >> 4) & AR5K_EEPROM_PCDAC_M); ath5k_eeprom_read_pcal_info_5111()
853 cdata->pwr[0] = ((val << 2) & AR5K_EEPROM_POWER_M); ath5k_eeprom_read_pcal_info_5111()
855 AR5K_EEPROM_READ(offset++, val); ath5k_eeprom_read_pcal_info_5111()
856 cdata->pwr[0] |= ((val >> 14) & 0x3); ath5k_eeprom_read_pcal_info_5111()
857 cdata->pwr[1] = ((val >> 8) & AR5K_EEPROM_POWER_M); ath5k_eeprom_read_pcal_info_5111()
858 cdata->pwr[2] = ((val >> 2) & AR5K_EEPROM_POWER_M); ath5k_eeprom_read_pcal_info_5111()
859 cdata->pwr[3] = ((val << 4) & AR5K_EEPROM_POWER_M); ath5k_eeprom_read_pcal_info_5111()
861 AR5K_EEPROM_READ(offset++, val); ath5k_eeprom_read_pcal_info_5111()
862 cdata->pwr[3] |= ((val >> 12) & 0xf); ath5k_eeprom_read_pcal_info_5111()
863 cdata->pwr[4] = ((val >> 6) & AR5K_EEPROM_POWER_M); ath5k_eeprom_read_pcal_info_5111()
864 cdata->pwr[5] = (val & AR5K_EEPROM_POWER_M); ath5k_eeprom_read_pcal_info_5111()
866 AR5K_EEPROM_READ(offset++, val); ath5k_eeprom_read_pcal_info_5111()
867 cdata->pwr[6] = ((val >> 10) & AR5K_EEPROM_POWER_M); ath5k_eeprom_read_pcal_info_5111()
868 cdata->pwr[7] = ((val >> 4) & AR5K_EEPROM_POWER_M); ath5k_eeprom_read_pcal_info_5111()
869 cdata->pwr[8] = ((val << 2) & AR5K_EEPROM_POWER_M); ath5k_eeprom_read_pcal_info_5111()
871 AR5K_EEPROM_READ(offset++, val); ath5k_eeprom_read_pcal_info_5111()
872 cdata->pwr[8] |= ((val >> 14) & 0x3); ath5k_eeprom_read_pcal_info_5111()
873 cdata->pwr[9] = ((val >> 8) & AR5K_EEPROM_POWER_M); ath5k_eeprom_read_pcal_info_5111()
874 cdata->pwr[10] = ((val >> 2) & AR5K_EEPROM_POWER_M); ath5k_eeprom_read_pcal_info_5111()
1024 u16 val; ath5k_eeprom_read_pcal_info_5112() local
1082 AR5K_EEPROM_READ(offset++, val); ath5k_eeprom_read_pcal_info_5112()
1083 chan_pcal_info->pwr_x0[c] = (s8) (val & 0xff); ath5k_eeprom_read_pcal_info_5112()
1084 chan_pcal_info->pwr_x0[++c] = (s8) ((val >> 8) & 0xff); ath5k_eeprom_read_pcal_info_5112()
1090 AR5K_EEPROM_READ(offset++, val); ath5k_eeprom_read_pcal_info_5112()
1091 chan_pcal_info->pcdac_x0[1] = (val & 0x1f); ath5k_eeprom_read_pcal_info_5112()
1092 chan_pcal_info->pcdac_x0[2] = ((val >> 5) & 0x1f); ath5k_eeprom_read_pcal_info_5112()
1093 chan_pcal_info->pcdac_x0[3] = ((val >> 10) & 0x1f); ath5k_eeprom_read_pcal_info_5112()
1098 AR5K_EEPROM_READ(offset++, val); ath5k_eeprom_read_pcal_info_5112()
1099 chan_pcal_info->pwr_x3[0] = (s8) (val & 0xff); ath5k_eeprom_read_pcal_info_5112()
1100 chan_pcal_info->pwr_x3[1] = (s8) ((val >> 8) & 0xff); ath5k_eeprom_read_pcal_info_5112()
1102 AR5K_EEPROM_READ(offset++, val); ath5k_eeprom_read_pcal_info_5112()
1103 chan_pcal_info->pwr_x3[2] = (val & 0xff); ath5k_eeprom_read_pcal_info_5112()
1113 chan_pcal_info->pcdac_x0[0] = ((val >> 8) & 0x3f); ath5k_eeprom_read_pcal_info_5112()
1119 gen_chan_info[i].max_pwr = (s8) ((val >> 8) & 0xff); ath5k_eeprom_read_pcal_info_5112()
1287 u16 val; ath5k_eeprom_read_pcal_info_2413() local
1343 AR5K_EEPROM_READ(offset++, val); ath5k_eeprom_read_pcal_info_2413()
1344 pcinfo->pwr_i[0] = val & 0x1f; ath5k_eeprom_read_pcal_info_2413()
1345 pcinfo->pddac_i[0] = (val >> 5) & 0x7f; ath5k_eeprom_read_pcal_info_2413()
1346 pcinfo->pwr[0][0] = (val >> 12) & 0xf; ath5k_eeprom_read_pcal_info_2413()
1348 AR5K_EEPROM_READ(offset++, val); ath5k_eeprom_read_pcal_info_2413()
1349 pcinfo->pddac[0][0] = val & 0x3f; ath5k_eeprom_read_pcal_info_2413()
1350 pcinfo->pwr[0][1] = (val >> 6) & 0xf; ath5k_eeprom_read_pcal_info_2413()
1351 pcinfo->pddac[0][1] = (val >> 10) & 0x3f; ath5k_eeprom_read_pcal_info_2413()
1353 AR5K_EEPROM_READ(offset++, val); ath5k_eeprom_read_pcal_info_2413()
1354 pcinfo->pwr[0][2] = val & 0xf; ath5k_eeprom_read_pcal_info_2413()
1355 pcinfo->pddac[0][2] = (val >> 4) & 0x3f; ath5k_eeprom_read_pcal_info_2413()
1366 pcinfo->pwr_i[1] = (val >> 10) & 0x1f; ath5k_eeprom_read_pcal_info_2413()
1368 pcinfo->pddac_i[1] = (val >> 15) & 0x1; ath5k_eeprom_read_pcal_info_2413()
1369 AR5K_EEPROM_READ(offset++, val); ath5k_eeprom_read_pcal_info_2413()
1370 pcinfo->pddac_i[1] |= (val & 0x3F) << 1; ath5k_eeprom_read_pcal_info_2413()
1372 pcinfo->pwr[1][0] = (val >> 6) & 0xf; ath5k_eeprom_read_pcal_info_2413()
1373 pcinfo->pddac[1][0] = (val >> 10) & 0x3f; ath5k_eeprom_read_pcal_info_2413()
1375 AR5K_EEPROM_READ(offset++, val); ath5k_eeprom_read_pcal_info_2413()
1376 pcinfo->pwr[1][1] = val & 0xf; ath5k_eeprom_read_pcal_info_2413()
1377 pcinfo->pddac[1][1] = (val >> 4) & 0x3f; ath5k_eeprom_read_pcal_info_2413()
1378 pcinfo->pwr[1][2] = (val >> 10) & 0xf; ath5k_eeprom_read_pcal_info_2413()
1380 pcinfo->pddac[1][2] = (val >> 14) & 0x3; ath5k_eeprom_read_pcal_info_2413()
1381 AR5K_EEPROM_READ(offset++, val); ath5k_eeprom_read_pcal_info_2413()
1382 pcinfo->pddac[1][2] |= (val & 0xF) << 2; ath5k_eeprom_read_pcal_info_2413()
1391 pcinfo->pwr[0][3] = (val >> 10) & 0xf; ath5k_eeprom_read_pcal_info_2413()
1393 pcinfo->pddac[0][3] = (val >> 14) & 0x3; ath5k_eeprom_read_pcal_info_2413()
1394 AR5K_EEPROM_READ(offset++, val); ath5k_eeprom_read_pcal_info_2413()
1395 pcinfo->pddac[0][3] |= (val & 0xF) << 2; ath5k_eeprom_read_pcal_info_2413()
1403 pcinfo->pwr_i[2] = (val >> 4) & 0x1f; ath5k_eeprom_read_pcal_info_2413()
1404 pcinfo->pddac_i[2] = (val >> 9) & 0x7f; ath5k_eeprom_read_pcal_info_2413()
1406 AR5K_EEPROM_READ(offset++, val); ath5k_eeprom_read_pcal_info_2413()
1407 pcinfo->pwr[2][0] = (val >> 0) & 0xf; ath5k_eeprom_read_pcal_info_2413()
1408 pcinfo->pddac[2][0] = (val >> 4) & 0x3f; ath5k_eeprom_read_pcal_info_2413()
1409 pcinfo->pwr[2][1] = (val >> 10) & 0xf; ath5k_eeprom_read_pcal_info_2413()
1411 pcinfo->pddac[2][1] = (val >> 14) & 0x3; ath5k_eeprom_read_pcal_info_2413()
1412 AR5K_EEPROM_READ(offset++, val); ath5k_eeprom_read_pcal_info_2413()
1413 pcinfo->pddac[2][1] |= (val & 0xF) << 2; ath5k_eeprom_read_pcal_info_2413()
1415 pcinfo->pwr[2][2] = (val >> 4) & 0xf; ath5k_eeprom_read_pcal_info_2413()
1416 pcinfo->pddac[2][2] = (val >> 8) & 0x3f; ath5k_eeprom_read_pcal_info_2413()
1421 pcinfo->pwr[1][3] = (val >> 4) & 0xf; ath5k_eeprom_read_pcal_info_2413()
1422 pcinfo->pddac[1][3] = (val >> 8) & 0x3f; ath5k_eeprom_read_pcal_info_2413()
1426 pcinfo->pwr_i[3] = (val >> 14) & 0x3; ath5k_eeprom_read_pcal_info_2413()
1427 AR5K_EEPROM_READ(offset++, val); ath5k_eeprom_read_pcal_info_2413()
1428 pcinfo->pwr_i[3] |= ((val >> 0) & 0x7) << 2; ath5k_eeprom_read_pcal_info_2413()
1430 pcinfo->pddac_i[3] = (val >> 3) & 0x7f; ath5k_eeprom_read_pcal_info_2413()
1431 pcinfo->pwr[3][0] = (val >> 10) & 0xf; ath5k_eeprom_read_pcal_info_2413()
1432 pcinfo->pddac[3][0] = (val >> 14) & 0x3; ath5k_eeprom_read_pcal_info_2413()
1434 AR5K_EEPROM_READ(offset++, val); ath5k_eeprom_read_pcal_info_2413()
1435 pcinfo->pddac[3][0] |= (val & 0xF) << 2; ath5k_eeprom_read_pcal_info_2413()
1436 pcinfo->pwr[3][1] = (val >> 4) & 0xf; ath5k_eeprom_read_pcal_info_2413()
1437 pcinfo->pddac[3][1] = (val >> 8) & 0x3f; ath5k_eeprom_read_pcal_info_2413()
1439 pcinfo->pwr[3][2] = (val >> 14) & 0x3; ath5k_eeprom_read_pcal_info_2413()
1440 AR5K_EEPROM_READ(offset++, val); ath5k_eeprom_read_pcal_info_2413()
1441 pcinfo->pwr[3][2] |= ((val >> 0) & 0x3) << 2; ath5k_eeprom_read_pcal_info_2413()
1443 pcinfo->pddac[3][2] = (val >> 2) & 0x3f; ath5k_eeprom_read_pcal_info_2413()
1444 pcinfo->pwr[3][3] = (val >> 8) & 0xf; ath5k_eeprom_read_pcal_info_2413()
1446 pcinfo->pddac[3][3] = (val >> 12) & 0xF; ath5k_eeprom_read_pcal_info_2413()
1447 AR5K_EEPROM_READ(offset++, val); ath5k_eeprom_read_pcal_info_2413()
1448 pcinfo->pddac[3][3] |= ((val >> 0) & 0x3) << 4; ath5k_eeprom_read_pcal_info_2413()
1450 pcinfo->pwr[2][3] = (val >> 14) & 0x3; ath5k_eeprom_read_pcal_info_2413()
1451 AR5K_EEPROM_READ(offset++, val); ath5k_eeprom_read_pcal_info_2413()
1452 pcinfo->pwr[2][3] |= ((val >> 0) & 0x3) << 2; ath5k_eeprom_read_pcal_info_2413()
1454 pcinfo->pddac[2][3] = (val >> 2) & 0x3f; ath5k_eeprom_read_pcal_info_2413()
1476 u16 val; ath5k_eeprom_read_target_rate_pwr_info() local
1504 AR5K_EEPROM_READ(offset++, val); ath5k_eeprom_read_target_rate_pwr_info()
1506 ath5k_eeprom_bin2freq(ee, (val >> 9) & 0x7f, mode); ath5k_eeprom_read_target_rate_pwr_info()
1508 rate_pcal_info[i].target_power_6to24 = ((val >> 3) & 0x3f); ath5k_eeprom_read_target_rate_pwr_info()
1509 rate_pcal_info[i].target_power_36 = (val << 3) & 0x3f; ath5k_eeprom_read_target_rate_pwr_info()
1511 AR5K_EEPROM_READ(offset++, val); ath5k_eeprom_read_target_rate_pwr_info()
1514 val == 0) { ath5k_eeprom_read_target_rate_pwr_info()
1519 rate_pcal_info[i].target_power_36 |= ((val >> 13) & 0x7); ath5k_eeprom_read_target_rate_pwr_info()
1520 rate_pcal_info[i].target_power_48 = ((val >> 7) & 0x3f); ath5k_eeprom_read_target_rate_pwr_info()
1521 rate_pcal_info[i].target_power_54 = ((val >> 1) & 0x3f); ath5k_eeprom_read_target_rate_pwr_info()
1525 AR5K_EEPROM_READ(offset++, val); ath5k_eeprom_read_target_rate_pwr_info()
1527 ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff, mode); ath5k_eeprom_read_target_rate_pwr_info()
1529 rate_pcal_info[i].target_power_6to24 = ((val >> 2) & 0x3f); ath5k_eeprom_read_target_rate_pwr_info()
1530 rate_pcal_info[i].target_power_36 = (val << 4) & 0x3f; ath5k_eeprom_read_target_rate_pwr_info()
1532 AR5K_EEPROM_READ(offset++, val); ath5k_eeprom_read_target_rate_pwr_info()
1535 val == 0) { ath5k_eeprom_read_target_rate_pwr_info()
1540 rate_pcal_info[i].target_power_36 |= (val >> 12) & 0xf; ath5k_eeprom_read_target_rate_pwr_info()
1541 rate_pcal_info[i].target_power_48 = ((val >> 6) & 0x3f); ath5k_eeprom_read_target_rate_pwr_info()
1542 rate_pcal_info[i].target_power_54 = (val & 0x3f); ath5k_eeprom_read_target_rate_pwr_info()
1606 u16 val; ath5k_eeprom_read_ctl_info() local
1613 AR5K_EEPROM_READ(offset++, val); ath5k_eeprom_read_ctl_info()
1614 ee->ee_ctl[i] = (val >> 8) & 0xff; ath5k_eeprom_read_ctl_info()
1615 ee->ee_ctl[i + 1] = val & 0xff; ath5k_eeprom_read_ctl_info()
1646 AR5K_EEPROM_READ(offset++, val); ath5k_eeprom_read_ctl_info()
1647 rep[j].freq = (val >> 8) & fmask; ath5k_eeprom_read_ctl_info()
1648 rep[j + 1].freq = val & fmask; ath5k_eeprom_read_ctl_info()
1651 AR5K_EEPROM_READ(offset++, val); ath5k_eeprom_read_ctl_info()
1652 rep[j].edge = (val >> 8) & pmask; ath5k_eeprom_read_ctl_info()
1653 rep[j].flag = (val >> 14) & 1; ath5k_eeprom_read_ctl_info()
1654 rep[j + 1].edge = val & pmask; ath5k_eeprom_read_ctl_info()
1655 rep[j + 1].flag = (val >> 6) & 1; ath5k_eeprom_read_ctl_info()
1658 AR5K_EEPROM_READ(offset++, val); ath5k_eeprom_read_ctl_info()
1659 rep[0].freq = (val >> 9) & fmask; ath5k_eeprom_read_ctl_info()
1660 rep[1].freq = (val >> 2) & fmask; ath5k_eeprom_read_ctl_info()
1661 rep[2].freq = (val << 5) & fmask; ath5k_eeprom_read_ctl_info()
1663 AR5K_EEPROM_READ(offset++, val); ath5k_eeprom_read_ctl_info()
1664 rep[2].freq |= (val >> 11) & 0x1f; ath5k_eeprom_read_ctl_info()
1665 rep[3].freq = (val >> 4) & fmask; ath5k_eeprom_read_ctl_info()
1666 rep[4].freq = (val << 3) & fmask; ath5k_eeprom_read_ctl_info()
1668 AR5K_EEPROM_READ(offset++, val); ath5k_eeprom_read_ctl_info()
1669 rep[4].freq |= (val >> 13) & 0x7; ath5k_eeprom_read_ctl_info()
1670 rep[5].freq = (val >> 6) & fmask; ath5k_eeprom_read_ctl_info()
1671 rep[6].freq = (val << 1) & fmask; ath5k_eeprom_read_ctl_info()
1673 AR5K_EEPROM_READ(offset++, val); ath5k_eeprom_read_ctl_info()
1674 rep[6].freq |= (val >> 15) & 0x1; ath5k_eeprom_read_ctl_info()
1675 rep[7].freq = (val >> 8) & fmask; ath5k_eeprom_read_ctl_info()
1677 rep[0].edge = (val >> 2) & pmask; ath5k_eeprom_read_ctl_info()
1678 rep[1].edge = (val << 4) & pmask; ath5k_eeprom_read_ctl_info()
1680 AR5K_EEPROM_READ(offset++, val); ath5k_eeprom_read_ctl_info()
1681 rep[1].edge |= (val >> 12) & 0xf; ath5k_eeprom_read_ctl_info()
1682 rep[2].edge = (val >> 6) & pmask; ath5k_eeprom_read_ctl_info()
1683 rep[3].edge = val & pmask; ath5k_eeprom_read_ctl_info()
1685 AR5K_EEPROM_READ(offset++, val); ath5k_eeprom_read_ctl_info()
1686 rep[4].edge = (val >> 10) & pmask; ath5k_eeprom_read_ctl_info()
1687 rep[5].edge = (val >> 4) & pmask; ath5k_eeprom_read_ctl_info()
1688 rep[6].edge = (val << 2) & pmask; ath5k_eeprom_read_ctl_info()
1690 AR5K_EEPROM_READ(offset++, val); ath5k_eeprom_read_ctl_info()
1691 rep[6].edge |= (val >> 14) & 0x3; ath5k_eeprom_read_ctl_info()
1692 rep[7].edge = (val >> 8) & pmask; ath5k_eeprom_read_ctl_info()
1709 u16 val; ath5k_eeprom_read_spur_chans() local
1724 AR5K_EEPROM_READ(offset, val); ath5k_eeprom_read_spur_chans()
1725 ee->ee_spur_chans[i][0] = val; ath5k_eeprom_read_spur_chans()
1727 val); ath5k_eeprom_read_spur_chans()
1728 ee->ee_spur_chans[i][1] = val; ath5k_eeprom_read_spur_chans()
/linux-4.1.27/arch/sparc/kernel/
H A Djump_label.c16 u32 val; arch_jump_label_transform() local
24 val = 0x10680000 | ((u32) off >> 2); arch_jump_label_transform()
27 val = 0x10800000 | ((u32) off >> 2); arch_jump_label_transform()
30 val = 0x01000000; arch_jump_label_transform()
35 *insn = val; arch_jump_label_transform()
/linux-4.1.27/tools/testing/selftests/powerpc/pmu/ebb/
H A Dreg_access_test.c19 uint64_t val, expected; reg_access() local
23 val = mfspr(SPRN_BESCR); reg_access()
25 FAIL_IF(val != expected); reg_access()
29 val = mfspr(SPRN_EBBHR); reg_access()
31 FAIL_IF(val != expected); reg_access()
H A Dpmc56_overflow_test.c21 uint64_t val; ebb_callee() local
23 val = mfspr(SPRN_BESCR); ebb_callee()
24 if (!(val & BESCR_PMEO)) { ebb_callee()
32 val = mfspr(SPRN_PMC5); ebb_callee()
33 if (val >= COUNTER_OVERFLOW) ebb_callee()
38 val = mfspr(SPRN_PMC6); ebb_callee()
39 if (val >= COUNTER_OVERFLOW) ebb_callee()
/linux-4.1.27/net/sched/
H A Dem_cmp.c30 u32 val = 0; em_cmp_match() local
37 val = *ptr; em_cmp_match()
41 val = get_unaligned_be16(ptr); em_cmp_match()
44 val = be16_to_cpu(val); em_cmp_match()
51 val = get_unaligned_be32(ptr); em_cmp_match()
54 val = be32_to_cpu(val); em_cmp_match()
62 val &= cmp->mask; em_cmp_match()
66 return val == cmp->val; em_cmp_match()
68 return val < cmp->val; em_cmp_match()
70 return val > cmp->val; em_cmp_match()
/linux-4.1.27/scripts/dtc/
H A Dtreesource.c64 static void write_propval_string(FILE *f, struct data val) write_propval_string() argument
66 const char *str = val.val; write_propval_string()
68 struct marker *m = val.markers; write_propval_string()
70 assert(str[val.len-1] == '\0'); write_propval_string()
79 for (i = 0; i < (val.len-1); i++) { write_propval_string()
132 assert (m->offset == val.len); for_each_marker_of_type()
137 static void write_propval_cells(FILE *f, struct data val) write_propval_cells() argument
139 void *propend = val.val + val.len; write_propval_cells()
140 cell_t *cp = (cell_t *)val.val; write_propval_cells()
141 struct marker *m = val.markers; write_propval_cells()
145 while (m && (m->offset <= ((char *)cp - val.val))) { write_propval_cells()
147 assert(m->offset == ((char *)cp - val.val)); write_propval_cells()
161 assert (m->offset == val.len); for_each_marker_of_type()
167 static void write_propval_bytes(FILE *f, struct data val) write_propval_bytes() argument
169 void *propend = val.val + val.len; write_propval_bytes()
170 const char *bp = val.val; write_propval_bytes()
171 struct marker *m = val.markers; write_propval_bytes()
175 while (m && (m->offset == (bp-val.val))) { write_propval_bytes()
189 assert (m->offset == val.len); for_each_marker_of_type()
197 int len = prop->val.len; write_propval()
198 const char *p = prop->val.val; write_propval()
199 struct marker *m = prop->val.markers; write_propval()
217 if ((m->offset > 0) && (prop->val.val[m->offset - 1] != '\0')) for_each_marker_of_type()
226 write_propval_string(f, prop->val);
228 write_propval_cells(f, prop->val);
230 write_propval_bytes(f, prop->val);
/linux-4.1.27/drivers/media/pci/cx18/
H A Dcx18-io.c27 void cx18_memset_io(struct cx18 *cx, void __iomem *addr, int val, size_t count) cx18_memset_io() argument
30 u16 val2 = val | (val << 8); cx18_memset_io()
35 cx18_writeb(cx, (u8) val, dst); cx18_memset_io()
55 cx18_writeb(cx, (u8) val, dst); cx18_memset_io()
58 void cx18_sw1_irq_enable(struct cx18 *cx, u32 val) cx18_sw1_irq_enable() argument
60 cx18_write_reg_expect(cx, val, SW1_INT_STATUS, ~val, val); cx18_sw1_irq_enable()
61 cx->sw1_irq_mask = cx18_read_reg(cx, SW1_INT_ENABLE_PCI) | val; cx18_sw1_irq_enable()
65 void cx18_sw1_irq_disable(struct cx18 *cx, u32 val) cx18_sw1_irq_disable() argument
67 cx->sw1_irq_mask = cx18_read_reg(cx, SW1_INT_ENABLE_PCI) & ~val; cx18_sw1_irq_disable()
71 void cx18_sw2_irq_enable(struct cx18 *cx, u32 val) cx18_sw2_irq_enable() argument
73 cx18_write_reg_expect(cx, val, SW2_INT_STATUS, ~val, val); cx18_sw2_irq_enable()
74 cx->sw2_irq_mask = cx18_read_reg(cx, SW2_INT_ENABLE_PCI) | val; cx18_sw2_irq_enable()
78 void cx18_sw2_irq_disable(struct cx18 *cx, u32 val) cx18_sw2_irq_disable() argument
80 cx->sw2_irq_mask = cx18_read_reg(cx, SW2_INT_ENABLE_PCI) & ~val; cx18_sw2_irq_disable()
84 void cx18_sw2_irq_disable_cpu(struct cx18 *cx, u32 val) cx18_sw2_irq_disable_cpu() argument
88 cx18_write_reg(cx, r & ~val, SW2_INT_ENABLE_CPU); cx18_sw2_irq_disable_cpu()
93 u32 val; cx18_setup_page() local
94 val = cx18_read_reg(cx, 0xD000F8); cx18_setup_page()
95 val = (val & ~0x1f00) | ((addr >> 17) & 0x1f00); cx18_setup_page()
96 cx18_write_reg(cx, val, 0xD000F8); cx18_setup_page()
H A Dcx18-io.h44 void cx18_raw_writel_noretry(struct cx18 *cx, u32 val, void __iomem *addr) cx18_raw_writel_noretry() argument
46 __raw_writel(val, addr); cx18_raw_writel_noretry()
49 static inline void cx18_raw_writel(struct cx18 *cx, u32 val, void __iomem *addr) cx18_raw_writel() argument
53 cx18_raw_writel_noretry(cx, val, addr); cx18_raw_writel()
54 if (val == cx18_raw_readl(cx, addr)) cx18_raw_writel()
66 void cx18_writel_noretry(struct cx18 *cx, u32 val, void __iomem *addr) cx18_writel_noretry() argument
68 writel(val, addr); cx18_writel_noretry()
71 static inline void cx18_writel(struct cx18 *cx, u32 val, void __iomem *addr) cx18_writel() argument
75 cx18_writel_noretry(cx, val, addr); cx18_writel()
76 if (val == cx18_readl(cx, addr)) cx18_writel()
82 void cx18_writel_expect(struct cx18 *cx, u32 val, void __iomem *addr, cx18_writel_expect() argument
89 cx18_writel_noretry(cx, val, addr); cx18_writel_expect()
104 void cx18_writew_noretry(struct cx18 *cx, u16 val, void __iomem *addr) cx18_writew_noretry() argument
106 writew(val, addr); cx18_writew_noretry()
109 static inline void cx18_writew(struct cx18 *cx, u16 val, void __iomem *addr) cx18_writew() argument
113 cx18_writew_noretry(cx, val, addr); cx18_writew()
114 if (val == cx18_readw(cx, addr)) cx18_writew()
125 void cx18_writeb_noretry(struct cx18 *cx, u8 val, void __iomem *addr) cx18_writeb_noretry() argument
127 writeb(val, addr); cx18_writeb_noretry()
130 static inline void cx18_writeb(struct cx18 *cx, u8 val, void __iomem *addr) cx18_writeb() argument
134 cx18_writeb_noretry(cx, val, addr); cx18_writeb()
135 if (val == cx18_readb(cx, addr)) cx18_writeb()
147 void cx18_memset_io(struct cx18 *cx, void __iomem *addr, int val, size_t count);
151 static inline void cx18_write_reg_noretry(struct cx18 *cx, u32 val, u32 reg) cx18_write_reg_noretry() argument
153 cx18_writel_noretry(cx, val, cx->reg_mem + reg); cx18_write_reg_noretry()
156 static inline void cx18_write_reg(struct cx18 *cx, u32 val, u32 reg) cx18_write_reg() argument
158 cx18_writel(cx, val, cx->reg_mem + reg); cx18_write_reg()
161 static inline void cx18_write_reg_expect(struct cx18 *cx, u32 val, u32 reg, cx18_write_reg_expect() argument
164 cx18_writel_expect(cx, val, cx->reg_mem + reg, eval, mask); cx18_write_reg_expect()
174 static inline void cx18_write_enc(struct cx18 *cx, u32 val, u32 addr) cx18_write_enc() argument
176 cx18_writel(cx, val, cx->enc_mem + addr); cx18_write_enc()
184 void cx18_sw1_irq_enable(struct cx18 *cx, u32 val);
185 void cx18_sw1_irq_disable(struct cx18 *cx, u32 val);
186 void cx18_sw2_irq_enable(struct cx18 *cx, u32 val);
187 void cx18_sw2_irq_disable(struct cx18 *cx, u32 val);
188 void cx18_sw2_irq_disable_cpu(struct cx18 *cx, u32 val);
/linux-4.1.27/arch/c6x/include/asm/
H A Dunaligned.h34 static inline void put_unaligned_le16(u16 val, void *p) put_unaligned_le16() argument
37 _p[0] = val; put_unaligned_le16()
38 _p[1] = val >> 8; put_unaligned_le16()
41 static inline void put_unaligned_be16(u16 val, void *p) put_unaligned_be16() argument
44 _p[0] = val >> 8; put_unaligned_be16()
45 _p[1] = val; put_unaligned_be16()
50 u32 val = (u32) p; get_unaligned32() local
53 : "+a"(val)); get_unaligned32()
54 return val; get_unaligned32()
57 static inline void put_unaligned32(u32 val, void *p) put_unaligned32() argument
60 : : "a"(val), "b"(p) : "memory"); put_unaligned32()
65 u64 val; get_unaligned64() local
68 : "=a"(val) : "a"(p)); get_unaligned64()
69 return val; get_unaligned64()
72 static inline void put_unaligned64(u64 val, const void *p) put_unaligned64() argument
75 : : "a"(val), "b"(p) : "memory"); put_unaligned64()
128 #define __put_unaligned_le(val, ptr) ({ \
132 *(u8 *)__gu_p = (__force u8)(val); \
135 put_unaligned_le16((__force u16)(val), __gu_p); \
138 put_unaligned_le32((__force u32)(val), __gu_p); \
141 put_unaligned_le64((__force u64)(val), __gu_p); \
149 #define __put_unaligned_be(val, ptr) ({ \
153 *(u8 *)__gu_p = (__force u8)(val); \
156 put_unaligned_be16((__force u16)(val), __gu_p); \
159 put_unaligned_be32((__force u32)(val), __gu_p); \
162 put_unaligned_be64((__force u64)(val), __gu_p); \
H A Dflat.h8 #define flat_put_addr_at_rp(rp, val, relval) put_unaligned(val, rp)
/linux-4.1.27/arch/x86/oprofile/
H A Dop_model_amd.c107 static inline u64 op_amd_randomize_ibs_op(u64 val) op_amd_randomize_ibs_op() argument
125 val += (s8)(random >> 4); op_amd_randomize_ibs_op()
127 val |= (u64)(random & IBS_RANDOM_MASK) << 32; op_amd_randomize_ibs_op()
129 return val; op_amd_randomize_ibs_op()
136 u64 val, ctl; op_amd_handle_ibs() local
145 rdmsrl(MSR_AMD64_IBSFETCHLINAD, val); op_amd_handle_ibs()
146 oprofile_write_reserve(&entry, regs, val, op_amd_handle_ibs()
148 oprofile_add_data64(&entry, val); op_amd_handle_ibs()
150 rdmsrl(MSR_AMD64_IBSFETCHPHYSAD, val); op_amd_handle_ibs()
151 oprofile_add_data64(&entry, val); op_amd_handle_ibs()
164 rdmsrl(MSR_AMD64_IBSOPRIP, val); op_amd_handle_ibs()
165 oprofile_write_reserve(&entry, regs, val, IBS_OP_CODE, op_amd_handle_ibs()
167 oprofile_add_data64(&entry, val); op_amd_handle_ibs()
168 rdmsrl(MSR_AMD64_IBSOPDATA, val); op_amd_handle_ibs()
169 oprofile_add_data64(&entry, val); op_amd_handle_ibs()
170 rdmsrl(MSR_AMD64_IBSOPDATA2, val); op_amd_handle_ibs()
171 oprofile_add_data64(&entry, val); op_amd_handle_ibs()
172 rdmsrl(MSR_AMD64_IBSOPDATA3, val); op_amd_handle_ibs()
173 oprofile_add_data64(&entry, val); op_amd_handle_ibs()
174 rdmsrl(MSR_AMD64_IBSDCLINAD, val); op_amd_handle_ibs()
175 oprofile_add_data64(&entry, val); op_amd_handle_ibs()
176 rdmsrl(MSR_AMD64_IBSDCPHYSAD, val); op_amd_handle_ibs()
177 oprofile_add_data64(&entry, val); op_amd_handle_ibs()
179 rdmsrl(MSR_AMD64_IBSBRTARGET, val); op_amd_handle_ibs()
180 oprofile_add_data(&entry, (unsigned long)val); op_amd_handle_ibs()
193 u64 val; op_amd_start_ibs() local
207 val = ibs_config.max_cnt_fetch >> 4; op_amd_start_ibs()
208 val = min(val, IBS_FETCH_MAX_CNT); op_amd_start_ibs()
209 ibs_config.max_cnt_fetch = val << 4; op_amd_start_ibs()
210 val |= ibs_config.rand_en ? IBS_FETCH_RAND_EN : 0; op_amd_start_ibs()
211 val |= IBS_FETCH_ENABLE; op_amd_start_ibs()
212 wrmsrl(MSR_AMD64_IBSFETCHCTL, val); op_amd_start_ibs()
216 val = ibs_config.max_cnt_op >> 4; op_amd_start_ibs()
222 val = clamp(val, 0x0081ULL, 0xFF80ULL); op_amd_start_ibs()
223 ibs_config.max_cnt_op = val << 4; op_amd_start_ibs()
231 val += IBS_RANDOM_MAXCNT_OFFSET; op_amd_start_ibs()
233 val = min(val, IBS_OP_MAX_CNT_EXT); op_amd_start_ibs()
235 val = min(val, IBS_OP_MAX_CNT); op_amd_start_ibs()
237 (val - IBS_RANDOM_MAXCNT_OFFSET) << 4; op_amd_start_ibs()
239 val = ((val & ~IBS_OP_MAX_CNT) << 4) | (val & IBS_OP_MAX_CNT); op_amd_start_ibs()
240 val |= ibs_config.dispatched_ops ? IBS_OP_CNT_CTL : 0; op_amd_start_ibs()
241 val |= IBS_OP_ENABLE; op_amd_start_ibs()
242 ibs_state.ibs_op_ctl = val; op_amd_start_ibs()
248 val = op_amd_randomize_ibs_op(ibs_state.ibs_op_ctl); op_amd_start_ibs()
249 wrmsrl(MSR_AMD64_IBSOPCTL, val); op_amd_start_ibs()
272 u64 val; op_mux_switch_ctrl() local
280 rdmsrl(msrs->controls[i].addr, val); op_mux_switch_ctrl()
281 val &= model->reserved; op_mux_switch_ctrl()
282 val |= op_x86_get_ctrl(model, &counter_config[virt]); op_mux_switch_ctrl()
283 wrmsrl(msrs->controls[i].addr, val); op_mux_switch_ctrl()
337 u64 val; op_amd_setup_ctrs() local
353 rdmsrl(msrs->controls[i].addr, val); op_amd_setup_ctrs()
354 if (val & ARCH_PERFMON_EVENTSEL_ENABLE) op_amd_setup_ctrs()
356 val &= model->reserved; op_amd_setup_ctrs()
357 wrmsrl(msrs->controls[i].addr, val); op_amd_setup_ctrs()
375 rdmsrl(msrs->controls[i].addr, val); op_amd_setup_ctrs()
376 val &= model->reserved; op_amd_setup_ctrs()
377 val |= op_x86_get_ctrl(model, &counter_config[virt]); op_amd_setup_ctrs()
378 wrmsrl(msrs->controls[i].addr, val); op_amd_setup_ctrs()
385 u64 val; op_amd_check_ctrs() local
392 rdmsrl(msrs->counters[i].addr, val); op_amd_check_ctrs()
394 if (val & OP_CTR_OVERFLOW) op_amd_check_ctrs()
408 u64 val; op_amd_start() local
414 rdmsrl(msrs->controls[i].addr, val); op_amd_start()
415 val |= ARCH_PERFMON_EVENTSEL_ENABLE; op_amd_start()
416 wrmsrl(msrs->controls[i].addr, val); op_amd_start()
424 u64 val; op_amd_stop() local
434 rdmsrl(msrs->controls[i].addr, val); op_amd_stop()
435 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE; op_amd_stop()
436 wrmsrl(msrs->controls[i].addr, val); op_amd_stop()
/linux-4.1.27/sound/synth/emux/
H A Demux_nrpn.c33 int (*convert)(int val);
54 int type, int val, int mode) send_converted_effect()
59 cval = table[i].convert(val); send_converted_effect()
99 static int fx_delay(int val);
100 static int fx_attack(int val);
101 static int fx_hold(int val);
102 static int fx_decay(int val);
103 static int fx_the_value(int val);
104 static int fx_twice_value(int val);
105 static int fx_conv_pitch(int val);
106 static int fx_conv_Q(int val);
141 static int fx_delay(int val) fx_delay() argument
143 return (unsigned short)snd_sf_calc_parm_delay(val); fx_delay()
146 static int fx_attack(int val) fx_attack() argument
148 return (unsigned short)snd_sf_calc_parm_attack(val); fx_attack()
151 static int fx_hold(int val) fx_hold() argument
153 return (unsigned short)snd_sf_calc_parm_hold(val); fx_hold()
156 static int fx_decay(int val) fx_decay() argument
158 return (unsigned short)snd_sf_calc_parm_decay(val); fx_decay()
161 static int fx_the_value(int val) fx_the_value() argument
163 return (unsigned short)(val & 0xff); fx_the_value()
166 static int fx_twice_value(int val) fx_twice_value() argument
168 return (unsigned short)((val * 2) & 0xff); fx_twice_value()
171 static int fx_conv_pitch(int val) fx_conv_pitch() argument
173 return (short)(val * 4096 / 1200); fx_conv_pitch()
176 static int fx_conv_Q(int val) fx_conv_Q() argument
178 return (unsigned short)((val / 8) & 0xff); fx_conv_Q()
222 static int gs_cutoff(int val) gs_cutoff() argument
224 return (val - 64) * gs_sense[FX_CUTOFF] / 50; gs_cutoff()
228 static int gs_filterQ(int val) gs_filterQ() argument
230 return (val - 64) * gs_sense[FX_RESONANCE] / 50; gs_filterQ()
234 static int gs_attack(int val) gs_attack() argument
236 return -(val - 64) * gs_sense[FX_ATTACK] / 50; gs_attack()
240 static int gs_decay(int val) gs_decay() argument
242 return -(val - 64) * gs_sense[FX_RELEASE] / 50; gs_decay()
246 static int gs_release(int val) gs_release() argument
248 return -(val - 64) * gs_sense[FX_RELEASE] / 50; gs_release()
252 static int gs_vib_rate(int val) gs_vib_rate() argument
254 return (val - 64) * gs_sense[FX_VIBRATE] / 50; gs_vib_rate()
258 static int gs_vib_depth(int val) gs_vib_depth() argument
260 return (val - 64) * gs_sense[FX_VIBDEPTH] / 50; gs_vib_depth()
264 static int gs_vib_delay(int val) gs_vib_delay() argument
266 return -(val - 64) * gs_sense[FX_VIBDELAY] / 50; gs_vib_delay()
297 int val; snd_emux_nrpn() local
300 val = (chan->control[MIDI_CTL_MSB_DATA_ENTRY] << 7) | snd_emux_nrpn()
302 val -= 8192; snd_emux_nrpn()
306 val, EMUX_FX_FLAG_SET); snd_emux_nrpn()
312 int val; snd_emux_nrpn() local
315 val = chan->control[MIDI_CTL_MSB_DATA_ENTRY]; snd_emux_nrpn()
319 val, EMUX_FX_FLAG_ADD); snd_emux_nrpn()
330 static int xg_cutoff(int val) xg_cutoff() argument
332 return (val - 64) * xg_sense[FX_CUTOFF] / 64; xg_cutoff()
336 static int xg_filterQ(int val) xg_filterQ() argument
338 return (val - 64) * xg_sense[FX_RESONANCE] / 64; xg_filterQ()
342 static int xg_attack(int val) xg_attack() argument
344 return -(val - 64) * xg_sense[FX_ATTACK] / 64; xg_attack()
348 static int xg_release(int val) xg_release() argument
350 return -(val - 64) * xg_sense[FX_RELEASE] / 64; xg_release()
51 send_converted_effect(struct nrpn_conv_table *table, int num_tables, struct snd_emux_port *port, struct snd_midi_channel *chan, int type, int val, int mode) send_converted_effect() argument
/linux-4.1.27/arch/sh/include/asm/
H A Dunaligned-sh4a.h93 static inline void nonnative_put_le16(u16 val, u8 *p) nonnative_put_le16() argument
95 *p++ = val; nonnative_put_le16()
96 *p++ = val >> 8; nonnative_put_le16()
99 static inline void nonnative_put_le32(u32 val, u8 *p) nonnative_put_le32() argument
101 nonnative_put_le16(val, p); nonnative_put_le32()
102 nonnative_put_le16(val >> 16, p + 2); nonnative_put_le32()
105 static inline void nonnative_put_le64(u64 val, u8 *p) nonnative_put_le64() argument
107 nonnative_put_le32(val, p); nonnative_put_le64()
108 nonnative_put_le32(val >> 32, p + 4); nonnative_put_le64()
111 static inline void nonnative_put_be16(u16 val, u8 *p) nonnative_put_be16() argument
113 *p++ = val >> 8; nonnative_put_be16()
114 *p++ = val; nonnative_put_be16()
117 static inline void nonnative_put_be32(u32 val, u8 *p) nonnative_put_be32() argument
119 nonnative_put_be16(val >> 16, p); nonnative_put_be32()
120 nonnative_put_be16(val, p + 2); nonnative_put_be32()
123 static inline void nonnative_put_be64(u64 val, u8 *p) nonnative_put_be64() argument
125 nonnative_put_be32(val >> 32, p); nonnative_put_be64()
126 nonnative_put_be32(val, p + 4); nonnative_put_be64()
129 static inline void put_unaligned_le16(u16 val, void *p) put_unaligned_le16() argument
132 __put_unaligned_cpu16(val, p); put_unaligned_le16()
134 nonnative_put_le16(val, p); put_unaligned_le16()
138 static inline void put_unaligned_le32(u32 val, void *p) put_unaligned_le32() argument
141 __put_unaligned_cpu32(val, p); put_unaligned_le32()
143 nonnative_put_le32(val, p); put_unaligned_le32()
147 static inline void put_unaligned_le64(u64 val, void *p) put_unaligned_le64() argument
150 __put_unaligned_cpu64(val, p); put_unaligned_le64()
152 nonnative_put_le64(val, p); put_unaligned_le64()
156 static inline void put_unaligned_be16(u16 val, void *p) put_unaligned_be16() argument
159 __put_unaligned_cpu16(val, p); put_unaligned_be16()
161 nonnative_put_be16(val, p); put_unaligned_be16()
165 static inline void put_unaligned_be32(u32 val, void *p) put_unaligned_be32() argument
168 __put_unaligned_cpu32(val, p); put_unaligned_be32()
170 nonnative_put_be32(val, p); put_unaligned_be32()
174 static inline void put_unaligned_be64(u64 val, void *p) put_unaligned_be64() argument
177 __put_unaligned_cpu64(val, p); put_unaligned_be64()
179 nonnative_put_be64(val, p); put_unaligned_be64()
/linux-4.1.27/tools/lib/traceevent/
H A Dplugin_sched_switch.c26 static void write_state(struct trace_seq *s, int val) write_state() argument
33 if (!(val & (1 << i))) write_state()
72 unsigned long long val; sched_wakeup_handler() local
74 if (pevent_get_field_val(s, event, "pid", record, &val, 1)) sched_wakeup_handler()
79 write_and_save_comm(field, record, s, val); sched_wakeup_handler()
82 trace_seq_printf(s, "%lld", val); sched_wakeup_handler()
84 if (pevent_get_field_val(s, event, "prio", record, &val, 0) == 0) sched_wakeup_handler()
85 trace_seq_printf(s, " [%lld]", val); sched_wakeup_handler()
87 if (pevent_get_field_val(s, event, "success", record, &val, 1) == 0) sched_wakeup_handler()
88 trace_seq_printf(s, " success=%lld", val); sched_wakeup_handler()
90 if (pevent_get_field_val(s, event, "target_cpu", record, &val, 0) == 0) sched_wakeup_handler()
91 trace_seq_printf(s, " CPU:%03llu", val); sched_wakeup_handler()
101 unsigned long long val; sched_switch_handler() local
103 if (pevent_get_field_val(s, event, "prev_pid", record, &val, 1)) sched_switch_handler()
108 write_and_save_comm(field, record, s, val); sched_switch_handler()
111 trace_seq_printf(s, "%lld ", val); sched_switch_handler()
113 if (pevent_get_field_val(s, event, "prev_prio", record, &val, 0) == 0) sched_switch_handler()
114 trace_seq_printf(s, "[%lld] ", val); sched_switch_handler()
116 if (pevent_get_field_val(s, event, "prev_state", record, &val, 0) == 0) sched_switch_handler()
117 write_state(s, val); sched_switch_handler()
121 if (pevent_get_field_val(s, event, "next_pid", record, &val, 1)) sched_switch_handler()
126 write_and_save_comm(field, record, s, val); sched_switch_handler()
129 trace_seq_printf(s, "%lld", val); sched_switch_handler()
131 if (pevent_get_field_val(s, event, "next_prio", record, &val, 0) == 0) sched_switch_handler()
132 trace_seq_printf(s, " [%lld]", val); sched_switch_handler()
H A Dplugin_cfg80211.c10 uint16_t *val = (uint16_t *) (unsigned long) args[0]; process___le16_to_cpup() local
11 return val ? (long long) le16toh(*val) : 0; process___le16_to_cpup()
/linux-4.1.27/arch/parisc/include/asm/
H A Dspecial_insns.h21 static inline void set_eiem(unsigned long val) set_eiem() argument
23 mtctl(val, 15); set_eiem()
35 #define mtsp(val, cr) \
36 { if (__builtin_constant_p(val) && ((val) == 0)) \
41 : "r" (val), "i" (cr) : "memory"); }
/linux-4.1.27/arch/arm/mach-davinci/
H A Dpm.c42 unsigned val; davinci_pm_suspend() local
47 val = __raw_readl(pdata->cpupll_reg_base + PLLCTL); davinci_pm_suspend()
48 val &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN); davinci_pm_suspend()
49 __raw_writel(val, pdata->cpupll_reg_base + PLLCTL); davinci_pm_suspend()
54 val = __raw_readl(pdata->cpupll_reg_base + PLLCTL); davinci_pm_suspend()
55 val |= PLLCTL_PLLPWRDN; davinci_pm_suspend()
56 __raw_writel(val, pdata->cpupll_reg_base + PLLCTL); davinci_pm_suspend()
60 val = __raw_readl(pdata->deepsleep_reg); davinci_pm_suspend()
61 val &= ~DEEPSLEEP_SLEEPCOUNT_MASK, davinci_pm_suspend()
62 val |= pdata->sleepcount; davinci_pm_suspend()
63 __raw_writel(val, pdata->deepsleep_reg); davinci_pm_suspend()
71 val = __raw_readl(pdata->cpupll_reg_base + PLLCTL); davinci_pm_suspend()
72 val &= ~PLLCTL_PLLRST; davinci_pm_suspend()
73 __raw_writel(val, pdata->cpupll_reg_base + PLLCTL); davinci_pm_suspend()
76 val = __raw_readl(pdata->cpupll_reg_base + PLLCTL); davinci_pm_suspend()
77 val &= ~PLLCTL_PLLPWRDN; davinci_pm_suspend()
78 __raw_writel(val, pdata->cpupll_reg_base + PLLCTL); davinci_pm_suspend()
84 val = __raw_readl(pdata->cpupll_reg_base + PLLCTL); davinci_pm_suspend()
85 val |= PLLCTL_PLLRST; davinci_pm_suspend()
86 __raw_writel(val, pdata->cpupll_reg_base + PLLCTL); davinci_pm_suspend()
92 val = __raw_readl(pdata->cpupll_reg_base + PLLCTL); davinci_pm_suspend()
93 val &= ~PLLCTL_PLLENSRC; davinci_pm_suspend()
94 val |= PLLCTL_PLLEN; davinci_pm_suspend()
95 __raw_writel(val, pdata->cpupll_reg_base + PLLCTL); davinci_pm_suspend()
/linux-4.1.27/security/selinux/ss/
H A Dsymtab.c15 unsigned int val; symhash() local
17 val = 0; symhash()
21 val = (val << 4 | (val >> (8*sizeof(unsigned int)-4))) ^ (*p); symhash()
22 return val & (h->size - 1); symhash()
/linux-4.1.27/drivers/net/ethernet/chelsio/cxgb/
H A Dmy3126.c38 u32 val; my3126_interrupt_handler() local
46 cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_STAT1, &val); my3126_interrupt_handler()
47 val16 = (u16) val; my3126_interrupt_handler()
65 OFFSET(SUNI1x10GEXP_REG_MSTAT_COUNTER_33_LOW), &val); my3126_interrupt_handler()
66 act_count += val; my3126_interrupt_handler()
69 t1_tpi_read(adapter, A_ELMER0_GPO, &val); my3126_interrupt_handler()
70 cphy->elmer_gpo = val; my3126_interrupt_handler()
72 if ( (val & (1 << 8)) || (val & (1 << 19)) || my3126_interrupt_handler()
75 val |= (1 << 9); my3126_interrupt_handler()
77 val |= (1 << 20); my3126_interrupt_handler()
81 val &= ~(1 << 9); my3126_interrupt_handler()
83 val &= ~(1 << 20); my3126_interrupt_handler()
87 t1_tpi_write(adapter, A_ELMER0_GPO, val); my3126_interrupt_handler()
89 cphy->elmer_gpo = val; my3126_interrupt_handler()
112 u32 val; my3126_get_link_status() local
117 cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_STAT1, &val); my3126_get_link_status()
118 val16 = (u16) val; my3126_get_link_status()
121 t1_tpi_read(adapter, A_ELMER0_GPO, &val); my3126_get_link_status()
122 cphy->elmer_gpo = val; my3126_get_link_status()
129 val &= ~(1 << 8); my3126_get_link_status()
131 val &= ~(1 << 19); my3126_get_link_status()
135 val |= (1 << 8); my3126_get_link_status()
137 val |= (1 << 19); my3126_get_link_status()
140 t1_tpi_write(adapter, A_ELMER0_GPO, val); my3126_get_link_status()
141 cphy->elmer_gpo = val; my3126_get_link_status()
188 u32 val; my3126_phy_reset() local
190 t1_tpi_read(adapter, A_ELMER0_GPO, &val); my3126_phy_reset()
191 val &= ~4; my3126_phy_reset()
192 t1_tpi_write(adapter, A_ELMER0_GPO, val); my3126_phy_reset()
195 t1_tpi_write(adapter, A_ELMER0_GPO, val | 4); my3126_phy_reset()
199 t1_tpi_read(adapter, A_ELMER0_GPO, &val); my3126_phy_reset()
200 val |= 0x8000; my3126_phy_reset()
201 t1_tpi_write(adapter, A_ELMER0_GPO, val); my3126_phy_reset()
/linux-4.1.27/drivers/gpu/drm/gma500/
H A Doaktrail_lvds_i2c.c65 #define LPC_WRITE_REG(chan, r, val) outl((val), (chan)->reg + (r))
70 u32 val, tmp; get_clock() local
72 val = LPC_READ_REG(chan, RGIO); get_clock()
73 val |= GPIO_CLOCK; get_clock()
74 LPC_WRITE_REG(chan, RGIO, val); get_clock()
76 val = (LPC_READ_REG(chan, RGLVL) & GPIO_CLOCK) ? 1 : 0; get_clock()
78 return val; get_clock()
84 u32 val, tmp; get_data() local
86 val = LPC_READ_REG(chan, RGIO); get_data()
87 val |= GPIO_DATA; get_data()
88 LPC_WRITE_REG(chan, RGIO, val); get_data()
90 val = (LPC_READ_REG(chan, RGLVL) & GPIO_DATA) ? 1 : 0; get_data()
92 return val; get_data()
98 u32 val; set_clock() local
101 val = LPC_READ_REG(chan, RGIO); set_clock()
102 val |= GPIO_CLOCK; set_clock()
103 LPC_WRITE_REG(chan, RGIO, val); set_clock()
105 val = LPC_READ_REG(chan, RGIO); set_clock()
106 val &= ~GPIO_CLOCK; set_clock()
107 LPC_WRITE_REG(chan, RGIO, val); set_clock()
108 val = LPC_READ_REG(chan, RGLVL); set_clock()
109 val &= ~GPIO_CLOCK; set_clock()
110 LPC_WRITE_REG(chan, RGLVL, val); set_clock()
117 u32 val; set_data() local
120 val = LPC_READ_REG(chan, RGIO); set_data()
121 val |= GPIO_DATA; set_data()
122 LPC_WRITE_REG(chan, RGIO, val); set_data()
124 val = LPC_READ_REG(chan, RGIO); set_data()
125 val &= ~GPIO_DATA; set_data()
126 LPC_WRITE_REG(chan, RGIO, val); set_data()
127 val = LPC_READ_REG(chan, RGLVL); set_data()
128 val &= ~GPIO_DATA; set_data()
129 LPC_WRITE_REG(chan, RGLVL, val); set_data()
/linux-4.1.27/drivers/clk/pistachio/
H A Dclk-pll.c65 static inline void pll_writel(struct pistachio_clk_pll *pll, u32 val, u32 reg) pll_writel() argument
67 writel(val, pll->base + reg); pll_writel()
115 u32 val; pll_gf40lp_frac_enable() local
117 val = pll_readl(pll, PLL_CTRL3); pll_gf40lp_frac_enable()
118 val &= ~(PLL_FRAC_CTRL3_PD | PLL_FRAC_CTRL3_FOUTPOSTDIVPD | pll_gf40lp_frac_enable()
120 pll_writel(pll, val, PLL_CTRL3); pll_gf40lp_frac_enable()
122 val = pll_readl(pll, PLL_CTRL4); pll_gf40lp_frac_enable()
123 val &= ~PLL_FRAC_CTRL4_BYPASS; pll_gf40lp_frac_enable()
124 pll_writel(pll, val, PLL_CTRL4); pll_gf40lp_frac_enable()
132 u32 val; pll_gf40lp_frac_disable() local
134 val = pll_readl(pll, PLL_CTRL3); pll_gf40lp_frac_disable()
135 val |= PLL_FRAC_CTRL3_PD; pll_gf40lp_frac_disable()
136 pll_writel(pll, val, PLL_CTRL3); pll_gf40lp_frac_disable()
152 u32 val; pll_gf40lp_frac_set_rate() local
162 val = pll_readl(pll, PLL_CTRL1); pll_gf40lp_frac_set_rate()
163 val &= ~((PLL_CTRL1_REFDIV_MASK << PLL_CTRL1_REFDIV_SHIFT) | pll_gf40lp_frac_set_rate()
165 val |= (params->refdiv << PLL_CTRL1_REFDIV_SHIFT) | pll_gf40lp_frac_set_rate()
167 pll_writel(pll, val, PLL_CTRL1); pll_gf40lp_frac_set_rate()
169 val = pll_readl(pll, PLL_CTRL2); pll_gf40lp_frac_set_rate()
170 val &= ~((PLL_FRAC_CTRL2_FRAC_MASK << PLL_FRAC_CTRL2_FRAC_SHIFT) | pll_gf40lp_frac_set_rate()
175 val |= (params->frac << PLL_FRAC_CTRL2_FRAC_SHIFT) | pll_gf40lp_frac_set_rate()
178 pll_writel(pll, val, PLL_CTRL2); pll_gf40lp_frac_set_rate()
193 u32 val, prediv, fbdiv, frac, postdiv1, postdiv2; pll_gf40lp_frac_recalc_rate() local
196 val = pll_readl(pll, PLL_CTRL1); pll_gf40lp_frac_recalc_rate()
197 prediv = (val >> PLL_CTRL1_REFDIV_SHIFT) & PLL_CTRL1_REFDIV_MASK; pll_gf40lp_frac_recalc_rate()
198 fbdiv = (val >> PLL_CTRL1_FBDIV_SHIFT) & PLL_CTRL1_FBDIV_MASK; pll_gf40lp_frac_recalc_rate()
200 val = pll_readl(pll, PLL_CTRL2); pll_gf40lp_frac_recalc_rate()
201 postdiv1 = (val >> PLL_FRAC_CTRL2_POSTDIV1_SHIFT) & pll_gf40lp_frac_recalc_rate()
203 postdiv2 = (val >> PLL_FRAC_CTRL2_POSTDIV2_SHIFT) & pll_gf40lp_frac_recalc_rate()
205 frac = (val >> PLL_FRAC_CTRL2_FRAC_SHIFT) & PLL_FRAC_CTRL2_FRAC_MASK; pll_gf40lp_frac_recalc_rate()
232 u32 val; pll_gf40lp_laint_enable() local
234 val = pll_readl(pll, PLL_CTRL1); pll_gf40lp_laint_enable()
235 val &= ~(PLL_INT_CTRL1_PD | pll_gf40lp_laint_enable()
237 pll_writel(pll, val, PLL_CTRL1); pll_gf40lp_laint_enable()
239 val = pll_readl(pll, PLL_CTRL2); pll_gf40lp_laint_enable()
240 val &= ~PLL_INT_CTRL2_BYPASS; pll_gf40lp_laint_enable()
241 pll_writel(pll, val, PLL_CTRL2); pll_gf40lp_laint_enable()
249 u32 val; pll_gf40lp_laint_disable() local
251 val = pll_readl(pll, PLL_CTRL1); pll_gf40lp_laint_disable()
252 val |= PLL_INT_CTRL1_PD; pll_gf40lp_laint_disable()
253 pll_writel(pll, val, PLL_CTRL1); pll_gf40lp_laint_disable()
269 u32 val; pll_gf40lp_laint_set_rate() local
279 val = pll_readl(pll, PLL_CTRL1); pll_gf40lp_laint_set_rate()
280 val &= ~((PLL_CTRL1_REFDIV_MASK << PLL_CTRL1_REFDIV_SHIFT) | pll_gf40lp_laint_set_rate()
284 val |= (params->refdiv << PLL_CTRL1_REFDIV_SHIFT) | pll_gf40lp_laint_set_rate()
288 pll_writel(pll, val, PLL_CTRL1); pll_gf40lp_laint_set_rate()
303 u32 val, prediv, fbdiv, postdiv1, postdiv2; pll_gf40lp_laint_recalc_rate() local
306 val = pll_readl(pll, PLL_CTRL1); pll_gf40lp_laint_recalc_rate()
307 prediv = (val >> PLL_CTRL1_REFDIV_SHIFT) & PLL_CTRL1_REFDIV_MASK; pll_gf40lp_laint_recalc_rate()
308 fbdiv = (val >> PLL_CTRL1_FBDIV_SHIFT) & PLL_CTRL1_FBDIV_MASK; pll_gf40lp_laint_recalc_rate()
309 postdiv1 = (val >> PLL_INT_CTRL1_POSTDIV1_SHIFT) & pll_gf40lp_laint_recalc_rate()
311 postdiv2 = (val >> PLL_INT_CTRL1_POSTDIV2_SHIFT) & pll_gf40lp_laint_recalc_rate()
/linux-4.1.27/arch/mips/include/asm/
H A Dmipsmtregs.h20 #define write_c0_mvpcontrol(val) __write_32bit_c0_register($0, 1, val)
26 #define write_c0_vpecontrol(val) __write_32bit_c0_register($1, 1, val)
29 #define write_c0_vpeconf0(val) __write_32bit_c0_register($1, 2, val)
32 #define write_c0_vpeconf1(val) __write_32bit_c0_register($1, 3, val)
35 #define write_c0_tcstatus(val) __write_32bit_c0_register($2, 1, val)
39 #define write_c0_tchalt(val) __write_32bit_c0_register($2, 4, val)
42 #define write_c0_tccontext(val) __write_32bit_c0_register($2, 5, val)
374 #define write_vpe_c0_vpecontrol(val) mttc0(1, 1, val)
376 #define write_vpe_c0_vpeconf0(val) mttc0(1, 2, val)
378 #define write_vpe_c0_vpeconf1(val) mttc0(1, 3, val)
380 #define write_vpe_c0_count(val) mttc0(9, 0, val)
382 #define write_vpe_c0_status(val) mttc0(12, 0, val)
384 #define write_vpe_c0_cause(val) mttc0(13, 0, val)
386 #define write_vpe_c0_config(val) mttc0(16, 0, val)
388 #define write_vpe_c0_config1(val) mttc0(16, 1, val)
390 #define write_vpe_c0_config7(val) mttc0(16, 7, val)
392 #define write_vpe_c0_ebase(val) mttc0(15, 1, val)
393 #define write_vpe_c0_compare(val) mttc0(11, 0, val)
396 #define write_vpe_c0_epc(val) mttc0(14, 0, val)
401 #define write_tc_c0_tcstatus(val) mttc0(2, 1, val)
403 #define write_tc_c0_tcbind(val) mttc0(2, 2, val)
405 #define write_tc_c0_tcrestart(val) mttc0(2, 3, val)
407 #define write_tc_c0_tchalt(val) mttc0(2, 4, val)
409 #define write_tc_c0_tccontext(val) mttc0(2, 5, val)
413 #define write_tc_gpr_sp(val) mttgpr(29, val)
415 #define write_tc_gpr_gp(val) mttgpr(28, val)
H A Dmipsregs.h871 #define write_r10k_perf_cntr(counter,val) \
876 : "r" (val), "i" (counter)); \
890 #define write_r10k_perf_cntl(counter,val) \
895 : "r" (val), "i" (counter)); \
974 #define __write_ulong_c0_register(reg, sel, val) \
977 __write_32bit_c0_register(reg, sel, val); \
979 __write_64bit_c0_register(reg, sel, val); \
1033 #define __write_64bit_c0_split(source, sel, val) \
1047 : : "r" (val)); \
1057 : : "r" (val)); \
1095 #define write_c0_index(val) __write_32bit_c0_register($0, 0, val)
1098 #define write_c0_random(val) __write_32bit_c0_register($1, 0, val)
1101 #define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val)
1104 #define writex_c0_entrylo0(val) __writex_32bit_c0_register(2, val)
1107 #define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val)
1110 #define writex_c0_entrylo1(val) __writex_32bit_c0_register(3, val)
1113 #define write_c0_conf(val) __write_32bit_c0_register($3, 0, val)
1116 #define write_c0_context(val) __write_ulong_c0_register($4, 0, val)
1119 #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
1122 #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
1125 #define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val)
1128 #define write_c0_wired(val) __write_32bit_c0_register($6, 0, val)
1133 #define write_c0_cache(val) __write_32bit_c0_register($7, 0, val)
1136 #define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val)
1139 #define write_c0_count(val) __write_32bit_c0_register($9, 0, val)
1142 #define write_c0_count2(val) __write_32bit_c0_register($9, 6, val)
1145 #define write_c0_count3(val) __write_32bit_c0_register($9, 7, val)
1148 #define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val)
1151 #define write_c0_compare(val) __write_32bit_c0_register($11, 0, val)
1154 #define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val)
1157 #define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val)
1161 #define write_c0_status(val) __write_32bit_c0_register($12, 0, val)
1164 #define write_c0_cause(val) __write_32bit_c0_register($13, 0, val)
1167 #define write_c0_epc(val) __write_ulong_c0_register($14, 0, val)
1181 #define write_c0_config(val) __write_32bit_c0_register($16, 0, val)
1182 #define write_c0_config1(val) __write_32bit_c0_register($16, 1, val)
1183 #define write_c0_config2(val) __write_32bit_c0_register($16, 2, val)
1184 #define write_c0_config3(val) __write_32bit_c0_register($16, 3, val)
1185 #define write_c0_config4(val) __write_32bit_c0_register($16, 4, val)
1186 #define write_c0_config5(val) __write_32bit_c0_register($16, 5, val)
1187 #define write_c0_config6(val) __write_32bit_c0_register($16, 6, val)
1188 #define write_c0_config7(val) __write_32bit_c0_register($16, 7, val)
1191 #define write_c0_lladdr(val) __write_ulong_c0_register($17, 0, val)
1193 #define write_c0_maar(val) __write_ulong_c0_register($17, 1, val)
1195 #define write_c0_maari(val) __write_32bit_c0_register($17, 2, val)
1208 #define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val)
1209 #define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val)
1210 #define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val)
1211 #define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val)
1212 #define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val)
1213 #define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val)
1214 #define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val)
1215 #define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val)
1229 #define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val)
1230 #define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val)
1231 #define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val)
1232 #define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val)
1233 #define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val)
1234 #define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val)
1235 #define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val)
1236 #define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val)
1239 #define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val)
1242 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
1245 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
1248 #define write_c0_diag(val) __write_32bit_c0_register($22, 0, val)
1251 #define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val)
1254 #define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val)
1257 #define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val)
1260 #define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val)
1263 #define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val)
1266 #define write_c0_debug(val) __write_32bit_c0_register($23, 0, val)
1269 #define write_c0_depc(val) __write_ulong_c0_register($24, 0, val)
1275 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
1277 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
1279 #define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
1281 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
1283 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
1285 #define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
1287 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
1289 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
1291 #define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
1293 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
1295 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
1297 #define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
1300 #define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val)
1303 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
1308 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
1311 #define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val)
1314 #define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val)
1317 #define write_c0_ddatalo(val) __write_32bit_c0_register($28, 3, val)
1320 #define write_c0_staglo(val) __write_32bit_c0_register($28, 4, val)
1323 #define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val)
1326 #define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val)
1330 #define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val)
1333 #define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val)
1336 #define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val)
1339 #define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val)
1342 #define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val)
1345 #define write_c0_cdmmbase(val) __write_ulong_c0_register($15, 2, val)
1349 #define write_c0_segctl0(val) __write_32bit_c0_register($5, 2, val)
1352 #define write_c0_segctl1(val) __write_32bit_c0_register($5, 3, val)
1355 #define write_c0_segctl2(val) __write_32bit_c0_register($5, 4, val)
1359 #define write_c0_pwbase(val) __write_ulong_c0_register($5, 5, val)
1362 #define write_c0_pwfield(val) __write_ulong_c0_register($5, 6, val)
1365 #define write_c0_pwsize(val) __write_ulong_c0_register($5, 7, val)
1368 #define write_c0_pwctl(val) __write_32bit_c0_register($6, 6, val)
1372 #define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val)
1375 #define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val)
1378 #define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
1384 #define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val)
1387 #define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val)
1391 #define write_c0_brcm_config_0(val) __write_32bit_c0_register($22, 0, val)
1394 #define write_c0_brcm_bus_pll(val) __write_32bit_c0_register($22, 4, val)
1397 #define write_c0_brcm_reset(val) __write_32bit_c0_register($22, 5, val)
1401 #define write_c0_brcm_cmt_intr(val) __write_32bit_c0_register($22, 1, val)
1404 #define write_c0_brcm_cmt_ctrl(val) __write_32bit_c0_register($22, 2, val)
1407 #define write_c0_brcm_cmt_local(val) __write_32bit_c0_register($22, 3, val)
1410 #define write_c0_brcm_config_1(val) __write_32bit_c0_register($22, 5, val)
1413 #define write_c0_brcm_cbr(val) __write_32bit_c0_register($22, 6, val)
1417 #define write_c0_brcm_config(val) __write_32bit_c0_register($22, 0, val)
1420 #define write_c0_brcm_mode(val) __write_32bit_c0_register($22, 1, val)
1423 #define write_c0_brcm_action(val) __write_32bit_c0_register($22, 2, val)
1426 #define write_c0_brcm_edsp(val) __write_32bit_c0_register($22, 3, val)
1429 #define write_c0_brcm_bootvec(val) __write_32bit_c0_register($22, 4, val)
1432 #define write_c0_brcm_sleepcount(val) __write_32bit_c0_register($22, 7, val)
1454 #define _write_32bit_cp1_register(dest, val, gas_hardfloat) \
1462 : : "r" (val)); \
1468 #define write_32bit_cp1_register(dest, val) \
1469 _write_32bit_cp1_register(dest, val, .set hardfloat)
1473 #define write_32bit_cp1_register(dest, val) \
1474 _write_32bit_cp1_register(dest, val, )
1492 #define wrdsp(val, mask) \
1500 : "r" (val), "i" (mask)); \
1708 #define wrdsp(val, mask) \
1719 : "r" (val), "i" (mask)); \
1738 #define _umips_dsp_mtxxx(val, ins) \
1748 : "r" (val), "i" (ins)); \
1754 #define _umips_dsp_mtlo(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x307c))
1755 #define _umips_dsp_mthi(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x207c))
1794 #define wrdsp(val, mask) \
1804 : "r" (val), "i" (mask)); \
1822 #define _dsp_mtxxx(val, ins) \
1831 : "r" (val), "i" (ins)); \
1837 #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
1838 #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
1958 change_c0_##name(unsigned int change, unsigned int val) \
1964 new |= (val & change); \
/linux-4.1.27/sound/soc/nuc900/
H A Dnuc900-ac97.c48 unsigned long timeout = 0x10000, val; nuc900_ac97_read() local
52 val = nuc900_checkready(); nuc900_ac97_read()
53 if (val) { nuc900_ac97_read()
62 val = AUDIO_READ(nuc900_audio->mmio + ACTL_ACOS0); nuc900_ac97_read()
63 val |= (VALID_FRAME | SLOT1_VALID); nuc900_ac97_read()
64 AUDIO_WRITE(nuc900_audio->mmio + ACTL_ACOS0, val); nuc900_ac97_read()
75 val = -EPERM; nuc900_ac97_read()
79 val = AUDIO_READ(nuc900_audio->mmio + ACTL_ACOS0) ; nuc900_ac97_read()
80 val &= ~SLOT1_VALID; nuc900_ac97_read()
81 AUDIO_WRITE(nuc900_audio->mmio + ACTL_ACOS0, val); nuc900_ac97_read()
89 val = (AUDIO_READ(nuc900_audio->mmio + ACTL_ACIS2) & 0xFFFF); nuc900_ac97_read()
93 return val; nuc900_ac97_read()
98 unsigned short val) nuc900_ac97_write()
113 AUDIO_WRITE(nuc900_audio->mmio + ACTL_ACOS2, val); nuc900_ac97_write()
141 unsigned long val; nuc900_ac97_warm_reset() local
146 val = AUDIO_READ(nuc900_audio->mmio + ACTL_ACCON); nuc900_ac97_warm_reset()
147 val |= AC_W_RES; nuc900_ac97_warm_reset()
148 AUDIO_WRITE(nuc900_audio->mmio + ACTL_ACCON, val); nuc900_ac97_warm_reset()
152 val = nuc900_checkready(); nuc900_ac97_warm_reset()
153 if (val) nuc900_ac97_warm_reset()
162 unsigned long val; nuc900_ac97_cold_reset() local
167 val = AUDIO_READ(nuc900_audio->mmio + ACTL_RESET); nuc900_ac97_cold_reset()
168 val |= ACTL_RESET_BIT; nuc900_ac97_cold_reset()
169 AUDIO_WRITE(nuc900_audio->mmio + ACTL_RESET, val); nuc900_ac97_cold_reset()
171 val = AUDIO_READ(nuc900_audio->mmio + ACTL_RESET); nuc900_ac97_cold_reset()
172 val &= (~ACTL_RESET_BIT); nuc900_ac97_cold_reset()
173 AUDIO_WRITE(nuc900_audio->mmio + ACTL_RESET, val); nuc900_ac97_cold_reset()
177 val = AUDIO_READ(nuc900_audio->mmio + ACTL_RESET); nuc900_ac97_cold_reset()
178 val |= AC_RESET; nuc900_ac97_cold_reset()
179 AUDIO_WRITE(nuc900_audio->mmio + ACTL_RESET, val); nuc900_ac97_cold_reset()
181 val = AUDIO_READ(nuc900_audio->mmio + ACTL_RESET); nuc900_ac97_cold_reset()
182 val &= ~AC_RESET; nuc900_ac97_cold_reset()
183 AUDIO_WRITE(nuc900_audio->mmio + ACTL_RESET, val); nuc900_ac97_cold_reset()
186 val = AUDIO_READ(nuc900_audio->mmio + ACTL_ACCON); nuc900_ac97_cold_reset()
187 val |= AC_C_RES; nuc900_ac97_cold_reset()
188 AUDIO_WRITE(nuc900_audio->mmio + ACTL_ACCON, val); nuc900_ac97_cold_reset()
190 val = AUDIO_READ(nuc900_audio->mmio + ACTL_ACCON); nuc900_ac97_cold_reset()
191 val &= (~AC_C_RES); nuc900_ac97_cold_reset()
192 AUDIO_WRITE(nuc900_audio->mmio + ACTL_ACCON, val); nuc900_ac97_cold_reset()
213 unsigned long val, tmp; nuc900_ac97_trigger() local
220 val = AUDIO_READ(nuc900_audio->mmio + ACTL_RESET); nuc900_ac97_trigger()
229 val |= AC_PLAY; nuc900_ac97_trigger()
235 val |= AC_RECORD; nuc900_ac97_trigger()
238 AUDIO_WRITE(nuc900_audio->mmio + ACTL_RESET, val); nuc900_ac97_trigger()
243 val = AUDIO_READ(nuc900_audio->mmio + ACTL_RESET); nuc900_ac97_trigger()
250 val &= ~AC_PLAY; nuc900_ac97_trigger()
253 val &= ~AC_RECORD; nuc900_ac97_trigger()
256 AUDIO_WRITE(nuc900_audio->mmio + ACTL_RESET, val); nuc900_ac97_trigger()
269 unsigned long val; nuc900_ac97_probe() local
277 val = AUDIO_READ(nuc900_audio->mmio + ACTL_CON); nuc900_ac97_probe()
278 val |= (IIS_AC_PIN_SEL | ACLINK_EN); nuc900_ac97_probe()
279 AUDIO_WRITE(nuc900_audio->mmio + ACTL_CON, val); nuc900_ac97_probe()
97 nuc900_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val) nuc900_ac97_write() argument
H A Dnuc900-pcm.c70 unsigned long val; nuc900_dma_start() local
72 val = AUDIO_READ(nuc900_audio->mmio + ACTL_CON); nuc900_dma_start()
73 val |= (T_DMA_IRQ | R_DMA_IRQ); nuc900_dma_start()
74 AUDIO_WRITE(nuc900_audio->mmio + ACTL_CON, val); nuc900_dma_start()
81 unsigned long val; nuc900_dma_stop() local
83 val = AUDIO_READ(nuc900_audio->mmio + ACTL_CON); nuc900_dma_stop()
84 val &= ~(T_DMA_IRQ | R_DMA_IRQ); nuc900_dma_stop()
85 AUDIO_WRITE(nuc900_audio->mmio + ACTL_CON, val); nuc900_dma_stop()
92 unsigned long val; nuc900_dma_interrupt() local
96 val = AUDIO_READ(nuc900_audio->mmio + ACTL_CON); nuc900_dma_interrupt()
98 if (val & R_DMA_IRQ) { nuc900_dma_interrupt()
99 AUDIO_WRITE(nuc900_audio->mmio + ACTL_CON, val | R_DMA_IRQ); nuc900_dma_interrupt()
101 val = AUDIO_READ(nuc900_audio->mmio + ACTL_RSR); nuc900_dma_interrupt()
103 if (val & R_DMA_MIDDLE_IRQ) { nuc900_dma_interrupt()
104 val |= R_DMA_MIDDLE_IRQ; nuc900_dma_interrupt()
105 AUDIO_WRITE(nuc900_audio->mmio + ACTL_RSR, val); nuc900_dma_interrupt()
108 if (val & R_DMA_END_IRQ) { nuc900_dma_interrupt()
109 val |= R_DMA_END_IRQ; nuc900_dma_interrupt()
110 AUDIO_WRITE(nuc900_audio->mmio + ACTL_RSR, val); nuc900_dma_interrupt()
112 } else if (val & T_DMA_IRQ) { nuc900_dma_interrupt()
113 AUDIO_WRITE(nuc900_audio->mmio + ACTL_CON, val | T_DMA_IRQ); nuc900_dma_interrupt()
115 val = AUDIO_READ(nuc900_audio->mmio + ACTL_PSR); nuc900_dma_interrupt()
117 if (val & P_DMA_MIDDLE_IRQ) { nuc900_dma_interrupt()
118 val |= P_DMA_MIDDLE_IRQ; nuc900_dma_interrupt()
119 AUDIO_WRITE(nuc900_audio->mmio + ACTL_PSR, val); nuc900_dma_interrupt()
122 if (val & P_DMA_END_IRQ) { nuc900_dma_interrupt()
123 val |= P_DMA_END_IRQ; nuc900_dma_interrupt()
124 AUDIO_WRITE(nuc900_audio->mmio + ACTL_PSR, val); nuc900_dma_interrupt()
149 unsigned long flags, val; nuc900_dma_prepare() local
156 val = AUDIO_READ(nuc900_audio->mmio + ACTL_RESET); nuc900_dma_prepare()
161 val &= ~(PLAY_LEFT_CHNNEL | PLAY_RIGHT_CHNNEL); nuc900_dma_prepare()
162 val |= PLAY_RIGHT_CHNNEL; nuc900_dma_prepare()
164 val &= ~(RECORD_LEFT_CHNNEL | RECORD_RIGHT_CHNNEL); nuc900_dma_prepare()
165 val |= RECORD_RIGHT_CHNNEL; nuc900_dma_prepare()
167 AUDIO_WRITE(nuc900_audio->mmio + ACTL_RESET, val); nuc900_dma_prepare()
171 val |= (PLAY_LEFT_CHNNEL | PLAY_RIGHT_CHNNEL); nuc900_dma_prepare()
173 val |= (RECORD_LEFT_CHNNEL | RECORD_RIGHT_CHNNEL); nuc900_dma_prepare()
174 AUDIO_WRITE(nuc900_audio->mmio + ACTL_RESET, val); nuc900_dma_prepare()
/linux-4.1.27/arch/xtensa/include/asm/
H A Dflat.h8 #define flat_put_addr_at_rp(rp, val, relval ) put_unaligned(val, rp)
/linux-4.1.27/include/math-emu/
H A Ddouble.h74 #define FP_UNPACK_RAW_D(X,val) _FP_UNPACK_RAW_2(D,X,val)
75 #define FP_UNPACK_RAW_DP(X,val) _FP_UNPACK_RAW_2_P(D,X,val)
76 #define FP_PACK_RAW_D(val,X) _FP_PACK_RAW_2(D,val,X)
77 #define FP_PACK_RAW_DP(val,X) \
80 _FP_PACK_RAW_2_P(D,val,X); \
83 #define FP_UNPACK_D(X,val) \
85 _FP_UNPACK_RAW_2(D,X,val); \
89 #define FP_UNPACK_DP(X,val) \
91 _FP_UNPACK_RAW_2_P(D,X,val); \
95 #define FP_PACK_D(val,X) \
98 _FP_PACK_RAW_2(D,val,X); \
101 #define FP_PACK_DP(val,X) \
105 _FP_PACK_RAW_2_P(D,val,X); \
146 #define FP_UNPACK_RAW_D(X,val) _FP_UNPACK_RAW_1(D,X,val)
147 #define FP_UNPACK_RAW_DP(X,val) _FP_UNPACK_RAW_1_P(D,X,val)
148 #define FP_PACK_RAW_D(val,X) _FP_PACK_RAW_1(D,val,X)
149 #define FP_PACK_RAW_DP(val,X) \
152 _FP_PACK_RAW_1_P(D,val,X); \
155 #define FP_UNPACK_D(X,val) \
157 _FP_UNPACK_RAW_1(D,X,val); \
161 #define FP_UNPACK_DP(X,val) \
163 _FP_UNPACK_RAW_1_P(D,X,val); \
167 #define FP_PACK_D(val,X) \
170 _FP_PACK_RAW_1(D,val,X); \
173 #define FP_PACK_DP(val,X) \
177 _FP_PACK_RAW_1_P(D,val,X); \
H A Dquad.h80 #define FP_UNPACK_RAW_Q(X,val) _FP_UNPACK_RAW_4(Q,X,val)
81 #define FP_UNPACK_RAW_QP(X,val) _FP_UNPACK_RAW_4_P(Q,X,val)
82 #define FP_PACK_RAW_Q(val,X) _FP_PACK_RAW_4(Q,val,X)
83 #define FP_PACK_RAW_QP(val,X) \
86 _FP_PACK_RAW_4_P(Q,val,X); \
89 #define FP_UNPACK_Q(X,val) \
91 _FP_UNPACK_RAW_4(Q,X,val); \
95 #define FP_UNPACK_QP(X,val) \
97 _FP_UNPACK_RAW_4_P(Q,X,val); \
101 #define FP_PACK_Q(val,X) \
104 _FP_PACK_RAW_4(Q,val,X); \
107 #define FP_PACK_QP(val,X) \
111 _FP_PACK_RAW_4_P(Q,val,X); \
153 #define FP_UNPACK_RAW_Q(X,val) _FP_UNPACK_RAW_2(Q,X,val)
154 #define FP_UNPACK_RAW_QP(X,val) _FP_UNPACK_RAW_2_P(Q,X,val)
155 #define FP_PACK_RAW_Q(val,X) _FP_PACK_RAW_2(Q,val,X)
156 #define FP_PACK_RAW_QP(val,X) \
159 _FP_PACK_RAW_2_P(Q,val,X); \
162 #define FP_UNPACK_Q(X,val) \
164 _FP_UNPACK_RAW_2(Q,X,val); \
168 #define FP_UNPACK_QP(X,val) \
170 _FP_UNPACK_RAW_2_P(Q,X,val); \
174 #define FP_PACK_Q(val,X) \
177 _FP_PACK_RAW_2(Q,val,X); \
180 #define FP_PACK_QP(val,X) \
184 _FP_PACK_RAW_2_P(Q,val,X); \
/linux-4.1.27/arch/arm64/include/asm/xen/
H A Devents.h19 #define xchg_xen_ulong(ptr, val) xchg((ptr), (val))
/linux-4.1.27/arch/cris/include/arch-v32/arch/hwregs/
H A Dreg_rdwr.h13 #define REG_WRITE(type, addr, val) \
14 do { *((volatile type *) (addr)) = (val); } while(0)
/linux-4.1.27/arch/arm/mach-iop13xx/
H A Dirq.c34 u32 val; read_intctl_0() local
35 asm volatile("mrc p6, 0, %0, c0, c4, 0":"=r" (val)); read_intctl_0()
36 return val; read_intctl_0()
38 static void write_intctl_0(u32 val) write_intctl_0() argument
40 asm volatile("mcr p6, 0, %0, c0, c4, 0"::"r" (val)); write_intctl_0()
47 u32 val; read_intctl_1() local
48 asm volatile("mrc p6, 0, %0, c1, c4, 0":"=r" (val)); read_intctl_1()
49 return val; read_intctl_1()
51 static void write_intctl_1(u32 val) write_intctl_1() argument
53 asm volatile("mcr p6, 0, %0, c1, c4, 0"::"r" (val)); write_intctl_1()
60 u32 val; read_intctl_2() local
61 asm volatile("mrc p6, 0, %0, c2, c4, 0":"=r" (val)); read_intctl_2()
62 return val; read_intctl_2()
64 static void write_intctl_2(u32 val) write_intctl_2() argument
66 asm volatile("mcr p6, 0, %0, c2, c4, 0"::"r" (val)); write_intctl_2()
73 u32 val; read_intctl_3() local
74 asm volatile("mrc p6, 0, %0, c3, c4, 0":"=r" (val)); read_intctl_3()
75 return val; read_intctl_3()
77 static void write_intctl_3(u32 val) write_intctl_3() argument
79 asm volatile("mcr p6, 0, %0, c3, c4, 0"::"r" (val)); write_intctl_3()
84 static void write_intstr_0(u32 val) write_intstr_0() argument
86 asm volatile("mcr p6, 0, %0, c0, c5, 0"::"r" (val)); write_intstr_0()
91 static void write_intstr_1(u32 val) write_intstr_1() argument
93 asm volatile("mcr p6, 0, %0, c1, c5, 0"::"r" (val)); write_intstr_1()
98 static void write_intstr_2(u32 val) write_intstr_2() argument
100 asm volatile("mcr p6, 0, %0, c2, c5, 0"::"r" (val)); write_intstr_2()
105 static void write_intstr_3(u32 val) write_intstr_3() argument
107 asm volatile("mcr p6, 0, %0, c3, c5, 0"::"r" (val)); write_intstr_3()
112 static void write_intbase(u32 val) write_intbase() argument
114 asm volatile("mcr p6, 0, %0, c0, c2, 0"::"r" (val)); write_intbase()
119 static void write_intsize(u32 val) write_intsize() argument
121 asm volatile("mcr p6, 0, %0, c2, c2, 0"::"r" (val)); write_intsize()
H A Dmsi.c32 u32 val; read_imipr_0() local
33 asm volatile("mrc p6, 0, %0, c8, c1, 0":"=r" (val)); read_imipr_0()
34 return val; read_imipr_0()
36 static void write_imipr_0(u32 val) write_imipr_0() argument
38 asm volatile("mcr p6, 0, %0, c8, c1, 0"::"r" (val)); write_imipr_0()
45 u32 val; read_imipr_1() local
46 asm volatile("mrc p6, 0, %0, c9, c1, 0":"=r" (val)); read_imipr_1()
47 return val; read_imipr_1()
49 static void write_imipr_1(u32 val) write_imipr_1() argument
51 asm volatile("mcr p6, 0, %0, c9, c1, 0"::"r" (val)); write_imipr_1()
58 u32 val; read_imipr_2() local
59 asm volatile("mrc p6, 0, %0, c10, c1, 0":"=r" (val)); read_imipr_2()
60 return val; read_imipr_2()
62 static void write_imipr_2(u32 val) write_imipr_2() argument
64 asm volatile("mcr p6, 0, %0, c10, c1, 0"::"r" (val)); write_imipr_2()
71 u32 val; read_imipr_3() local
72 asm volatile("mrc p6, 0, %0, c11, c1, 0":"=r" (val)); read_imipr_3()
73 return val; read_imipr_3()
75 static void write_imipr_3(u32 val) write_imipr_3() argument
77 asm volatile("mcr p6, 0, %0, c11, c1, 0"::"r" (val)); write_imipr_3()
/linux-4.1.27/kernel/sched/
H A Dcpuacct.h4 extern void cpuacct_account_field(struct task_struct *p, int index, u64 val);
13 cpuacct_account_field(struct task_struct *p, int index, u64 val) cpuacct_account_field() argument
/linux-4.1.27/arch/score/include/asm/
H A Dtlbflush.h38 unsigned long val; pevn_get() local
43 : "=r" (val)); pevn_get()
45 return val; pevn_get()
48 static inline void pevn_set(unsigned long val) pevn_set() argument
53 : : "r" (val)); pevn_set()
56 static inline void pectx_set(unsigned long val) pectx_set() argument
61 : : "r" (val)); pectx_set()
66 unsigned long val; pectx_get() local
70 : "=r" (val)); pectx_get()
71 return val; pectx_get()
75 unsigned long val; tlblock_get() local
80 : "=r" (val)); tlblock_get()
81 return val; tlblock_get()
83 static inline void tlblock_set(unsigned long val) tlblock_set() argument
88 : : "r" (val)); tlblock_set()
91 static inline void tlbpt_set(unsigned long val) tlbpt_set() argument
96 : : "r" (val)); tlbpt_set()
101 long val; tlbpt_get() local
106 : "=r" (val)); tlbpt_get()
108 return val; tlbpt_get()
111 static inline void peaddr_set(unsigned long val) peaddr_set() argument
116 : : "r" (val)); peaddr_set()
/linux-4.1.27/arch/avr32/include/uapi/asm/
H A Dswab.h22 static inline __attribute_const__ __u16 __arch_swab16(__u16 val) __arch_swab16() argument
24 return __builtin_bswap_16(val); __arch_swab16()
28 static inline __attribute_const__ __u32 __arch_swab32(__u32 val) __arch_swab32() argument
30 return __builtin_bswap_32(val); __arch_swab32()
/linux-4.1.27/tools/power/cpupower/utils/helpers/
H A Dmsr.c26 int read_msr(int cpu, unsigned int idx, unsigned long long *val) read_msr() argument
37 if (read(fd, val, sizeof *val) != sizeof *val) read_msr()
55 int write_msr(int cpu, unsigned int idx, unsigned long long val) write_msr() argument
66 if (write(fd, &val, sizeof val) != sizeof val) write_msr()
77 unsigned long long val; msr_intel_get_perf_bias() local
83 ret = read_msr(cpu, MSR_IA32_ENERGY_PERF_BIAS, &val); msr_intel_get_perf_bias()
86 return val; msr_intel_get_perf_bias()
89 int msr_intel_set_perf_bias(unsigned int cpu, unsigned int val) msr_intel_set_perf_bias() argument
96 ret = write_msr(cpu, MSR_IA32_ENERGY_PERF_BIAS, val); msr_intel_set_perf_bias()
104 unsigned long long val; msr_intel_get_turbo_ratio() local
110 ret = read_msr(cpu, MSR_NEHALEM_TURBO_RATIO_LIMIT, &val); msr_intel_get_turbo_ratio()
113 return val; msr_intel_get_turbo_ratio()
H A Damd.c29 unsigned long long val; member in union:msr_pstate
37 t = pstate.val & 0xf; get_did()
77 unsigned long long val; decode_pstates() local
86 if (read_msr(cpu, MSR_AMD_PSTATE_LIMIT, &val)) decode_pstates()
89 psmax = (val >> 4) & 0x7; decode_pstates()
91 if (read_msr(cpu, MSR_AMD_PSTATE_STATUS, &val)) decode_pstates()
94 pscur = val & 0x7; decode_pstates()
104 if (read_msr(cpu, MSR_AMD_PSTATE + i, &pstate.val)) decode_pstates()
116 uint8_t val = 0; amd_pci_get_num_boost_states() local
125 val = pci_read_byte(device, 0x15c); amd_pci_get_num_boost_states()
126 if (val & 3) amd_pci_get_num_boost_states()
130 *states = (val >> 2) & 7; amd_pci_get_num_boost_states()
/linux-4.1.27/drivers/char/hw_random/
H A Diproc-rng200.c59 uint32_t val; iproc_rng200_restart() local
62 val = ioread32(rng_base + RNG_CTRL_OFFSET); iproc_rng200_restart()
63 val &= ~RNG_CTRL_RNG_RBGEN_MASK; iproc_rng200_restart()
64 val |= RNG_CTRL_RNG_RBGEN_DISABLE; iproc_rng200_restart()
65 iowrite32(val, rng_base + RNG_CTRL_OFFSET); iproc_rng200_restart()
71 val = ioread32(rng_base + RBG_SOFT_RESET_OFFSET); iproc_rng200_restart()
72 val |= RBG_SOFT_RESET; iproc_rng200_restart()
73 iowrite32(val, rng_base + RBG_SOFT_RESET_OFFSET); iproc_rng200_restart()
75 val = ioread32(rng_base + RNG_SOFT_RESET_OFFSET); iproc_rng200_restart()
76 val |= RNG_SOFT_RESET; iproc_rng200_restart()
77 iowrite32(val, rng_base + RNG_SOFT_RESET_OFFSET); iproc_rng200_restart()
79 val = ioread32(rng_base + RNG_SOFT_RESET_OFFSET); iproc_rng200_restart()
80 val &= ~RNG_SOFT_RESET; iproc_rng200_restart()
81 iowrite32(val, rng_base + RNG_SOFT_RESET_OFFSET); iproc_rng200_restart()
83 val = ioread32(rng_base + RBG_SOFT_RESET_OFFSET); iproc_rng200_restart()
84 val &= ~RBG_SOFT_RESET; iproc_rng200_restart()
85 iowrite32(val, rng_base + RBG_SOFT_RESET_OFFSET); iproc_rng200_restart()
88 val = ioread32(rng_base + RNG_CTRL_OFFSET); iproc_rng200_restart()
89 val &= ~RNG_CTRL_RNG_RBGEN_MASK; iproc_rng200_restart()
90 val |= RNG_CTRL_RNG_RBGEN_ENABLE; iproc_rng200_restart()
91 iowrite32(val, rng_base + RNG_CTRL_OFFSET); iproc_rng200_restart()
158 uint32_t val; iproc_rng200_init() local
161 val = ioread32(priv->base + RNG_CTRL_OFFSET); iproc_rng200_init()
162 val &= ~RNG_CTRL_RNG_RBGEN_MASK; iproc_rng200_init()
163 val |= RNG_CTRL_RNG_RBGEN_ENABLE; iproc_rng200_init()
164 iowrite32(val, priv->base + RNG_CTRL_OFFSET); iproc_rng200_init()
172 uint32_t val; iproc_rng200_cleanup() local
175 val = ioread32(priv->base + RNG_CTRL_OFFSET); iproc_rng200_cleanup()
176 val &= ~RNG_CTRL_RNG_RBGEN_MASK; iproc_rng200_cleanup()
177 val |= RNG_CTRL_RNG_RBGEN_DISABLE; iproc_rng200_cleanup()
178 iowrite32(val, priv->base + RNG_CTRL_OFFSET); iproc_rng200_cleanup()
/linux-4.1.27/include/linux/mfd/
H A Dti_am335x_tscadc.h48 #define STEPENB(val) ((val) << 0)
49 #define ENB(val) (1 << (val))
66 #define STEPCONFIG_MODE(val) ((val) << 0)
70 #define STEPCONFIG_AVG(val) ((val) << 2)
79 #define STEPCONFIG_INM(val) ((val) << 15)
82 #define STEPCONFIG_INP(val) ((val) << 19)
89 #define STEPDELAY_OPEN(val) ((val) << 0)
92 #define STEPDELAY_SAMPLE(val) ((val) << 24)
97 #define STEPCHARGE_RFP(val) ((val) << 12)
100 #define STEPCHARGE_INM(val) ((val) << 15)
103 #define STEPCHARGE_INP(val) ((val) << 19)
105 #define STEPCHARGE_RFM(val) ((val) << 23)
110 #define CHARGEDLY_OPEN(val) ((val) << 0)
119 #define CNTRLREG_AFE_CTRL(val) ((val) << 5)
185 void am335x_tsc_se_set_cache(struct ti_tscadc_dev *tsadc, u32 val);
186 void am335x_tsc_se_set_once(struct ti_tscadc_dev *tsadc, u32 val);
187 void am335x_tsc_se_clr(struct ti_tscadc_dev *tsadc, u32 val);
/linux-4.1.27/drivers/media/i2c/s5c73m3/
H A Ds5c73m3-ctrls.c49 ctrl->val = V4L2_AUTO_FOCUS_STATUS_BUSY; s5c73m3_get_af_status()
53 ctrl->val = V4L2_AUTO_FOCUS_STATUS_REACHED; s5c73m3_get_af_status()
61 ctrl->val = V4L2_AUTO_FOCUS_STATUS_FAILED; s5c73m3_get_af_status()
88 static int s5c73m3_set_colorfx(struct s5c73m3 *state, int val) s5c73m3_set_colorfx() argument
100 if (colorfx[i][0] != val) s5c73m3_set_colorfx()
123 switch (ctrls->exposure_metering->val) { s5c73m3_set_exposure()
139 u16 exp_bias = ctrls->exposure_bias->val; s5c73m3_set_exposure()
145 ctrls->exposure_bias->val, ctrls->exposure_metering->val, ret); s5c73m3_set_exposure()
150 static int s5c73m3_set_white_balance(struct s5c73m3 *state, int val) s5c73m3_set_white_balance() argument
163 if (wb[i][0] != val) s5c73m3_set_white_balance()
184 if (c->focus_auto->val) s5c73m3_af_run()
193 bool awb_lock = ctrl->val & V4L2_LOCK_WHITE_BALANCE; s5c73m3_3a_lock()
194 bool ae_lock = ctrl->val & V4L2_LOCK_EXPOSURE; s5c73m3_3a_lock()
195 bool af_lock = ctrl->val & V4L2_LOCK_FOCUS; s5c73m3_3a_lock()
198 if ((ctrl->val ^ ctrl->cur.val) & V4L2_LOCK_EXPOSURE) { s5c73m3_3a_lock()
205 if (((ctrl->val ^ ctrl->cur.val) & V4L2_LOCK_WHITE_BALANCE) s5c73m3_3a_lock()
206 && state->ctrls.auto_wb->val) { s5c73m3_3a_lock()
213 if ((ctrl->val ^ ctrl->cur.val) & V4L2_LOCK_FOCUS) s5c73m3_3a_lock()
225 u16 mode = (c->af_distance->val == V4L2_AUTO_FOCUS_RANGE_MACRO) s5c73m3_set_auto_focus()
232 if (!ret || (c->focus_auto->is_new && c->focus_auto->val) || s5c73m3_set_auto_focus()
235 else if ((c->focus_auto->is_new && !c->focus_auto->val) || s5c73m3_set_auto_focus()
244 static int s5c73m3_set_contrast(struct s5c73m3 *state, int val) s5c73m3_set_contrast() argument
246 u16 reg = (val < 0) ? -val + 2 : val; s5c73m3_set_contrast()
250 static int s5c73m3_set_saturation(struct s5c73m3 *state, int val) s5c73m3_set_saturation() argument
252 u16 reg = (val < 0) ? -val + 2 : val; s5c73m3_set_saturation()
256 static int s5c73m3_set_sharpness(struct s5c73m3 *state, int val) s5c73m3_set_sharpness() argument
258 u16 reg = (val < 0) ? -val + 2 : val; s5c73m3_set_sharpness()
262 static int s5c73m3_set_iso(struct s5c73m3 *state, int val) s5c73m3_set_iso() argument
266 if (val == V4L2_ISO_SENSITIVITY_MANUAL) s5c73m3_set_iso()
267 iso = state->ctrls.iso->val + 1; s5c73m3_set_iso()
274 static int s5c73m3_set_stabilization(struct s5c73m3 *state, int val) s5c73m3_set_stabilization() argument
278 v4l2_dbg(1, s5c73m3_dbg, sd, "Image stabilization: %d\n", val); s5c73m3_set_stabilization()
280 return s5c73m3_isp_command(state, COMM_FRAME_RATE, val ? s5c73m3_set_stabilization()
298 static int s5c73m3_set_scene_program(struct s5c73m3 *state, int val) s5c73m3_set_scene_program() argument
318 v4l2_ctrl_get_menu(state->ctrls.scene_mode->id)[val]); s5c73m3_set_scene_program()
320 return s5c73m3_isp_command(state, COMM_SCENE_MODE, scene_lookup[val]); s5c73m3_set_scene_program()
323 static int s5c73m3_set_power_line_freq(struct s5c73m3 *state, int val) s5c73m3_set_power_line_freq() argument
327 switch (val) { s5c73m3_set_power_line_freq()
352 ctrl->name, ctrl->val); s5c73m3_s_ctrl()
374 ret = s5c73m3_set_white_balance(state, ctrl->val); s5c73m3_s_ctrl()
378 ret = s5c73m3_set_contrast(state, ctrl->val); s5c73m3_s_ctrl()
382 ret = s5c73m3_set_colorfx(state, ctrl->val); s5c73m3_s_ctrl()
386 ret = s5c73m3_set_exposure(state, ctrl->val); s5c73m3_s_ctrl()
390 ret = s5c73m3_set_auto_focus(state, ctrl->val); s5c73m3_s_ctrl()
394 ret = s5c73m3_set_stabilization(state, ctrl->val); s5c73m3_s_ctrl()
398 ret = s5c73m3_set_iso(state, ctrl->val); s5c73m3_s_ctrl()
402 ret = s5c73m3_set_jpeg_quality(state, ctrl->val); s5c73m3_s_ctrl()
406 ret = s5c73m3_set_power_line_freq(state, ctrl->val); s5c73m3_s_ctrl()
410 ret = s5c73m3_set_saturation(state, ctrl->val); s5c73m3_s_ctrl()
414 ret = s5c73m3_set_scene_program(state, ctrl->val); s5c73m3_s_ctrl()
418 ret = s5c73m3_set_sharpness(state, ctrl->val); s5c73m3_s_ctrl()
422 ret = s5c73m3_isp_command(state, COMM_WDR, !!ctrl->val); s5c73m3_s_ctrl()
426 ret = s5c73m3_isp_command(state, COMM_ZOOM_STEP, ctrl->val); s5c73m3_s_ctrl()
/linux-4.1.27/drivers/misc/mei/
H A Dmei-trace.h30 TP_PROTO(const struct device *dev, const char *reg, u32 offs, u32 val),
31 TP_ARGS(dev, reg, offs, val),
36 __field(u32, val)
42 __entry->val = val;
45 __get_str(dev), __entry->reg, __entry->offs, __entry->val)
49 TP_PROTO(const struct device *dev, const char *reg, u32 offs, u32 val),
50 TP_ARGS(dev, reg, offs, val),
55 __field(u32, val)
61 __entry->val = val;
64 __get_str(dev), __entry->reg, __entry->offs, __entry->val)
/linux-4.1.27/drivers/gpu/drm/i915/
H A Dintel_sideband.c43 u32 port, u32 opcode, u32 addr, u32 *val) vlv_sideband_rw()
62 I915_WRITE(VLV_IOSF_DATA, *val); vlv_sideband_rw()
72 *val = I915_READ(VLV_IOSF_DATA); vlv_sideband_rw()
80 u32 val = 0; vlv_punit_read() local
86 SB_CRRDDA_NP, addr, &val); vlv_punit_read()
89 return val; vlv_punit_read()
92 void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val) vlv_punit_write() argument
98 SB_CRWRDA_NP, addr, &val); vlv_punit_write()
104 u32 val = 0; vlv_bunit_read() local
107 SB_CRRDDA_NP, reg, &val); vlv_bunit_read()
109 return val; vlv_bunit_read()
112 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) vlv_bunit_write() argument
115 SB_CRWRDA_NP, reg, &val); vlv_bunit_write()
120 u32 val = 0; vlv_nc_read() local
126 SB_CRRDDA_NP, addr, &val); vlv_nc_read()
129 return val; vlv_nc_read()
134 u32 val = 0; vlv_gpio_nc_read() local
136 SB_CRRDDA_NP, reg, &val); vlv_gpio_nc_read()
137 return val; vlv_gpio_nc_read()
140 void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) vlv_gpio_nc_write() argument
143 SB_CRWRDA_NP, reg, &val); vlv_gpio_nc_write()
148 u32 val = 0; vlv_cck_read() local
150 SB_CRRDDA_NP, reg, &val); vlv_cck_read()
151 return val; vlv_cck_read()
154 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) vlv_cck_write() argument
157 SB_CRWRDA_NP, reg, &val); vlv_cck_write()
162 u32 val = 0; vlv_ccu_read() local
164 SB_CRRDDA_NP, reg, &val); vlv_ccu_read()
165 return val; vlv_ccu_read()
168 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) vlv_ccu_write() argument
171 SB_CRWRDA_NP, reg, &val); vlv_ccu_write()
176 u32 val = 0; vlv_gps_core_read() local
178 SB_CRRDDA_NP, reg, &val); vlv_gps_core_read()
179 return val; vlv_gps_core_read()
182 void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) vlv_gps_core_write() argument
185 SB_CRWRDA_NP, reg, &val); vlv_gps_core_write()
190 u32 val = 0; vlv_dpio_read() local
193 SB_MRD_NP, reg, &val); vlv_dpio_read()
199 WARN(val == 0xffffffff, "DPIO read pipe %c reg 0x%x == 0x%x\n", vlv_dpio_read()
200 pipe_name(pipe), reg, val); vlv_dpio_read()
202 return val; vlv_dpio_read()
205 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val) vlv_dpio_write() argument
208 SB_MWR_NP, reg, &val); vlv_dpio_write()
272 u32 val = 0; vlv_flisdsi_read() local
274 reg, &val); vlv_flisdsi_read()
275 return val; vlv_flisdsi_read()
278 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) vlv_flisdsi_write() argument
281 reg, &val); vlv_flisdsi_write()
42 vlv_sideband_rw(struct drm_i915_private *dev_priv, u32 devfn, u32 port, u32 opcode, u32 addr, u32 *val) vlv_sideband_rw() argument
H A Dintel_hdmi.c140 u32 val = I915_READ(VIDEO_DIP_CTL); g4x_write_infoframe() local
143 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); g4x_write_infoframe()
145 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ g4x_write_infoframe()
146 val |= g4x_infoframe_index(type); g4x_write_infoframe()
148 val &= ~g4x_infoframe_enable(type); g4x_write_infoframe()
150 I915_WRITE(VIDEO_DIP_CTL, val); g4x_write_infoframe()
162 val |= g4x_infoframe_enable(type); g4x_write_infoframe()
163 val &= ~VIDEO_DIP_FREQ_MASK; g4x_write_infoframe()
164 val |= VIDEO_DIP_FREQ_VSYNC; g4x_write_infoframe()
166 I915_WRITE(VIDEO_DIP_CTL, val); g4x_write_infoframe()
175 u32 val = I915_READ(VIDEO_DIP_CTL); g4x_infoframe_enabled() local
177 if (VIDEO_DIP_PORT(intel_dig_port->port) == (val & VIDEO_DIP_PORT_MASK)) g4x_infoframe_enabled()
178 return val & VIDEO_DIP_ENABLE; g4x_infoframe_enabled()
192 u32 val = I915_READ(reg); ibx_write_infoframe() local
194 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); ibx_write_infoframe()
196 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ ibx_write_infoframe()
197 val |= g4x_infoframe_index(type); ibx_write_infoframe()
199 val &= ~g4x_infoframe_enable(type); ibx_write_infoframe()
201 I915_WRITE(reg, val); ibx_write_infoframe()
213 val |= g4x_infoframe_enable(type); ibx_write_infoframe()
214 val &= ~VIDEO_DIP_FREQ_MASK; ibx_write_infoframe()
215 val |= VIDEO_DIP_FREQ_VSYNC; ibx_write_infoframe()
217 I915_WRITE(reg, val); ibx_write_infoframe()
227 u32 val = I915_READ(reg); ibx_infoframe_enabled() local
229 return val & VIDEO_DIP_ENABLE; ibx_infoframe_enabled()
241 u32 val = I915_READ(reg); cpt_write_infoframe() local
243 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); cpt_write_infoframe()
245 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ cpt_write_infoframe()
246 val |= g4x_infoframe_index(type); cpt_write_infoframe()
251 val &= ~g4x_infoframe_enable(type); cpt_write_infoframe()
253 I915_WRITE(reg, val); cpt_write_infoframe()
265 val |= g4x_infoframe_enable(type); cpt_write_infoframe()
266 val &= ~VIDEO_DIP_FREQ_MASK; cpt_write_infoframe()
267 val |= VIDEO_DIP_FREQ_VSYNC; cpt_write_infoframe()
269 I915_WRITE(reg, val); cpt_write_infoframe()
279 u32 val = I915_READ(reg); cpt_infoframe_enabled() local
281 return val & VIDEO_DIP_ENABLE; cpt_infoframe_enabled()
293 u32 val = I915_READ(reg); vlv_write_infoframe() local
295 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); vlv_write_infoframe()
297 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ vlv_write_infoframe()
298 val |= g4x_infoframe_index(type); vlv_write_infoframe()
300 val &= ~g4x_infoframe_enable(type); vlv_write_infoframe()
302 I915_WRITE(reg, val); vlv_write_infoframe()
314 val |= g4x_infoframe_enable(type); vlv_write_infoframe()
315 val &= ~VIDEO_DIP_FREQ_MASK; vlv_write_infoframe()
316 val |= VIDEO_DIP_FREQ_VSYNC; vlv_write_infoframe()
318 I915_WRITE(reg, val); vlv_write_infoframe()
328 u32 val = I915_READ(reg); vlv_infoframe_enabled() local
330 return val & VIDEO_DIP_ENABLE; vlv_infoframe_enabled()
344 u32 val = I915_READ(ctl_reg); hsw_write_infoframe() local
352 val &= ~hsw_infoframe_enable(type); hsw_write_infoframe()
353 I915_WRITE(ctl_reg, val); hsw_write_infoframe()
365 val |= hsw_infoframe_enable(type); hsw_write_infoframe()
366 I915_WRITE(ctl_reg, val); hsw_write_infoframe()
376 u32 val = I915_READ(ctl_reg); hsw_infoframe_enabled() local
378 return val & (VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_SPD_HSW | hsw_infoframe_enabled()
490 u32 val = I915_READ(reg); g4x_set_infoframes() local
504 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; g4x_set_infoframes()
507 if (!(val & VIDEO_DIP_ENABLE)) g4x_set_infoframes()
509 val &= ~VIDEO_DIP_ENABLE; g4x_set_infoframes()
510 I915_WRITE(reg, val); g4x_set_infoframes()
515 if (port != (val & VIDEO_DIP_PORT_MASK)) { g4x_set_infoframes()
516 if (val & VIDEO_DIP_ENABLE) { g4x_set_infoframes()
517 val &= ~VIDEO_DIP_ENABLE; g4x_set_infoframes()
518 I915_WRITE(reg, val); g4x_set_infoframes()
521 val &= ~VIDEO_DIP_PORT_MASK; g4x_set_infoframes()
522 val |= port; g4x_set_infoframes()
525 val |= VIDEO_DIP_ENABLE; g4x_set_infoframes()
526 val &= ~VIDEO_DIP_ENABLE_VENDOR; g4x_set_infoframes()
528 I915_WRITE(reg, val); g4x_set_infoframes()
545 u32 val = I915_READ(reg); ibx_set_infoframes() local
551 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; ibx_set_infoframes()
554 if (!(val & VIDEO_DIP_ENABLE)) ibx_set_infoframes()
556 val &= ~VIDEO_DIP_ENABLE; ibx_set_infoframes()
557 I915_WRITE(reg, val); ibx_set_infoframes()
562 if (port != (val & VIDEO_DIP_PORT_MASK)) { ibx_set_infoframes()
563 if (val & VIDEO_DIP_ENABLE) { ibx_set_infoframes()
564 val &= ~VIDEO_DIP_ENABLE; ibx_set_infoframes()
565 I915_WRITE(reg, val); ibx_set_infoframes()
568 val &= ~VIDEO_DIP_PORT_MASK; ibx_set_infoframes()
569 val |= port; ibx_set_infoframes()
572 val |= VIDEO_DIP_ENABLE; ibx_set_infoframes()
573 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | ibx_set_infoframes()
576 I915_WRITE(reg, val); ibx_set_infoframes()
592 u32 val = I915_READ(reg); cpt_set_infoframes() local
597 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; cpt_set_infoframes()
600 if (!(val & VIDEO_DIP_ENABLE)) cpt_set_infoframes()
602 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI); cpt_set_infoframes()
603 I915_WRITE(reg, val); cpt_set_infoframes()
609 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; cpt_set_infoframes()
610 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | cpt_set_infoframes()
613 I915_WRITE(reg, val); cpt_set_infoframes()
630 u32 val = I915_READ(reg); vlv_set_infoframes() local
636 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; vlv_set_infoframes()
639 if (!(val & VIDEO_DIP_ENABLE)) vlv_set_infoframes()
641 val &= ~VIDEO_DIP_ENABLE; vlv_set_infoframes()
642 I915_WRITE(reg, val); vlv_set_infoframes()
647 if (port != (val & VIDEO_DIP_PORT_MASK)) { vlv_set_infoframes()
648 if (val & VIDEO_DIP_ENABLE) { vlv_set_infoframes()
649 val &= ~VIDEO_DIP_ENABLE; vlv_set_infoframes()
650 I915_WRITE(reg, val); vlv_set_infoframes()
653 val &= ~VIDEO_DIP_PORT_MASK; vlv_set_infoframes()
654 val |= port; vlv_set_infoframes()
657 val |= VIDEO_DIP_ENABLE; vlv_set_infoframes()
658 val &= ~(VIDEO_DIP_ENABLE_AVI | VIDEO_DIP_ENABLE_VENDOR | vlv_set_infoframes()
661 I915_WRITE(reg, val); vlv_set_infoframes()
677 u32 val = I915_READ(reg); hsw_set_infoframes() local
687 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW | hsw_set_infoframes()
690 I915_WRITE(reg, val); hsw_set_infoframes()
1176 uint64_t val) intel_hdmi_set_property()
1184 ret = drm_object_property_set_value(&connector->base, property, val); intel_hdmi_set_property()
1189 enum hdmi_force_audio i = val; intel_hdmi_set_property()
1213 switch (val) { intel_hdmi_set_property()
1237 switch (val) { intel_hdmi_set_property()
1288 u32 val; vlv_hdmi_pre_enable() local
1292 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); vlv_hdmi_pre_enable()
1293 val = 0; vlv_hdmi_pre_enable()
1295 val |= (1<<21); vlv_hdmi_pre_enable()
1297 val &= ~(1<<21); vlv_hdmi_pre_enable()
1298 val |= 0x001000c4; vlv_hdmi_pre_enable()
1299 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); vlv_hdmi_pre_enable()
1367 u32 val; chv_hdmi_pre_pll_enable() local
1375 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); chv_hdmi_pre_pll_enable()
1376 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); chv_hdmi_pre_pll_enable()
1378 val |= CHV_BUFLEFTENA1_FORCE; chv_hdmi_pre_pll_enable()
1380 val |= CHV_BUFRIGHTENA1_FORCE; chv_hdmi_pre_pll_enable()
1381 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); chv_hdmi_pre_pll_enable()
1383 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); chv_hdmi_pre_pll_enable()
1384 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); chv_hdmi_pre_pll_enable()
1386 val |= CHV_BUFLEFTENA2_FORCE; chv_hdmi_pre_pll_enable()
1388 val |= CHV_BUFRIGHTENA2_FORCE; chv_hdmi_pre_pll_enable()
1389 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); chv_hdmi_pre_pll_enable()
1393 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch)); chv_hdmi_pre_pll_enable()
1394 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; chv_hdmi_pre_pll_enable()
1396 val &= ~CHV_PCS_USEDCLKCHANNEL; chv_hdmi_pre_pll_enable()
1398 val |= CHV_PCS_USEDCLKCHANNEL; chv_hdmi_pre_pll_enable()
1399 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val); chv_hdmi_pre_pll_enable()
1401 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch)); chv_hdmi_pre_pll_enable()
1402 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; chv_hdmi_pre_pll_enable()
1404 val &= ~CHV_PCS_USEDCLKCHANNEL; chv_hdmi_pre_pll_enable()
1406 val |= CHV_PCS_USEDCLKCHANNEL; chv_hdmi_pre_pll_enable()
1407 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val); chv_hdmi_pre_pll_enable()
1414 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch)); chv_hdmi_pre_pll_enable()
1416 val &= ~CHV_CMN_USEDCLKCHANNEL; chv_hdmi_pre_pll_enable()
1418 val |= CHV_CMN_USEDCLKCHANNEL; chv_hdmi_pre_pll_enable()
1419 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val); chv_hdmi_pre_pll_enable()
1449 u32 val; chv_hdmi_post_disable() local
1454 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); chv_hdmi_post_disable()
1455 val |= CHV_PCS_REQ_SOFTRESET_EN; chv_hdmi_post_disable()
1456 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); chv_hdmi_post_disable()
1458 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); chv_hdmi_post_disable()
1459 val |= CHV_PCS_REQ_SOFTRESET_EN; chv_hdmi_post_disable()
1460 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); chv_hdmi_post_disable()
1462 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); chv_hdmi_post_disable()
1463 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); chv_hdmi_post_disable()
1464 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); chv_hdmi_post_disable()
1466 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); chv_hdmi_post_disable()
1467 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); chv_hdmi_post_disable()
1468 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); chv_hdmi_post_disable()
1486 u32 val; chv_hdmi_pre_enable() local
1491 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); chv_hdmi_pre_enable()
1492 val &= ~DPIO_LANEDESKEW_STRAP_OVRD; chv_hdmi_pre_enable()
1493 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); chv_hdmi_pre_enable()
1495 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); chv_hdmi_pre_enable()
1496 val &= ~DPIO_LANEDESKEW_STRAP_OVRD; chv_hdmi_pre_enable()
1497 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); chv_hdmi_pre_enable()
1500 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); chv_hdmi_pre_enable()
1501 val |= CHV_PCS_REQ_SOFTRESET_EN; chv_hdmi_pre_enable()
1502 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); chv_hdmi_pre_enable()
1504 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); chv_hdmi_pre_enable()
1505 val |= CHV_PCS_REQ_SOFTRESET_EN; chv_hdmi_pre_enable()
1506 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); chv_hdmi_pre_enable()
1508 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); chv_hdmi_pre_enable()
1509 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); chv_hdmi_pre_enable()
1510 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); chv_hdmi_pre_enable()
1512 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); chv_hdmi_pre_enable()
1513 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); chv_hdmi_pre_enable()
1514 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); chv_hdmi_pre_enable()
1528 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); chv_hdmi_pre_enable()
1529 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); chv_hdmi_pre_enable()
1530 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); chv_hdmi_pre_enable()
1531 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; chv_hdmi_pre_enable()
1532 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); chv_hdmi_pre_enable()
1534 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); chv_hdmi_pre_enable()
1535 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); chv_hdmi_pre_enable()
1536 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); chv_hdmi_pre_enable()
1537 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; chv_hdmi_pre_enable()
1538 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); chv_hdmi_pre_enable()
1540 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch)); chv_hdmi_pre_enable()
1541 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); chv_hdmi_pre_enable()
1542 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; chv_hdmi_pre_enable()
1543 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val); chv_hdmi_pre_enable()
1545 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch)); chv_hdmi_pre_enable()
1546 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); chv_hdmi_pre_enable()
1547 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; chv_hdmi_pre_enable()
1548 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val); chv_hdmi_pre_enable()
1553 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i)); chv_hdmi_pre_enable()
1554 val &= ~DPIO_SWING_DEEMPH9P5_MASK; chv_hdmi_pre_enable()
1555 val |= 128 << DPIO_SWING_DEEMPH9P5_SHIFT; chv_hdmi_pre_enable()
1556 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val); chv_hdmi_pre_enable()
1560 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); chv_hdmi_pre_enable()
1561 val &= ~DPIO_SWING_MARGIN000_MASK; chv_hdmi_pre_enable()
1562 val |= 102 << DPIO_SWING_MARGIN000_SHIFT; chv_hdmi_pre_enable()
1563 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); chv_hdmi_pre_enable()
1568 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); chv_hdmi_pre_enable()
1569 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN; chv_hdmi_pre_enable()
1570 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); chv_hdmi_pre_enable()
1575 val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW3(ch)); chv_hdmi_pre_enable()
1577 val |= DPIO_TX_UNIQ_TRANS_SCALE_CH1; chv_hdmi_pre_enable()
1579 val |= DPIO_TX_UNIQ_TRANS_SCALE_CH0; chv_hdmi_pre_enable()
1580 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(ch), val); chv_hdmi_pre_enable()
1587 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); chv_hdmi_pre_enable()
1588 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; chv_hdmi_pre_enable()
1589 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); chv_hdmi_pre_enable()
1591 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); chv_hdmi_pre_enable()
1592 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; chv_hdmi_pre_enable()
1593 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); chv_hdmi_pre_enable()
1596 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30); chv_hdmi_pre_enable()
1597 val |= DPIO_LRC_BYPASS; chv_hdmi_pre_enable()
1598 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val); chv_hdmi_pre_enable()
1174 intel_hdmi_set_property(struct drm_connector *connector, struct drm_property *property, uint64_t val) intel_hdmi_set_property() argument
/linux-4.1.27/arch/x86/um/shared/sysdep/
H A Dkernel-offsets.h7 #define DEFINE(sym, val) \
8 asm volatile("\n->" #sym " %0 " #val : : "i" (val))
/linux-4.1.27/drivers/gpu/host1x/hw/
H A Ddebug_hw.c41 static unsigned int show_channel_command(struct output *o, u32 val) show_channel_command() argument
46 switch (val >> 28) { show_channel_command()
48 mask = val & 0x3f; show_channel_command()
51 val >> 6 & 0x3ff, show_channel_command()
52 val >> 16 & 0xfff, mask); show_channel_command()
56 val >> 6 & 0x3ff); show_channel_command()
62 val >> 16 & 0xfff); show_channel_command()
63 return val & 0xffff; show_channel_command()
67 val >> 16 & 0xfff); show_channel_command()
68 return val & 0xffff; show_channel_command()
71 mask = val & 0xffff; show_channel_command()
73 val >> 16 & 0xfff, mask); show_channel_command()
78 val >> 16 & 0xfff, val & 0xffff); show_channel_command()
82 host1x_debug_output(o, "RESTART(offset=%08x)\n", val << 4); show_channel_command()
87 val >> 16 & 0xfff, val >> 15 & 0x1, show_channel_command()
88 val >> 14 & 0x1, val & 0x3fff); show_channel_command()
92 subop = val >> 24 & 0xf; show_channel_command()
95 val & 0xff); show_channel_command()
98 val & 0xff); show_channel_command()
100 host1x_debug_output(o, "EXTEND_UNKNOWN(%08x)\n", val); show_channel_command()
128 u32 val = *(map_addr + offset / 4 + i); show_gather() local
131 host1x_debug_output(o, "%08x: %08x:", addr, val); show_gather()
132 data_count = show_channel_command(o, val); show_gather()
134 host1x_debug_output(o, "%08x%s", val, show_gather()
185 u32 val, base, baseval; host1x_debug_show_channel_cdma() local
204 host1x_debug_output(o, "waiting on syncpt %d val %d\n", host1x_debug_show_channel_cdma()
214 val = cbread & 0xffff; host1x_debug_show_channel_cdma()
215 host1x_debug_output(o, "waiting on syncpt %d val %d (base %d = %d; offset = %d)\n", host1x_debug_show_channel_cdma()
216 cbread >> 24, baseval + val, base, host1x_debug_show_channel_cdma()
217 baseval, val); host1x_debug_show_channel_cdma()
219 host1x_debug_output(o, "active class %02x, offset %04x, val %08x\n", host1x_debug_show_channel_cdma()
236 u32 val, rd_ptr, wr_ptr, start, end; host1x_debug_show_channel_fifo() local
241 val = host1x_ch_readl(ch, HOST1X_CHANNEL_FIFOSTAT); host1x_debug_show_channel_fifo()
242 host1x_debug_output(o, "FIFOSTAT %08x\n", val); host1x_debug_show_channel_fifo()
243 if (HOST1X_CHANNEL_FIFOSTAT_CFEMPTY_V(val)) { host1x_debug_show_channel_fifo()
253 val = host1x_sync_readl(host, HOST1X_SYNC_CFPEEK_PTRS); host1x_debug_show_channel_fifo()
254 rd_ptr = HOST1X_SYNC_CFPEEK_PTRS_CF_RD_PTR_V(val); host1x_debug_show_channel_fifo()
255 wr_ptr = HOST1X_SYNC_CFPEEK_PTRS_CF_WR_PTR_V(val); host1x_debug_show_channel_fifo()
257 val = host1x_sync_readl(host, HOST1X_SYNC_CF_SETUP(ch->id)); host1x_debug_show_channel_fifo()
258 start = HOST1X_SYNC_CF_SETUP_BASE_V(val); host1x_debug_show_channel_fifo()
259 end = HOST1X_SYNC_CF_SETUP_LIMIT_V(val); host1x_debug_show_channel_fifo()
267 val = host1x_sync_readl(host, HOST1X_SYNC_CFPEEK_READ); host1x_debug_show_channel_fifo()
270 host1x_debug_output(o, "%08x:", val); host1x_debug_show_channel_fifo()
271 data_count = show_channel_command(o, val); host1x_debug_show_channel_fifo()
273 host1x_debug_output(o, "%08x%s", val, host1x_debug_show_channel_fifo()
/linux-4.1.27/fs/ncpfs/
H A Dgetopt.c25 * Returns opts->val if a matching entry in the 'opts' array is found,
32 char *val; ncp_getopt() local
41 if ((val = strchr (token, '=')) != NULL) { ncp_getopt()
42 *val++ = 0; ncp_getopt()
44 *optarg = val; ncp_getopt()
47 if (!val) { ncp_getopt()
49 return opts->val; ncp_getopt()
56 int rc = kstrtoul(val, 0, value); ncp_getopt()
60 caller, token, val); ncp_getopt()
63 return opts->val; ncp_getopt()
66 return opts->val; ncp_getopt()
69 caller, val, token); ncp_getopt()
/linux-4.1.27/arch/powerpc/sysdev/
H A Dgrackle.c32 unsigned int val; grackle_set_stg() local
35 val = in_le32(bp->cfg_data); grackle_set_stg()
36 val = enable? (val | GRACKLE_PICR1_STG) : grackle_set_stg()
37 (val & ~GRACKLE_PICR1_STG); grackle_set_stg()
39 out_le32(bp->cfg_data, val); grackle_set_stg()
45 unsigned int val; grackle_set_loop_snoop() local
48 val = in_le32(bp->cfg_data); grackle_set_loop_snoop()
49 val = enable? (val | GRACKLE_PICR1_LOOPSNOOP) : grackle_set_loop_snoop()
50 (val & ~GRACKLE_PICR1_LOOPSNOOP); grackle_set_loop_snoop()
52 out_le32(bp->cfg_data, val); grackle_set_loop_snoop()
/linux-4.1.27/arch/powerpc/sysdev/qe_lib/
H A Dusb.c27 u32 val; qe_usb_clock_set() local
30 case QE_CLK3: val = QE_CMXGCR_USBCS_CLK3; break; qe_usb_clock_set()
31 case QE_CLK5: val = QE_CMXGCR_USBCS_CLK5; break; qe_usb_clock_set()
32 case QE_CLK7: val = QE_CMXGCR_USBCS_CLK7; break; qe_usb_clock_set()
33 case QE_CLK9: val = QE_CMXGCR_USBCS_CLK9; break; qe_usb_clock_set()
34 case QE_CLK13: val = QE_CMXGCR_USBCS_CLK13; break; qe_usb_clock_set()
35 case QE_CLK17: val = QE_CMXGCR_USBCS_CLK17; break; qe_usb_clock_set()
36 case QE_CLK19: val = QE_CMXGCR_USBCS_CLK19; break; qe_usb_clock_set()
37 case QE_CLK21: val = QE_CMXGCR_USBCS_CLK21; break; qe_usb_clock_set()
38 case QE_BRG9: val = QE_CMXGCR_USBCS_BRG9; break; qe_usb_clock_set()
39 case QE_BRG10: val = QE_CMXGCR_USBCS_BRG10; break; qe_usb_clock_set()
50 clrsetbits_be32(&mux->cmxgcr, QE_CMXGCR_USBCS, val); qe_usb_clock_set()
/linux-4.1.27/arch/arm/mach-iop33x/
H A Dirq.c25 static void intctl0_write(u32 val) intctl0_write() argument
27 asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val)); intctl0_write()
30 static void intctl1_write(u32 val) intctl1_write() argument
32 asm volatile("mcr p6, 0, %0, c1, c0, 0" : : "r" (val)); intctl1_write()
35 static void intstr0_write(u32 val) intstr0_write() argument
37 asm volatile("mcr p6, 0, %0, c2, c0, 0" : : "r" (val)); intstr0_write()
40 static void intstr1_write(u32 val) intstr1_write() argument
42 asm volatile("mcr p6, 0, %0, c3, c0, 0" : : "r" (val)); intstr1_write()
45 static void intbase_write(u32 val) intbase_write() argument
47 asm volatile("mcr p6, 0, %0, c12, c0, 0" : : "r" (val)); intbase_write()
50 static void intsize_write(u32 val) intsize_write() argument
52 asm volatile("mcr p6, 0, %0, c13, c0, 0" : : "r" (val)); intsize_write()
/linux-4.1.27/tools/virtio/linux/
H A Dvirtio_config.h43 static inline u16 virtio16_to_cpu(struct virtio_device *vdev, __virtio16 val) virtio16_to_cpu() argument
45 return __virtio16_to_cpu(virtio_has_feature(vdev, VIRTIO_F_VERSION_1), val); virtio16_to_cpu()
48 static inline __virtio16 cpu_to_virtio16(struct virtio_device *vdev, u16 val) cpu_to_virtio16() argument
50 return __cpu_to_virtio16(virtio_has_feature(vdev, VIRTIO_F_VERSION_1), val); cpu_to_virtio16()
53 static inline u32 virtio32_to_cpu(struct virtio_device *vdev, __virtio32 val) virtio32_to_cpu() argument
55 return __virtio32_to_cpu(virtio_has_feature(vdev, VIRTIO_F_VERSION_1), val); virtio32_to_cpu()
58 static inline __virtio32 cpu_to_virtio32(struct virtio_device *vdev, u32 val) cpu_to_virtio32() argument
60 return __cpu_to_virtio32(virtio_has_feature(vdev, VIRTIO_F_VERSION_1), val); cpu_to_virtio32()
63 static inline u64 virtio64_to_cpu(struct virtio_device *vdev, __virtio64 val) virtio64_to_cpu() argument
65 return __virtio64_to_cpu(virtio_has_feature(vdev, VIRTIO_F_VERSION_1), val); virtio64_to_cpu()
68 static inline __virtio64 cpu_to_virtio64(struct virtio_device *vdev, u64 val) cpu_to_virtio64() argument
70 return __cpu_to_virtio64(virtio_has_feature(vdev, VIRTIO_F_VERSION_1), val); cpu_to_virtio64()
/linux-4.1.27/drivers/gpu/drm/msm/mdp/mdp4/
H A Dmdp4.xml.h112 static inline uint32_t MDP4_VERSION_MINOR(uint32_t val) MDP4_VERSION_MINOR() argument
114 return ((val) << MDP4_VERSION_MINOR__SHIFT) & MDP4_VERSION_MINOR__MASK; MDP4_VERSION_MINOR()
118 static inline uint32_t MDP4_VERSION_MAJOR(uint32_t val) MDP4_VERSION_MAJOR() argument
120 return ((val) << MDP4_VERSION_MAJOR__SHIFT) & MDP4_VERSION_MAJOR__MASK; MDP4_VERSION_MAJOR()
140 static inline uint32_t MDP4_DISP_INTF_SEL_PRIM(enum mdp4_intf val) MDP4_DISP_INTF_SEL_PRIM() argument
142 return ((val) << MDP4_DISP_INTF_SEL_PRIM__SHIFT) & MDP4_DISP_INTF_SEL_PRIM__MASK; MDP4_DISP_INTF_SEL_PRIM()
146 static inline uint32_t MDP4_DISP_INTF_SEL_SEC(enum mdp4_intf val) MDP4_DISP_INTF_SEL_SEC() argument
148 return ((val) << MDP4_DISP_INTF_SEL_SEC__SHIFT) & MDP4_DISP_INTF_SEL_SEC__MASK; MDP4_DISP_INTF_SEL_SEC()
152 static inline uint32_t MDP4_DISP_INTF_SEL_EXT(enum mdp4_intf val) MDP4_DISP_INTF_SEL_EXT() argument
154 return ((val) << MDP4_DISP_INTF_SEL_EXT__SHIFT) & MDP4_DISP_INTF_SEL_EXT__MASK; MDP4_DISP_INTF_SEL_EXT()
182 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE0(enum mdp_mixer_stage_id val) MDP4_LAYERMIXER2_IN_CFG_PIPE0() argument
184 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE0__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE0__MASK; MDP4_LAYERMIXER2_IN_CFG_PIPE0()
189 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE1(enum mdp_mixer_stage_id val) MDP4_LAYERMIXER2_IN_CFG_PIPE1() argument
191 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE1__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE1__MASK; MDP4_LAYERMIXER2_IN_CFG_PIPE1()
196 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE2(enum mdp_mixer_stage_id val) MDP4_LAYERMIXER2_IN_CFG_PIPE2() argument
198 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE2__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE2__MASK; MDP4_LAYERMIXER2_IN_CFG_PIPE2()
203 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE3(enum mdp_mixer_stage_id val) MDP4_LAYERMIXER2_IN_CFG_PIPE3() argument
205 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE3__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE3__MASK; MDP4_LAYERMIXER2_IN_CFG_PIPE3()
210 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE4(enum mdp_mixer_stage_id val) MDP4_LAYERMIXER2_IN_CFG_PIPE4() argument
212 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE4__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE4__MASK; MDP4_LAYERMIXER2_IN_CFG_PIPE4()
217 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE5(enum mdp_mixer_stage_id val) MDP4_LAYERMIXER2_IN_CFG_PIPE5() argument
219 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE5__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE5__MASK; MDP4_LAYERMIXER2_IN_CFG_PIPE5()
224 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE6(enum mdp_mixer_stage_id val) MDP4_LAYERMIXER2_IN_CFG_PIPE6() argument
226 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE6__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE6__MASK; MDP4_LAYERMIXER2_IN_CFG_PIPE6()
231 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE7(enum mdp_mixer_stage_id val) MDP4_LAYERMIXER2_IN_CFG_PIPE7() argument
233 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE7__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE7__MASK; MDP4_LAYERMIXER2_IN_CFG_PIPE7()
242 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE0(enum mdp_mixer_stage_id val) MDP4_LAYERMIXER_IN_CFG_PIPE0() argument
244 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE0__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE0__MASK; MDP4_LAYERMIXER_IN_CFG_PIPE0()
249 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE1(enum mdp_mixer_stage_id val) MDP4_LAYERMIXER_IN_CFG_PIPE1() argument
251 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE1__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE1__MASK; MDP4_LAYERMIXER_IN_CFG_PIPE1()
256 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE2(enum mdp_mixer_stage_id val) MDP4_LAYERMIXER_IN_CFG_PIPE2() argument
258 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE2__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE2__MASK; MDP4_LAYERMIXER_IN_CFG_PIPE2()
263 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE3(enum mdp_mixer_stage_id val) MDP4_LAYERMIXER_IN_CFG_PIPE3() argument
265 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE3__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE3__MASK; MDP4_LAYERMIXER_IN_CFG_PIPE3()
270 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE4(enum mdp_mixer_stage_id val) MDP4_LAYERMIXER_IN_CFG_PIPE4() argument
272 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE4__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE4__MASK; MDP4_LAYERMIXER_IN_CFG_PIPE4()
277 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE5(enum mdp_mixer_stage_id val) MDP4_LAYERMIXER_IN_CFG_PIPE5() argument
279 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE5__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE5__MASK; MDP4_LAYERMIXER_IN_CFG_PIPE5()
284 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE6(enum mdp_mixer_stage_id val) MDP4_LAYERMIXER_IN_CFG_PIPE6() argument
286 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE6__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE6__MASK; MDP4_LAYERMIXER_IN_CFG_PIPE6()
291 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE7(enum mdp_mixer_stage_id val) MDP4_LAYERMIXER_IN_CFG_PIPE7() argument
293 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE7__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE7__MASK; MDP4_LAYERMIXER_IN_CFG_PIPE7()
325 static inline uint32_t MDP4_OVLP_SIZE_HEIGHT(uint32_t val) MDP4_OVLP_SIZE_HEIGHT() argument
327 return ((val) << MDP4_OVLP_SIZE_HEIGHT__SHIFT) & MDP4_OVLP_SIZE_HEIGHT__MASK; MDP4_OVLP_SIZE_HEIGHT()
331 static inline uint32_t MDP4_OVLP_SIZE_WIDTH(uint32_t val) MDP4_OVLP_SIZE_WIDTH() argument
333 return ((val) << MDP4_OVLP_SIZE_WIDTH__SHIFT) & MDP4_OVLP_SIZE_WIDTH__MASK; MDP4_OVLP_SIZE_WIDTH()
357 static inline uint32_t MDP4_OVLP_STAGE_OP_FG_ALPHA(enum mdp_alpha_type val) MDP4_OVLP_STAGE_OP_FG_ALPHA() argument
359 return ((val) << MDP4_OVLP_STAGE_OP_FG_ALPHA__SHIFT) & MDP4_OVLP_STAGE_OP_FG_ALPHA__MASK; MDP4_OVLP_STAGE_OP_FG_ALPHA()
365 static inline uint32_t MDP4_OVLP_STAGE_OP_BG_ALPHA(enum mdp_alpha_type val) MDP4_OVLP_STAGE_OP_BG_ALPHA() argument
367 return ((val) << MDP4_OVLP_STAGE_OP_BG_ALPHA__SHIFT) & MDP4_OVLP_STAGE_OP_BG_ALPHA__MASK; MDP4_OVLP_STAGE_OP_BG_ALPHA()
460 static inline uint32_t MDP4_DMA_CONFIG_G_BPC(enum mdp_bpc val) MDP4_DMA_CONFIG_G_BPC() argument
462 return ((val) << MDP4_DMA_CONFIG_G_BPC__SHIFT) & MDP4_DMA_CONFIG_G_BPC__MASK; MDP4_DMA_CONFIG_G_BPC()
466 static inline uint32_t MDP4_DMA_CONFIG_B_BPC(enum mdp_bpc val) MDP4_DMA_CONFIG_B_BPC() argument
468 return ((val) << MDP4_DMA_CONFIG_B_BPC__SHIFT) & MDP4_DMA_CONFIG_B_BPC__MASK; MDP4_DMA_CONFIG_B_BPC()
472 static inline uint32_t MDP4_DMA_CONFIG_R_BPC(enum mdp_bpc val) MDP4_DMA_CONFIG_R_BPC() argument
474 return ((val) << MDP4_DMA_CONFIG_R_BPC__SHIFT) & MDP4_DMA_CONFIG_R_BPC__MASK; MDP4_DMA_CONFIG_R_BPC()
479 static inline uint32_t MDP4_DMA_CONFIG_PACK(uint32_t val) MDP4_DMA_CONFIG_PACK() argument
481 return ((val) << MDP4_DMA_CONFIG_PACK__SHIFT) & MDP4_DMA_CONFIG_PACK__MASK; MDP4_DMA_CONFIG_PACK()
489 static inline uint32_t MDP4_DMA_SRC_SIZE_HEIGHT(uint32_t val) MDP4_DMA_SRC_SIZE_HEIGHT() argument
491 return ((val) << MDP4_DMA_SRC_SIZE_HEIGHT__SHIFT) & MDP4_DMA_SRC_SIZE_HEIGHT__MASK; MDP4_DMA_SRC_SIZE_HEIGHT()
495 static inline uint32_t MDP4_DMA_SRC_SIZE_WIDTH(uint32_t val) MDP4_DMA_SRC_SIZE_WIDTH() argument
497 return ((val) << MDP4_DMA_SRC_SIZE_WIDTH__SHIFT) & MDP4_DMA_SRC_SIZE_WIDTH__MASK; MDP4_DMA_SRC_SIZE_WIDTH()
507 static inline uint32_t MDP4_DMA_DST_SIZE_HEIGHT(uint32_t val) MDP4_DMA_DST_SIZE_HEIGHT() argument
509 return ((val) << MDP4_DMA_DST_SIZE_HEIGHT__SHIFT) & MDP4_DMA_DST_SIZE_HEIGHT__MASK; MDP4_DMA_DST_SIZE_HEIGHT()
513 static inline uint32_t MDP4_DMA_DST_SIZE_WIDTH(uint32_t val) MDP4_DMA_DST_SIZE_WIDTH() argument
515 return ((val) << MDP4_DMA_DST_SIZE_WIDTH__SHIFT) & MDP4_DMA_DST_SIZE_WIDTH__MASK; MDP4_DMA_DST_SIZE_WIDTH()
521 static inline uint32_t MDP4_DMA_CURSOR_SIZE_WIDTH(uint32_t val) MDP4_DMA_CURSOR_SIZE_WIDTH() argument
523 return ((val) << MDP4_DMA_CURSOR_SIZE_WIDTH__SHIFT) & MDP4_DMA_CURSOR_SIZE_WIDTH__MASK; MDP4_DMA_CURSOR_SIZE_WIDTH()
527 static inline uint32_t MDP4_DMA_CURSOR_SIZE_HEIGHT(uint32_t val) MDP4_DMA_CURSOR_SIZE_HEIGHT() argument
529 return ((val) << MDP4_DMA_CURSOR_SIZE_HEIGHT__SHIFT) & MDP4_DMA_CURSOR_SIZE_HEIGHT__MASK; MDP4_DMA_CURSOR_SIZE_HEIGHT()
537 static inline uint32_t MDP4_DMA_CURSOR_POS_X(uint32_t val) MDP4_DMA_CURSOR_POS_X() argument
539 return ((val) << MDP4_DMA_CURSOR_POS_X__SHIFT) & MDP4_DMA_CURSOR_POS_X__MASK; MDP4_DMA_CURSOR_POS_X()
543 static inline uint32_t MDP4_DMA_CURSOR_POS_Y(uint32_t val) MDP4_DMA_CURSOR_POS_Y() argument
545 return ((val) << MDP4_DMA_CURSOR_POS_Y__SHIFT) & MDP4_DMA_CURSOR_POS_Y__MASK; MDP4_DMA_CURSOR_POS_Y()
552 static inline uint32_t MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT(enum mdp4_cursor_format val) MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT() argument
554 return ((val) << MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__SHIFT) & MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__MASK; MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT()
594 static inline uint32_t MDP4_PIPE_SRC_SIZE_HEIGHT(uint32_t val) MDP4_PIPE_SRC_SIZE_HEIGHT() argument
596 return ((val) << MDP4_PIPE_SRC_SIZE_HEIGHT__SHIFT) & MDP4_PIPE_SRC_SIZE_HEIGHT__MASK; MDP4_PIPE_SRC_SIZE_HEIGHT()
600 static inline uint32_t MDP4_PIPE_SRC_SIZE_WIDTH(uint32_t val) MDP4_PIPE_SRC_SIZE_WIDTH() argument
602 return ((val) << MDP4_PIPE_SRC_SIZE_WIDTH__SHIFT) & MDP4_PIPE_SRC_SIZE_WIDTH__MASK; MDP4_PIPE_SRC_SIZE_WIDTH()
608 static inline uint32_t MDP4_PIPE_SRC_XY_Y(uint32_t val) MDP4_PIPE_SRC_XY_Y() argument
610 return ((val) << MDP4_PIPE_SRC_XY_Y__SHIFT) & MDP4_PIPE_SRC_XY_Y__MASK; MDP4_PIPE_SRC_XY_Y()
614 static inline uint32_t MDP4_PIPE_SRC_XY_X(uint32_t val) MDP4_PIPE_SRC_XY_X() argument
616 return ((val) << MDP4_PIPE_SRC_XY_X__SHIFT) & MDP4_PIPE_SRC_XY_X__MASK; MDP4_PIPE_SRC_XY_X()
622 static inline uint32_t MDP4_PIPE_DST_SIZE_HEIGHT(uint32_t val) MDP4_PIPE_DST_SIZE_HEIGHT() argument
624 return ((val) << MDP4_PIPE_DST_SIZE_HEIGHT__SHIFT) & MDP4_PIPE_DST_SIZE_HEIGHT__MASK; MDP4_PIPE_DST_SIZE_HEIGHT()
628 static inline uint32_t MDP4_PIPE_DST_SIZE_WIDTH(uint32_t val) MDP4_PIPE_DST_SIZE_WIDTH() argument
630 return ((val) << MDP4_PIPE_DST_SIZE_WIDTH__SHIFT) & MDP4_PIPE_DST_SIZE_WIDTH__MASK; MDP4_PIPE_DST_SIZE_WIDTH()
636 static inline uint32_t MDP4_PIPE_DST_XY_Y(uint32_t val) MDP4_PIPE_DST_XY_Y() argument
638 return ((val) << MDP4_PIPE_DST_XY_Y__SHIFT) & MDP4_PIPE_DST_XY_Y__MASK; MDP4_PIPE_DST_XY_Y()
642 static inline uint32_t MDP4_PIPE_DST_XY_X(uint32_t val) MDP4_PIPE_DST_XY_X() argument
644 return ((val) << MDP4_PIPE_DST_XY_X__SHIFT) & MDP4_PIPE_DST_XY_X__MASK; MDP4_PIPE_DST_XY_X()
658 static inline uint32_t MDP4_PIPE_SRC_STRIDE_A_P0(uint32_t val) MDP4_PIPE_SRC_STRIDE_A_P0() argument
660 return ((val) << MDP4_PIPE_SRC_STRIDE_A_P0__SHIFT) & MDP4_PIPE_SRC_STRIDE_A_P0__MASK; MDP4_PIPE_SRC_STRIDE_A_P0()
664 static inline uint32_t MDP4_PIPE_SRC_STRIDE_A_P1(uint32_t val) MDP4_PIPE_SRC_STRIDE_A_P1() argument
666 return ((val) << MDP4_PIPE_SRC_STRIDE_A_P1__SHIFT) & MDP4_PIPE_SRC_STRIDE_A_P1__MASK; MDP4_PIPE_SRC_STRIDE_A_P1()
672 static inline uint32_t MDP4_PIPE_SRC_STRIDE_B_P2(uint32_t val) MDP4_PIPE_SRC_STRIDE_B_P2() argument
674 return ((val) << MDP4_PIPE_SRC_STRIDE_B_P2__SHIFT) & MDP4_PIPE_SRC_STRIDE_B_P2__MASK; MDP4_PIPE_SRC_STRIDE_B_P2()
678 static inline uint32_t MDP4_PIPE_SRC_STRIDE_B_P3(uint32_t val) MDP4_PIPE_SRC_STRIDE_B_P3() argument
680 return ((val) << MDP4_PIPE_SRC_STRIDE_B_P3__SHIFT) & MDP4_PIPE_SRC_STRIDE_B_P3__MASK; MDP4_PIPE_SRC_STRIDE_B_P3()
686 static inline uint32_t MDP4_PIPE_FRAME_SIZE_HEIGHT(uint32_t val) MDP4_PIPE_FRAME_SIZE_HEIGHT() argument
688 return ((val) << MDP4_PIPE_FRAME_SIZE_HEIGHT__SHIFT) & MDP4_PIPE_FRAME_SIZE_HEIGHT__MASK; MDP4_PIPE_FRAME_SIZE_HEIGHT()
692 static inline uint32_t MDP4_PIPE_FRAME_SIZE_WIDTH(uint32_t val) MDP4_PIPE_FRAME_SIZE_WIDTH() argument
694 return ((val) << MDP4_PIPE_FRAME_SIZE_WIDTH__SHIFT) & MDP4_PIPE_FRAME_SIZE_WIDTH__MASK; MDP4_PIPE_FRAME_SIZE_WIDTH()
700 static inline uint32_t MDP4_PIPE_SRC_FORMAT_G_BPC(enum mdp_bpc val) MDP4_PIPE_SRC_FORMAT_G_BPC() argument
702 return ((val) << MDP4_PIPE_SRC_FORMAT_G_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_G_BPC__MASK; MDP4_PIPE_SRC_FORMAT_G_BPC()
706 static inline uint32_t MDP4_PIPE_SRC_FORMAT_B_BPC(enum mdp_bpc val) MDP4_PIPE_SRC_FORMAT_B_BPC() argument
708 return ((val) << MDP4_PIPE_SRC_FORMAT_B_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_B_BPC__MASK; MDP4_PIPE_SRC_FORMAT_B_BPC()
712 static inline uint32_t MDP4_PIPE_SRC_FORMAT_R_BPC(enum mdp_bpc val) MDP4_PIPE_SRC_FORMAT_R_BPC() argument
714 return ((val) << MDP4_PIPE_SRC_FORMAT_R_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_R_BPC__MASK; MDP4_PIPE_SRC_FORMAT_R_BPC()
718 static inline uint32_t MDP4_PIPE_SRC_FORMAT_A_BPC(enum mdp_bpc_alpha val) MDP4_PIPE_SRC_FORMAT_A_BPC() argument
720 return ((val) << MDP4_PIPE_SRC_FORMAT_A_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_A_BPC__MASK; MDP4_PIPE_SRC_FORMAT_A_BPC()
725 static inline uint32_t MDP4_PIPE_SRC_FORMAT_CPP(uint32_t val) MDP4_PIPE_SRC_FORMAT_CPP() argument
727 return ((val) << MDP4_PIPE_SRC_FORMAT_CPP__SHIFT) & MDP4_PIPE_SRC_FORMAT_CPP__MASK; MDP4_PIPE_SRC_FORMAT_CPP()
732 static inline uint32_t MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT(uint32_t val) MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT() argument
734 return ((val) << MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT) & MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK; MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT()
740 static inline uint32_t MDP4_PIPE_SRC_FORMAT_FETCH_PLANES(uint32_t val) MDP4_PIPE_SRC_FORMAT_FETCH_PLANES() argument
742 return ((val) << MDP4_PIPE_SRC_FORMAT_FETCH_PLANES__SHIFT) & MDP4_PIPE_SRC_FORMAT_FETCH_PLANES__MASK; MDP4_PIPE_SRC_FORMAT_FETCH_PLANES()
747 static inline uint32_t MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP(enum mdp_chroma_samp_type val) MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP() argument
749 return ((val) << MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT) & MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK; MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP()
753 static inline uint32_t MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT(enum mdp4_frame_format val) MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT() argument
755 return ((val) << MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT__SHIFT) & MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT__MASK; MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT()
761 static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM0(uint32_t val) MDP4_PIPE_SRC_UNPACK_ELEM0() argument
763 return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM0__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM0__MASK; MDP4_PIPE_SRC_UNPACK_ELEM0()
767 static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM1(uint32_t val) MDP4_PIPE_SRC_UNPACK_ELEM1() argument
769 return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM1__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM1__MASK; MDP4_PIPE_SRC_UNPACK_ELEM1()
773 static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM2(uint32_t val) MDP4_PIPE_SRC_UNPACK_ELEM2() argument
775 return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM2__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM2__MASK; MDP4_PIPE_SRC_UNPACK_ELEM2()
779 static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM3(uint32_t val) MDP4_PIPE_SRC_UNPACK_ELEM3() argument
781 return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM3__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM3__MASK; MDP4_PIPE_SRC_UNPACK_ELEM3()
789 static inline uint32_t MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL(enum mdp4_scale_unit val) MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL() argument
791 return ((val) << MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL__SHIFT) & MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL__MASK; MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL()
795 static inline uint32_t MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL(enum mdp4_scale_unit val) MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL() argument
797 return ((val) << MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL__SHIFT) & MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL__MASK; MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL()
847 static inline uint32_t MDP4_LCDC_HSYNC_CTRL_PULSEW(uint32_t val) MDP4_LCDC_HSYNC_CTRL_PULSEW() argument
849 return ((val) << MDP4_LCDC_HSYNC_CTRL_PULSEW__SHIFT) & MDP4_LCDC_HSYNC_CTRL_PULSEW__MASK; MDP4_LCDC_HSYNC_CTRL_PULSEW()
853 static inline uint32_t MDP4_LCDC_HSYNC_CTRL_PERIOD(uint32_t val) MDP4_LCDC_HSYNC_CTRL_PERIOD() argument
855 return ((val) << MDP4_LCDC_HSYNC_CTRL_PERIOD__SHIFT) & MDP4_LCDC_HSYNC_CTRL_PERIOD__MASK; MDP4_LCDC_HSYNC_CTRL_PERIOD()
865 static inline uint32_t MDP4_LCDC_DISPLAY_HCTRL_START(uint32_t val) MDP4_LCDC_DISPLAY_HCTRL_START() argument
867 return ((val) << MDP4_LCDC_DISPLAY_HCTRL_START__SHIFT) & MDP4_LCDC_DISPLAY_HCTRL_START__MASK; MDP4_LCDC_DISPLAY_HCTRL_START()
871 static inline uint32_t MDP4_LCDC_DISPLAY_HCTRL_END(uint32_t val) MDP4_LCDC_DISPLAY_HCTRL_END() argument
873 return ((val) << MDP4_LCDC_DISPLAY_HCTRL_END__SHIFT) & MDP4_LCDC_DISPLAY_HCTRL_END__MASK; MDP4_LCDC_DISPLAY_HCTRL_END()
883 static inline uint32_t MDP4_LCDC_ACTIVE_HCTL_START(uint32_t val) MDP4_LCDC_ACTIVE_HCTL_START() argument
885 return ((val) << MDP4_LCDC_ACTIVE_HCTL_START__SHIFT) & MDP4_LCDC_ACTIVE_HCTL_START__MASK; MDP4_LCDC_ACTIVE_HCTL_START()
889 static inline uint32_t MDP4_LCDC_ACTIVE_HCTL_END(uint32_t val) MDP4_LCDC_ACTIVE_HCTL_END() argument
891 return ((val) << MDP4_LCDC_ACTIVE_HCTL_END__SHIFT) & MDP4_LCDC_ACTIVE_HCTL_END__MASK; MDP4_LCDC_ACTIVE_HCTL_END()
904 static inline uint32_t MDP4_LCDC_UNDERFLOW_CLR_COLOR(uint32_t val) MDP4_LCDC_UNDERFLOW_CLR_COLOR() argument
906 return ((val) << MDP4_LCDC_UNDERFLOW_CLR_COLOR__SHIFT) & MDP4_LCDC_UNDERFLOW_CLR_COLOR__MASK; MDP4_LCDC_UNDERFLOW_CLR_COLOR()
942 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0(uint32_t val) MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0() argument
944 return ((val) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0__MASK; MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0()
948 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1(uint32_t val) MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1() argument
950 return ((val) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1__MASK; MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1()
954 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2(uint32_t val) MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2() argument
956 return ((val) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2__MASK; MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2()
960 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3(uint32_t val) MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3() argument
962 return ((val) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3__MASK; MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3()
968 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4(uint32_t val) MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4() argument
970 return ((val) << MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4__MASK; MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4()
974 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5(uint32_t val) MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5() argument
976 return ((val) << MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5__MASK; MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5()
980 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6(uint32_t val) MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6() argument
982 return ((val) << MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6__MASK; MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6()
1021 static inline uint32_t MDP4_DTV_HSYNC_CTRL_PULSEW(uint32_t val) MDP4_DTV_HSYNC_CTRL_PULSEW() argument
1023 return ((val) << MDP4_DTV_HSYNC_CTRL_PULSEW__SHIFT) & MDP4_DTV_HSYNC_CTRL_PULSEW__MASK; MDP4_DTV_HSYNC_CTRL_PULSEW()
1027 static inline uint32_t MDP4_DTV_HSYNC_CTRL_PERIOD(uint32_t val) MDP4_DTV_HSYNC_CTRL_PERIOD() argument
1029 return ((val) << MDP4_DTV_HSYNC_CTRL_PERIOD__SHIFT) & MDP4_DTV_HSYNC_CTRL_PERIOD__MASK; MDP4_DTV_HSYNC_CTRL_PERIOD()
1039 static inline uint32_t MDP4_DTV_DISPLAY_HCTRL_START(uint32_t val) MDP4_DTV_DISPLAY_HCTRL_START() argument
1041 return ((val) << MDP4_DTV_DISPLAY_HCTRL_START__SHIFT) & MDP4_DTV_DISPLAY_HCTRL_START__MASK; MDP4_DTV_DISPLAY_HCTRL_START()
1045 static inline uint32_t MDP4_DTV_DISPLAY_HCTRL_END(uint32_t val) MDP4_DTV_DISPLAY_HCTRL_END() argument
1047 return ((val) << MDP4_DTV_DISPLAY_HCTRL_END__SHIFT) & MDP4_DTV_DISPLAY_HCTRL_END__MASK; MDP4_DTV_DISPLAY_HCTRL_END()
1057 static inline uint32_t MDP4_DTV_ACTIVE_HCTL_START(uint32_t val) MDP4_DTV_ACTIVE_HCTL_START() argument
1059 return ((val) << MDP4_DTV_ACTIVE_HCTL_START__SHIFT) & MDP4_DTV_ACTIVE_HCTL_START__MASK; MDP4_DTV_ACTIVE_HCTL_START()
1063 static inline uint32_t MDP4_DTV_ACTIVE_HCTL_END(uint32_t val) MDP4_DTV_ACTIVE_HCTL_END() argument
1065 return ((val) << MDP4_DTV_ACTIVE_HCTL_END__SHIFT) & MDP4_DTV_ACTIVE_HCTL_END__MASK; MDP4_DTV_ACTIVE_HCTL_END()
1078 static inline uint32_t MDP4_DTV_UNDERFLOW_CLR_COLOR(uint32_t val) MDP4_DTV_UNDERFLOW_CLR_COLOR() argument
1080 return ((val) << MDP4_DTV_UNDERFLOW_CLR_COLOR__SHIFT) & MDP4_DTV_UNDERFLOW_CLR_COLOR__MASK; MDP4_DTV_UNDERFLOW_CLR_COLOR()
1100 static inline uint32_t MDP4_DSI_HSYNC_CTRL_PULSEW(uint32_t val) MDP4_DSI_HSYNC_CTRL_PULSEW() argument
1102 return ((val) << MDP4_DSI_HSYNC_CTRL_PULSEW__SHIFT) & MDP4_DSI_HSYNC_CTRL_PULSEW__MASK; MDP4_DSI_HSYNC_CTRL_PULSEW()
1106 static inline uint32_t MDP4_DSI_HSYNC_CTRL_PERIOD(uint32_t val) MDP4_DSI_HSYNC_CTRL_PERIOD() argument
1108 return ((val) << MDP4_DSI_HSYNC_CTRL_PERIOD__SHIFT) & MDP4_DSI_HSYNC_CTRL_PERIOD__MASK; MDP4_DSI_HSYNC_CTRL_PERIOD()
1118 static inline uint32_t MDP4_DSI_DISPLAY_HCTRL_START(uint32_t val) MDP4_DSI_DISPLAY_HCTRL_START() argument
1120 return ((val) << MDP4_DSI_DISPLAY_HCTRL_START__SHIFT) & MDP4_DSI_DISPLAY_HCTRL_START__MASK; MDP4_DSI_DISPLAY_HCTRL_START()
1124 static inline uint32_t MDP4_DSI_DISPLAY_HCTRL_END(uint32_t val) MDP4_DSI_DISPLAY_HCTRL_END() argument
1126 return ((val) << MDP4_DSI_DISPLAY_HCTRL_END__SHIFT) & MDP4_DSI_DISPLAY_HCTRL_END__MASK; MDP4_DSI_DISPLAY_HCTRL_END()
1136 static inline uint32_t MDP4_DSI_ACTIVE_HCTL_START(uint32_t val) MDP4_DSI_ACTIVE_HCTL_START() argument
1138 return ((val) << MDP4_DSI_ACTIVE_HCTL_START__SHIFT) & MDP4_DSI_ACTIVE_HCTL_START__MASK; MDP4_DSI_ACTIVE_HCTL_START()
1142 static inline uint32_t MDP4_DSI_ACTIVE_HCTL_END(uint32_t val) MDP4_DSI_ACTIVE_HCTL_END() argument
1144 return ((val) << MDP4_DSI_ACTIVE_HCTL_END__SHIFT) & MDP4_DSI_ACTIVE_HCTL_END__MASK; MDP4_DSI_ACTIVE_HCTL_END()
1157 static inline uint32_t MDP4_DSI_UNDERFLOW_CLR_COLOR(uint32_t val) MDP4_DSI_UNDERFLOW_CLR_COLOR() argument
1159 return ((val) << MDP4_DSI_UNDERFLOW_CLR_COLOR__SHIFT) & MDP4_DSI_UNDERFLOW_CLR_COLOR__MASK; MDP4_DSI_UNDERFLOW_CLR_COLOR()
/linux-4.1.27/drivers/gpu/drm/sti/
H A Dsti_awg_utils.c121 long int val; sti_awg_generate_code_data_enable_mode() local
127 val = timing->blanking_level; sti_awg_generate_code_data_enable_mode()
129 ret |= awg_generate_instr(RPLSET, val, 0, data_en, fwparams); sti_awg_generate_code_data_enable_mode()
131 val = timing->trailing_lines - 1; sti_awg_generate_code_data_enable_mode()
133 ret |= awg_generate_instr(REPLAY, val, 0, data_en, fwparams); sti_awg_generate_code_data_enable_mode()
138 val = timing->blanking_level; sti_awg_generate_code_data_enable_mode()
140 ret |= awg_generate_instr(RPLSET, val, 0, data_en, fwparams); sti_awg_generate_code_data_enable_mode()
142 val = timing->trailing_pixels - 1; sti_awg_generate_code_data_enable_mode()
144 ret |= awg_generate_instr(SKIP, val, 0, data_en, fwparams); sti_awg_generate_code_data_enable_mode()
148 val = timing->blanking_level; sti_awg_generate_code_data_enable_mode()
151 val, 0, data_en, fwparams); sti_awg_generate_code_data_enable_mode()
155 val = timing->active_pixels - 1; sti_awg_generate_code_data_enable_mode()
157 ret |= awg_generate_instr(SKIP, val, 0, data_en, fwparams); sti_awg_generate_code_data_enable_mode()
160 val = timing->blanking_level; sti_awg_generate_code_data_enable_mode()
162 ret |= awg_generate_instr(SET, val, 0, data_en, fwparams); sti_awg_generate_code_data_enable_mode()
166 val = timing->active_lines - 1; sti_awg_generate_code_data_enable_mode()
168 ret |= awg_generate_instr(REPLAY, val, 0, data_en, fwparams); sti_awg_generate_code_data_enable_mode()
172 val = timing->blanking_level; sti_awg_generate_code_data_enable_mode()
174 ret |= awg_generate_instr(RPLSET, val, 0, data_en, fwparams); sti_awg_generate_code_data_enable_mode()
176 val = timing->blanking_lines - 1; sti_awg_generate_code_data_enable_mode()
178 ret |= awg_generate_instr(REPLAY, val, 0, data_en, fwparams); sti_awg_generate_code_data_enable_mode()
/linux-4.1.27/arch/m68k/atari/
H A Dtime.c63 static void mste_read(struct MSTE_RTC *val) mste_read() argument
65 #define COPY(v) val->v=(mste_rtc.v & 0xf) mste_read()
73 } while (val->sec_ones != (mste_rtc.sec_ones & 0xf)); mste_read()
77 static void mste_write(struct MSTE_RTC *val) mste_write() argument
79 #define COPY(v) mste_rtc.v=val->v mste_write()
87 } while (val->sec_ones != (mste_rtc.sec_ones & 0xf)); mste_write()
98 #define RTC_WRITE(reg,val) \
101 tt_rtc.data = (val); \
111 struct MSTE_RTC val; atari_mste_hwclk() local
120 val.sec_ones = t->tm_sec % 10; atari_mste_hwclk()
121 val.sec_tens = t->tm_sec / 10; atari_mste_hwclk()
122 val.min_ones = t->tm_min % 10; atari_mste_hwclk()
123 val.min_tens = t->tm_min / 10; atari_mste_hwclk()
131 val.hr_ones = hour % 10; atari_mste_hwclk()
132 val.hr_tens = hour / 10; atari_mste_hwclk()
133 val.day_ones = t->tm_mday % 10; atari_mste_hwclk()
134 val.day_tens = t->tm_mday / 10; atari_mste_hwclk()
135 val.mon_ones = (t->tm_mon+1) % 10; atari_mste_hwclk()
136 val.mon_tens = (t->tm_mon+1) / 10; atari_mste_hwclk()
138 val.year_ones = year % 10; atari_mste_hwclk()
139 val.year_tens = year / 10; atari_mste_hwclk()
140 val.weekday = t->tm_wday; atari_mste_hwclk()
141 mste_write(&val); atari_mste_hwclk()
143 val.year_ones = (year % 4); /* leap year register */ atari_mste_hwclk()
147 mste_read(&val); atari_mste_hwclk()
148 t->tm_sec = val.sec_ones + val.sec_tens * 10; atari_mste_hwclk()
149 t->tm_min = val.min_ones + val.min_tens * 10; atari_mste_hwclk()
150 hour = val.hr_ones + val.hr_tens * 10; atari_mste_hwclk()
158 t->tm_mday = val.day_ones + val.day_tens * 10; atari_mste_hwclk()
159 t->tm_mon = val.mon_ones + val.mon_tens * 10 - 1; atari_mste_hwclk()
160 t->tm_year = val.year_ones + val.year_tens * 10 + 80; atari_mste_hwclk()
161 t->tm_wday = val.weekday; atari_mste_hwclk()
292 struct MSTE_RTC val; atari_mste_set_clock_mmss() local
295 mste_read(&val); atari_mste_set_clock_mmss()
296 rtc_minutes= val.min_ones + val.min_tens * 10; atari_mste_set_clock_mmss()
301 val.sec_ones = real_seconds % 10; atari_mste_set_clock_mmss()
302 val.sec_tens = real_seconds / 10; atari_mste_set_clock_mmss()
303 val.min_ones = real_minutes % 10; atari_mste_set_clock_mmss()
304 val.min_tens = real_minutes / 10; atari_mste_set_clock_mmss()
305 mste_write(&val); atari_mste_set_clock_mmss()
/linux-4.1.27/sound/pcmcia/pdaudiocf/
H A Dpdaudiocf_core.c63 static void pdacf_ak4117_write(void *private_data, unsigned char reg, unsigned char val) pdacf_ak4117_write() argument
79 outw((u16)reg << 8 | val | (1<<13), chip->port + PDAUDIOCF_REG_AK_IFR); pdacf_ak4117_write()
106 u16 val; pdacf_reset() local
108 val = pdacf_reg_read(chip, PDAUDIOCF_REG_SCR); pdacf_reset()
109 val |= PDAUDIOCF_PDN; pdacf_reset()
110 val &= ~PDAUDIOCF_RECORD; /* for sure */ pdacf_reset()
111 pdacf_reg_write(chip, PDAUDIOCF_REG_SCR, val); pdacf_reset()
113 val |= PDAUDIOCF_RST; pdacf_reset()
114 pdacf_reg_write(chip, PDAUDIOCF_REG_SCR, val); pdacf_reset()
116 val &= ~PDAUDIOCF_RST; pdacf_reset()
117 pdacf_reg_write(chip, PDAUDIOCF_REG_SCR, val); pdacf_reset()
120 val &= ~PDAUDIOCF_PDN; pdacf_reset()
121 pdacf_reg_write(chip, PDAUDIOCF_REG_SCR, val); pdacf_reset()
176 u16 val; snd_pdacf_ak4117_change() local
181 val = chip->regmap[PDAUDIOCF_REG_SCR>>1]; snd_pdacf_ak4117_change()
183 val |= PDAUDIOCF_BLUE_LED_OFF; snd_pdacf_ak4117_change()
185 val &= ~PDAUDIOCF_BLUE_LED_OFF; snd_pdacf_ak4117_change()
186 pdacf_reg_write(chip, PDAUDIOCF_REG_SCR, val); snd_pdacf_ak4117_change()
193 u16 val; snd_pdacf_ak4117_create() local
213 val = pdacf_reg_read(chip, PDAUDIOCF_REG_TCR); snd_pdacf_ak4117_create()
215 val &= ~(PDAUDIOCF_ELIMAKMBIT|PDAUDIOCF_TESTDATASEL); snd_pdacf_ak4117_create()
217 val |= PDAUDIOCF_ELIMAKMBIT; snd_pdacf_ak4117_create()
218 val &= ~PDAUDIOCF_TESTDATASEL; snd_pdacf_ak4117_create()
220 pdacf_reg_write(chip, PDAUDIOCF_REG_TCR, val); snd_pdacf_ak4117_create()
223 val = pdacf_reg_read(chip, PDAUDIOCF_REG_SCR); snd_pdacf_ak4117_create()
224 val &= ~(PDAUDIOCF_CLKDIV0 | PDAUDIOCF_CLKDIV1); /* use 24.576Mhz clock */ snd_pdacf_ak4117_create()
225 val &= ~(PDAUDIOCF_RED_LED_OFF|PDAUDIOCF_BLUE_LED_OFF); snd_pdacf_ak4117_create()
226 val |= PDAUDIOCF_DATAFMT0 | PDAUDIOCF_DATAFMT1; /* 24-bit data */ snd_pdacf_ak4117_create()
227 pdacf_reg_write(chip, PDAUDIOCF_REG_SCR, val); snd_pdacf_ak4117_create()
230 val = pdacf_reg_read(chip, PDAUDIOCF_REG_IER); snd_pdacf_ak4117_create()
231 val &= ~(PDAUDIOCF_IRQLVLEN0 | PDAUDIOCF_IRQLVLEN1); snd_pdacf_ak4117_create()
232 val &= ~(PDAUDIOCF_BLUEDUTY0 | PDAUDIOCF_REDDUTY0 | PDAUDIOCF_REDDUTY1); snd_pdacf_ak4117_create()
233 val |= PDAUDIOCF_BLUEDUTY1 | PDAUDIOCF_HALFRATE; snd_pdacf_ak4117_create()
234 val |= PDAUDIOCF_IRQOVREN | PDAUDIOCF_IRQAKMEN; snd_pdacf_ak4117_create()
235 pdacf_reg_write(chip, PDAUDIOCF_REG_IER, val); snd_pdacf_ak4117_create()
248 u16 val; snd_pdacf_powerdown() local
250 val = pdacf_reg_read(chip, PDAUDIOCF_REG_SCR); snd_pdacf_powerdown()
251 chip->suspend_reg_scr = val; snd_pdacf_powerdown()
252 val |= PDAUDIOCF_RED_LED_OFF | PDAUDIOCF_BLUE_LED_OFF; snd_pdacf_powerdown()
253 pdacf_reg_write(chip, PDAUDIOCF_REG_SCR, val); snd_pdacf_powerdown()
255 val = inw(chip->port + PDAUDIOCF_REG_IER); snd_pdacf_powerdown()
256 val &= ~(PDAUDIOCF_IRQOVREN|PDAUDIOCF_IRQAKMEN|PDAUDIOCF_IRQLVLEN0|PDAUDIOCF_IRQLVLEN1); snd_pdacf_powerdown()
257 outw(val, chip->port + PDAUDIOCF_REG_IER); snd_pdacf_powerdown()
265 u16 val; snd_pdacf_suspend() local
270 val = inw(chip->port + PDAUDIOCF_REG_IER); snd_pdacf_suspend()
271 val &= ~(PDAUDIOCF_IRQOVREN|PDAUDIOCF_IRQAKMEN|PDAUDIOCF_IRQLVLEN0|PDAUDIOCF_IRQLVLEN1); snd_pdacf_suspend()
272 outw(val, chip->port + PDAUDIOCF_REG_IER); snd_pdacf_suspend()
/linux-4.1.27/arch/powerpc/include/asm/
H A Dfeature-fixups.h40 #define MAKE_FTR_SECTION_ENTRY(msk, val, label, sect) \
47 FTR_ENTRY_LONG val; \
62 #define END_FTR_SECTION_NESTED(msk, val, label) \
64 MAKE_FTR_SECTION_ENTRY(msk, val, label, __ftr_fixup)
66 #define END_FTR_SECTION(msk, val) \
67 END_FTR_SECTION_NESTED(msk, val, 97)
74 #define ALT_FTR_SECTION_END_NESTED(msk, val, label) \
75 MAKE_FTR_SECTION_ENTRY(msk, val, label, __ftr_fixup)
80 #define ALT_FTR_SECTION_END(msk, val) \
81 ALT_FTR_SECTION_END_NESTED(msk, val, 97)
91 #define END_MMU_FTR_SECTION_NESTED(msk, val, label) \
93 MAKE_FTR_SECTION_ENTRY(msk, val, label, __mmu_ftr_fixup)
95 #define END_MMU_FTR_SECTION(msk, val) \
96 END_MMU_FTR_SECTION_NESTED(msk, val, 97)
104 #define ALT_MMU_FTR_SECTION_END_NESTED(msk, val, label) \
105 MAKE_FTR_SECTION_ENTRY(msk, val, label, __mmu_ftr_fixup)
110 #define ALT_MMU_FTR_SECTION_END(msk, val) \
111 ALT_MMU_FTR_SECTION_END_NESTED(msk, val, 97)
121 #define END_FW_FTR_SECTION_NESTED(msk, val, label) \
123 MAKE_FTR_SECTION_ENTRY(msk, val, label, __fw_ftr_fixup)
125 #define END_FW_FTR_SECTION(msk, val) \
126 END_FW_FTR_SECTION_NESTED(msk, val, 97)
134 #define ALT_FW_FTR_SECTION_END_NESTED(msk, val, label) \
135 MAKE_FTR_SECTION_ENTRY(msk, val, label, __fw_ftr_fixup)
140 #define ALT_FW_FTR_SECTION_END(msk, val) \
141 ALT_FW_FTR_SECTION_END_NESTED(msk, val, 97)
149 #define ASM_FTR_IF(section_if, section_else, msk, val) \
154 stringify_in_c(ALT_FTR_SECTION_END((msk), (val)))
162 #define ASM_MMU_FTR_IF(section_if, section_else, msk, val) \
167 stringify_in_c(ALT_MMU_FTR_SECTION_END((msk), (val)))
/linux-4.1.27/arch/arm/mach-hisi/
H A Dhotplug.c81 u32 val = 0; set_cpu_hi3620() local
94 val = CPU0_DBG_SRST_REQ_EN | CPU0_NEON_SRST_REQ_EN set_cpu_hi3620()
96 writel_relaxed(val << cpu, ctrl_base + SCCPURSTDIS); set_cpu_hi3620()
98 val |= CPU0_HPM_SRST_REQ_EN; set_cpu_hi3620()
99 writel_relaxed(val << cpu, ctrl_base + SCCPURSTEN); set_cpu_hi3620()
108 val = readl_relaxed(ctrl_base + SCPERCTRL0); set_cpu_hi3620()
109 val &= ~(CPU0_WFI_MASK_CFG << cpu); set_cpu_hi3620()
110 writel_relaxed(val, ctrl_base + SCPERCTRL0); set_cpu_hi3620()
113 val = CPU0_DBG_SRST_REQ_EN | CPU0_NEON_SRST_REQ_EN set_cpu_hi3620()
115 writel_relaxed(val << cpu, ctrl_base + SCCPURSTDIS); set_cpu_hi3620()
118 val = readl_relaxed(ctrl_base + SCPERCTRL0); set_cpu_hi3620()
119 val |= (CPU0_WFI_MASK_CFG << cpu); set_cpu_hi3620()
120 writel_relaxed(val, ctrl_base + SCPERCTRL0); set_cpu_hi3620()
133 val = CPU0_DBG_SRST_REQ_EN | CPU0_NEON_SRST_REQ_EN set_cpu_hi3620()
135 writel_relaxed(val << cpu, ctrl_base + SCCPURSTEN); set_cpu_hi3620()
185 u32 val = 0; hix5hd2_set_cpu() local
193 val = readl_relaxed(ctrl_base + HIX5HD2_PERI_PMC0); hix5hd2_set_cpu()
194 val &= ~(PMC0_CPU1_WAIT_MTCOMS_ACK | PMC0_CPU1_POWERDOWN); hix5hd2_set_cpu()
195 val |= PMC0_CPU1_PMC_ENABLE; hix5hd2_set_cpu()
196 writel_relaxed(val, ctrl_base + HIX5HD2_PERI_PMC0); hix5hd2_set_cpu()
198 val = readl_relaxed(ctrl_base + HIX5HD2_PERI_CRG20); hix5hd2_set_cpu()
199 val &= ~CRG20_CPU1_RESET; hix5hd2_set_cpu()
200 writel_relaxed(val, ctrl_base + HIX5HD2_PERI_CRG20); hix5hd2_set_cpu()
203 val = readl_relaxed(ctrl_base + HIX5HD2_PERI_PMC0); hix5hd2_set_cpu()
204 val |= PMC0_CPU1_PMC_ENABLE | PMC0_CPU1_POWERDOWN; hix5hd2_set_cpu()
205 val &= ~PMC0_CPU1_WAIT_MTCOMS_ACK; hix5hd2_set_cpu()
206 writel_relaxed(val, ctrl_base + HIX5HD2_PERI_PMC0); hix5hd2_set_cpu()
209 val = readl_relaxed(ctrl_base + HIX5HD2_PERI_CRG20); hix5hd2_set_cpu()
210 val |= CRG20_CPU1_RESET; hix5hd2_set_cpu()
211 writel_relaxed(val, ctrl_base + HIX5HD2_PERI_CRG20); hix5hd2_set_cpu()
/linux-4.1.27/drivers/pci/host/
H A Dpci-exynos.c105 static inline void exynos_elb_writel(struct exynos_pcie *pcie, u32 val, u32 reg) exynos_elb_writel() argument
107 writel(val, pcie->elbi_base + reg); exynos_elb_writel()
115 static inline void exynos_phy_writel(struct exynos_pcie *pcie, u32 val, u32 reg) exynos_phy_writel() argument
117 writel(val, pcie->phy_base + reg); exynos_phy_writel()
125 static inline void exynos_blk_writel(struct exynos_pcie *pcie, u32 val, u32 reg) exynos_blk_writel() argument
127 writel(val, pcie->block_base + reg); exynos_blk_writel()
137 u32 val; exynos_pcie_sideband_dbi_w_mode() local
141 val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_SLV_AWMISC); exynos_pcie_sideband_dbi_w_mode()
142 val |= PCIE_ELBI_SLV_DBI_ENABLE; exynos_pcie_sideband_dbi_w_mode()
143 exynos_elb_writel(exynos_pcie, val, PCIE_ELBI_SLV_AWMISC); exynos_pcie_sideband_dbi_w_mode()
145 val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_SLV_AWMISC); exynos_pcie_sideband_dbi_w_mode()
146 val &= ~PCIE_ELBI_SLV_DBI_ENABLE; exynos_pcie_sideband_dbi_w_mode()
147 exynos_elb_writel(exynos_pcie, val, PCIE_ELBI_SLV_AWMISC); exynos_pcie_sideband_dbi_w_mode()
153 u32 val; exynos_pcie_sideband_dbi_r_mode() local
157 val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_SLV_ARMISC); exynos_pcie_sideband_dbi_r_mode()
158 val |= PCIE_ELBI_SLV_DBI_ENABLE; exynos_pcie_sideband_dbi_r_mode()
159 exynos_elb_writel(exynos_pcie, val, PCIE_ELBI_SLV_ARMISC); exynos_pcie_sideband_dbi_r_mode()
161 val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_SLV_ARMISC); exynos_pcie_sideband_dbi_r_mode()
162 val &= ~PCIE_ELBI_SLV_DBI_ENABLE; exynos_pcie_sideband_dbi_r_mode()
163 exynos_elb_writel(exynos_pcie, val, PCIE_ELBI_SLV_ARMISC); exynos_pcie_sideband_dbi_r_mode()
169 u32 val; exynos_pcie_assert_core_reset() local
172 val = exynos_elb_readl(exynos_pcie, PCIE_CORE_RESET); exynos_pcie_assert_core_reset()
173 val &= ~PCIE_CORE_RESET_ENABLE; exynos_pcie_assert_core_reset()
174 exynos_elb_writel(exynos_pcie, val, PCIE_CORE_RESET); exynos_pcie_assert_core_reset()
182 u32 val; exynos_pcie_deassert_core_reset() local
185 val = exynos_elb_readl(exynos_pcie, PCIE_CORE_RESET); exynos_pcie_deassert_core_reset()
186 val |= PCIE_CORE_RESET_ENABLE; exynos_pcie_deassert_core_reset()
188 exynos_elb_writel(exynos_pcie, val, PCIE_CORE_RESET); exynos_pcie_deassert_core_reset()
218 u32 val; exynos_pcie_power_on_phy() local
221 val = exynos_phy_readl(exynos_pcie, PCIE_PHY_COMMON_POWER); exynos_pcie_power_on_phy()
222 val &= ~PCIE_PHY_COMMON_PD_CMN; exynos_pcie_power_on_phy()
223 exynos_phy_writel(exynos_pcie, val, PCIE_PHY_COMMON_POWER); exynos_pcie_power_on_phy()
225 val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV0_POWER); exynos_pcie_power_on_phy()
226 val &= ~PCIE_PHY_TRSV0_PD_TSV; exynos_pcie_power_on_phy()
227 exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV0_POWER); exynos_pcie_power_on_phy()
229 val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV1_POWER); exynos_pcie_power_on_phy()
230 val &= ~PCIE_PHY_TRSV1_PD_TSV; exynos_pcie_power_on_phy()
231 exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV1_POWER); exynos_pcie_power_on_phy()
233 val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV2_POWER); exynos_pcie_power_on_phy()
234 val &= ~PCIE_PHY_TRSV2_PD_TSV; exynos_pcie_power_on_phy()
235 exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV2_POWER); exynos_pcie_power_on_phy()
237 val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV3_POWER); exynos_pcie_power_on_phy()
238 val &= ~PCIE_PHY_TRSV3_PD_TSV; exynos_pcie_power_on_phy()
239 exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV3_POWER); exynos_pcie_power_on_phy()
244 u32 val; exynos_pcie_power_off_phy() local
247 val = exynos_phy_readl(exynos_pcie, PCIE_PHY_COMMON_POWER); exynos_pcie_power_off_phy()
248 val |= PCIE_PHY_COMMON_PD_CMN; exynos_pcie_power_off_phy()
249 exynos_phy_writel(exynos_pcie, val, PCIE_PHY_COMMON_POWER); exynos_pcie_power_off_phy()
251 val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV0_POWER); exynos_pcie_power_off_phy()
252 val |= PCIE_PHY_TRSV0_PD_TSV; exynos_pcie_power_off_phy()
253 exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV0_POWER); exynos_pcie_power_off_phy()
255 val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV1_POWER); exynos_pcie_power_off_phy()
256 val |= PCIE_PHY_TRSV1_PD_TSV; exynos_pcie_power_off_phy()
257 exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV1_POWER); exynos_pcie_power_off_phy()
259 val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV2_POWER); exynos_pcie_power_off_phy()
260 val |= PCIE_PHY_TRSV2_PD_TSV; exynos_pcie_power_off_phy()
261 exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV2_POWER); exynos_pcie_power_off_phy()
263 val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV3_POWER); exynos_pcie_power_off_phy()
264 val |= PCIE_PHY_TRSV3_PD_TSV; exynos_pcie_power_off_phy()
265 exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV3_POWER); exynos_pcie_power_off_phy()
319 u32 val; exynos_pcie_establish_link() local
366 val = exynos_blk_readl(exynos_pcie, exynos_pcie_establish_link()
368 dev_info(pp->dev, "PLL Locked: 0x%x\n", val); exynos_pcie_establish_link()
385 u32 val; exynos_pcie_clear_irq_pulse() local
388 val = exynos_elb_readl(exynos_pcie, PCIE_IRQ_PULSE); exynos_pcie_clear_irq_pulse()
389 exynos_elb_writel(exynos_pcie, val, PCIE_IRQ_PULSE); exynos_pcie_clear_irq_pulse()
394 u32 val; exynos_pcie_enable_irq_pulse() local
398 val = IRQ_INTA_ASSERT | IRQ_INTB_ASSERT | exynos_pcie_enable_irq_pulse()
400 exynos_elb_writel(exynos_pcie, val, PCIE_IRQ_EN_PULSE); exynos_pcie_enable_irq_pulse()
420 u32 val; exynos_pcie_msi_init() local
426 val = exynos_elb_readl(exynos_pcie, PCIE_IRQ_EN_LEVEL); exynos_pcie_msi_init()
427 val |= IRQ_MSI_ENABLE; exynos_pcie_msi_init()
428 exynos_elb_writel(exynos_pcie, val, PCIE_IRQ_EN_LEVEL); exynos_pcie_msi_init()
440 void __iomem *dbi_base, u32 *val) exynos_pcie_readl_rc()
443 *val = readl(dbi_base); exynos_pcie_readl_rc()
448 u32 val, void __iomem *dbi_base) exynos_pcie_writel_rc()
451 writel(val, dbi_base); exynos_pcie_writel_rc()
456 u32 *val) exynos_pcie_rd_own_conf()
461 ret = dw_pcie_cfg_read(pp->dbi_base + (where & ~0x3), where, size, val); exynos_pcie_rd_own_conf()
467 u32 val) exynos_pcie_wr_own_conf()
473 where, size, val); exynos_pcie_wr_own_conf()
481 u32 val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_RDLH_LINKUP); exynos_pcie_link_up() local
483 if (val == PCIE_ELBI_LTSSM_ENABLE) exynos_pcie_link_up()
439 exynos_pcie_readl_rc(struct pcie_port *pp, void __iomem *dbi_base, u32 *val) exynos_pcie_readl_rc() argument
447 exynos_pcie_writel_rc(struct pcie_port *pp, u32 val, void __iomem *dbi_base) exynos_pcie_writel_rc() argument
455 exynos_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, u32 *val) exynos_pcie_rd_own_conf() argument
466 exynos_pcie_wr_own_conf(struct pcie_port *pp, int where, int size, u32 val) exynos_pcie_wr_own_conf() argument
/linux-4.1.27/drivers/soc/tegra/fuse/
H A Dspeedo-tegra20.c68 u32 val; tegra20_init_speedo_data() local
81 val = 0; tegra20_init_speedo_data()
85 val = (val << 1) | (reg & 0x1); tegra20_init_speedo_data()
87 val = val * SPEEDO_MULT; tegra20_init_speedo_data()
88 pr_debug("Tegra CPU speedo value %u\n", val); tegra20_init_speedo_data()
91 if (val <= cpu_process_speedos[sku_info->soc_speedo_id][i]) tegra20_init_speedo_data()
96 val = 0; tegra20_init_speedo_data()
100 val = (val << 1) | (reg & 0x1); tegra20_init_speedo_data()
102 val = val * SPEEDO_MULT; tegra20_init_speedo_data()
103 pr_debug("Core speedo value %u\n", val); tegra20_init_speedo_data()
106 if (val <= core_process_speedos[sku_info->soc_speedo_id][i]) tegra20_init_speedo_data()
/linux-4.1.27/arch/arm/mach-imx/
H A Dsrc.c50 u32 val; imx_src_reset_module() local
61 val = readl_relaxed(src_base + SRC_SCR); imx_src_reset_module()
62 val |= bit; imx_src_reset_module()
63 writel_relaxed(val, src_base + SRC_SCR); imx_src_reset_module()
87 u32 mask, val; imx_enable_cpu() local
92 val = readl_relaxed(src_base + SRC_SCR); imx_enable_cpu()
93 val = enable ? val | mask : val & ~mask; imx_enable_cpu()
94 val |= 1 << (BP_SRC_SCR_CORE1_RST + cpu - 1); imx_enable_cpu()
95 writel_relaxed(val, src_base + SRC_SCR); imx_enable_cpu()
121 u32 val; imx_src_init() local
138 val = readl_relaxed(src_base + SRC_SCR); imx_src_init()
139 val &= ~(1 << BP_SRC_SCR_WARM_RESET_ENABLE); imx_src_init()
140 writel_relaxed(val, src_base + SRC_SCR); imx_src_init()
/linux-4.1.27/drivers/clk/tegra/
H A Dclk-pll.c191 #define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset)
192 #define pll_writel_base(val, p) pll_writel(val, p->params->base_reg, p)
193 #define pll_writel_misc(val, p) pll_writel(val, p->params->misc_reg, p)
194 #define pll_override_writel(val, offset, p) writel(val, p->pmc + offset)
225 u32 val; clk_pll_enable_lock() local
233 val = pll_readl_misc(pll); clk_pll_enable_lock()
234 val |= BIT(pll->params->lock_enable_bit_idx); clk_pll_enable_lock()
235 pll_writel_misc(val, pll); clk_pll_enable_lock()
241 u32 val, lock_mask; clk_pll_wait_for_lock() local
258 val = readl_relaxed(lock_addr); clk_pll_wait_for_lock()
259 if ((val & lock_mask) == lock_mask) { clk_pll_wait_for_lock()
275 u32 val; clk_pll_is_enabled() local
278 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); clk_pll_is_enabled()
279 if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE) clk_pll_is_enabled()
280 return val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE ? 1 : 0; clk_pll_is_enabled()
283 val = pll_readl_base(pll); clk_pll_is_enabled()
285 return val & PLL_BASE_ENABLE ? 1 : 0; clk_pll_is_enabled()
291 u32 val; _clk_pll_enable() local
295 val = pll_readl_base(pll); _clk_pll_enable()
297 val &= ~PLL_BASE_BYPASS; _clk_pll_enable()
298 val |= PLL_BASE_ENABLE; _clk_pll_enable()
299 pll_writel_base(val, pll); _clk_pll_enable()
302 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); _clk_pll_enable()
303 val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE; _clk_pll_enable()
304 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE); _clk_pll_enable()
311 u32 val; _clk_pll_disable() local
313 val = pll_readl_base(pll); _clk_pll_disable()
315 val &= ~PLL_BASE_BYPASS; _clk_pll_disable()
316 val &= ~PLL_BASE_ENABLE; _clk_pll_disable()
317 pll_writel_base(val, pll); _clk_pll_disable()
320 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); _clk_pll_disable()
321 val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE; _clk_pll_disable()
322 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE); _clk_pll_disable()
482 u32 val; _update_pll_mnp() local
489 val = pll_override_readl(params->pmc_divp_reg, pll); _update_pll_mnp()
490 val &= ~(divp_mask(pll) << div_nmp->override_divp_shift); _update_pll_mnp()
491 val |= cfg->p << div_nmp->override_divp_shift; _update_pll_mnp()
492 pll_override_writel(val, params->pmc_divp_reg, pll); _update_pll_mnp()
494 val = pll_override_readl(params->pmc_divnm_reg, pll); _update_pll_mnp()
495 val &= ~(divm_mask(pll) << div_nmp->override_divm_shift) | _update_pll_mnp()
497 val |= (cfg->m << div_nmp->override_divm_shift) | _update_pll_mnp()
499 pll_override_writel(val, params->pmc_divnm_reg, pll); _update_pll_mnp()
501 val = pll_readl_base(pll); _update_pll_mnp()
503 val &= ~(divm_mask_shifted(pll) | divn_mask_shifted(pll) | _update_pll_mnp()
506 val |= (cfg->m << divm_shift(pll)) | _update_pll_mnp()
510 pll_writel_base(val, pll); _update_pll_mnp()
517 u32 val; _get_pll_mnp() local
524 val = pll_override_readl(params->pmc_divp_reg, pll); _get_pll_mnp()
525 cfg->p = (val >> div_nmp->override_divp_shift) & divp_mask(pll); _get_pll_mnp()
527 val = pll_override_readl(params->pmc_divnm_reg, pll); _get_pll_mnp()
528 cfg->m = (val >> div_nmp->override_divm_shift) & divm_mask(pll); _get_pll_mnp()
529 cfg->n = (val >> div_nmp->override_divn_shift) & divn_mask(pll); _get_pll_mnp()
531 val = pll_readl_base(pll); _get_pll_mnp()
533 cfg->m = (val >> div_nmp->divm_shift) & divm_mask(pll); _get_pll_mnp()
534 cfg->n = (val >> div_nmp->divn_shift) & divn_mask(pll); _get_pll_mnp()
535 cfg->p = (val >> div_nmp->divp_shift) & divp_mask(pll); _get_pll_mnp()
543 u32 val; _update_pll_cpcon() local
545 val = pll_readl_misc(pll); _update_pll_cpcon()
547 val &= ~(PLL_MISC_CPCON_MASK << PLL_MISC_CPCON_SHIFT); _update_pll_cpcon()
548 val |= cfg->cpcon << PLL_MISC_CPCON_SHIFT; _update_pll_cpcon()
551 val &= ~(PLL_MISC_LFCON_MASK << PLL_MISC_LFCON_SHIFT); _update_pll_cpcon()
553 val |= 1 << PLL_MISC_LFCON_SHIFT; _update_pll_cpcon()
555 val &= ~(1 << PLL_MISC_DCCON_SHIFT); _update_pll_cpcon()
557 val |= 1 << PLL_MISC_DCCON_SHIFT; _update_pll_cpcon()
560 pll_writel_misc(val, pll); _update_pll_cpcon()
651 u32 val; clk_pll_recalc_rate() local
655 val = pll_readl_base(pll); clk_pll_recalc_rate()
657 if ((pll->params->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS)) clk_pll_recalc_rate()
661 !(val & PLL_BASE_OVERRIDE)) { clk_pll_recalc_rate()
690 u32 val; clk_plle_training() local
700 val = readl(pll->pmc + PMC_SATA_PWRGT); clk_plle_training()
701 val |= PMC_SATA_PWRGT_PLLE_IDDQ_VALUE; clk_plle_training()
702 writel(val, pll->pmc + PMC_SATA_PWRGT); clk_plle_training()
704 val = readl(pll->pmc + PMC_SATA_PWRGT); clk_plle_training()
705 val |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL; clk_plle_training()
706 writel(val, pll->pmc + PMC_SATA_PWRGT); clk_plle_training()
708 val = readl(pll->pmc + PMC_SATA_PWRGT); clk_plle_training()
709 val &= ~PMC_SATA_PWRGT_PLLE_IDDQ_VALUE; clk_plle_training()
710 writel(val, pll->pmc + PMC_SATA_PWRGT); clk_plle_training()
712 val = pll_readl_misc(pll); clk_plle_training()
716 val = pll_readl_misc(pll); clk_plle_training()
717 if (val & PLLE_MISC_READY) clk_plle_training()
734 u32 val; clk_plle_enable() local
742 val = pll_readl_misc(pll); clk_plle_enable()
743 val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK); clk_plle_enable()
744 pll_writel_misc(val, pll); clk_plle_enable()
746 val = pll_readl_misc(pll); clk_plle_enable()
747 if (!(val & PLLE_MISC_READY)) { clk_plle_enable()
755 val = pll_readl_base(pll); clk_plle_enable()
756 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) | clk_plle_enable()
758 val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT); clk_plle_enable()
759 val |= sel.m << divm_shift(pll); clk_plle_enable()
760 val |= sel.n << divn_shift(pll); clk_plle_enable()
761 val |= sel.p << divp_shift(pll); clk_plle_enable()
762 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT; clk_plle_enable()
763 pll_writel_base(val, pll); clk_plle_enable()
766 val = pll_readl_misc(pll); clk_plle_enable()
767 val |= PLLE_MISC_SETUP_VALUE; clk_plle_enable()
768 val |= PLLE_MISC_LOCK_ENABLE; clk_plle_enable()
769 pll_writel_misc(val, pll); clk_plle_enable()
771 val = readl(pll->clk_base + PLLE_SS_CTRL); clk_plle_enable()
772 val &= ~PLLE_SS_COEFFICIENTS_MASK; clk_plle_enable()
773 val |= PLLE_SS_DISABLE; clk_plle_enable()
774 writel(val, pll->clk_base + PLLE_SS_CTRL); clk_plle_enable()
776 val = pll_readl_base(pll); clk_plle_enable()
777 val |= (PLL_BASE_BYPASS | PLL_BASE_ENABLE); clk_plle_enable()
778 pll_writel_base(val, pll); clk_plle_enable()
789 u32 val = pll_readl_base(pll); clk_plle_recalc_rate() local
793 divp = (val >> pll->params->div_nmp->divp_shift) & (divp_mask(pll)); clk_plle_recalc_rate()
794 divn = (val >> pll->params->div_nmp->divn_shift) & (divn_mask(pll)); clk_plle_recalc_rate()
795 divm = (val >> pll->params->div_nmp->divm_shift) & (divm_mask(pll)); clk_plle_recalc_rate()
842 u32 val; _setup_dynamic_ramp() local
867 val = step_a << pll_params->stepa_shift; _setup_dynamic_ramp()
868 val |= step_b << pll_params->stepb_shift; _setup_dynamic_ramp()
869 writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg); _setup_dynamic_ramp()
879 u32 val; clk_pll_iddq_enable() local
885 val = pll_readl(pll->params->iddq_reg, pll); clk_pll_iddq_enable()
886 val &= ~BIT(pll->params->iddq_bit_idx); clk_pll_iddq_enable()
887 pll_writel(val, pll->params->iddq_reg, pll); clk_pll_iddq_enable()
904 u32 val; clk_pll_iddq_disable() local
911 val = pll_readl(pll->params->iddq_reg, pll); clk_pll_iddq_disable()
912 val |= BIT(pll->params->iddq_bit_idx); clk_pll_iddq_disable()
913 pll_writel(val, pll->params->iddq_reg, pll); clk_pll_iddq_disable()
1061 u32 val; _pllcx_strobe() local
1063 val = pll_readl_misc(pll); _pllcx_strobe()
1064 val |= PLLCX_MISC_STROBE; _pllcx_strobe()
1065 pll_writel_misc(val, pll); _pllcx_strobe()
1068 val &= ~PLLCX_MISC_STROBE; _pllcx_strobe()
1069 pll_writel_misc(val, pll); _pllcx_strobe()
1075 u32 val; clk_pllc_enable() local
1085 val = pll_readl_misc(pll); clk_pllc_enable()
1086 val &= ~PLLCX_MISC_RESET; clk_pllc_enable()
1087 pll_writel_misc(val, pll); clk_pllc_enable()
1103 u32 val; _clk_pllc_disable() local
1107 val = pll_readl_misc(pll); _clk_pllc_disable()
1108 val |= PLLCX_MISC_RESET; _clk_pllc_disable()
1109 pll_writel_misc(val, pll); _clk_pllc_disable()
1130 u32 val, n_threshold; _pllcx_update_dynamic_coef() local
1152 val = pll_readl_misc(pll); _pllcx_update_dynamic_coef()
1153 val &= ~(PLLCX_MISC_SDM_DIV_MASK | PLLCX_MISC_FILT_DIV_MASK); _pllcx_update_dynamic_coef()
1154 val |= n <= n_threshold ? _pllcx_update_dynamic_coef()
1156 pll_writel_misc(val, pll); _pllcx_update_dynamic_coef()
1288 u32 val; clk_plle_tegra114_enable() local
1299 val = pll_readl_base(pll); clk_plle_tegra114_enable()
1300 val &= ~BIT(29); /* Disable lock override */ clk_plle_tegra114_enable()
1301 pll_writel_base(val, pll); clk_plle_tegra114_enable()
1303 val = pll_readl(pll->params->aux_reg, pll); clk_plle_tegra114_enable()
1304 val |= PLLE_AUX_ENABLE_SWCTL; clk_plle_tegra114_enable()
1305 val &= ~PLLE_AUX_SEQ_ENABLE; clk_plle_tegra114_enable()
1306 pll_writel(val, pll->params->aux_reg, pll); clk_plle_tegra114_enable()
1309 val = pll_readl_misc(pll); clk_plle_tegra114_enable()
1310 val |= PLLE_MISC_LOCK_ENABLE; clk_plle_tegra114_enable()
1311 val |= PLLE_MISC_IDDQ_SW_CTRL; clk_plle_tegra114_enable()
1312 val &= ~PLLE_MISC_IDDQ_SW_VALUE; clk_plle_tegra114_enable()
1313 val |= PLLE_MISC_PLLE_PTS; clk_plle_tegra114_enable()
1314 val |= PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK; clk_plle_tegra114_enable()
1315 pll_writel_misc(val, pll); clk_plle_tegra114_enable()
1318 val = pll_readl(PLLE_SS_CTRL, pll); clk_plle_tegra114_enable()
1319 val |= PLLE_SS_DISABLE; clk_plle_tegra114_enable()
1320 pll_writel(val, PLLE_SS_CTRL, pll); clk_plle_tegra114_enable()
1322 val = pll_readl_base(pll); clk_plle_tegra114_enable()
1323 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) | clk_plle_tegra114_enable()
1325 val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT); clk_plle_tegra114_enable()
1326 val |= sel.m << divm_shift(pll); clk_plle_tegra114_enable()
1327 val |= sel.n << divn_shift(pll); clk_plle_tegra114_enable()
1328 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT; clk_plle_tegra114_enable()
1329 pll_writel_base(val, pll); clk_plle_tegra114_enable()
1338 val = pll_readl(PLLE_SS_CTRL, pll); clk_plle_tegra114_enable()
1339 val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT); clk_plle_tegra114_enable()
1340 val &= ~PLLE_SS_COEFFICIENTS_MASK; clk_plle_tegra114_enable()
1341 val |= PLLE_SS_COEFFICIENTS_VAL; clk_plle_tegra114_enable()
1342 pll_writel(val, PLLE_SS_CTRL, pll); clk_plle_tegra114_enable()
1343 val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS); clk_plle_tegra114_enable()
1344 pll_writel(val, PLLE_SS_CTRL, pll); clk_plle_tegra114_enable()
1346 val &= ~PLLE_SS_CNTL_INTERP_RESET; clk_plle_tegra114_enable()
1347 pll_writel(val, PLLE_SS_CTRL, pll); clk_plle_tegra114_enable()
1351 val = pll_readl_misc(pll); clk_plle_tegra114_enable()
1352 val &= ~PLLE_MISC_IDDQ_SW_CTRL; clk_plle_tegra114_enable()
1353 pll_writel_misc(val, pll); clk_plle_tegra114_enable()
1355 val = pll_readl(pll->params->aux_reg, pll); clk_plle_tegra114_enable()
1356 val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SEQ_START_STATE); clk_plle_tegra114_enable()
1357 val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL); clk_plle_tegra114_enable()
1358 pll_writel(val, pll->params->aux_reg, pll); clk_plle_tegra114_enable()
1360 val |= PLLE_AUX_SEQ_ENABLE; clk_plle_tegra114_enable()
1361 pll_writel(val, pll->params->aux_reg, pll); clk_plle_tegra114_enable()
1363 val = pll_readl(XUSBIO_PLL_CFG0, pll); clk_plle_tegra114_enable()
1364 val |= (XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET | clk_plle_tegra114_enable()
1366 val &= ~(XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL | clk_plle_tegra114_enable()
1368 pll_writel(val, XUSBIO_PLL_CFG0, pll); clk_plle_tegra114_enable()
1370 val |= XUSBIO_PLL_CFG0_SEQ_ENABLE; clk_plle_tegra114_enable()
1371 pll_writel(val, XUSBIO_PLL_CFG0, pll); clk_plle_tegra114_enable()
1374 val = pll_readl(SATA_PLL_CFG0, pll); clk_plle_tegra114_enable()
1375 val &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL; clk_plle_tegra114_enable()
1376 val |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET; clk_plle_tegra114_enable()
1377 val |= SATA_PLL_CFG0_SEQ_START_STATE; clk_plle_tegra114_enable()
1378 pll_writel(val, SATA_PLL_CFG0, pll); clk_plle_tegra114_enable()
1382 val = pll_readl(SATA_PLL_CFG0, pll); clk_plle_tegra114_enable()
1383 val |= SATA_PLL_CFG0_SEQ_ENABLE; clk_plle_tegra114_enable()
1384 pll_writel(val, SATA_PLL_CFG0, pll); clk_plle_tegra114_enable()
1397 u32 val; clk_plle_tegra114_disable() local
1404 val = pll_readl_misc(pll); clk_plle_tegra114_disable()
1405 val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE; clk_plle_tegra114_disable()
1406 pll_writel_misc(val, pll); clk_plle_tegra114_disable()
1568 u32 val, val_iddq; tegra_clk_register_pllxc() local
1588 val = readl_relaxed(clk_base + pll_params->base_reg); tegra_clk_register_pllxc()
1591 if (val & PLL_BASE_ENABLE) tegra_clk_register_pllxc()
1617 u32 val; tegra_clk_register_pllre() local
1631 val = pll_readl_base(pll); tegra_clk_register_pllre()
1632 if (val & PLL_BASE_ENABLE) tegra_clk_register_pllre()
1633 WARN_ON(val & pll_params->iddq_bit_idx); tegra_clk_register_pllre()
1638 val = m << divm_shift(pll); tegra_clk_register_pllre()
1639 val |= (pll_params->vco_min / parent_rate) << divn_shift(pll); tegra_clk_register_pllre()
1640 pll_writel_base(val, pll); tegra_clk_register_pllre()
1645 val = pll_readl_misc(pll); tegra_clk_register_pllre()
1646 val &= ~BIT(29); tegra_clk_register_pllre()
1647 pll_writel_misc(val, pll); tegra_clk_register_pllre()
1778 u32 val, val_aux; tegra_clk_register_plle_tegra114() local
1787 val = pll_readl_base(pll); tegra_clk_register_plle_tegra114()
1790 if (val & PLL_BASE_ENABLE) { tegra_clk_register_plle_tegra114()
1829 u32 val; tegra_clk_register_pllss() local
1847 val = pll_readl_base(pll); tegra_clk_register_pllss()
1848 val &= ~PLLSS_REF_SRC_SEL_MASK; tegra_clk_register_pllss()
1849 pll_writel_base(val, pll); tegra_clk_register_pllss()
1876 val = pll_readl_base(pll); tegra_clk_register_pllss()
1877 if (val & PLL_BASE_ENABLE) { tegra_clk_register_pllss()
1878 if (val & BIT(pll_params->iddq_bit_idx)) { tegra_clk_register_pllss()
1884 val |= BIT(pll_params->iddq_bit_idx); tegra_clk_register_pllss()
1886 val &= ~PLLSS_LOCK_OVERRIDE; tegra_clk_register_pllss()
1887 pll_writel_base(val, pll); tegra_clk_register_pllss()
/linux-4.1.27/include/drm/
H A Ddrm_os_linux.h15 static inline void writeq(u64 val, void __iomem *reg) writeq() argument
17 writel(val & 0xffffffff, reg); writeq()
18 writel(val >> 32, reg + 0x4UL); writeq()
32 #define DRM_WRITE8(map, offset, val) writeb(val, ((void __iomem *)(map)->handle) + (offset))
34 #define DRM_WRITE16(map, offset, val) writew(val, ((void __iomem *)(map)->handle) + (offset))
36 #define DRM_WRITE32(map, offset, val) writel(val, ((void __iomem *)(map)->handle) + (offset))
41 #define DRM_WRITE64(map, offset, val) writeq(val, ((void __iomem *)(map)->handle) + (offset))
/linux-4.1.27/arch/arm/plat-samsung/
H A Dwakeup-mask.c26 u32 val; samsung_sync_wakemask() local
28 val = __raw_readl(reg); samsung_sync_wakemask()
32 val |= mask->bit; samsung_sync_wakemask()
40 val &= ~mask->bit; samsung_sync_wakemask()
42 val |= mask->bit; samsung_sync_wakemask()
45 printk(KERN_INFO "wakemask %08x => %08x\n", __raw_readl(reg), val); samsung_sync_wakemask()
46 __raw_writel(val, reg); samsung_sync_wakemask()
/linux-4.1.27/tools/perf/util/
H A Dstat.c5 void update_stats(struct stats *stats, u64 val) update_stats() argument
10 delta = val - stats->mean; update_stats()
12 stats->M2 += delta*(val - stats->mean); update_stats()
14 if (val > stats->max) update_stats()
15 stats->max = val; update_stats()
17 if (val < stats->min) update_stats()
18 stats->min = val; update_stats()
/linux-4.1.27/drivers/net/irda/
H A Dvia-ircc.h160 #define GetBit(val,bit) val = (unsigned char) ((val>>bit) & 0x1)
162 #define SetBit(val,bit) val= (unsigned char ) (val | (0x1 << bit))
164 #define ResetBit(val,bit) val= (unsigned char ) (val & ~(0x1 << bit))
318 #define CRC16(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,7,val) //0 for 32 CRC
320 #define SetVFIR(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_H_0,5,val)
321 #define SetFIR(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,6,val)
322 #define SetMIR(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,5,val)
323 #define SetSIR(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,4,val)
325 #define SIRFilter(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,3,val)
326 #define Filter(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,2,val)
327 #define InvertTX(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,1,val)
328 #define InvertRX(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,0,val)
330 #define EnableTX(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_H_0,4,val)
331 #define EnableRX(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_H_0,3,val)
332 #define EnableDMA(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_H_0,2,val)
333 #define SIRRecvAny(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_H_0,1,val)
334 #define DiableTrans(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_H_0,0,val)
336 #define SetSIRBOF(BaseAddr,val) WriteReg(BaseAddr,I_SIR_BOF,val)
337 #define SetSIREOF(BaseAddr,val) WriteReg(BaseAddr,I_SIR_EOF,val)
341 #define EnPhys(BaseAddr,val) WriteRegBit(BaseAddr,I_ST_CT_0,7,val)
351 #define DisableAdjacentPulseWidth(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_3,5,val) //1 disable
352 #define DisablePulseWidthAdjust(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_3,4,val) //1 disable
353 #define UseOneRX(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_3,1,val) //0 use two RX
354 #define SlowIRRXLowActive(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_3,0,val) //0 show RX high=1 in SIR
356 #define EnAllInt(BaseAddr,val) WriteRegBit(BaseAddr,H_CT,7,val)
357 #define TXStart(BaseAddr,val) WriteRegBit(BaseAddr,H_CT,6,val)
358 #define RXStart(BaseAddr,val) WriteRegBit(BaseAddr,H_CT,5,val)
359 #define ClearRXInt(BaseAddr,val) WriteRegBit(BaseAddr,H_CT,4,val) // 1 clear
366 #define EnTXDMA(BaseAddr,val) WriteRegBit(BaseAddr,M_CT,7,val)
367 #define EnRXDMA(BaseAddr,val) WriteRegBit(BaseAddr,M_CT,6,val)
368 #define SwapDMA(BaseAddr,val) WriteRegBit(BaseAddr,M_CT,5,val)
369 #define EnInternalLoop(BaseAddr,val) WriteRegBit(BaseAddr,M_CT,4,val)
370 #define EnExternalLoop(BaseAddr,val) WriteRegBit(BaseAddr,M_CT,3,val)
372 #define EnTXFIFOHalfLevelInt(BaseAddr,val) WriteRegBit(BaseAddr,TX_CT_1,4,val) //half empty int (1 half)
373 #define EnTXFIFOUnderrunEOMInt(BaseAddr,val) WriteRegBit(BaseAddr,TX_CT_1,5,val)
374 #define EnTXFIFOReadyInt(BaseAddr,val) WriteRegBit(BaseAddr,TX_CT_1,6,val) //int when reach it threshold (setting by bit 4)
376 #define ForceUnderrun(BaseAddr,val) WriteRegBit(BaseAddr,TX_CT_2,7,val) // force an underrun int
377 #define EnTXCRC(BaseAddr,val) WriteRegBit(BaseAddr,TX_CT_2,6,val) //1 for FIR,MIR...0 (not SIR)
378 #define ForceBADCRC(BaseAddr,val) WriteRegBit(BaseAddr,TX_CT_2,5,val) //force an bad CRC
379 #define SendSIP(BaseAddr,val) WriteRegBit(BaseAddr,TX_CT_2,4,val) //send indication pulse for prevent SIR disturb
380 #define ClearEnTX(BaseAddr,val) WriteRegBit(BaseAddr,TX_CT_2,3,val) // opposite to EnTX
384 #define EnRXSpecInt(BaseAddr,val) WriteRegBit(BaseAddr,RX_CT,0,val)
385 #define EnRXFIFOReadyInt(BaseAddr,val) WriteRegBit(BaseAddr,RX_CT,1,val) //enable int when reach it threshold (setting by bit 7)
386 #define EnRXFIFOHalfLevelInt(BaseAddr,val) WriteRegBit(BaseAddr,RX_CT,7,val) //enable int when (1) half full...or (0) just not full
392 #define EnGPIOtoRX2(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_4,7,val)
393 #define EnTimerInt(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_4,1,val)
394 #define ClearTimerInt(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_4,0,val)
396 #define WriteGIO(BaseAddr,val) WriteRegBit(BaseAddr,I_T_C_L,7,val)
399 #define WriteTX(BaseAddr,val) WriteRegBit(BaseAddr,I_T_C_L,0,val)
401 #define EnRX2(BaseAddr,val) WriteRegBit(BaseAddr,I_T_C_H,7,val)
807 static void SetVFIR(__u16 BaseAddr, __u8 val) SetVFIR() argument
813 WriteRegBit(BaseAddr, I_CF_H_0, 5, val); SetVFIR()
816 static void SetFIR(__u16 BaseAddr, __u8 val) SetFIR() argument
823 WriteRegBit(BaseAddr, I_CF_L_0, 6, val); SetFIR()
826 static void SetMIR(__u16 BaseAddr, __u8 val) SetMIR() argument
833 WriteRegBit(BaseAddr, I_CF_L_0, 5, val); SetMIR()
836 static void SetSIR(__u16 BaseAddr, __u8 val) SetSIR() argument
843 WriteRegBit(BaseAddr, I_CF_L_0, 4, val); SetSIR()
/linux-4.1.27/drivers/gpu/drm/msm/mdp/mdp5/
H A Dmdp5.xml.h153 static inline uint32_t MDSS_HW_VERSION_STEP(uint32_t val) MDSS_HW_VERSION_STEP() argument
155 return ((val) << MDSS_HW_VERSION_STEP__SHIFT) & MDSS_HW_VERSION_STEP__MASK; MDSS_HW_VERSION_STEP()
159 static inline uint32_t MDSS_HW_VERSION_MINOR(uint32_t val) MDSS_HW_VERSION_MINOR() argument
161 return ((val) << MDSS_HW_VERSION_MINOR__SHIFT) & MDSS_HW_VERSION_MINOR__MASK; MDSS_HW_VERSION_MINOR()
165 static inline uint32_t MDSS_HW_VERSION_MAJOR(uint32_t val) MDSS_HW_VERSION_MAJOR() argument
167 return ((val) << MDSS_HW_VERSION_MAJOR__SHIFT) & MDSS_HW_VERSION_MAJOR__MASK; MDSS_HW_VERSION_MAJOR()
189 static inline uint32_t MDP5_MDP_HW_VERSION_STEP(uint32_t val) MDP5_MDP_HW_VERSION_STEP() argument
191 return ((val) << MDP5_MDP_HW_VERSION_STEP__SHIFT) & MDP5_MDP_HW_VERSION_STEP__MASK; MDP5_MDP_HW_VERSION_STEP()
195 static inline uint32_t MDP5_MDP_HW_VERSION_MINOR(uint32_t val) MDP5_MDP_HW_VERSION_MINOR() argument
197 return ((val) << MDP5_MDP_HW_VERSION_MINOR__SHIFT) & MDP5_MDP_HW_VERSION_MINOR__MASK; MDP5_MDP_HW_VERSION_MINOR()
201 static inline uint32_t MDP5_MDP_HW_VERSION_MAJOR(uint32_t val) MDP5_MDP_HW_VERSION_MAJOR() argument
203 return ((val) << MDP5_MDP_HW_VERSION_MAJOR__SHIFT) & MDP5_MDP_HW_VERSION_MAJOR__MASK; MDP5_MDP_HW_VERSION_MAJOR()
209 static inline uint32_t MDP5_MDP_DISP_INTF_SEL_INTF0(enum mdp5_intf_type val) MDP5_MDP_DISP_INTF_SEL_INTF0() argument
211 return ((val) << MDP5_MDP_DISP_INTF_SEL_INTF0__SHIFT) & MDP5_MDP_DISP_INTF_SEL_INTF0__MASK; MDP5_MDP_DISP_INTF_SEL_INTF0()
215 static inline uint32_t MDP5_MDP_DISP_INTF_SEL_INTF1(enum mdp5_intf_type val) MDP5_MDP_DISP_INTF_SEL_INTF1() argument
217 return ((val) << MDP5_MDP_DISP_INTF_SEL_INTF1__SHIFT) & MDP5_MDP_DISP_INTF_SEL_INTF1__MASK; MDP5_MDP_DISP_INTF_SEL_INTF1()
221 static inline uint32_t MDP5_MDP_DISP_INTF_SEL_INTF2(enum mdp5_intf_type val) MDP5_MDP_DISP_INTF_SEL_INTF2() argument
223 return ((val) << MDP5_MDP_DISP_INTF_SEL_INTF2__SHIFT) & MDP5_MDP_DISP_INTF_SEL_INTF2__MASK; MDP5_MDP_DISP_INTF_SEL_INTF2()
227 static inline uint32_t MDP5_MDP_DISP_INTF_SEL_INTF3(enum mdp5_intf_type val) MDP5_MDP_DISP_INTF_SEL_INTF3() argument
229 return ((val) << MDP5_MDP_DISP_INTF_SEL_INTF3__SHIFT) & MDP5_MDP_DISP_INTF_SEL_INTF3__MASK; MDP5_MDP_DISP_INTF_SEL_INTF3()
252 static inline uint32_t MDP5_MDP_SMP_ALLOC_W_REG_CLIENT0(uint32_t val) MDP5_MDP_SMP_ALLOC_W_REG_CLIENT0() argument
254 return ((val) << MDP5_MDP_SMP_ALLOC_W_REG_CLIENT0__SHIFT) & MDP5_MDP_SMP_ALLOC_W_REG_CLIENT0__MASK; MDP5_MDP_SMP_ALLOC_W_REG_CLIENT0()
258 static inline uint32_t MDP5_MDP_SMP_ALLOC_W_REG_CLIENT1(uint32_t val) MDP5_MDP_SMP_ALLOC_W_REG_CLIENT1() argument
260 return ((val) << MDP5_MDP_SMP_ALLOC_W_REG_CLIENT1__SHIFT) & MDP5_MDP_SMP_ALLOC_W_REG_CLIENT1__MASK; MDP5_MDP_SMP_ALLOC_W_REG_CLIENT1()
264 static inline uint32_t MDP5_MDP_SMP_ALLOC_W_REG_CLIENT2(uint32_t val) MDP5_MDP_SMP_ALLOC_W_REG_CLIENT2() argument
266 return ((val) << MDP5_MDP_SMP_ALLOC_W_REG_CLIENT2__SHIFT) & MDP5_MDP_SMP_ALLOC_W_REG_CLIENT2__MASK; MDP5_MDP_SMP_ALLOC_W_REG_CLIENT2()
274 static inline uint32_t MDP5_MDP_SMP_ALLOC_R_REG_CLIENT0(uint32_t val) MDP5_MDP_SMP_ALLOC_R_REG_CLIENT0() argument
276 return ((val) << MDP5_MDP_SMP_ALLOC_R_REG_CLIENT0__SHIFT) & MDP5_MDP_SMP_ALLOC_R_REG_CLIENT0__MASK; MDP5_MDP_SMP_ALLOC_R_REG_CLIENT0()
280 static inline uint32_t MDP5_MDP_SMP_ALLOC_R_REG_CLIENT1(uint32_t val) MDP5_MDP_SMP_ALLOC_R_REG_CLIENT1() argument
282 return ((val) << MDP5_MDP_SMP_ALLOC_R_REG_CLIENT1__SHIFT) & MDP5_MDP_SMP_ALLOC_R_REG_CLIENT1__MASK; MDP5_MDP_SMP_ALLOC_R_REG_CLIENT1()
286 static inline uint32_t MDP5_MDP_SMP_ALLOC_R_REG_CLIENT2(uint32_t val) MDP5_MDP_SMP_ALLOC_R_REG_CLIENT2() argument
288 return ((val) << MDP5_MDP_SMP_ALLOC_R_REG_CLIENT2__SHIFT) & MDP5_MDP_SMP_ALLOC_R_REG_CLIENT2__MASK; MDP5_MDP_SMP_ALLOC_R_REG_CLIENT2()
308 static inline uint32_t MDP5_MDP_IGC_LUT_REG_VAL(uint32_t val) MDP5_MDP_IGC_LUT_REG_VAL() argument
310 return ((val) << MDP5_MDP_IGC_LUT_REG_VAL__SHIFT) & MDP5_MDP_IGC_LUT_REG_VAL__MASK; MDP5_MDP_IGC_LUT_REG_VAL()
361 static inline uint32_t MDP5_CTL_LAYER_REG_VIG0(enum mdp_mixer_stage_id val) MDP5_CTL_LAYER_REG_VIG0() argument
363 return ((val) << MDP5_CTL_LAYER_REG_VIG0__SHIFT) & MDP5_CTL_LAYER_REG_VIG0__MASK; MDP5_CTL_LAYER_REG_VIG0()
367 static inline uint32_t MDP5_CTL_LAYER_REG_VIG1(enum mdp_mixer_stage_id val) MDP5_CTL_LAYER_REG_VIG1() argument
369 return ((val) << MDP5_CTL_LAYER_REG_VIG1__SHIFT) & MDP5_CTL_LAYER_REG_VIG1__MASK; MDP5_CTL_LAYER_REG_VIG1()
373 static inline uint32_t MDP5_CTL_LAYER_REG_VIG2(enum mdp_mixer_stage_id val) MDP5_CTL_LAYER_REG_VIG2() argument
375 return ((val) << MDP5_CTL_LAYER_REG_VIG2__SHIFT) & MDP5_CTL_LAYER_REG_VIG2__MASK; MDP5_CTL_LAYER_REG_VIG2()
379 static inline uint32_t MDP5_CTL_LAYER_REG_RGB0(enum mdp_mixer_stage_id val) MDP5_CTL_LAYER_REG_RGB0() argument
381 return ((val) << MDP5_CTL_LAYER_REG_RGB0__SHIFT) & MDP5_CTL_LAYER_REG_RGB0__MASK; MDP5_CTL_LAYER_REG_RGB0()
385 static inline uint32_t MDP5_CTL_LAYER_REG_RGB1(enum mdp_mixer_stage_id val) MDP5_CTL_LAYER_REG_RGB1() argument
387 return ((val) << MDP5_CTL_LAYER_REG_RGB1__SHIFT) & MDP5_CTL_LAYER_REG_RGB1__MASK; MDP5_CTL_LAYER_REG_RGB1()
391 static inline uint32_t MDP5_CTL_LAYER_REG_RGB2(enum mdp_mixer_stage_id val) MDP5_CTL_LAYER_REG_RGB2() argument
393 return ((val) << MDP5_CTL_LAYER_REG_RGB2__SHIFT) & MDP5_CTL_LAYER_REG_RGB2__MASK; MDP5_CTL_LAYER_REG_RGB2()
397 static inline uint32_t MDP5_CTL_LAYER_REG_DMA0(enum mdp_mixer_stage_id val) MDP5_CTL_LAYER_REG_DMA0() argument
399 return ((val) << MDP5_CTL_LAYER_REG_DMA0__SHIFT) & MDP5_CTL_LAYER_REG_DMA0__MASK; MDP5_CTL_LAYER_REG_DMA0()
403 static inline uint32_t MDP5_CTL_LAYER_REG_DMA1(enum mdp_mixer_stage_id val) MDP5_CTL_LAYER_REG_DMA1() argument
405 return ((val) << MDP5_CTL_LAYER_REG_DMA1__SHIFT) & MDP5_CTL_LAYER_REG_DMA1__MASK; MDP5_CTL_LAYER_REG_DMA1()
411 static inline uint32_t MDP5_CTL_LAYER_REG_VIG3(enum mdp_mixer_stage_id val) MDP5_CTL_LAYER_REG_VIG3() argument
413 return ((val) << MDP5_CTL_LAYER_REG_VIG3__SHIFT) & MDP5_CTL_LAYER_REG_VIG3__MASK; MDP5_CTL_LAYER_REG_VIG3()
417 static inline uint32_t MDP5_CTL_LAYER_REG_RGB3(enum mdp_mixer_stage_id val) MDP5_CTL_LAYER_REG_RGB3() argument
419 return ((val) << MDP5_CTL_LAYER_REG_RGB3__SHIFT) & MDP5_CTL_LAYER_REG_RGB3__MASK; MDP5_CTL_LAYER_REG_RGB3()
425 static inline uint32_t MDP5_CTL_OP_MODE(enum mdp5_ctl_mode val) MDP5_CTL_OP_MODE() argument
427 return ((val) << MDP5_CTL_OP_MODE__SHIFT) & MDP5_CTL_OP_MODE__MASK; MDP5_CTL_OP_MODE()
431 static inline uint32_t MDP5_CTL_OP_INTF_NUM(enum mdp5_intfnum val) MDP5_CTL_OP_INTF_NUM() argument
433 return ((val) << MDP5_CTL_OP_INTF_NUM__SHIFT) & MDP5_CTL_OP_INTF_NUM__MASK; MDP5_CTL_OP_INTF_NUM()
439 static inline uint32_t MDP5_CTL_OP_PACK_3D(enum mdp5_pack_3d val) MDP5_CTL_OP_PACK_3D() argument
441 return ((val) << MDP5_CTL_OP_PACK_3D__SHIFT) & MDP5_CTL_OP_PACK_3D__MASK; MDP5_CTL_OP_PACK_3D()
500 static inline uint32_t MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT(enum mdp5_data_format val) MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT() argument
502 return ((val) << MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT__SHIFT) & MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT__MASK; MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT()
506 static inline uint32_t MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT(enum mdp5_data_format val) MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT() argument
508 return ((val) << MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT__SHIFT) & MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT__MASK; MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT()
521 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11(uint32_t val) MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11() argument
523 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11__MASK; MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11()
527 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12(uint32_t val) MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12() argument
529 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12__MASK; MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12()
535 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13(uint32_t val) MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13() argument
537 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13__MASK; MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13()
541 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21(uint32_t val) MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21() argument
543 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21__MASK; MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21()
549 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22(uint32_t val) MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22() argument
551 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22__MASK; MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22()
555 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23(uint32_t val) MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23() argument
557 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23__MASK; MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23()
563 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31(uint32_t val) MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31() argument
565 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31__MASK; MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31()
569 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32(uint32_t val) MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32() argument
571 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32__MASK; MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32()
577 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33(uint32_t val) MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33() argument
579 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33__MASK; MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33()
587 static inline uint32_t MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH(uint32_t val) MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH() argument
589 return ((val) << MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH__SHIFT) & MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH__MASK; MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH()
593 static inline uint32_t MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW(uint32_t val) MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW() argument
595 return ((val) << MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW__SHIFT) & MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW__MASK; MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW()
603 static inline uint32_t MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH(uint32_t val) MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH() argument
605 return ((val) << MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH__SHIFT) & MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH__MASK; MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH()
609 static inline uint32_t MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW(uint32_t val) MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW() argument
611 return ((val) << MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW__SHIFT) & MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW__MASK; MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW()
619 static inline uint32_t MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE(uint32_t val) MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE() argument
621 return ((val) << MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE__SHIFT) & MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE__MASK; MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE()
629 static inline uint32_t MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE(uint32_t val) MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE() argument
631 return ((val) << MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE__SHIFT) & MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE__MASK; MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE()
637 static inline uint32_t MDP5_PIPE_SRC_SIZE_HEIGHT(uint32_t val) MDP5_PIPE_SRC_SIZE_HEIGHT() argument
639 return ((val) << MDP5_PIPE_SRC_SIZE_HEIGHT__SHIFT) & MDP5_PIPE_SRC_SIZE_HEIGHT__MASK; MDP5_PIPE_SRC_SIZE_HEIGHT()
643 static inline uint32_t MDP5_PIPE_SRC_SIZE_WIDTH(uint32_t val) MDP5_PIPE_SRC_SIZE_WIDTH() argument
645 return ((val) << MDP5_PIPE_SRC_SIZE_WIDTH__SHIFT) & MDP5_PIPE_SRC_SIZE_WIDTH__MASK; MDP5_PIPE_SRC_SIZE_WIDTH()
651 static inline uint32_t MDP5_PIPE_SRC_IMG_SIZE_HEIGHT(uint32_t val) MDP5_PIPE_SRC_IMG_SIZE_HEIGHT() argument
653 return ((val) << MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__SHIFT) & MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__MASK; MDP5_PIPE_SRC_IMG_SIZE_HEIGHT()
657 static inline uint32_t MDP5_PIPE_SRC_IMG_SIZE_WIDTH(uint32_t val) MDP5_PIPE_SRC_IMG_SIZE_WIDTH() argument
659 return ((val) << MDP5_PIPE_SRC_IMG_SIZE_WIDTH__SHIFT) & MDP5_PIPE_SRC_IMG_SIZE_WIDTH__MASK; MDP5_PIPE_SRC_IMG_SIZE_WIDTH()
665 static inline uint32_t MDP5_PIPE_SRC_XY_Y(uint32_t val) MDP5_PIPE_SRC_XY_Y() argument
667 return ((val) << MDP5_PIPE_SRC_XY_Y__SHIFT) & MDP5_PIPE_SRC_XY_Y__MASK; MDP5_PIPE_SRC_XY_Y()
671 static inline uint32_t MDP5_PIPE_SRC_XY_X(uint32_t val) MDP5_PIPE_SRC_XY_X() argument
673 return ((val) << MDP5_PIPE_SRC_XY_X__SHIFT) & MDP5_PIPE_SRC_XY_X__MASK; MDP5_PIPE_SRC_XY_X()
679 static inline uint32_t MDP5_PIPE_OUT_SIZE_HEIGHT(uint32_t val) MDP5_PIPE_OUT_SIZE_HEIGHT() argument
681 return ((val) << MDP5_PIPE_OUT_SIZE_HEIGHT__SHIFT) & MDP5_PIPE_OUT_SIZE_HEIGHT__MASK; MDP5_PIPE_OUT_SIZE_HEIGHT()
685 static inline uint32_t MDP5_PIPE_OUT_SIZE_WIDTH(uint32_t val) MDP5_PIPE_OUT_SIZE_WIDTH() argument
687 return ((val) << MDP5_PIPE_OUT_SIZE_WIDTH__SHIFT) & MDP5_PIPE_OUT_SIZE_WIDTH__MASK; MDP5_PIPE_OUT_SIZE_WIDTH()
693 static inline uint32_t MDP5_PIPE_OUT_XY_Y(uint32_t val) MDP5_PIPE_OUT_XY_Y() argument
695 return ((val) << MDP5_PIPE_OUT_XY_Y__SHIFT) & MDP5_PIPE_OUT_XY_Y__MASK; MDP5_PIPE_OUT_XY_Y()
699 static inline uint32_t MDP5_PIPE_OUT_XY_X(uint32_t val) MDP5_PIPE_OUT_XY_X() argument
701 return ((val) << MDP5_PIPE_OUT_XY_X__SHIFT) & MDP5_PIPE_OUT_XY_X__MASK; MDP5_PIPE_OUT_XY_X()
715 static inline uint32_t MDP5_PIPE_SRC_STRIDE_A_P0(uint32_t val) MDP5_PIPE_SRC_STRIDE_A_P0() argument
717 return ((val) << MDP5_PIPE_SRC_STRIDE_A_P0__SHIFT) & MDP5_PIPE_SRC_STRIDE_A_P0__MASK; MDP5_PIPE_SRC_STRIDE_A_P0()
721 static inline uint32_t MDP5_PIPE_SRC_STRIDE_A_P1(uint32_t val) MDP5_PIPE_SRC_STRIDE_A_P1() argument
723 return ((val) << MDP5_PIPE_SRC_STRIDE_A_P1__SHIFT) & MDP5_PIPE_SRC_STRIDE_A_P1__MASK; MDP5_PIPE_SRC_STRIDE_A_P1()
729 static inline uint32_t MDP5_PIPE_SRC_STRIDE_B_P2(uint32_t val) MDP5_PIPE_SRC_STRIDE_B_P2() argument
731 return ((val) << MDP5_PIPE_SRC_STRIDE_B_P2__SHIFT) & MDP5_PIPE_SRC_STRIDE_B_P2__MASK; MDP5_PIPE_SRC_STRIDE_B_P2()
735 static inline uint32_t MDP5_PIPE_SRC_STRIDE_B_P3(uint32_t val) MDP5_PIPE_SRC_STRIDE_B_P3() argument
737 return ((val) << MDP5_PIPE_SRC_STRIDE_B_P3__SHIFT) & MDP5_PIPE_SRC_STRIDE_B_P3__MASK; MDP5_PIPE_SRC_STRIDE_B_P3()
745 static inline uint32_t MDP5_PIPE_SRC_FORMAT_G_BPC(enum mdp_bpc val) MDP5_PIPE_SRC_FORMAT_G_BPC() argument
747 return ((val) << MDP5_PIPE_SRC_FORMAT_G_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_G_BPC__MASK; MDP5_PIPE_SRC_FORMAT_G_BPC()
751 static inline uint32_t MDP5_PIPE_SRC_FORMAT_B_BPC(enum mdp_bpc val) MDP5_PIPE_SRC_FORMAT_B_BPC() argument
753 return ((val) << MDP5_PIPE_SRC_FORMAT_B_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_B_BPC__MASK; MDP5_PIPE_SRC_FORMAT_B_BPC()
757 static inline uint32_t MDP5_PIPE_SRC_FORMAT_R_BPC(enum mdp_bpc val) MDP5_PIPE_SRC_FORMAT_R_BPC() argument
759 return ((val) << MDP5_PIPE_SRC_FORMAT_R_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_R_BPC__MASK; MDP5_PIPE_SRC_FORMAT_R_BPC()
763 static inline uint32_t MDP5_PIPE_SRC_FORMAT_A_BPC(enum mdp_bpc_alpha val) MDP5_PIPE_SRC_FORMAT_A_BPC() argument
765 return ((val) << MDP5_PIPE_SRC_FORMAT_A_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_A_BPC__MASK; MDP5_PIPE_SRC_FORMAT_A_BPC()
770 static inline uint32_t MDP5_PIPE_SRC_FORMAT_CPP(uint32_t val) MDP5_PIPE_SRC_FORMAT_CPP() argument
772 return ((val) << MDP5_PIPE_SRC_FORMAT_CPP__SHIFT) & MDP5_PIPE_SRC_FORMAT_CPP__MASK; MDP5_PIPE_SRC_FORMAT_CPP()
777 static inline uint32_t MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(uint32_t val) MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT() argument
779 return ((val) << MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT) & MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK; MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT()
785 static inline uint32_t MDP5_PIPE_SRC_FORMAT_NUM_PLANES(enum mdp_sspp_fetch_type val) MDP5_PIPE_SRC_FORMAT_NUM_PLANES() argument
787 return ((val) << MDP5_PIPE_SRC_FORMAT_NUM_PLANES__SHIFT) & MDP5_PIPE_SRC_FORMAT_NUM_PLANES__MASK; MDP5_PIPE_SRC_FORMAT_NUM_PLANES()
791 static inline uint32_t MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(enum mdp_chroma_samp_type val) MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP() argument
793 return ((val) << MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT) & MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK; MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP()
799 static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM0(uint32_t val) MDP5_PIPE_SRC_UNPACK_ELEM0() argument
801 return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM0__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM0__MASK; MDP5_PIPE_SRC_UNPACK_ELEM0()
805 static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM1(uint32_t val) MDP5_PIPE_SRC_UNPACK_ELEM1() argument
807 return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM1__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM1__MASK; MDP5_PIPE_SRC_UNPACK_ELEM1()
811 static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM2(uint32_t val) MDP5_PIPE_SRC_UNPACK_ELEM2() argument
813 return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM2__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM2__MASK; MDP5_PIPE_SRC_UNPACK_ELEM2()
817 static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM3(uint32_t val) MDP5_PIPE_SRC_UNPACK_ELEM3() argument
819 return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM3__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM3__MASK; MDP5_PIPE_SRC_UNPACK_ELEM3()
826 static inline uint32_t MDP5_PIPE_SRC_OP_MODE_BWC(enum mdp5_pipe_bwc val) MDP5_PIPE_SRC_OP_MODE_BWC() argument
828 return ((val) << MDP5_PIPE_SRC_OP_MODE_BWC__SHIFT) & MDP5_PIPE_SRC_OP_MODE_BWC__MASK; MDP5_PIPE_SRC_OP_MODE_BWC()
863 static inline uint32_t MDP5_PIPE_DECIMATION_VERT(uint32_t val) MDP5_PIPE_DECIMATION_VERT() argument
865 return ((val) << MDP5_PIPE_DECIMATION_VERT__SHIFT) & MDP5_PIPE_DECIMATION_VERT__MASK; MDP5_PIPE_DECIMATION_VERT()
869 static inline uint32_t MDP5_PIPE_DECIMATION_HORZ(uint32_t val) MDP5_PIPE_DECIMATION_HORZ() argument
871 return ((val) << MDP5_PIPE_DECIMATION_HORZ__SHIFT) & MDP5_PIPE_DECIMATION_HORZ__MASK; MDP5_PIPE_DECIMATION_HORZ()
879 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_MIN_FILTER(enum mdp5_scale_filter val) MDP5_PIPE_SCALE_CONFIG_SCALEX_MIN_FILTER() argument
881 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEX_MIN_FILTER__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEX_MIN_FILTER__MASK; MDP5_PIPE_SCALE_CONFIG_SCALEX_MIN_FILTER()
885 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_MIN_FILTER(enum mdp5_scale_filter val) MDP5_PIPE_SCALE_CONFIG_SCALEY_MIN_FILTER() argument
887 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEY_MIN_FILTER__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEY_MIN_FILTER__MASK; MDP5_PIPE_SCALE_CONFIG_SCALEY_MIN_FILTER()
891 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_CR_FILTER(enum mdp5_scale_filter val) MDP5_PIPE_SCALE_CONFIG_SCALEX_CR_FILTER() argument
893 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEX_CR_FILTER__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEX_CR_FILTER__MASK; MDP5_PIPE_SCALE_CONFIG_SCALEX_CR_FILTER()
897 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_CR_FILTER(enum mdp5_scale_filter val) MDP5_PIPE_SCALE_CONFIG_SCALEY_CR_FILTER() argument
899 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEY_CR_FILTER__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEY_CR_FILTER__MASK; MDP5_PIPE_SCALE_CONFIG_SCALEY_CR_FILTER()
903 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_MAX_FILTER(enum mdp5_scale_filter val) MDP5_PIPE_SCALE_CONFIG_SCALEX_MAX_FILTER() argument
905 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEX_MAX_FILTER__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEX_MAX_FILTER__MASK; MDP5_PIPE_SCALE_CONFIG_SCALEX_MAX_FILTER()
909 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_MAX_FILTER(enum mdp5_scale_filter val) MDP5_PIPE_SCALE_CONFIG_SCALEY_MAX_FILTER() argument
911 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEY_MAX_FILTER__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEY_MAX_FILTER__MASK; MDP5_PIPE_SCALE_CONFIG_SCALEY_MAX_FILTER()
949 static inline uint32_t MDP5_LM_OUT_SIZE_HEIGHT(uint32_t val) MDP5_LM_OUT_SIZE_HEIGHT() argument
951 return ((val) << MDP5_LM_OUT_SIZE_HEIGHT__SHIFT) & MDP5_LM_OUT_SIZE_HEIGHT__MASK; MDP5_LM_OUT_SIZE_HEIGHT()
955 static inline uint32_t MDP5_LM_OUT_SIZE_WIDTH(uint32_t val) MDP5_LM_OUT_SIZE_WIDTH() argument
957 return ((val) << MDP5_LM_OUT_SIZE_WIDTH__SHIFT) & MDP5_LM_OUT_SIZE_WIDTH__MASK; MDP5_LM_OUT_SIZE_WIDTH()
969 static inline uint32_t MDP5_LM_BLEND_OP_MODE_FG_ALPHA(enum mdp_alpha_type val) MDP5_LM_BLEND_OP_MODE_FG_ALPHA() argument
971 return ((val) << MDP5_LM_BLEND_OP_MODE_FG_ALPHA__SHIFT) & MDP5_LM_BLEND_OP_MODE_FG_ALPHA__MASK; MDP5_LM_BLEND_OP_MODE_FG_ALPHA()
979 static inline uint32_t MDP5_LM_BLEND_OP_MODE_BG_ALPHA(enum mdp_alpha_type val) MDP5_LM_BLEND_OP_MODE_BG_ALPHA() argument
981 return ((val) << MDP5_LM_BLEND_OP_MODE_BG_ALPHA__SHIFT) & MDP5_LM_BLEND_OP_MODE_BG_ALPHA__MASK; MDP5_LM_BLEND_OP_MODE_BG_ALPHA()
1011 static inline uint32_t MDP5_LM_CURSOR_IMG_SIZE_SRC_W(uint32_t val) MDP5_LM_CURSOR_IMG_SIZE_SRC_W() argument
1013 return ((val) << MDP5_LM_CURSOR_IMG_SIZE_SRC_W__SHIFT) & MDP5_LM_CURSOR_IMG_SIZE_SRC_W__MASK; MDP5_LM_CURSOR_IMG_SIZE_SRC_W()
1017 static inline uint32_t MDP5_LM_CURSOR_IMG_SIZE_SRC_H(uint32_t val) MDP5_LM_CURSOR_IMG_SIZE_SRC_H() argument
1019 return ((val) << MDP5_LM_CURSOR_IMG_SIZE_SRC_H__SHIFT) & MDP5_LM_CURSOR_IMG_SIZE_SRC_H__MASK; MDP5_LM_CURSOR_IMG_SIZE_SRC_H()
1025 static inline uint32_t MDP5_LM_CURSOR_SIZE_ROI_W(uint32_t val) MDP5_LM_CURSOR_SIZE_ROI_W() argument
1027 return ((val) << MDP5_LM_CURSOR_SIZE_ROI_W__SHIFT) & MDP5_LM_CURSOR_SIZE_ROI_W__MASK; MDP5_LM_CURSOR_SIZE_ROI_W()
1031 static inline uint32_t MDP5_LM_CURSOR_SIZE_ROI_H(uint32_t val) MDP5_LM_CURSOR_SIZE_ROI_H() argument
1033 return ((val) << MDP5_LM_CURSOR_SIZE_ROI_H__SHIFT) & MDP5_LM_CURSOR_SIZE_ROI_H__MASK; MDP5_LM_CURSOR_SIZE_ROI_H()
1039 static inline uint32_t MDP5_LM_CURSOR_XY_SRC_X(uint32_t val) MDP5_LM_CURSOR_XY_SRC_X() argument
1041 return ((val) << MDP5_LM_CURSOR_XY_SRC_X__SHIFT) & MDP5_LM_CURSOR_XY_SRC_X__MASK; MDP5_LM_CURSOR_XY_SRC_X()
1045 static inline uint32_t MDP5_LM_CURSOR_XY_SRC_Y(uint32_t val) MDP5_LM_CURSOR_XY_SRC_Y() argument
1047 return ((val) << MDP5_LM_CURSOR_XY_SRC_Y__SHIFT) & MDP5_LM_CURSOR_XY_SRC_Y__MASK; MDP5_LM_CURSOR_XY_SRC_Y()
1053 static inline uint32_t MDP5_LM_CURSOR_STRIDE_STRIDE(uint32_t val) MDP5_LM_CURSOR_STRIDE_STRIDE() argument
1055 return ((val) << MDP5_LM_CURSOR_STRIDE_STRIDE__SHIFT) & MDP5_LM_CURSOR_STRIDE_STRIDE__MASK; MDP5_LM_CURSOR_STRIDE_STRIDE()
1061 static inline uint32_t MDP5_LM_CURSOR_FORMAT_FORMAT(enum mdp5_cursor_format val) MDP5_LM_CURSOR_FORMAT_FORMAT() argument
1063 return ((val) << MDP5_LM_CURSOR_FORMAT_FORMAT__SHIFT) & MDP5_LM_CURSOR_FORMAT_FORMAT__MASK; MDP5_LM_CURSOR_FORMAT_FORMAT()
1071 static inline uint32_t MDP5_LM_CURSOR_START_XY_X_START(uint32_t val) MDP5_LM_CURSOR_START_XY_X_START() argument
1073 return ((val) << MDP5_LM_CURSOR_START_XY_X_START__SHIFT) & MDP5_LM_CURSOR_START_XY_X_START__MASK; MDP5_LM_CURSOR_START_XY_X_START()
1077 static inline uint32_t MDP5_LM_CURSOR_START_XY_Y_START(uint32_t val) MDP5_LM_CURSOR_START_XY_Y_START() argument
1079 return ((val) << MDP5_LM_CURSOR_START_XY_Y_START__SHIFT) & MDP5_LM_CURSOR_START_XY_Y_START__MASK; MDP5_LM_CURSOR_START_XY_Y_START()
1086 static inline uint32_t MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL(enum mdp5_cursor_alpha val) MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL() argument
1088 return ((val) << MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL__SHIFT) & MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL__MASK; MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL()
1120 static inline uint32_t MDP5_DSPP_OP_MODE_IGC_TBL_IDX(uint32_t val) MDP5_DSPP_OP_MODE_IGC_TBL_IDX() argument
1122 return ((val) << MDP5_DSPP_OP_MODE_IGC_TBL_IDX__SHIFT) & MDP5_DSPP_OP_MODE_IGC_TBL_IDX__MASK; MDP5_DSPP_OP_MODE_IGC_TBL_IDX()
1166 static inline uint32_t MDP5_PP_SYNC_CONFIG_VSYNC_COUNT(uint32_t val) MDP5_PP_SYNC_CONFIG_VSYNC_COUNT() argument
1168 return ((val) << MDP5_PP_SYNC_CONFIG_VSYNC_COUNT__SHIFT) & MDP5_PP_SYNC_CONFIG_VSYNC_COUNT__MASK; MDP5_PP_SYNC_CONFIG_VSYNC_COUNT()
1178 static inline uint32_t MDP5_PP_SYNC_WRCOUNT_LINE_COUNT(uint32_t val) MDP5_PP_SYNC_WRCOUNT_LINE_COUNT() argument
1180 return ((val) << MDP5_PP_SYNC_WRCOUNT_LINE_COUNT__SHIFT) & MDP5_PP_SYNC_WRCOUNT_LINE_COUNT__MASK; MDP5_PP_SYNC_WRCOUNT_LINE_COUNT()
1184 static inline uint32_t MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT(uint32_t val) MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT() argument
1186 return ((val) << MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT__SHIFT) & MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT__MASK; MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT()
1194 static inline uint32_t MDP5_PP_INT_COUNT_VAL_LINE_COUNT(uint32_t val) MDP5_PP_INT_COUNT_VAL_LINE_COUNT() argument
1196 return ((val) << MDP5_PP_INT_COUNT_VAL_LINE_COUNT__SHIFT) & MDP5_PP_INT_COUNT_VAL_LINE_COUNT__MASK; MDP5_PP_INT_COUNT_VAL_LINE_COUNT()
1200 static inline uint32_t MDP5_PP_INT_COUNT_VAL_FRAME_COUNT(uint32_t val) MDP5_PP_INT_COUNT_VAL_FRAME_COUNT() argument
1202 return ((val) << MDP5_PP_INT_COUNT_VAL_FRAME_COUNT__SHIFT) & MDP5_PP_INT_COUNT_VAL_FRAME_COUNT__MASK; MDP5_PP_INT_COUNT_VAL_FRAME_COUNT()
1208 static inline uint32_t MDP5_PP_SYNC_THRESH_START(uint32_t val) MDP5_PP_SYNC_THRESH_START() argument
1210 return ((val) << MDP5_PP_SYNC_THRESH_START__SHIFT) & MDP5_PP_SYNC_THRESH_START__MASK; MDP5_PP_SYNC_THRESH_START()
1214 static inline uint32_t MDP5_PP_SYNC_THRESH_CONTINUE(uint32_t val) MDP5_PP_SYNC_THRESH_CONTINUE() argument
1216 return ((val) << MDP5_PP_SYNC_THRESH_CONTINUE__SHIFT) & MDP5_PP_SYNC_THRESH_CONTINUE__MASK; MDP5_PP_SYNC_THRESH_CONTINUE()
1257 static inline uint32_t MDP5_INTF_HSYNC_CTL_PULSEW(uint32_t val) MDP5_INTF_HSYNC_CTL_PULSEW() argument
1259 return ((val) << MDP5_INTF_HSYNC_CTL_PULSEW__SHIFT) & MDP5_INTF_HSYNC_CTL_PULSEW__MASK; MDP5_INTF_HSYNC_CTL_PULSEW()
1263 static inline uint32_t MDP5_INTF_HSYNC_CTL_PERIOD(uint32_t val) MDP5_INTF_HSYNC_CTL_PERIOD() argument
1265 return ((val) << MDP5_INTF_HSYNC_CTL_PERIOD__SHIFT) & MDP5_INTF_HSYNC_CTL_PERIOD__MASK; MDP5_INTF_HSYNC_CTL_PERIOD()
1287 static inline uint32_t MDP5_INTF_ACTIVE_VSTART_F0_VAL(uint32_t val) MDP5_INTF_ACTIVE_VSTART_F0_VAL() argument
1289 return ((val) << MDP5_INTF_ACTIVE_VSTART_F0_VAL__SHIFT) & MDP5_INTF_ACTIVE_VSTART_F0_VAL__MASK; MDP5_INTF_ACTIVE_VSTART_F0_VAL()
1296 static inline uint32_t MDP5_INTF_ACTIVE_VSTART_F1_VAL(uint32_t val) MDP5_INTF_ACTIVE_VSTART_F1_VAL() argument
1298 return ((val) << MDP5_INTF_ACTIVE_VSTART_F1_VAL__SHIFT) & MDP5_INTF_ACTIVE_VSTART_F1_VAL__MASK; MDP5_INTF_ACTIVE_VSTART_F1_VAL()
1308 static inline uint32_t MDP5_INTF_DISPLAY_HCTL_START(uint32_t val) MDP5_INTF_DISPLAY_HCTL_START() argument
1310 return ((val) << MDP5_INTF_DISPLAY_HCTL_START__SHIFT) & MDP5_INTF_DISPLAY_HCTL_START__MASK; MDP5_INTF_DISPLAY_HCTL_START()
1314 static inline uint32_t MDP5_INTF_DISPLAY_HCTL_END(uint32_t val) MDP5_INTF_DISPLAY_HCTL_END() argument
1316 return ((val) << MDP5_INTF_DISPLAY_HCTL_END__SHIFT) & MDP5_INTF_DISPLAY_HCTL_END__MASK; MDP5_INTF_DISPLAY_HCTL_END()
1322 static inline uint32_t MDP5_INTF_ACTIVE_HCTL_START(uint32_t val) MDP5_INTF_ACTIVE_HCTL_START() argument
1324 return ((val) << MDP5_INTF_ACTIVE_HCTL_START__SHIFT) & MDP5_INTF_ACTIVE_HCTL_START__MASK; MDP5_INTF_ACTIVE_HCTL_START()
1328 static inline uint32_t MDP5_INTF_ACTIVE_HCTL_END(uint32_t val) MDP5_INTF_ACTIVE_HCTL_END() argument
1330 return ((val) << MDP5_INTF_ACTIVE_HCTL_END__SHIFT) & MDP5_INTF_ACTIVE_HCTL_END__MASK; MDP5_INTF_ACTIVE_HCTL_END()
/linux-4.1.27/arch/powerpc/platforms/cell/
H A Dpmu.c55 #define READ_SHADOW_REG(val, reg) \
59 (val) = shadow_regs->reg; \
62 #define READ_MMIO_UPPER32(val, reg) \
66 (val) = (u32)(in_be64(&pmd_regs->reg) >> 32); \
76 u32 val_in_latch, val = 0; cbe_read_phys_ctr() local
83 READ_SHADOW_REG(val, pm_ctr[phys_ctr]); cbe_read_phys_ctr()
85 READ_MMIO_UPPER32(val, pm_ctr[phys_ctr]); cbe_read_phys_ctr()
89 return val; cbe_read_phys_ctr()
93 void cbe_write_phys_ctr(u32 cpu, u32 phys_ctr, u32 val) cbe_write_phys_ctr() argument
103 WRITE_WO_MMIO(pm_ctr[phys_ctr], val); cbe_write_phys_ctr()
128 u32 val; cbe_read_ctr() local
131 val = cbe_read_phys_ctr(cpu, phys_ctr); cbe_read_ctr()
134 val = (ctr < NR_PHYS_CTRS) ? (val >> 16) : (val & 0xffff); cbe_read_ctr()
136 return val; cbe_read_ctr()
140 void cbe_write_ctr(u32 cpu, u32 ctr, u32 val) cbe_write_ctr() argument
151 val = (val << 16) | (phys_val & 0xffff); cbe_write_ctr()
153 val = (val & 0xffff) | (phys_val & 0xffff0000); cbe_write_ctr()
156 cbe_write_phys_ctr(cpu, phys_ctr, val); cbe_write_ctr()
176 void cbe_write_pm07_control(u32 cpu, u32 ctr, u32 val) cbe_write_pm07_control() argument
179 WRITE_WO_MMIO(pm07_control[ctr], val); cbe_write_pm07_control()
189 u32 val = 0; cbe_read_pm() local
193 READ_SHADOW_REG(val, group_control); cbe_read_pm()
197 READ_SHADOW_REG(val, debug_bus_control); cbe_read_pm()
201 READ_MMIO_UPPER32(val, trace_address); cbe_read_pm()
205 READ_SHADOW_REG(val, ext_tr_timer); cbe_read_pm()
209 READ_MMIO_UPPER32(val, pm_status); cbe_read_pm()
213 READ_SHADOW_REG(val, pm_control); cbe_read_pm()
217 READ_MMIO_UPPER32(val, pm_interval); cbe_read_pm()
221 READ_SHADOW_REG(val, pm_start_stop); cbe_read_pm()
225 return val; cbe_read_pm()
229 void cbe_write_pm(u32 cpu, enum pm_reg_name reg, u32 val) cbe_write_pm() argument
233 WRITE_WO_MMIO(group_control, val); cbe_write_pm()
237 WRITE_WO_MMIO(debug_bus_control, val); cbe_write_pm()
241 WRITE_WO_MMIO(trace_address, val); cbe_write_pm()
245 WRITE_WO_MMIO(ext_tr_timer, val); cbe_write_pm()
249 WRITE_WO_MMIO(pm_status, val); cbe_write_pm()
253 WRITE_WO_MMIO(pm_control, val); cbe_write_pm()
257 WRITE_WO_MMIO(pm_interval, val); cbe_write_pm()
261 WRITE_WO_MMIO(pm_start_stop, val); cbe_write_pm()
/linux-4.1.27/drivers/mfd/
H A Dpcf50633-gpio.c38 int pcf50633_gpio_set(struct pcf50633 *pcf, int gpio, u8 val) pcf50633_gpio_set() argument
44 return pcf50633_reg_set_bit_mask(pcf, reg, 0x07, val); pcf50633_gpio_set()
50 u8 reg, val; pcf50633_gpio_get() local
53 val = pcf50633_reg_read(pcf, reg) & 0x07; pcf50633_gpio_get()
55 return val; pcf50633_gpio_get()
61 u8 val, reg; pcf50633_gpio_invert_set() local
64 val = !!invert << 3; pcf50633_gpio_invert_set()
66 return pcf50633_reg_set_bit_mask(pcf, reg, 1 << 3, val); pcf50633_gpio_invert_set()
72 u8 reg, val; pcf50633_gpio_invert_get() local
75 val = pcf50633_reg_read(pcf, reg); pcf50633_gpio_invert_get()
77 return val & (1 << 3); pcf50633_gpio_invert_get()
84 u8 reg, val, mask; pcf50633_gpio_power_supply_set() local
89 val = !!on << (gpio - PCF50633_GPIO1); pcf50633_gpio_power_supply_set()
92 return pcf50633_reg_set_bit_mask(pcf, reg, mask, val); pcf50633_gpio_power_supply_set()
/linux-4.1.27/arch/arm/include/asm/
H A Darch_timer.h21 void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val) arch_timer_reg_write_cp15() argument
26 asm volatile("mcr p15, 0, %0, c14, c2, 1" : : "r" (val)); arch_timer_reg_write_cp15()
29 asm volatile("mcr p15, 0, %0, c14, c2, 0" : : "r" (val)); arch_timer_reg_write_cp15()
35 asm volatile("mcr p15, 0, %0, c14, c3, 1" : : "r" (val)); arch_timer_reg_write_cp15()
38 asm volatile("mcr p15, 0, %0, c14, c3, 0" : : "r" (val)); arch_timer_reg_write_cp15()
49 u32 val = 0; arch_timer_reg_read_cp15() local
54 asm volatile("mrc p15, 0, %0, c14, c2, 1" : "=r" (val)); arch_timer_reg_read_cp15()
57 asm volatile("mrc p15, 0, %0, c14, c2, 0" : "=r" (val)); arch_timer_reg_read_cp15()
63 asm volatile("mrc p15, 0, %0, c14, c3, 1" : "=r" (val)); arch_timer_reg_read_cp15()
66 asm volatile("mrc p15, 0, %0, c14, c3, 0" : "=r" (val)); arch_timer_reg_read_cp15()
71 return val; arch_timer_reg_read_cp15()
76 u32 val; arch_timer_get_cntfrq() local
77 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (val)); arch_timer_get_cntfrq()
78 return val; arch_timer_get_cntfrq()
/linux-4.1.27/arch/arm/mach-netx/
H A Dgeneric.c94 unsigned int val, irq; netx_hif_irq_type() local
96 val = readl(NETX_DPMAS_IF_CONF1); netx_hif_irq_type()
102 val |= (1 << 26) << irq; netx_hif_irq_type()
106 val &= ~((1 << 26) << irq); netx_hif_irq_type()
110 val &= ~((1 << 26) << irq); netx_hif_irq_type()
114 val |= (1 << 26) << irq; netx_hif_irq_type()
117 writel(val, NETX_DPMAS_IF_CONF1); netx_hif_irq_type()
125 unsigned int val, irq; netx_hif_ack_irq() local
130 val = readl(NETX_DPMAS_INT_EN); netx_hif_ack_irq()
131 val &= ~((1 << 24) << irq); netx_hif_ack_irq()
132 writel(val, NETX_DPMAS_INT_EN); netx_hif_ack_irq()
140 unsigned int val, irq; netx_hif_mask_irq() local
143 val = readl(NETX_DPMAS_INT_EN); netx_hif_mask_irq()
144 val &= ~((1 << 24) << irq); netx_hif_mask_irq()
145 writel(val, NETX_DPMAS_INT_EN); netx_hif_mask_irq()
152 unsigned int val, irq; netx_hif_unmask_irq() local
155 val = readl(NETX_DPMAS_INT_EN); netx_hif_unmask_irq()
156 val |= (1 << 24) << irq; netx_hif_unmask_irq()
157 writel(val, NETX_DPMAS_INT_EN); netx_hif_unmask_irq()
/linux-4.1.27/arch/arm/kernel/
H A Dperf_event_xscale.c99 u32 val; xscale1pmu_read_pmnc() local
100 asm volatile("mrc p14, 0, %0, c0, c0, 0" : "=r" (val)); xscale1pmu_read_pmnc()
101 return val; xscale1pmu_read_pmnc()
105 xscale1pmu_write_pmnc(u32 val) xscale1pmu_write_pmnc() argument
108 val &= 0xffff77f; xscale1pmu_write_pmnc()
109 asm volatile("mcr p14, 0, %0, c0, c0, 0" : : "r" (val)); xscale1pmu_write_pmnc()
198 unsigned long val, mask, evt, flags; xscale1pmu_enable_event() local
225 val = xscale1pmu_read_pmnc(); xscale1pmu_enable_event()
226 val &= ~mask; xscale1pmu_enable_event()
227 val |= evt; xscale1pmu_enable_event()
228 xscale1pmu_write_pmnc(val); xscale1pmu_enable_event()
234 unsigned long val, mask, evt, flags; xscale1pmu_disable_event() local
259 val = xscale1pmu_read_pmnc(); xscale1pmu_disable_event()
260 val &= ~mask; xscale1pmu_disable_event()
261 val |= evt; xscale1pmu_disable_event()
262 xscale1pmu_write_pmnc(val); xscale1pmu_disable_event()
289 unsigned long flags, val; xscale1pmu_start() local
293 val = xscale1pmu_read_pmnc(); xscale1pmu_start()
294 val |= XSCALE_PMU_ENABLE; xscale1pmu_start()
295 xscale1pmu_write_pmnc(val); xscale1pmu_start()
301 unsigned long flags, val; xscale1pmu_stop() local
305 val = xscale1pmu_read_pmnc(); xscale1pmu_stop()
306 val &= ~XSCALE_PMU_ENABLE; xscale1pmu_stop()
307 xscale1pmu_write_pmnc(val); xscale1pmu_stop()
315 u32 val = 0; xscale1pmu_read_counter() local
319 asm volatile("mrc p14, 0, %0, c1, c0, 0" : "=r" (val)); xscale1pmu_read_counter()
322 asm volatile("mrc p14, 0, %0, c2, c0, 0" : "=r" (val)); xscale1pmu_read_counter()
325 asm volatile("mrc p14, 0, %0, c3, c0, 0" : "=r" (val)); xscale1pmu_read_counter()
329 return val; xscale1pmu_read_counter()
332 static inline void xscale1pmu_write_counter(struct perf_event *event, u32 val) xscale1pmu_write_counter() argument
339 asm volatile("mcr p14, 0, %0, c1, c0, 0" : : "r" (val)); xscale1pmu_write_counter()
342 asm volatile("mcr p14, 0, %0, c2, c0, 0" : : "r" (val)); xscale1pmu_write_counter()
345 asm volatile("mcr p14, 0, %0, c3, c0, 0" : : "r" (val)); xscale1pmu_write_counter()
397 u32 val; xscale2pmu_read_pmnc() local
398 asm volatile("mrc p14, 0, %0, c0, c1, 0" : "=r" (val)); xscale2pmu_read_pmnc()
400 return val & 0xff000009; xscale2pmu_read_pmnc()
404 xscale2pmu_write_pmnc(u32 val) xscale2pmu_write_pmnc() argument
407 val &= 0xf; xscale2pmu_write_pmnc()
408 asm volatile("mcr p14, 0, %0, c0, c1, 0" : : "r" (val)); xscale2pmu_write_pmnc()
414 u32 val; xscale2pmu_read_overflow_flags() local
415 asm volatile("mrc p14, 0, %0, c5, c1, 0" : "=r" (val)); xscale2pmu_read_overflow_flags()
416 return val; xscale2pmu_read_overflow_flags()
420 xscale2pmu_write_overflow_flags(u32 val) xscale2pmu_write_overflow_flags() argument
422 asm volatile("mcr p14, 0, %0, c5, c1, 0" : : "r" (val)); xscale2pmu_write_overflow_flags()
428 u32 val; xscale2pmu_read_event_select() local
429 asm volatile("mrc p14, 0, %0, c8, c1, 0" : "=r" (val)); xscale2pmu_read_event_select()
430 return val; xscale2pmu_read_event_select()
434 xscale2pmu_write_event_select(u32 val) xscale2pmu_write_event_select() argument
436 asm volatile("mcr p14, 0, %0, c8, c1, 0" : : "r"(val)); xscale2pmu_write_event_select()
442 u32 val; xscale2pmu_read_int_enable() local
443 asm volatile("mrc p14, 0, %0, c4, c1, 0" : "=r" (val)); xscale2pmu_read_int_enable()
444 return val; xscale2pmu_read_int_enable()
448 xscale2pmu_write_int_enable(u32 val) xscale2pmu_write_int_enable() argument
450 asm volatile("mcr p14, 0, %0, c4, c1, 0" : : "r" (val)); xscale2pmu_write_int_enable()
653 unsigned long flags, val; xscale2pmu_start() local
657 val = xscale2pmu_read_pmnc() & ~XSCALE_PMU_CNT64; xscale2pmu_start()
658 val |= XSCALE_PMU_ENABLE; xscale2pmu_start()
659 xscale2pmu_write_pmnc(val); xscale2pmu_start()
665 unsigned long flags, val; xscale2pmu_stop() local
669 val = xscale2pmu_read_pmnc(); xscale2pmu_stop()
670 val &= ~XSCALE_PMU_ENABLE; xscale2pmu_stop()
671 xscale2pmu_write_pmnc(val); xscale2pmu_stop()
679 u32 val = 0; xscale2pmu_read_counter() local
683 asm volatile("mrc p14, 0, %0, c1, c1, 0" : "=r" (val)); xscale2pmu_read_counter()
686 asm volatile("mrc p14, 0, %0, c0, c2, 0" : "=r" (val)); xscale2pmu_read_counter()
689 asm volatile("mrc p14, 0, %0, c1, c2, 0" : "=r" (val)); xscale2pmu_read_counter()
692 asm volatile("mrc p14, 0, %0, c2, c2, 0" : "=r" (val)); xscale2pmu_read_counter()
695 asm volatile("mrc p14, 0, %0, c3, c2, 0" : "=r" (val)); xscale2pmu_read_counter()
699 return val; xscale2pmu_read_counter()
702 static inline void xscale2pmu_write_counter(struct perf_event *event, u32 val) xscale2pmu_write_counter() argument
709 asm volatile("mcr p14, 0, %0, c1, c1, 0" : : "r" (val)); xscale2pmu_write_counter()
712 asm volatile("mcr p14, 0, %0, c0, c2, 0" : : "r" (val)); xscale2pmu_write_counter()
715 asm volatile("mcr p14, 0, %0, c1, c2, 0" : : "r" (val)); xscale2pmu_write_counter()
718 asm volatile("mcr p14, 0, %0, c2, c2, 0" : : "r" (val)); xscale2pmu_write_counter()
721 asm volatile("mcr p14, 0, %0, c3, c2, 0" : : "r" (val)); xscale2pmu_write_counter()
/linux-4.1.27/drivers/media/pci/bt8xx/
H A Dbttv-audio-hook.c78 unsigned int val, con; gvbctv5pci_audio() local
83 val = gpio_read(); gvbctv5pci_audio()
96 if (con != (val & 0x300)) { gvbctv5pci_audio()
102 switch (val & 0x70) { gvbctv5pci_audio()
145 int val = 0; avermedia_tvphone_audio() local
149 val = 0x02; avermedia_tvphone_audio()
151 val = 0x01; avermedia_tvphone_audio()
152 if (val) { avermedia_tvphone_audio()
153 gpio_bits(0x03,val); avermedia_tvphone_audio()
167 int val = 0; avermedia_tv_stereo_audio() local
171 val = 0x01; avermedia_tv_stereo_audio()
173 val = 0x02; avermedia_tv_stereo_audio()
174 btaor(val, ~0x03, BT848_GPIO_DATA); avermedia_tv_stereo_audio()
188 int val = 0; lt9415_audio() local
197 val = 0x0080; lt9415_audio()
199 val = 0x0880; lt9415_audio()
202 val = 0; lt9415_audio()
203 gpio_bits(0x0880, val); lt9415_audio()
237 unsigned long val = 0; winfast2000_audio() local
242 val = 0x420000; winfast2000_audio()
244 val = 0x420000; winfast2000_audio()
246 val = 0x410000; winfast2000_audio()
248 val = 0x020000; winfast2000_audio()
249 if (val) { winfast2000_audio()
250 gpio_bits(0x430000, val); winfast2000_audio()
270 unsigned int val = 0; pvbt878p9b_audio() local
277 val = 0x01; pvbt878p9b_audio()
281 val = 0x02; pvbt878p9b_audio()
283 if (val) { pvbt878p9b_audio()
284 gpio_bits(0x03,val); pvbt878p9b_audio()
301 unsigned int val = 0xffff; fv2000s_audio() local
308 val = 0x0000; fv2000s_audio()
312 val = 0x1080; /*-dk-???: 0x0880, 0x0080, 0x1800 ... */ fv2000s_audio()
314 if (val != 0xffff) { fv2000s_audio()
315 gpio_bits(0x1800, val); fv2000s_audio()
331 unsigned long val = 0; windvr_audio() local
335 val = 0x040000; windvr_audio()
337 val = 0; windvr_audio()
339 val = 0x100000; windvr_audio()
341 val = 0; windvr_audio()
342 if (val) { windvr_audio()
343 gpio_bits(0x140000, val); windvr_audio()
/linux-4.1.27/drivers/hwmon/
H A Dadt7411.c67 int val, tmp; adt7411_read_10_bit() local
71 val = i2c_smbus_read_byte_data(client, lsb_reg); adt7411_read_10_bit()
72 if (val < 0) adt7411_read_10_bit()
75 tmp = (val >> lsb_shift) & 3; adt7411_read_10_bit()
76 val = i2c_smbus_read_byte_data(client, msb_reg); adt7411_read_10_bit()
78 if (val >= 0) adt7411_read_10_bit()
79 val = (val << 2) | tmp; adt7411_read_10_bit()
84 return val; adt7411_read_10_bit()
91 int ret, val; adt7411_modify_bit() local
100 val = ret | bit; adt7411_modify_bit()
102 val = ret & ~bit; adt7411_modify_bit()
104 ret = i2c_smbus_write_byte_data(client, reg, val); adt7411_modify_bit()
127 int val = adt7411_read_10_bit(client, ADT7411_REG_INT_TEMP_VDD_LSB, adt7411_show_temp() local
130 if (val < 0) adt7411_show_temp()
131 return val; adt7411_show_temp()
133 val = val & 0x200 ? val - 0x400 : val; /* 10 bit signed */ adt7411_show_temp()
135 return sprintf(buf, "%d\n", val * 250); adt7411_show_temp()
144 int val; adt7411_show_input() local
149 val = i2c_smbus_read_byte_data(client, ADT7411_REG_CFG3); adt7411_show_input()
150 if (val < 0) adt7411_show_input()
153 if (val & ADT7411_CFG3_REF_VDD) { adt7411_show_input()
154 val = adt7411_read_10_bit(client, adt7411_show_input()
157 if (val < 0) adt7411_show_input()
160 data->vref_cached = val * 7000 / 1024; adt7411_show_input()
170 val = adt7411_read_10_bit(client, lsb_reg, adt7411_show_input()
172 if (val < 0) adt7411_show_input()
175 val = sprintf(buf, "%u\n", val * data->vref_cached / 1024); adt7411_show_input()
178 return val; adt7411_show_input()
256 int val; adt7411_detect() local
261 val = i2c_smbus_read_byte_data(client, ADT7411_REG_MANUFACTURER_ID); adt7411_detect()
262 if (val < 0 || val != ADT7411_MANUFACTURER_ID) { adt7411_detect()
265 val, ADT7411_MANUFACTURER_ID); adt7411_detect()
269 val = i2c_smbus_read_byte_data(client, ADT7411_REG_DEVICE_ID); adt7411_detect()
270 if (val < 0 || val != ADT7411_DEVICE_ID) { adt7411_detect()
273 val, ADT7411_DEVICE_ID); adt7411_detect()
H A Dsch5627.c101 int i, val; sch5627_update_device() local
115 val = sch56xx_read_virtual_reg12(data->addr, sch5627_update_device()
119 if (unlikely(val < 0)) { sch5627_update_device()
120 ret = ERR_PTR(val); sch5627_update_device()
123 data->temp[i] = val; sch5627_update_device()
127 val = sch56xx_read_virtual_reg16(data->addr, sch5627_update_device()
129 if (unlikely(val < 0)) { sch5627_update_device()
130 ret = ERR_PTR(val); sch5627_update_device()
133 data->fan[i] = val; sch5627_update_device()
137 val = sch56xx_read_virtual_reg12(data->addr, sch5627_update_device()
141 if (unlikely(val < 0)) { sch5627_update_device()
142 ret = ERR_PTR(val); sch5627_update_device()
145 data->in[i] = val; sch5627_update_device()
158 int i, val; sch5627_read_limits() local
165 val = sch56xx_read_virtual_reg(data->addr, sch5627_read_limits()
167 if (val < 0) sch5627_read_limits()
168 return val; sch5627_read_limits()
169 data->temp_max[i] = val; sch5627_read_limits()
171 val = sch56xx_read_virtual_reg(data->addr, sch5627_read_limits()
173 if (val < 0) sch5627_read_limits()
174 return val; sch5627_read_limits()
175 data->temp_crit[i] = val; sch5627_read_limits()
178 val = sch56xx_read_virtual_reg16(data->addr, sch5627_read_limits()
180 if (val < 0) sch5627_read_limits()
181 return val; sch5627_read_limits()
182 data->fan_min[i] = val; sch5627_read_limits()
219 int val; show_temp() local
224 val = reg_to_temp(data->temp[attr->index]); show_temp()
225 return snprintf(buf, PAGE_SIZE, "%d\n", val); show_temp()
245 int val; show_temp_max() local
247 val = reg_to_temp_limit(data->temp_max[attr->index]); show_temp_max()
248 return snprintf(buf, PAGE_SIZE, "%d\n", val); show_temp_max()
256 int val; show_temp_crit() local
258 val = reg_to_temp_limit(data->temp_crit[attr->index]); show_temp_crit()
259 return snprintf(buf, PAGE_SIZE, "%d\n", val); show_temp_crit()
267 int val; show_fan() local
272 val = reg_to_rpm(data->fan[attr->index]); show_fan()
273 if (val < 0) show_fan()
274 return val; show_fan()
276 return snprintf(buf, PAGE_SIZE, "%d\n", val); show_fan()
297 int val = reg_to_rpm(data->fan_min[attr->index]); show_fan_min() local
298 if (val < 0) show_fan_min()
299 return val; show_fan_min()
301 return snprintf(buf, PAGE_SIZE, "%d\n", val); show_fan_min()
309 int val; show_in() local
314 val = DIV_ROUND_CLOSEST( show_in()
317 return snprintf(buf, PAGE_SIZE, "%d\n", val); show_in()
471 int err, build_code, build_id, hwmon_rev, val; sch5627_probe() local
482 val = sch56xx_read_virtual_reg(data->addr, SCH5627_REG_HWMON_ID); sch5627_probe()
483 if (val < 0) { sch5627_probe()
484 err = val; sch5627_probe()
487 if (val != SCH5627_HWMON_ID) { sch5627_probe()
489 val, SCH5627_HWMON_ID); sch5627_probe()
494 val = sch56xx_read_virtual_reg(data->addr, SCH5627_REG_COMPANY_ID); sch5627_probe()
495 if (val < 0) { sch5627_probe()
496 err = val; sch5627_probe()
499 if (val != SCH5627_COMPANY_ID) { sch5627_probe()
501 val, SCH5627_COMPANY_ID); sch5627_probe()
506 val = sch56xx_read_virtual_reg(data->addr, SCH5627_REG_PRIMARY_ID); sch5627_probe()
507 if (val < 0) { sch5627_probe()
508 err = val; sch5627_probe()
511 if (val != SCH5627_PRIMARY_ID) { sch5627_probe()
513 val, SCH5627_PRIMARY_ID); sch5627_probe()
539 val = sch56xx_read_virtual_reg(data->addr, SCH5627_REG_CTRL); sch5627_probe()
540 if (val < 0) { sch5627_probe()
541 err = val; sch5627_probe()
544 data->control = val; sch5627_probe()
/linux-4.1.27/drivers/media/dvb-frontends/
H A Dlgdt3306a.c117 static int lgdt3306a_write_reg(struct lgdt3306a_state *state, u16 reg, u8 val) lgdt3306a_write_reg() argument
120 u8 buf[] = { reg >> 8, reg & 0xff, val }; lgdt3306a_write_reg()
126 dbg_reg("reg: 0x%04x, val: 0x%02x\n", reg, val); lgdt3306a_write_reg()
141 static int lgdt3306a_read_reg(struct lgdt3306a_state *state, u16 reg, u8 *val) lgdt3306a_read_reg() argument
149 .flags = I2C_M_RD, .buf = val, .len = 1 }, lgdt3306a_read_reg()
162 dbg_reg("reg: 0x%04x, val: 0x%02x\n", reg, *val); lgdt3306a_read_reg()
179 u8 val; lgdt3306a_set_reg_bit() local
184 ret = lgdt3306a_read_reg(state, reg, &val); lgdt3306a_set_reg_bit()
188 val &= ~(1 << bit); lgdt3306a_set_reg_bit()
189 val |= (onoff & 1) << bit; lgdt3306a_set_reg_bit()
191 ret = lgdt3306a_write_reg(state, reg, val); lgdt3306a_set_reg_bit()
220 u8 val; lgdt3306a_mpeg_mode() local
238 ret = lgdt3306a_read_reg(state, 0x0070, &val); lgdt3306a_mpeg_mode()
242 val |= 0x10; /* TPCLKSUPB=0x10 */ lgdt3306a_mpeg_mode()
245 val &= ~0x10; lgdt3306a_mpeg_mode()
247 ret = lgdt3306a_write_reg(state, 0x0070, val); lgdt3306a_mpeg_mode()
258 u8 val; lgdt3306a_mpeg_mode_polarity() local
263 ret = lgdt3306a_read_reg(state, 0x0070, &val); lgdt3306a_mpeg_mode_polarity()
267 val &= ~0x06; /* TPCLKPOL=0x04, TPVALPOL=0x02 */ lgdt3306a_mpeg_mode_polarity()
270 val |= 0x04; lgdt3306a_mpeg_mode_polarity()
272 val |= 0x02; lgdt3306a_mpeg_mode_polarity()
274 ret = lgdt3306a_write_reg(state, 0x0070, val); lgdt3306a_mpeg_mode_polarity()
284 u8 val; lgdt3306a_mpeg_tristate() local
290 ret = lgdt3306a_read_reg(state, 0x0070, &val); lgdt3306a_mpeg_tristate()
297 val &= ~0xa8; lgdt3306a_mpeg_tristate()
298 ret = lgdt3306a_write_reg(state, 0x0070, val); lgdt3306a_mpeg_tristate()
313 ret = lgdt3306a_read_reg(state, 0x0070, &val); lgdt3306a_mpeg_tristate()
317 val |= 0xa8; /* enable bus */ lgdt3306a_mpeg_tristate()
318 ret = lgdt3306a_write_reg(state, 0x0070, val); lgdt3306a_mpeg_tristate()
377 u8 val; lgdt3306a_set_vsb() local
383 ret = lgdt3306a_read_reg(state, 0x0002, &val); lgdt3306a_set_vsb()
384 val &= 0xf7; /* SPECINVAUTO Off */ lgdt3306a_set_vsb()
385 val |= 0x04; /* SPECINV On */ lgdt3306a_set_vsb()
386 ret = lgdt3306a_write_reg(state, 0x0002, val); lgdt3306a_set_vsb()
396 ret = lgdt3306a_read_reg(state, 0x0009, &val); lgdt3306a_set_vsb()
397 val &= 0xe3; lgdt3306a_set_vsb()
398 val |= 0x0c; /* STDOPDETTMODE[2:0]=3 */ lgdt3306a_set_vsb()
399 ret = lgdt3306a_write_reg(state, 0x0009, val); lgdt3306a_set_vsb()
404 ret = lgdt3306a_read_reg(state, 0x0009, &val); lgdt3306a_set_vsb()
405 val &= 0xfc; /* STDOPDETCMODE[1:0]=0 */ lgdt3306a_set_vsb()
406 ret = lgdt3306a_write_reg(state, 0x0009, val); lgdt3306a_set_vsb()
411 ret = lgdt3306a_read_reg(state, 0x000d, &val); lgdt3306a_set_vsb()
412 val &= 0xbf; /* SAMPLING4XFEN=0 */ lgdt3306a_set_vsb()
413 ret = lgdt3306a_write_reg(state, 0x000d, val); lgdt3306a_set_vsb()
473 ret = lgdt3306a_read_reg(state, 0x001e, &val); lgdt3306a_set_vsb()
474 val &= 0x0f; lgdt3306a_set_vsb()
475 val |= 0xa0; lgdt3306a_set_vsb()
476 ret = lgdt3306a_write_reg(state, 0x001e, val); lgdt3306a_set_vsb()
482 ret = lgdt3306a_read_reg(state, 0x211f, &val); lgdt3306a_set_vsb()
483 val &= 0xef; lgdt3306a_set_vsb()
484 ret = lgdt3306a_write_reg(state, 0x211f, val); lgdt3306a_set_vsb()
488 ret = lgdt3306a_read_reg(state, 0x1061, &val); lgdt3306a_set_vsb()
489 val &= 0xf8; lgdt3306a_set_vsb()
490 val |= 0x04; lgdt3306a_set_vsb()
491 ret = lgdt3306a_write_reg(state, 0x1061, val); lgdt3306a_set_vsb()
493 ret = lgdt3306a_read_reg(state, 0x103d, &val); lgdt3306a_set_vsb()
494 val &= 0xcf; lgdt3306a_set_vsb()
495 ret = lgdt3306a_write_reg(state, 0x103d, val); lgdt3306a_set_vsb()
499 ret = lgdt3306a_read_reg(state, 0x2141, &val); lgdt3306a_set_vsb()
500 val &= 0x3f; lgdt3306a_set_vsb()
501 ret = lgdt3306a_write_reg(state, 0x2141, val); lgdt3306a_set_vsb()
503 ret = lgdt3306a_read_reg(state, 0x2135, &val); lgdt3306a_set_vsb()
504 val &= 0x0f; lgdt3306a_set_vsb()
505 val |= 0x70; lgdt3306a_set_vsb()
506 ret = lgdt3306a_write_reg(state, 0x2135, val); lgdt3306a_set_vsb()
508 ret = lgdt3306a_read_reg(state, 0x0003, &val); lgdt3306a_set_vsb()
509 val &= 0xf7; lgdt3306a_set_vsb()
510 ret = lgdt3306a_write_reg(state, 0x0003, val); lgdt3306a_set_vsb()
512 ret = lgdt3306a_read_reg(state, 0x001c, &val); lgdt3306a_set_vsb()
513 val &= 0x7f; lgdt3306a_set_vsb()
514 ret = lgdt3306a_write_reg(state, 0x001c, val); lgdt3306a_set_vsb()
517 ret = lgdt3306a_read_reg(state, 0x2179, &val); lgdt3306a_set_vsb()
518 val &= 0xf8; lgdt3306a_set_vsb()
519 ret = lgdt3306a_write_reg(state, 0x2179, val); lgdt3306a_set_vsb()
521 ret = lgdt3306a_read_reg(state, 0x217a, &val); lgdt3306a_set_vsb()
522 val &= 0xf8; lgdt3306a_set_vsb()
523 ret = lgdt3306a_write_reg(state, 0x217a, val); lgdt3306a_set_vsb()
537 u8 val; lgdt3306a_set_qam() local
548 ret = lgdt3306a_read_reg(state, 0x0002, &val); lgdt3306a_set_qam()
549 val &= 0xfb; /* SPECINV Off */ lgdt3306a_set_qam()
550 val |= 0x08; /* SPECINVAUTO On */ lgdt3306a_set_qam()
551 ret = lgdt3306a_write_reg(state, 0x0002, val); lgdt3306a_set_qam()
556 ret = lgdt3306a_read_reg(state, 0x0009, &val); lgdt3306a_set_qam()
557 val &= 0xe3; /* STDOPDETTMODE[2:0]=0 VSB Off */ lgdt3306a_set_qam()
558 ret = lgdt3306a_write_reg(state, 0x0009, val); lgdt3306a_set_qam()
563 ret = lgdt3306a_read_reg(state, 0x0009, &val); lgdt3306a_set_qam()
564 val &= 0xfc; lgdt3306a_set_qam()
565 val |= 0x02; /* STDOPDETCMODE[1:0]=1=Manual 2=Auto */ lgdt3306a_set_qam()
566 ret = lgdt3306a_write_reg(state, 0x0009, val); lgdt3306a_set_qam()
571 ret = lgdt3306a_read_reg(state, 0x101a, &val); lgdt3306a_set_qam()
572 val &= 0xf8; lgdt3306a_set_qam()
574 val |= 0x02; /* QMDQMODE[2:0]=2=QAM64 */ lgdt3306a_set_qam()
576 val |= 0x04; /* QMDQMODE[2:0]=4=QAM256 */ lgdt3306a_set_qam()
578 ret = lgdt3306a_write_reg(state, 0x101a, val); lgdt3306a_set_qam()
583 ret = lgdt3306a_read_reg(state, 0x000d, &val); lgdt3306a_set_qam()
584 val &= 0xbf; lgdt3306a_set_qam()
585 val |= 0x40; /* SAMPLING4XFEN=1 */ lgdt3306a_set_qam()
586 ret = lgdt3306a_write_reg(state, 0x000d, val); lgdt3306a_set_qam()
591 ret = lgdt3306a_read_reg(state, 0x0024, &val); lgdt3306a_set_qam()
592 val &= 0x00; lgdt3306a_set_qam()
593 ret = lgdt3306a_write_reg(state, 0x0024, val); lgdt3306a_set_qam()
814 u8 val; lgdt3306a_init() local
864 ret = lgdt3306a_read_reg(state, 0x0005, &val); lgdt3306a_init()
867 val &= 0xc0; lgdt3306a_init()
868 val |= 0x25; lgdt3306a_init()
869 ret = lgdt3306a_write_reg(state, 0x0005, val); lgdt3306a_init()
877 ret = lgdt3306a_read_reg(state, 0x000d, &val); lgdt3306a_init()
880 val &= 0xc0; lgdt3306a_init()
881 val |= 0x18; lgdt3306a_init()
882 ret = lgdt3306a_write_reg(state, 0x000d, val); lgdt3306a_init()
888 ret = lgdt3306a_read_reg(state, 0x0005, &val); lgdt3306a_init()
891 val &= 0xc0; lgdt3306a_init()
892 val |= 0x25; lgdt3306a_init()
893 ret = lgdt3306a_write_reg(state, 0x0005, val); lgdt3306a_init()
901 ret = lgdt3306a_read_reg(state, 0x000d, &val); lgdt3306a_init()
904 val &= 0xc0; lgdt3306a_init()
905 val |= 0x19; lgdt3306a_init()
906 ret = lgdt3306a_write_reg(state, 0x000d, val); lgdt3306a_init()
925 ret = lgdt3306a_read_reg(state, 0x103c, &val); lgdt3306a_init()
926 val &= 0x0f; lgdt3306a_init()
927 val |= 0x20; /* SAMGSAUTOSTL_V[3:0] = 2 */ lgdt3306a_init()
928 ret = lgdt3306a_write_reg(state, 0x103c, val); lgdt3306a_init()
931 ret = lgdt3306a_read_reg(state, 0x103d, &val); lgdt3306a_init()
932 val &= 0xfc; lgdt3306a_init()
933 val |= 0x03; lgdt3306a_init()
934 ret = lgdt3306a_write_reg(state, 0x103d, val); lgdt3306a_init()
937 ret = lgdt3306a_read_reg(state, 0x1036, &val); lgdt3306a_init()
938 val &= 0xf0; lgdt3306a_init()
939 val |= 0x0c; lgdt3306a_init()
940 ret = lgdt3306a_write_reg(state, 0x1036, val); lgdt3306a_init()
943 ret = lgdt3306a_read_reg(state, 0x211f, &val); lgdt3306a_init()
944 val &= 0xef; /* do not use imaginary of CIR */ lgdt3306a_init()
945 ret = lgdt3306a_write_reg(state, 0x211f, val); lgdt3306a_init()
948 ret = lgdt3306a_read_reg(state, 0x2849, &val); lgdt3306a_init()
949 val &= 0xef; /* NOUSENOSIGDET=0, enable no signal detector */ lgdt3306a_init()
950 ret = lgdt3306a_write_reg(state, 0x2849, val); lgdt3306a_init()
1068 u8 val; lgdt3306a_monitor_vsb() local
1073 ret = lgdt3306a_read_reg(state, 0x21a1, &val); lgdt3306a_monitor_vsb()
1076 snrRef = val & 0x3f; lgdt3306a_monitor_vsb()
1082 ret = lgdt3306a_read_reg(state, 0x2191, &val); lgdt3306a_monitor_vsb()
1085 nCombDet = (val & 0x80) >> 7; lgdt3306a_monitor_vsb()
1087 ret = lgdt3306a_read_reg(state, 0x2180, &val); lgdt3306a_monitor_vsb()
1090 fbDlyCir = (val & 0x03) << 8; lgdt3306a_monitor_vsb()
1092 ret = lgdt3306a_read_reg(state, 0x2181, &val); lgdt3306a_monitor_vsb()
1095 fbDlyCir |= val; lgdt3306a_monitor_vsb()
1101 ret = lgdt3306a_read_reg(state, 0x1061, &val); lgdt3306a_monitor_vsb()
1104 val &= 0xf8; lgdt3306a_monitor_vsb()
1109 val |= 0x00; /* final bandwidth = 0 */ lgdt3306a_monitor_vsb()
1111 val |= 0x04; /* final bandwidth = 4 */ lgdt3306a_monitor_vsb()
1113 ret = lgdt3306a_write_reg(state, 0x1061, val); lgdt3306a_monitor_vsb()
1118 ret = lgdt3306a_read_reg(state, 0x0024, &val); lgdt3306a_monitor_vsb()
1121 val &= 0x0f; lgdt3306a_monitor_vsb()
1123 val |= 0x50; lgdt3306a_monitor_vsb()
1125 ret = lgdt3306a_write_reg(state, 0x0024, val); lgdt3306a_monitor_vsb()
1130 ret = lgdt3306a_read_reg(state, 0x103d, &val); lgdt3306a_monitor_vsb()
1133 val &= 0xcf; lgdt3306a_monitor_vsb()
1134 val |= 0x20; lgdt3306a_monitor_vsb()
1135 ret = lgdt3306a_write_reg(state, 0x103d, val); lgdt3306a_monitor_vsb()
1143 u8 val = 0; lgdt3306a_check_oper_mode() local
1146 ret = lgdt3306a_read_reg(state, 0x0081, &val); lgdt3306a_check_oper_mode()
1150 if (val & 0x80) { lgdt3306a_check_oper_mode()
1154 if (val & 0x08) { lgdt3306a_check_oper_mode()
1155 ret = lgdt3306a_read_reg(state, 0x00a6, &val); lgdt3306a_check_oper_mode()
1158 val = val >> 2; lgdt3306a_check_oper_mode()
1159 if (val & 0x01) { lgdt3306a_check_oper_mode()
1175 u8 val = 0; lgdt3306a_check_lock_status() local
1185 ret = lgdt3306a_read_reg(state, 0x00a6, &val); lgdt3306a_check_lock_status()
1189 if ((val & 0x80) == 0x80) lgdt3306a_check_lock_status()
1199 ret = lgdt3306a_read_reg(state, 0x0080, &val); lgdt3306a_check_lock_status()
1203 if ((val & 0x40) == 0x40) lgdt3306a_check_lock_status()
1215 ret = lgdt3306a_read_reg(state, 0x1094, &val); lgdt3306a_check_lock_status()
1219 if ((val & 0x80) == 0x80) lgdt3306a_check_lock_status()
1233 ret = lgdt3306a_read_reg(state, 0x0080, &val); lgdt3306a_check_lock_status()
1237 if ((val & 0x10) == 0x10) lgdt3306a_check_lock_status()
1260 u8 val = 0; lgdt3306a_check_neverlock_status() local
1264 ret = lgdt3306a_read_reg(state, 0x0080, &val); lgdt3306a_check_neverlock_status()
1267 lockStatus = (enum lgdt3306a_neverlock_status)(val & 0x03); lgdt3306a_check_neverlock_status()
1276 u8 val = 0; lgdt3306a_pre_monitoring() local
1286 ret = lgdt3306a_read_reg(state, 0x21a1, &val); lgdt3306a_pre_monitoring()
1289 snrRef = val & 0x3f; lgdt3306a_pre_monitoring()
1292 ret = lgdt3306a_read_reg(state, 0x2199, &val); lgdt3306a_pre_monitoring()
1295 mainStrong = (val & 0x40) >> 6; lgdt3306a_pre_monitoring()
1297 ret = lgdt3306a_read_reg(state, 0x0090, &val); lgdt3306a_pre_monitoring()
1300 aiccrejStatus = (val & 0xf0) >> 4; lgdt3306a_pre_monitoring()
1310 ret = lgdt3306a_read_reg(state, 0x2135, &val); lgdt3306a_pre_monitoring()
1313 val &= 0x0f; lgdt3306a_pre_monitoring()
1314 val |= 0xa0; lgdt3306a_pre_monitoring()
1315 ret = lgdt3306a_write_reg(state, 0x2135, val); lgdt3306a_pre_monitoring()
1319 ret = lgdt3306a_read_reg(state, 0x2141, &val); lgdt3306a_pre_monitoring()
1322 val &= 0x3f; lgdt3306a_pre_monitoring()
1323 val |= 0x80; lgdt3306a_pre_monitoring()
1324 ret = lgdt3306a_write_reg(state, 0x2141, val); lgdt3306a_pre_monitoring()
1332 ret = lgdt3306a_read_reg(state, 0x2135, &val); lgdt3306a_pre_monitoring()
1335 val &= 0x0f; lgdt3306a_pre_monitoring()
1336 val |= 0x70; lgdt3306a_pre_monitoring()
1337 ret = lgdt3306a_write_reg(state, 0x2135, val); lgdt3306a_pre_monitoring()
1341 ret = lgdt3306a_read_reg(state, 0x2141, &val); lgdt3306a_pre_monitoring()
1344 val &= 0x3f; lgdt3306a_pre_monitoring()
1345 val |= 0x40; lgdt3306a_pre_monitoring()
1346 ret = lgdt3306a_write_reg(state, 0x2141, val); lgdt3306a_pre_monitoring()
1421 u8 val; lgdt3306a_get_packet_error() local
1424 ret = lgdt3306a_read_reg(state, 0x00fa, &val); lgdt3306a_get_packet_error()
1428 return val; lgdt3306a_get_packet_error()
1784 u8 val; lgdt3306a_attach() local
1804 ret = lgdt3306a_read_reg(state, 0x0000, &val); lgdt3306a_attach()
1807 if ((val & 0x74) != 0x74) { lgdt3306a_attach()
1808 pr_warn("expected 0x74, got 0x%x\n", (val & 0x74)); lgdt3306a_attach()
1814 ret = lgdt3306a_read_reg(state, 0x0001, &val); lgdt3306a_attach()
1817 if ((val & 0xf6) != 0xc6) { lgdt3306a_attach()
1818 pr_warn("expected 0xc6, got 0x%x\n", (val & 0xf6)); lgdt3306a_attach()
1824 ret = lgdt3306a_read_reg(state, 0x0002, &val); lgdt3306a_attach()
1827 if ((val & 0x73) != 0x03) { lgdt3306a_attach()
1828 pr_warn("expected 0x03, got 0x%x\n", (val & 0x73)); lgdt3306a_attach()
/linux-4.1.27/drivers/gpio/
H A Dgpio-mb86s7x.c56 u32 val; mb86s70_gpio_request() local
60 val = readl(gchip->base + PFR(gpio)); mb86s70_gpio_request()
61 if (!(val & OFFSET(gpio))) { mb86s70_gpio_request()
66 val &= ~OFFSET(gpio); mb86s70_gpio_request()
67 writel(val, gchip->base + PFR(gpio)); mb86s70_gpio_request()
78 u32 val; mb86s70_gpio_free() local
82 val = readl(gchip->base + PFR(gpio)); mb86s70_gpio_free()
83 val |= OFFSET(gpio); mb86s70_gpio_free()
84 writel(val, gchip->base + PFR(gpio)); mb86s70_gpio_free()
93 unsigned char val; mb86s70_gpio_direction_input() local
97 val = readl(gchip->base + DDR(gpio)); mb86s70_gpio_direction_input()
98 val &= ~OFFSET(gpio); mb86s70_gpio_direction_input()
99 writel(val, gchip->base + DDR(gpio)); mb86s70_gpio_direction_input()
111 unsigned char val; mb86s70_gpio_direction_output() local
115 val = readl(gchip->base + PDR(gpio)); mb86s70_gpio_direction_output()
117 val |= OFFSET(gpio); mb86s70_gpio_direction_output()
119 val &= ~OFFSET(gpio); mb86s70_gpio_direction_output()
120 writel(val, gchip->base + PDR(gpio)); mb86s70_gpio_direction_output()
122 val = readl(gchip->base + DDR(gpio)); mb86s70_gpio_direction_output()
123 val |= OFFSET(gpio); mb86s70_gpio_direction_output()
124 writel(val, gchip->base + DDR(gpio)); mb86s70_gpio_direction_output()
142 unsigned char val; mb86s70_gpio_set() local
146 val = readl(gchip->base + PDR(gpio)); mb86s70_gpio_set()
148 val |= OFFSET(gpio); mb86s70_gpio_set()
150 val &= ~OFFSET(gpio); mb86s70_gpio_set()
151 writel(val, gchip->base + PDR(gpio)); mb86s70_gpio_set()
/linux-4.1.27/drivers/misc/cxl/
H A Dpci.c55 #define CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val) \
56 pci_write_config_byte(dev, vsec + 0xa, val)
74 #define CXL_WRITE_VSEC_IMAGE_STATE(dev, vsec, val) \
75 pci_write_config_byte(dev, vsec + 0x13, val)
93 #define EXTRACT_PPC_BIT(val, bit) (!!(val & PPC_BIT(bit)))
94 #define EXTRACT_PPC_BITS(val, bs, be) ((val & PPC_BITMASK(bs, be)) >> PPC_BITLSHIFT(be))
97 #define AFUD_NUM_INTS_PER_PROC(val) EXTRACT_PPC_BITS(val, 0, 15)
98 #define AFUD_NUM_PROCS(val) EXTRACT_PPC_BITS(val, 16, 31)
99 #define AFUD_NUM_CRS(val) EXTRACT_PPC_BITS(val, 32, 47)
100 #define AFUD_MULTIMODE(val) EXTRACT_PPC_BIT(val, 48)
101 #define AFUD_PUSH_BLOCK_TRANSFER(val) EXTRACT_PPC_BIT(val, 55)
102 #define AFUD_DEDICATED_PROCESS(val) EXTRACT_PPC_BIT(val, 59)
103 #define AFUD_AFU_DIRECTED(val) EXTRACT_PPC_BIT(val, 61)
104 #define AFUD_TIME_SLICED(val) EXTRACT_PPC_BIT(val, 63)
106 #define AFUD_CR_LEN(val) EXTRACT_PPC_BITS(val, 8, 63)
109 #define AFUD_PPPSA_PP(val) EXTRACT_PPC_BIT(val, 6)
110 #define AFUD_PPPSA_PSA(val) EXTRACT_PPC_BIT(val, 7)
111 #define AFUD_PPPSA_LEN(val) EXTRACT_PPC_BITS(val, 8, 63)
114 #define AFUD_EB_LEN(val) EXTRACT_PPC_BITS(val, 8, 63)
120 u32 val; cxl_afu_cr_read16() local
122 val = cxl_afu_cr_read32(afu, cr, aligned_off); cxl_afu_cr_read16()
123 return (val >> ((off & 0x2) * 8)) & 0xffff; cxl_afu_cr_read16()
129 u32 val; cxl_afu_cr_read8() local
131 val = cxl_afu_cr_read32(afu, cr, aligned_off); cxl_afu_cr_read8()
132 return (val >> ((off & 0x3) * 8)) & 0xff; cxl_afu_cr_read8()
173 u16 val; find_cxl_vsec() local
176 pci_read_config_word(dev, vsec + 0x4, &val); find_cxl_vsec()
177 if (val == CXL_PCI_VSEC_ID) find_cxl_vsec()
187 u32 val; dump_cxl_config_space() local
191 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &val); dump_cxl_config_space()
192 dev_info(&dev->dev, "BAR0: %#.8x\n", val); dump_cxl_config_space()
193 pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, &val); dump_cxl_config_space()
194 dev_info(&dev->dev, "BAR1: %#.8x\n", val); dump_cxl_config_space()
195 pci_read_config_dword(dev, PCI_BASE_ADDRESS_2, &val); dump_cxl_config_space()
196 dev_info(&dev->dev, "BAR2: %#.8x\n", val); dump_cxl_config_space()
197 pci_read_config_dword(dev, PCI_BASE_ADDRESS_3, &val); dump_cxl_config_space()
198 dev_info(&dev->dev, "BAR3: %#.8x\n", val); dump_cxl_config_space()
199 pci_read_config_dword(dev, PCI_BASE_ADDRESS_4, &val); dump_cxl_config_space()
200 dev_info(&dev->dev, "BAR4: %#.8x\n", val); dump_cxl_config_space()
201 pci_read_config_dword(dev, PCI_BASE_ADDRESS_5, &val); dump_cxl_config_space()
202 dev_info(&dev->dev, "BAR5: %#.8x\n", val); dump_cxl_config_space()
217 pci_read_config_dword(dev, vsec + 0x0, &val); dump_cxl_config_space()
218 show_reg("Cap ID", (val >> 0) & 0xffff); dump_cxl_config_space()
219 show_reg("Cap Ver", (val >> 16) & 0xf); dump_cxl_config_space()
220 show_reg("Next Cap Ptr", (val >> 20) & 0xfff); dump_cxl_config_space()
221 pci_read_config_dword(dev, vsec + 0x4, &val); dump_cxl_config_space()
222 show_reg("VSEC ID", (val >> 0) & 0xffff); dump_cxl_config_space()
223 show_reg("VSEC Rev", (val >> 16) & 0xf); dump_cxl_config_space()
224 show_reg("VSEC Length", (val >> 20) & 0xfff); dump_cxl_config_space()
225 pci_read_config_dword(dev, vsec + 0x8, &val); dump_cxl_config_space()
226 show_reg("Num AFUs", (val >> 0) & 0xff); dump_cxl_config_space()
227 show_reg("Status", (val >> 8) & 0xff); dump_cxl_config_space()
228 show_reg("Mode Control", (val >> 16) & 0xff); dump_cxl_config_space()
229 show_reg("Reserved", (val >> 24) & 0xff); dump_cxl_config_space()
230 pci_read_config_dword(dev, vsec + 0xc, &val); dump_cxl_config_space()
231 show_reg("PSL Rev", (val >> 0) & 0xffff); dump_cxl_config_space()
232 show_reg("CAIA Ver", (val >> 16) & 0xffff); dump_cxl_config_space()
233 pci_read_config_dword(dev, vsec + 0x10, &val); dump_cxl_config_space()
234 show_reg("Base Image Rev", (val >> 0) & 0xffff); dump_cxl_config_space()
235 show_reg("Reserved", (val >> 16) & 0x0fff); dump_cxl_config_space()
236 show_reg("Image Control", (val >> 28) & 0x3); dump_cxl_config_space()
237 show_reg("Reserved", (val >> 30) & 0x1); dump_cxl_config_space()
238 show_reg("Image Loaded", (val >> 31) & 0x1); dump_cxl_config_space()
240 pci_read_config_dword(dev, vsec + 0x14, &val); dump_cxl_config_space()
241 show_reg("Reserved", val); dump_cxl_config_space()
242 pci_read_config_dword(dev, vsec + 0x18, &val); dump_cxl_config_space()
243 show_reg("Reserved", val); dump_cxl_config_space()
244 pci_read_config_dword(dev, vsec + 0x1c, &val); dump_cxl_config_space()
245 show_reg("Reserved", val); dump_cxl_config_space()
247 pci_read_config_dword(dev, vsec + 0x20, &val); dump_cxl_config_space()
248 show_reg("AFU Descriptor Offset", val); dump_cxl_config_space()
249 pci_read_config_dword(dev, vsec + 0x24, &val); dump_cxl_config_space()
250 show_reg("AFU Descriptor Size", val); dump_cxl_config_space()
251 pci_read_config_dword(dev, vsec + 0x28, &val); dump_cxl_config_space()
252 show_reg("Problem State Offset", val); dump_cxl_config_space()
253 pci_read_config_dword(dev, vsec + 0x2c, &val); dump_cxl_config_space()
254 show_reg("Problem State Size", val); dump_cxl_config_space()
256 pci_read_config_dword(dev, vsec + 0x30, &val); dump_cxl_config_space()
257 show_reg("Reserved", val); dump_cxl_config_space()
258 pci_read_config_dword(dev, vsec + 0x34, &val); dump_cxl_config_space()
259 show_reg("Reserved", val); dump_cxl_config_space()
260 pci_read_config_dword(dev, vsec + 0x38, &val); dump_cxl_config_space()
261 show_reg("Reserved", val); dump_cxl_config_space()
262 pci_read_config_dword(dev, vsec + 0x3c, &val); dump_cxl_config_space()
263 show_reg("Reserved", val); dump_cxl_config_space()
265 pci_read_config_dword(dev, vsec + 0x40, &val); dump_cxl_config_space()
266 show_reg("PSL Programming Port", val); dump_cxl_config_space()
267 pci_read_config_dword(dev, vsec + 0x44, &val); dump_cxl_config_space()
268 show_reg("PSL Programming Control", val); dump_cxl_config_space()
270 pci_read_config_dword(dev, vsec + 0x48, &val); dump_cxl_config_space()
271 show_reg("Reserved", val); dump_cxl_config_space()
272 pci_read_config_dword(dev, vsec + 0x4c, &val); dump_cxl_config_space()
273 show_reg("Reserved", val); dump_cxl_config_space()
275 pci_read_config_dword(dev, vsec + 0x50, &val); dump_cxl_config_space()
276 show_reg("Flash Address Register", val); dump_cxl_config_space()
277 pci_read_config_dword(dev, vsec + 0x54, &val); dump_cxl_config_space()
278 show_reg("Flash Size Register", val); dump_cxl_config_space()
279 pci_read_config_dword(dev, vsec + 0x58, &val); dump_cxl_config_space()
280 show_reg("Flash Status/Control Register", val); dump_cxl_config_space()
281 pci_read_config_dword(dev, vsec + 0x58, &val); dump_cxl_config_space()
282 show_reg("Flash Data Port", val); dump_cxl_config_space()
289 u64 val; dump_afu_descriptor() local
294 val = AFUD_READ_INFO(afu); dump_afu_descriptor()
295 show_reg("num_ints_per_process", AFUD_NUM_INTS_PER_PROC(val)); dump_afu_descriptor()
296 show_reg("num_of_processes", AFUD_NUM_PROCS(val)); dump_afu_descriptor()
297 show_reg("num_of_afu_CRs", AFUD_NUM_CRS(val)); dump_afu_descriptor()
298 show_reg("req_prog_mode", val & 0xffffULL); dump_afu_descriptor()
300 val = AFUD_READ(afu, 0x8); dump_afu_descriptor()
301 show_reg("Reserved", val); dump_afu_descriptor()
302 val = AFUD_READ(afu, 0x10); dump_afu_descriptor()
303 show_reg("Reserved", val); dump_afu_descriptor()
304 val = AFUD_READ(afu, 0x18); dump_afu_descriptor()
305 show_reg("Reserved", val); dump_afu_descriptor()
307 val = AFUD_READ_CR(afu); dump_afu_descriptor()
308 show_reg("Reserved", (val >> (63-7)) & 0xff); dump_afu_descriptor()
309 show_reg("AFU_CR_len", AFUD_CR_LEN(val)); dump_afu_descriptor()
311 val = AFUD_READ_CR_OFF(afu); dump_afu_descriptor()
312 show_reg("AFU_CR_offset", val); dump_afu_descriptor()
314 val = AFUD_READ_PPPSA(afu); dump_afu_descriptor()
315 show_reg("PerProcessPSA_control", (val >> (63-7)) & 0xff); dump_afu_descriptor()
316 show_reg("PerProcessPSA Length", AFUD_PPPSA_LEN(val)); dump_afu_descriptor()
318 val = AFUD_READ_PPPSA_OFF(afu); dump_afu_descriptor()
319 show_reg("PerProcessPSA_offset", val); dump_afu_descriptor()
321 val = AFUD_READ_EB(afu); dump_afu_descriptor()
322 show_reg("Reserved", (val >> (63-7)) & 0xff); dump_afu_descriptor()
323 show_reg("AFU_EB_len", AFUD_EB_LEN(val)); dump_afu_descriptor()
325 val = AFUD_READ_EB_OFF(afu); dump_afu_descriptor()
326 show_reg("AFU_EB_offset", val); dump_afu_descriptor()
470 u8 val; switch_card_to_cxl() local
480 if ((rc = CXL_READ_VSEC_MODE_CONTROL(dev, vsec, &val))) { switch_card_to_cxl()
484 val &= ~CXL_VSEC_PROTOCOL_MASK; switch_card_to_cxl()
485 val |= CXL_VSEC_PROTOCOL_256TB | CXL_VSEC_PROTOCOL_ENABLE; switch_card_to_cxl()
486 if ((rc = CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val))) { switch_card_to_cxl()
572 u64 val; cxl_read_afu_descriptor() local
574 val = AFUD_READ_INFO(afu); cxl_read_afu_descriptor()
575 afu->pp_irqs = AFUD_NUM_INTS_PER_PROC(val); cxl_read_afu_descriptor()
576 afu->max_procs_virtualised = AFUD_NUM_PROCS(val); cxl_read_afu_descriptor()
577 afu->crs_num = AFUD_NUM_CRS(val); cxl_read_afu_descriptor()
579 if (AFUD_AFU_DIRECTED(val)) cxl_read_afu_descriptor()
581 if (AFUD_DEDICATED_PROCESS(val)) cxl_read_afu_descriptor()
583 if (AFUD_TIME_SLICED(val)) cxl_read_afu_descriptor()
586 val = AFUD_READ_PPPSA(afu); cxl_read_afu_descriptor()
587 afu->pp_size = AFUD_PPPSA_LEN(val) * 4096; cxl_read_afu_descriptor()
588 afu->psa = AFUD_PPPSA_PSA(val); cxl_read_afu_descriptor()
589 if ((afu->pp_psa = AFUD_PPPSA_PP(val))) cxl_read_afu_descriptor()
592 val = AFUD_READ_CR(afu); cxl_read_afu_descriptor()
593 afu->crs_len = AFUD_CR_LEN(val) * 256; cxl_read_afu_descriptor()
/linux-4.1.27/arch/m32r/kernel/
H A Dalign.c12 int val; get_reg() local
15 val = *(unsigned long *)(&regs->r0 + nr); get_reg()
17 val = *(unsigned long *)(&regs->r4 + (nr - 4)); get_reg()
19 val = *(unsigned long *)(&regs->r7 + (nr - 7)); get_reg()
21 val = *(unsigned long *)(&regs->fp + (nr - 13)); get_reg()
23 return val; get_reg()
26 static void set_reg(struct pt_regs *regs, int nr, int val) set_reg() argument
29 *(unsigned long *)(&regs->r0 + nr) = val; set_reg()
31 *(unsigned long *)(&regs->r4 + (nr - 4)) = val; set_reg()
33 *(unsigned long *)(&regs->r7 + (nr - 7)) = val; set_reg()
35 *(unsigned long *)(&regs->fp + (nr - 13)) = val; set_reg()
85 int val; emu_addi() local
87 val = get_reg(regs, dest); emu_addi()
88 val += imm; emu_addi()
89 set_reg(regs, dest, val); emu_addi()
107 int val; emu_add() local
109 val = get_reg(regs, dest); emu_add()
110 val += get_reg(regs, src); emu_add()
111 set_reg(regs, dest, val); emu_add()
119 unsigned int val, tmp; emu_addx() local
121 val = regs->psw & PSW_BC ? 1 : 0; emu_addx()
123 val += tmp; emu_addx()
124 val += (unsigned int)get_reg(regs, REG2(insn)); emu_addx()
125 set_reg(regs, dest, val); emu_addx()
128 if (val < tmp) emu_addx()
139 int val; emu_and() local
141 val = get_reg(regs, dest); emu_and()
142 val &= get_reg(regs, REG2(insn)); emu_and()
143 set_reg(regs, dest, val); emu_and()
191 int val; emu_mv() local
193 val = get_reg(regs, REG2(insn)); emu_mv()
194 set_reg(regs, REG1(insn), val); emu_mv()
201 int val; emu_neg() local
203 val = get_reg(regs, REG2(insn)); emu_neg()
204 set_reg(regs, REG1(insn), 0 - val); emu_neg()
211 int val; emu_not() local
213 val = get_reg(regs, REG2(insn)); emu_not()
214 set_reg(regs, REG1(insn), ~val); emu_not()
222 int val; emu_or() local
224 val = get_reg(regs, dest); emu_or()
225 val |= get_reg(regs, REG2(insn)); emu_or()
226 set_reg(regs, dest, val); emu_or()
234 int val; emu_sub() local
236 val = get_reg(regs, dest); emu_sub()
237 val -= get_reg(regs, REG2(insn)); emu_sub()
238 set_reg(regs, dest, val); emu_sub()
246 unsigned int val, tmp; emu_subx() local
248 val = tmp = get_reg(regs, dest); emu_subx()
249 val -= (unsigned int)get_reg(regs, REG2(insn)); emu_subx()
250 val -= regs->psw & PSW_BC ? 1 : 0; emu_subx()
251 set_reg(regs, dest, val); emu_subx()
254 if (val > tmp) emu_subx()
265 unsigned int val; emu_xor() local
267 val = (unsigned int)get_reg(regs, dest); emu_xor()
268 val ^= (unsigned int)get_reg(regs, REG2(insn)); emu_xor()
269 set_reg(regs, dest, val); emu_xor()
334 unsigned long val; emu_mvfacmi_a0() local
336 val = (regs->acc0h << 16) | (regs->acc0l >> 16); emu_mvfacmi_a0()
337 set_reg(regs, REG1(insn), (int)val); emu_mvfacmi_a0()
344 unsigned long val; emu_mvfacmi_a1() local
346 val = (regs->acc1h << 16) | (regs->acc1l >> 16); emu_mvfacmi_a1()
347 set_reg(regs, REG1(insn), (int)val); emu_mvfacmi_a1()
489 unsigned long val; emu_ld() local
501 if (copy_from_user(&val, ucp, size)) emu_ld()
505 val >>= 16; emu_ld()
508 if ((insn16 & 0x00f0) == 0x00a0 && (val & 0x8000)) emu_ld()
509 val |= 0xffff0000; emu_ld()
511 set_reg(regs, REG1(insn16), val); emu_ld()
523 unsigned long val; emu_st() local
536 val = get_reg(regs, REG1(insn16)); emu_st()
538 val <<= 16; emu_st()
550 if (copy_to_user(ucp, &val, size)) emu_st()
/linux-4.1.27/arch/tile/include/gxio/
H A Dcommon.h33 #define __gxio_mmio_write8(addr, val) writeb((val), (addr))
34 #define __gxio_mmio_write16(addr, val) writew((val), (addr))
35 #define __gxio_mmio_write32(addr, val) writel((val), (addr))
36 #define __gxio_mmio_write64(addr, val) writeq((val), (addr))
38 #define __gxio_mmio_write(addr, val) __gxio_mmio_write64((addr), (val))
/linux-4.1.27/arch/powerpc/boot/
H A Dio.h20 static inline void out_8(volatile unsigned char *addr, int val) out_8() argument
23 : "=m" (*addr) : "r" (val)); out_8()
45 static inline void out_le16(volatile u16 *addr, int val) out_le16() argument
48 : "r" (val), "r" (addr)); out_le16()
51 static inline void out_be16(volatile u16 *addr, int val) out_be16() argument
54 : "=m" (*addr) : "r" (val)); out_be16()
75 static inline void out_le32(volatile unsigned *addr, int val) out_le32() argument
78 : "r" (val), "r" (addr)); out_le32()
81 static inline void out_be32(volatile unsigned *addr, int val) out_be32() argument
84 : "=m" (*addr) : "r" (val)); out_be32()
/linux-4.1.27/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/
H A Diop_version_defs.h21 #define REG_WR( scope, inst, reg, val ) \
23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
34 #define REG_WR_VECT( scope, inst, reg, index, val ) \
37 (index) * STRIDE_##scope##_##reg, (val) )
46 #define REG_WR_INT( scope, inst, reg, val ) \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
57 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
59 (index) * STRIDE_##scope##_##reg, (val) )
63 #define REG_TYPE_CONV( type, orgtype, val ) \
64 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
/linux-4.1.27/sound/soc/davinci/
H A Ddavinci-mcasp.h143 #define TXROT(val) (val)
145 #define TXSSZ(val) (val<<4)
146 #define TXPBIT(val) (val<<8)
147 #define TXPAD(val) (val<<13)
149 #define FSXDLY(val) (val<<16)
154 #define RXROT(val) (val)
156 #define RXSSZ(val) (val<<4)
157 #define RXPBIT(val) (val<<8)
158 #define RXPAD(val) (val<<13)
160 #define FSRDLY(val) (val<<16)
168 #define FSXMOD(val) (val<<7)
176 #define FSRMOD(val) (val<<7)
181 #define ACLKXDIV(val) (val)
190 #define ACLKRDIV(val) (val)
200 #define AHCLKXDIV(val) (val)
209 #define AHCLKRDIV(val) (val)
217 #define MODE(val) (val)
218 #define DISMOD (val)(val<<2)
229 #define LBGENMODE(val) (val<<2)
265 #define MUTENA(val) (val)
/linux-4.1.27/drivers/net/ethernet/neterion/
H A Ds2io-regs.h77 #define ADAPTER_UDPI(val) vBIT(val,36,4)
96 #define GET_PCI_MODE(val) ((val & vBIT(0xF, 0, 4)) >> 60)
224 #define SCHED_INT_CTRL_INT2MSI(val) vBIT(val,10,6)
228 #define TXREQTO_VAL(val) vBIT(val,0,32)
266 #define SET_UPDT_CLICKS(val) vBIT(val, 32, 32)
272 #define MDIO_MMD_INDX_ADDR(val) vBIT(val, 0, 16)
273 #define MDIO_MMD_DEV_ADDR(val) vBIT(val, 19, 5)
274 #define MDIO_MMS_PRT_ADDR(val) vBIT(val, 27, 5)
275 #define MDIO_CTRL_START_TRANS(val) vBIT(val, 56, 4)
276 #define MDIO_OP(val) vBIT(val, 60, 2)
281 #define MDIO_MDIO_DATA(val) vBIT(val, 32, 16)
292 #define I2C_CONTROL_CNTL_END(val) (val & vBIT(0x1,28,4))
293 #define I2C_CONTROL_GET_DATA(val) (u32)(val & 0xFFFFFFFF)
294 #define I2C_CONTROL_SET_DATA(val) vBIT(val,32,32)
301 #define MISC_LINK_STABILITY_PRD(val) vBIT(val,29,3)
309 #define WREQ_SPLIT_MASK_SET_MASK(val) vBIT(val, 52, 12)
397 #define TX_FIFO_PARTITION_0_PRI(val) vBIT(val,5,3)
398 #define TX_FIFO_PARTITION_0_LEN(val) vBIT(val,19,13)
399 #define TX_FIFO_PARTITION_1_PRI(val) vBIT(val,37,3)
400 #define TX_FIFO_PARTITION_1_LEN(val) vBIT(val,51,13 )
403 #define TX_FIFO_PARTITION_2_PRI(val) vBIT(val,5,3)
404 #define TX_FIFO_PARTITION_2_LEN(val) vBIT(val,19,13)
405 #define TX_FIFO_PARTITION_3_PRI(val) vBIT(val,37,3)
406 #define TX_FIFO_PARTITION_3_LEN(val) vBIT(val,51,13)
409 #define TX_FIFO_PARTITION_4_PRI(val) vBIT(val,5,3)
410 #define TX_FIFO_PARTITION_4_LEN(val) vBIT(val,19,13)
411 #define TX_FIFO_PARTITION_5_PRI(val) vBIT(val,37,3)
412 #define TX_FIFO_PARTITION_5_LEN(val) vBIT(val,51,13)
415 #define TX_FIFO_PARTITION_6_PRI(val) vBIT(val,5,3)
416 #define TX_FIFO_PARTITION_6_LEN(val) vBIT(val,19,13)
417 #define TX_FIFO_PARTITION_7_PRI(val) vBIT(val,37,3)
418 #define TX_FIFO_PARTITION_7_LEN(val) vBIT(val,51,13)
535 #define RX_QUEUE_0_PRIORITY(val) vBIT(val,5,3)
536 #define RX_QUEUE_1_PRIORITY(val) vBIT(val,13,3)
537 #define RX_QUEUE_2_PRIORITY(val) vBIT(val,21,3)
538 #define RX_QUEUE_3_PRIORITY(val) vBIT(val,29,3)
539 #define RX_QUEUE_4_PRIORITY(val) vBIT(val,37,3)
540 #define RX_QUEUE_5_PRIORITY(val) vBIT(val,45,3)
541 #define RX_QUEUE_6_PRIORITY(val) vBIT(val,53,3)
542 #define RX_QUEUE_7_PRIORITY(val) vBIT(val,61,3)
578 #define PRC_CTRL_RXD_BACKOFF_INTERVAL(val) vBIT(val,40,24)
698 #define MAC_RMAC_INVLD_IPG_THR(val) vBIT(val,16,8)
701 #define TMAC_AVG_IPG(val) vBIT(val,0,8)
704 #define RMAC_MAX_PYLD_LEN(val) vBIT(val,2,14)
719 #define RMAC_CFG_KEY(val) vBIT(val,0,16)
763 #define RMAC_PAUSE_HG_PTIME(val) vBIT(val,16,16)
791 #define RTS_DIX_MAP_ETYPE(val) vBIT(val,0,16)
792 #define RTS_DIX_MAP_SCW(val) s2BIT(val,21)
808 #define RTS_PN_CAM_DATA_PORT(val) vBIT(val,8,16)
809 #define RTS_PN_CAM_DATA_SCW(val) vBIT(val,24,8)
897 #define MC_RLDRAM_SET_REF_PERIOD(val) vBIT(val, 0, 16)
/linux-4.1.27/drivers/gpu/drm/armada/
H A Darmada_overlay.c22 #define K2R(val) (((val) >> 0) & 0xff)
23 #define K2G(val) (((val) >> 8) & 0xff)
24 #define K2B(val) (((val) >> 16) & 0xff)
108 uint32_t val, ctrl0; armada_plane_update() local
137 val = (src_h & 0xffff0000) | src_w >> 16; armada_plane_update()
138 dplane->src_hw = val; armada_plane_update()
139 writel_relaxed(val, dcrtc->base + LCD_SPU_DMA_HPXL_VLN); armada_plane_update()
140 val = crtc_h << 16 | crtc_w; armada_plane_update()
141 dplane->dst_hw = val; armada_plane_update()
142 writel_relaxed(val, dcrtc->base + LCD_SPU_DZM_HPXL_VLN); armada_plane_update()
143 val = crtc_y << 16 | crtc_x; armada_plane_update()
144 dplane->dst_yx = val; armada_plane_update()
145 writel_relaxed(val, dcrtc->base + LCD_SPU_DMA_OVSA_HPXL_VLN); armada_plane_update()
203 val = fb->pitches[0] << 16 | fb->pitches[0]; armada_plane_update()
204 armada_reg_queue_set(dplane->vbl.regs, idx, val, armada_plane_update()
206 val = fb->pitches[1] << 16 | fb->pitches[2]; armada_plane_update()
207 armada_reg_queue_set(dplane->vbl.regs, idx, val, armada_plane_update()
211 val = (src_h & 0xffff0000) | src_w >> 16; armada_plane_update()
212 if (dplane->src_hw != val) { armada_plane_update()
213 dplane->src_hw = val; armada_plane_update()
214 armada_reg_queue_set(dplane->vbl.regs, idx, val, armada_plane_update()
217 val = crtc_h << 16 | crtc_w; armada_plane_update()
218 if (dplane->dst_hw != val) { armada_plane_update()
219 dplane->dst_hw = val; armada_plane_update()
220 armada_reg_queue_set(dplane->vbl.regs, idx, val, armada_plane_update()
223 val = crtc_y << 16 | crtc_x; armada_plane_update()
224 if (dplane->dst_yx != val) { armada_plane_update()
225 dplane->dst_yx = val; armada_plane_update()
226 armada_reg_queue_set(dplane->vbl.regs, idx, val, armada_plane_update()
286 struct drm_property *property, uint64_t val) armada_plane_set_property()
294 dplane->prop.colorkey_yr = CCC(K2R(val)); armada_plane_set_property()
295 dplane->prop.colorkey_ug = CCC(K2G(val)); armada_plane_set_property()
296 dplane->prop.colorkey_vb = CCC(K2B(val)); armada_plane_set_property()
301 dplane->prop.colorkey_yr |= K2R(val) << 16; armada_plane_set_property()
303 dplane->prop.colorkey_ug |= K2G(val) << 16; armada_plane_set_property()
305 dplane->prop.colorkey_vb |= K2B(val) << 16; armada_plane_set_property()
309 dplane->prop.colorkey_yr |= K2R(val) << 24; armada_plane_set_property()
311 dplane->prop.colorkey_ug |= K2G(val) << 24; armada_plane_set_property()
313 dplane->prop.colorkey_vb |= K2B(val) << 24; armada_plane_set_property()
317 dplane->prop.colorkey_yr |= K2R(val) << 8; armada_plane_set_property()
319 dplane->prop.colorkey_ug |= K2G(val) << 8; armada_plane_set_property()
321 dplane->prop.colorkey_vb |= K2B(val) << 8; armada_plane_set_property()
325 dplane->prop.colorkey_yr |= K2R(val); armada_plane_set_property()
327 dplane->prop.colorkey_ug |= K2G(val); armada_plane_set_property()
329 dplane->prop.colorkey_vb |= K2B(val); armada_plane_set_property()
333 dplane->prop.colorkey_mode |= CFG_CKMODE(val); armada_plane_set_property()
336 dplane->prop.brightness = val - 256; armada_plane_set_property()
339 dplane->prop.contrast = val; armada_plane_set_property()
342 dplane->prop.saturation = val; armada_plane_set_property()
285 armada_plane_set_property(struct drm_plane *plane, struct drm_property *property, uint64_t val) armada_plane_set_property() argument
/linux-4.1.27/drivers/gpu/drm/msm/dsi/
H A Ddsi.xml.h103 static inline uint32_t DSI_6G_HW_VERSION_MAJOR(uint32_t val) DSI_6G_HW_VERSION_MAJOR() argument
105 return ((val) << DSI_6G_HW_VERSION_MAJOR__SHIFT) & DSI_6G_HW_VERSION_MAJOR__MASK; DSI_6G_HW_VERSION_MAJOR()
109 static inline uint32_t DSI_6G_HW_VERSION_MINOR(uint32_t val) DSI_6G_HW_VERSION_MINOR() argument
111 return ((val) << DSI_6G_HW_VERSION_MINOR__SHIFT) & DSI_6G_HW_VERSION_MINOR__MASK; DSI_6G_HW_VERSION_MINOR()
115 static inline uint32_t DSI_6G_HW_VERSION_STEP(uint32_t val) DSI_6G_HW_VERSION_STEP() argument
117 return ((val) << DSI_6G_HW_VERSION_STEP__SHIFT) & DSI_6G_HW_VERSION_STEP__MASK; DSI_6G_HW_VERSION_STEP()
146 static inline uint32_t DSI_VID_CFG0_VIRT_CHANNEL(uint32_t val) DSI_VID_CFG0_VIRT_CHANNEL() argument
148 return ((val) << DSI_VID_CFG0_VIRT_CHANNEL__SHIFT) & DSI_VID_CFG0_VIRT_CHANNEL__MASK; DSI_VID_CFG0_VIRT_CHANNEL()
152 static inline uint32_t DSI_VID_CFG0_DST_FORMAT(enum dsi_vid_dst_format val) DSI_VID_CFG0_DST_FORMAT() argument
154 return ((val) << DSI_VID_CFG0_DST_FORMAT__SHIFT) & DSI_VID_CFG0_DST_FORMAT__MASK; DSI_VID_CFG0_DST_FORMAT()
158 static inline uint32_t DSI_VID_CFG0_TRAFFIC_MODE(enum dsi_traffic_mode val) DSI_VID_CFG0_TRAFFIC_MODE() argument
160 return ((val) << DSI_VID_CFG0_TRAFFIC_MODE__SHIFT) & DSI_VID_CFG0_TRAFFIC_MODE__MASK; DSI_VID_CFG0_TRAFFIC_MODE()
175 static inline uint32_t DSI_VID_CFG1_RGB_SWAP(enum dsi_rgb_swap val) DSI_VID_CFG1_RGB_SWAP() argument
177 return ((val) << DSI_VID_CFG1_RGB_SWAP__SHIFT) & DSI_VID_CFG1_RGB_SWAP__MASK; DSI_VID_CFG1_RGB_SWAP()
183 static inline uint32_t DSI_ACTIVE_H_START(uint32_t val) DSI_ACTIVE_H_START() argument
185 return ((val) << DSI_ACTIVE_H_START__SHIFT) & DSI_ACTIVE_H_START__MASK; DSI_ACTIVE_H_START()
189 static inline uint32_t DSI_ACTIVE_H_END(uint32_t val) DSI_ACTIVE_H_END() argument
191 return ((val) << DSI_ACTIVE_H_END__SHIFT) & DSI_ACTIVE_H_END__MASK; DSI_ACTIVE_H_END()
197 static inline uint32_t DSI_ACTIVE_V_START(uint32_t val) DSI_ACTIVE_V_START() argument
199 return ((val) << DSI_ACTIVE_V_START__SHIFT) & DSI_ACTIVE_V_START__MASK; DSI_ACTIVE_V_START()
203 static inline uint32_t DSI_ACTIVE_V_END(uint32_t val) DSI_ACTIVE_V_END() argument
205 return ((val) << DSI_ACTIVE_V_END__SHIFT) & DSI_ACTIVE_V_END__MASK; DSI_ACTIVE_V_END()
211 static inline uint32_t DSI_TOTAL_H_TOTAL(uint32_t val) DSI_TOTAL_H_TOTAL() argument
213 return ((val) << DSI_TOTAL_H_TOTAL__SHIFT) & DSI_TOTAL_H_TOTAL__MASK; DSI_TOTAL_H_TOTAL()
217 static inline uint32_t DSI_TOTAL_V_TOTAL(uint32_t val) DSI_TOTAL_V_TOTAL() argument
219 return ((val) << DSI_TOTAL_V_TOTAL__SHIFT) & DSI_TOTAL_V_TOTAL__MASK; DSI_TOTAL_V_TOTAL()
225 static inline uint32_t DSI_ACTIVE_HSYNC_START(uint32_t val) DSI_ACTIVE_HSYNC_START() argument
227 return ((val) << DSI_ACTIVE_HSYNC_START__SHIFT) & DSI_ACTIVE_HSYNC_START__MASK; DSI_ACTIVE_HSYNC_START()
231 static inline uint32_t DSI_ACTIVE_HSYNC_END(uint32_t val) DSI_ACTIVE_HSYNC_END() argument
233 return ((val) << DSI_ACTIVE_HSYNC_END__SHIFT) & DSI_ACTIVE_HSYNC_END__MASK; DSI_ACTIVE_HSYNC_END()
239 static inline uint32_t DSI_ACTIVE_VSYNC_HPOS_START(uint32_t val) DSI_ACTIVE_VSYNC_HPOS_START() argument
241 return ((val) << DSI_ACTIVE_VSYNC_HPOS_START__SHIFT) & DSI_ACTIVE_VSYNC_HPOS_START__MASK; DSI_ACTIVE_VSYNC_HPOS_START()
245 static inline uint32_t DSI_ACTIVE_VSYNC_HPOS_END(uint32_t val) DSI_ACTIVE_VSYNC_HPOS_END() argument
247 return ((val) << DSI_ACTIVE_VSYNC_HPOS_END__SHIFT) & DSI_ACTIVE_VSYNC_HPOS_END__MASK; DSI_ACTIVE_VSYNC_HPOS_END()
253 static inline uint32_t DSI_ACTIVE_VSYNC_VPOS_START(uint32_t val) DSI_ACTIVE_VSYNC_VPOS_START() argument
255 return ((val) << DSI_ACTIVE_VSYNC_VPOS_START__SHIFT) & DSI_ACTIVE_VSYNC_VPOS_START__MASK; DSI_ACTIVE_VSYNC_VPOS_START()
259 static inline uint32_t DSI_ACTIVE_VSYNC_VPOS_END(uint32_t val) DSI_ACTIVE_VSYNC_VPOS_END() argument
261 return ((val) << DSI_ACTIVE_VSYNC_VPOS_END__SHIFT) & DSI_ACTIVE_VSYNC_VPOS_END__MASK; DSI_ACTIVE_VSYNC_VPOS_END()
272 static inline uint32_t DSI_CMD_CFG0_DST_FORMAT(enum dsi_cmd_dst_format val) DSI_CMD_CFG0_DST_FORMAT() argument
274 return ((val) << DSI_CMD_CFG0_DST_FORMAT__SHIFT) & DSI_CMD_CFG0_DST_FORMAT__MASK; DSI_CMD_CFG0_DST_FORMAT()
281 static inline uint32_t DSI_CMD_CFG0_INTERLEAVE_MAX(uint32_t val) DSI_CMD_CFG0_INTERLEAVE_MAX() argument
283 return ((val) << DSI_CMD_CFG0_INTERLEAVE_MAX__SHIFT) & DSI_CMD_CFG0_INTERLEAVE_MAX__MASK; DSI_CMD_CFG0_INTERLEAVE_MAX()
287 static inline uint32_t DSI_CMD_CFG0_RGB_SWAP(enum dsi_rgb_swap val) DSI_CMD_CFG0_RGB_SWAP() argument
289 return ((val) << DSI_CMD_CFG0_RGB_SWAP__SHIFT) & DSI_CMD_CFG0_RGB_SWAP__MASK; DSI_CMD_CFG0_RGB_SWAP()
295 static inline uint32_t DSI_CMD_CFG1_WR_MEM_START(uint32_t val) DSI_CMD_CFG1_WR_MEM_START() argument
297 return ((val) << DSI_CMD_CFG1_WR_MEM_START__SHIFT) & DSI_CMD_CFG1_WR_MEM_START__MASK; DSI_CMD_CFG1_WR_MEM_START()
301 static inline uint32_t DSI_CMD_CFG1_WR_MEM_CONTINUE(uint32_t val) DSI_CMD_CFG1_WR_MEM_CONTINUE() argument
303 return ((val) << DSI_CMD_CFG1_WR_MEM_CONTINUE__SHIFT) & DSI_CMD_CFG1_WR_MEM_CONTINUE__MASK; DSI_CMD_CFG1_WR_MEM_CONTINUE()
314 static inline uint32_t DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE(uint32_t val) DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE() argument
316 return ((val) << DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__SHIFT) & DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__MASK; DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE()
320 static inline uint32_t DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL(uint32_t val) DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL() argument
322 return ((val) << DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__SHIFT) & DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__MASK; DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL()
326 static inline uint32_t DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT(uint32_t val) DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT() argument
328 return ((val) << DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__SHIFT) & DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__MASK; DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT()
334 static inline uint32_t DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL(uint32_t val) DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL() argument
336 return ((val) << DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__MASK; DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL()
340 static inline uint32_t DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL(uint32_t val) DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL() argument
342 return ((val) << DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__MASK; DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL()
354 static inline uint32_t DSI_TRIG_CTRL_DMA_TRIGGER(enum dsi_cmd_trigger val) DSI_TRIG_CTRL_DMA_TRIGGER() argument
356 return ((val) << DSI_TRIG_CTRL_DMA_TRIGGER__SHIFT) & DSI_TRIG_CTRL_DMA_TRIGGER__MASK; DSI_TRIG_CTRL_DMA_TRIGGER()
360 static inline uint32_t DSI_TRIG_CTRL_MDP_TRIGGER(enum dsi_cmd_trigger val) DSI_TRIG_CTRL_MDP_TRIGGER() argument
362 return ((val) << DSI_TRIG_CTRL_MDP_TRIGGER__SHIFT) & DSI_TRIG_CTRL_MDP_TRIGGER__MASK; DSI_TRIG_CTRL_MDP_TRIGGER()
366 static inline uint32_t DSI_TRIG_CTRL_STREAM(uint32_t val) DSI_TRIG_CTRL_STREAM() argument
368 return ((val) << DSI_TRIG_CTRL_STREAM__SHIFT) & DSI_TRIG_CTRL_STREAM__MASK; DSI_TRIG_CTRL_STREAM()
382 static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(uint32_t val) DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE() argument
384 return ((val) << DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__SHIFT) & DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__MASK; DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE()
388 static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(uint32_t val) DSI_CLKOUT_TIMING_CTRL_T_CLK_POST() argument
390 return ((val) << DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__SHIFT) & DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__MASK; DSI_CLKOUT_TIMING_CTRL_T_CLK_POST()
400 static inline uint32_t DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(enum dsi_lane_swap val) DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL() argument
402 return ((val) << DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__SHIFT) & DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__MASK; DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL()
429 static inline uint32_t DSI_RDBK_DATA_CTRL_COUNT(uint32_t val) DSI_RDBK_DATA_CTRL_COUNT() argument
431 return ((val) << DSI_RDBK_DATA_CTRL_COUNT__SHIFT) & DSI_RDBK_DATA_CTRL_COUNT__MASK; DSI_RDBK_DATA_CTRL_COUNT()
438 static inline uint32_t DSI_VERSION_MAJOR(uint32_t val) DSI_VERSION_MAJOR() argument
440 return ((val) << DSI_VERSION_MAJOR__SHIFT) & DSI_VERSION_MAJOR__MASK; DSI_VERSION_MAJOR()
700 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val) DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO() argument
702 return ((val) << DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK; DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO()
708 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val) DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL() argument
710 return ((val) << DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK; DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL()
716 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val) DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE() argument
718 return ((val) << DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK; DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE()
727 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val) DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT() argument
729 return ((val) << DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK; DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT()
735 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val) DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO() argument
737 return ((val) << DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK; DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO()
743 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val) DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE() argument
745 return ((val) << DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK; DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE()
751 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val) DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL() argument
753 return ((val) << DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK; DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL()
759 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val) DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST() argument
761 return ((val) << DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__MASK; DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST()
767 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val) DSI_28nm_PHY_TIMING_CTRL_9_TA_GO() argument
769 return ((val) << DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__MASK; DSI_28nm_PHY_TIMING_CTRL_9_TA_GO()
773 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val) DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE() argument
775 return ((val) << DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__MASK; DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE()
781 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val) DSI_28nm_PHY_TIMING_CTRL_10_TA_GET() argument
783 return ((val) << DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__MASK; DSI_28nm_PHY_TIMING_CTRL_10_TA_GET()
789 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val) DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD() argument
791 return ((val) << DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK; DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD()
/linux-4.1.27/drivers/clk/
H A Dclk-nspire.c45 static void nspire_clkinfo_cx(u32 val, struct nspire_clk_info *clk) nspire_clkinfo_cx() argument
47 if (EXTRACT(val, FIXED_BASE)) nspire_clkinfo_cx()
50 clk->base_clock = 6 * EXTRACT(val, CX_BASE) * MHZ; nspire_clkinfo_cx()
52 clk->base_cpu_ratio = EXTRACT(val, BASE_CPU) * EXTRACT(val, CX_UNKNOWN); nspire_clkinfo_cx()
53 clk->base_ahb_ratio = clk->base_cpu_ratio * (EXTRACT(val, CPU_AHB) + 1); nspire_clkinfo_cx()
56 static void nspire_clkinfo_classic(u32 val, struct nspire_clk_info *clk) nspire_clkinfo_classic() argument
58 if (EXTRACT(val, FIXED_BASE)) nspire_clkinfo_classic()
61 clk->base_clock = (300 - 6 * EXTRACT(val, CLASSIC_BASE)) * MHZ; nspire_clkinfo_classic()
63 clk->base_cpu_ratio = EXTRACT(val, BASE_CPU) * 2; nspire_clkinfo_classic()
64 clk->base_ahb_ratio = clk->base_cpu_ratio * (EXTRACT(val, CPU_AHB) + 1); nspire_clkinfo_classic()
70 u32 val; nspire_ahbdiv_setup() local
80 val = readl(io); nspire_ahbdiv_setup()
83 get_clkinfo(val, &info); nspire_ahbdiv_setup()
112 u32 val; nspire_clk_setup() local
121 val = readl(io); nspire_clk_setup()
124 get_clkinfo(val, &info); nspire_clk_setup()
/linux-4.1.27/include/net/
H A Dinetpeer.h70 static inline struct inet_peer *inetpeer_ptr(unsigned long val) inetpeer_ptr() argument
72 BUG_ON(val & INETPEER_BASE_BIT); inetpeer_ptr()
73 return (struct inet_peer *) val; inetpeer_ptr()
76 static inline struct inet_peer_base *inetpeer_base_ptr(unsigned long val) inetpeer_base_ptr() argument
78 if (!(val & INETPEER_BASE_BIT)) inetpeer_base_ptr()
80 val &= ~INETPEER_BASE_BIT; inetpeer_base_ptr()
81 return (struct inet_peer_base *) val; inetpeer_base_ptr()
84 static inline bool inetpeer_ptr_is_peer(unsigned long val) inetpeer_ptr_is_peer() argument
86 return !(val & INETPEER_BASE_BIT); inetpeer_ptr_is_peer()
89 static inline void __inetpeer_ptr_set_peer(unsigned long *val, struct inet_peer *peer) __inetpeer_ptr_set_peer() argument
92 *val = (unsigned long) peer; __inetpeer_ptr_set_peer()
97 unsigned long val = (unsigned long) peer; inetpeer_ptr_set_peer() local
101 cmpxchg(ptr, orig, val) != orig) inetpeer_ptr_set_peer()
113 unsigned long val = *from; inetpeer_transfer_peer() local
115 *to = val; inetpeer_transfer_peer()
116 if (inetpeer_ptr_is_peer(val)) { inetpeer_transfer_peer()
117 struct inet_peer *peer = inetpeer_ptr(val); inetpeer_transfer_peer()
/linux-4.1.27/arch/arm/mach-at91/
H A Dsam9_smc.c78 u32 val = __raw_readl(base + AT91_SMC_MODE); sam9_smc_cs_read_mode() local
80 config->mode = (val & ~AT91_SMC_NWECYCLE); sam9_smc_cs_read_mode()
81 config->tdf_cycles = (val & AT91_SMC_NWECYCLE) >> 16 ; sam9_smc_cs_read_mode()
94 u32 val; sam9_smc_cs_read() local
97 val = __raw_readl(base + AT91_SMC_SETUP); sam9_smc_cs_read()
99 config->nwe_setup = val & AT91_SMC_NWESETUP; sam9_smc_cs_read()
100 config->ncs_write_setup = (val & AT91_SMC_NCS_WRSETUP) >> 8; sam9_smc_cs_read()
101 config->nrd_setup = (val & AT91_SMC_NRDSETUP) >> 16; sam9_smc_cs_read()
102 config->ncs_read_setup = (val & AT91_SMC_NCS_RDSETUP) >> 24; sam9_smc_cs_read()
105 val = __raw_readl(base + AT91_SMC_PULSE); sam9_smc_cs_read()
107 config->nwe_pulse = val & AT91_SMC_NWEPULSE; sam9_smc_cs_read()
108 config->ncs_write_pulse = (val & AT91_SMC_NCS_WRPULSE) >> 8; sam9_smc_cs_read()
109 config->nrd_pulse = (val & AT91_SMC_NRDPULSE) >> 16; sam9_smc_cs_read()
110 config->ncs_read_pulse = (val & AT91_SMC_NCS_RDPULSE) >> 24; sam9_smc_cs_read()
113 val = __raw_readl(base + AT91_SMC_CYCLE); sam9_smc_cs_read()
115 config->write_cycle = val & AT91_SMC_NWECYCLE; sam9_smc_cs_read()
116 config->read_cycle = (val & AT91_SMC_NRDCYCLE) >> 16; sam9_smc_cs_read()
/linux-4.1.27/arch/tile/lib/
H A Dspinlock_32.c106 u32 val; arch_read_trylock() local
108 val = __insn_tns((int *)&rwlock->lock); arch_read_trylock()
109 if (likely((val << _RD_COUNT_WIDTH) == 0)) { arch_read_trylock()
110 val += 1 << RD_COUNT_SHIFT; arch_read_trylock()
111 rwlock->lock = val; arch_read_trylock()
113 BUG_ON(val == 0); /* we don't expect wraparound */ arch_read_trylock()
116 if ((val & 1) == 0) arch_read_trylock()
117 rwlock->lock = val; arch_read_trylock()
141 u32 val, iterations = 0; arch_read_unlock() local
146 val = __insn_tns((int *)&rwlock->lock); arch_read_unlock()
147 if (likely((val & 1) == 0)) { arch_read_unlock()
148 rwlock->lock = val - (1 << _RD_COUNT_SHIFT); arch_read_unlock()
172 u32 val = __insn_tns((int *)&rwlock->lock); arch_write_lock() local
174 if (likely(val == 0)) { arch_write_lock()
184 if (!(val & 1)) { arch_write_lock()
185 if ((val >> RD_COUNT_SHIFT) == 0) arch_write_lock()
187 rwlock->lock = val; arch_write_lock()
190 val = __insn_tns((int *)&rwlock->lock); arch_write_lock()
194 rwlock->lock = __insn_addb(val, 1 << WR_NEXT_SHIFT); arch_write_lock()
195 my_ticket_ = val >> WR_NEXT_SHIFT; arch_write_lock()
199 u32 curr_ = val >> WR_CURR_SHIFT; arch_write_lock()
212 while ((val = rwlock->lock) & 1) arch_write_lock()
220 u32 val = __insn_tns((int *)&rwlock->lock); arch_write_trylock() local
226 if (unlikely(val != 0)) { arch_write_trylock()
227 if (!(val & 1)) arch_write_trylock()
228 rwlock->lock = val; arch_write_trylock()
240 u32 val, eq, mask; arch_write_unlock() local
243 val = __insn_tns((int *)&rwlock->lock); arch_write_unlock()
244 if (likely(val == (1 << _WR_NEXT_SHIFT))) { arch_write_unlock()
248 while (unlikely(val & 1)) { arch_write_unlock()
251 val = __insn_tns((int *)&rwlock->lock); arch_write_unlock()
254 val = __insn_addb(val, mask); arch_write_unlock()
255 eq = __insn_seqb(val, val << (WR_CURR_SHIFT - WR_NEXT_SHIFT)); arch_write_unlock()
256 val = __insn_mz(eq & mask, val); arch_write_unlock()
257 rwlock->lock = val; arch_write_unlock()
/linux-4.1.27/drivers/clk/hisilicon/
H A Dclk-hix5hd2.c175 u32 val; clk_ether_prepare() local
177 val = readl_relaxed(clk->ctrl_reg); clk_ether_prepare()
178 val |= clk->ctrl_clk_mask | clk->ctrl_rst_mask; clk_ether_prepare()
179 writel_relaxed(val, clk->ctrl_reg); clk_ether_prepare()
180 val &= ~(clk->ctrl_rst_mask); clk_ether_prepare()
181 writel_relaxed(val, clk->ctrl_reg); clk_ether_prepare()
183 val = readl_relaxed(clk->phy_reg); clk_ether_prepare()
184 val |= clk->phy_clk_mask; clk_ether_prepare()
185 val &= ~(clk->phy_rst_mask); clk_ether_prepare()
186 writel_relaxed(val, clk->phy_reg); clk_ether_prepare()
189 val &= ~(clk->phy_clk_mask); clk_ether_prepare()
190 val |= clk->phy_rst_mask; clk_ether_prepare()
191 writel_relaxed(val, clk->phy_reg); clk_ether_prepare()
194 val |= clk->phy_clk_mask; clk_ether_prepare()
195 val &= ~(clk->phy_rst_mask); clk_ether_prepare()
196 writel_relaxed(val, clk->phy_reg); clk_ether_prepare()
204 u32 val; clk_ether_unprepare() local
206 val = readl_relaxed(clk->ctrl_reg); clk_ether_unprepare()
207 val &= ~(clk->ctrl_clk_mask); clk_ether_unprepare()
208 writel_relaxed(val, clk->ctrl_reg); clk_ether_unprepare()
219 u32 val; clk_complex_enable() local
221 val = readl_relaxed(clk->ctrl_reg); clk_complex_enable()
222 val |= clk->ctrl_clk_mask; clk_complex_enable()
223 val &= ~(clk->ctrl_rst_mask); clk_complex_enable()
224 writel_relaxed(val, clk->ctrl_reg); clk_complex_enable()
226 val = readl_relaxed(clk->phy_reg); clk_complex_enable()
227 val |= clk->phy_clk_mask; clk_complex_enable()
228 val &= ~(clk->phy_rst_mask); clk_complex_enable()
229 writel_relaxed(val, clk->phy_reg); clk_complex_enable()
237 u32 val; clk_complex_disable() local
239 val = readl_relaxed(clk->ctrl_reg); clk_complex_disable()
240 val |= clk->ctrl_rst_mask; clk_complex_disable()
241 val &= ~(clk->ctrl_clk_mask); clk_complex_disable()
242 writel_relaxed(val, clk->ctrl_reg); clk_complex_disable()
244 val = readl_relaxed(clk->phy_reg); clk_complex_disable()
245 val |= clk->phy_rst_mask; clk_complex_disable()
246 val &= ~(clk->phy_clk_mask); clk_complex_disable()
247 writel_relaxed(val, clk->phy_reg); clk_complex_disable()
/linux-4.1.27/arch/mips/include/asm/mach-ralink/
H A Dralink_regs.h19 static inline void rt_sysc_w32(u32 val, unsigned reg) rt_sysc_w32() argument
21 __raw_writel(val, rt_sysc_membase + reg); rt_sysc_w32()
31 u32 val = rt_sysc_r32(reg) & ~clr; rt_sysc_m32() local
33 __raw_writel(val | set, rt_sysc_membase + reg); rt_sysc_m32()
36 static inline void rt_memc_w32(u32 val, unsigned reg) rt_memc_w32() argument
38 __raw_writel(val, rt_memc_membase + reg); rt_memc_w32()
/linux-4.1.27/arch/ia64/include/asm/
H A Dacenv.h25 unsigned int old, new, val; ia64_acpi_acquire_global_lock() local
29 val = ia64_cmpxchg4_acq(lock, new, old); ia64_acpi_acquire_global_lock()
30 } while (unlikely (val != old)); ia64_acpi_acquire_global_lock()
37 unsigned int old, new, val; ia64_acpi_release_global_lock() local
41 val = ia64_cmpxchg4_acq(lock, new, old); ia64_acpi_release_global_lock()
42 } while (unlikely (val != old)); ia64_acpi_release_global_lock()
/linux-4.1.27/net/bluetooth/
H A Dhci_debugfs.c203 u8 i, val[16]; uuids_show() local
210 val[i] = uuid->uuid[15 - i]; uuids_show()
212 seq_printf(f, "%pUb\n", val); uuids_show()
260 static int conn_info_min_age_set(void *data, u64 val) conn_info_min_age_set() argument
264 if (val == 0 || val > hdev->conn_info_max_age) conn_info_min_age_set()
268 hdev->conn_info_min_age = val; conn_info_min_age_set()
274 static int conn_info_min_age_get(void *data, u64 *val) conn_info_min_age_get() argument
279 *val = hdev->conn_info_min_age; conn_info_min_age_get()
288 static int conn_info_max_age_set(void *data, u64 val) conn_info_max_age_set() argument
292 if (val == 0 || val < hdev->conn_info_min_age) conn_info_max_age_set()
296 hdev->conn_info_max_age = val; conn_info_max_age_set()
302 static int conn_info_max_age_get(void *data, u64 *val) conn_info_max_age_get() argument
307 *val = hdev->conn_info_max_age; conn_info_max_age_get()
431 HCI_LINK_KEY_SIZE, key->val, key->pin_len); link_keys_show()
473 static int voice_setting_get(void *data, u64 *val) voice_setting_get() argument
478 *val = hdev->voice_setting; voice_setting_get()
505 static int auto_accept_delay_set(void *data, u64 val) auto_accept_delay_set() argument
510 hdev->auto_accept_delay = val; auto_accept_delay_set()
516 static int auto_accept_delay_get(void *data, u64 *val) auto_accept_delay_get() argument
521 *val = hdev->auto_accept_delay; auto_accept_delay_get()
530 static int idle_timeout_set(void *data, u64 val) idle_timeout_set() argument
534 if (val != 0 && (val < 500 || val > 3600000)) idle_timeout_set()
538 hdev->idle_timeout = val; idle_timeout_set()
544 static int idle_timeout_get(void *data, u64 *val) idle_timeout_get() argument
549 *val = hdev->idle_timeout; idle_timeout_get()
558 static int sniff_min_interval_set(void *data, u64 val) sniff_min_interval_set() argument
562 if (val == 0 || val % 2 || val > hdev->sniff_max_interval) sniff_min_interval_set()
566 hdev->sniff_min_interval = val; sniff_min_interval_set()
572 static int sniff_min_interval_get(void *data, u64 *val) sniff_min_interval_get() argument
577 *val = hdev->sniff_min_interval; sniff_min_interval_get()
586 static int sniff_max_interval_set(void *data, u64 val) sniff_max_interval_set() argument
590 if (val == 0 || val % 2 || val < hdev->sniff_min_interval) sniff_max_interval_set()
594 hdev->sniff_max_interval = val; sniff_max_interval_set()
600 static int sniff_max_interval_get(void *data, u64 *val) sniff_max_interval_get() argument
605 *val = hdev->sniff_max_interval; sniff_max_interval_get()
672 static int rpa_timeout_set(void *data, u64 val) rpa_timeout_set() argument
679 if (val < 30 || val > (60 * 60 * 24)) rpa_timeout_set()
683 hdev->rpa_timeout = val; rpa_timeout_set()
689 static int rpa_timeout_get(void *data, u64 *val) rpa_timeout_get() argument
694 *val = hdev->rpa_timeout; rpa_timeout_get()
830 16, irk->val, &irk->rpa); identity_resolving_keys_show()
860 __le64_to_cpu(ltk->rand), 16, ltk->val); long_term_keys_show()
878 static int conn_min_interval_set(void *data, u64 val) conn_min_interval_set() argument
882 if (val < 0x0006 || val > 0x0c80 || val > hdev->le_conn_max_interval) conn_min_interval_set()
886 hdev->le_conn_min_interval = val; conn_min_interval_set()
892 static int conn_min_interval_get(void *data, u64 *val) conn_min_interval_get() argument
897 *val = hdev->le_conn_min_interval; conn_min_interval_get()
906 static int conn_max_interval_set(void *data, u64 val) conn_max_interval_set() argument
910 if (val < 0x0006 || val > 0x0c80 || val < hdev->le_conn_min_interval) conn_max_interval_set()
914 hdev->le_conn_max_interval = val; conn_max_interval_set()
920 static int conn_max_interval_get(void *data, u64 *val) conn_max_interval_get() argument
925 *val = hdev->le_conn_max_interval; conn_max_interval_get()
934 static int conn_latency_set(void *data, u64 val) conn_latency_set() argument
938 if (val > 0x01f3) conn_latency_set()
942 hdev->le_conn_latency = val; conn_latency_set()
948 static int conn_latency_get(void *data, u64 *val) conn_latency_get() argument
953 *val = hdev->le_conn_latency; conn_latency_get()
962 static int supervision_timeout_set(void *data, u64 val) supervision_timeout_set() argument
966 if (val < 0x000a || val > 0x0c80) supervision_timeout_set()
970 hdev->le_supv_timeout = val; supervision_timeout_set()
976 static int supervision_timeout_get(void *data, u64 *val) supervision_timeout_get() argument
981 *val = hdev->le_supv_timeout; supervision_timeout_get()
990 static int adv_channel_map_set(void *data, u64 val) adv_channel_map_set() argument
994 if (val < 0x01 || val > 0x07) adv_channel_map_set()
998 hdev->le_adv_channel_map = val; adv_channel_map_set()
1004 static int adv_channel_map_get(void *data, u64 *val) adv_channel_map_get() argument
1009 *val = hdev->le_adv_channel_map; adv_channel_map_get()
1018 static int adv_min_interval_set(void *data, u64 val) adv_min_interval_set() argument
1022 if (val < 0x0020 || val > 0x4000 || val > hdev->le_adv_max_interval) adv_min_interval_set()
1026 hdev->le_adv_min_interval = val; adv_min_interval_set()
1032 static int adv_min_interval_get(void *data, u64 *val) adv_min_interval_get() argument
1037 *val = hdev->le_adv_min_interval; adv_min_interval_get()
1046 static int adv_max_interval_set(void *data, u64 val) adv_max_interval_set() argument
1050 if (val < 0x0020 || val > 0x4000 || val < hdev->le_adv_min_interval) adv_max_interval_set()
1054 hdev->le_adv_max_interval = val; adv_max_interval_set()
1060 static int adv_max_interval_get(void *data, u64 *val) adv_max_interval_get() argument
1065 *val = hdev->le_adv_max_interval; adv_max_interval_get()
/linux-4.1.27/samples/bpf/
H A Dtracex4_user.c19 long long val; member in struct:pair
33 long long val = time_get_ns(); print_old_objects() local
43 if (val - v.val < 1000000000ll) print_old_objects()
47 next_key, (val - v.val) / 1000000000ll, v.ip); print_old_objects()
/linux-4.1.27/drivers/gpu/drm/exynos/
H A Dexynos7_drm_decon.c100 u32 val = readl(ctx->regs + WINCON(win)); decon_clear_channel() local
102 if (val & WINCONx_ENWIN) { decon_clear_channel()
103 val &= ~WINCONx_ENWIN; decon_clear_channel()
104 writel(val, ctx->regs + WINCON(win)); decon_clear_channel()
179 u32 val, clkdiv; decon_commit() local
195 val = VIDTCON0_VBPD(vbpd - 1) | VIDTCON0_VFPD(vfpd - 1); decon_commit()
196 writel(val, ctx->regs + VIDTCON0); decon_commit()
198 val = VIDTCON1_VSPW(vsync_len - 1); decon_commit()
199 writel(val, ctx->regs + VIDTCON1); decon_commit()
207 val = VIDTCON2_HBPD(hbpd - 1) | VIDTCON2_HFPD(hfpd - 1); decon_commit()
208 writel(val, ctx->regs + VIDTCON2); decon_commit()
210 val = VIDTCON3_HSPW(hsync_len - 1); decon_commit()
211 writel(val, ctx->regs + VIDTCON3); decon_commit()
215 val = VIDTCON4_LINEVAL(mode->vdisplay - 1) | decon_commit()
217 writel(val, ctx->regs + VIDTCON4); decon_commit()
225 val = VIDCON0_ENVID | VIDCON0_ENVID_F; decon_commit()
226 writel(val, ctx->regs + VIDCON0); decon_commit()
230 val = VCLKCON1_CLKVAL_NUM_VCLK(clkdiv - 1); decon_commit()
231 writel(val, ctx->regs + VCLKCON1); decon_commit()
232 writel(val, ctx->regs + VCLKCON2); decon_commit()
235 val = readl(ctx->regs + DECON_UPDATE); decon_commit()
236 val |= DECON_UPDATE_STANDALONE_F; decon_commit()
237 writel(val, ctx->regs + DECON_UPDATE); decon_commit()
243 u32 val; decon_enable_vblank() local
249 val = readl(ctx->regs + VIDINTCON0); decon_enable_vblank()
251 val |= VIDINTCON0_INT_ENABLE; decon_enable_vblank()
254 val |= VIDINTCON0_INT_FRAME; decon_enable_vblank()
255 val &= ~VIDINTCON0_FRAMESEL0_MASK; decon_enable_vblank()
256 val |= VIDINTCON0_FRAMESEL0_VSYNC; decon_enable_vblank()
259 writel(val, ctx->regs + VIDINTCON0); decon_enable_vblank()
268 u32 val; decon_disable_vblank() local
274 val = readl(ctx->regs + VIDINTCON0); decon_disable_vblank()
276 val &= ~VIDINTCON0_INT_ENABLE; decon_disable_vblank()
278 val &= ~VIDINTCON0_INT_FRAME; decon_disable_vblank()
280 writel(val, ctx->regs + VIDINTCON0); decon_disable_vblank()
287 unsigned long val; decon_win_set_pixfmt() local
290 val = readl(ctx->regs + WINCON(win)); decon_win_set_pixfmt()
291 val &= ~WINCONx_BPPMODE_MASK; decon_win_set_pixfmt()
295 val |= WINCONx_BPPMODE_16BPP_565; decon_win_set_pixfmt()
296 val |= WINCONx_BURSTLEN_16WORD; decon_win_set_pixfmt()
299 val |= WINCONx_BPPMODE_24BPP_xRGB; decon_win_set_pixfmt()
300 val |= WINCONx_BURSTLEN_16WORD; decon_win_set_pixfmt()
303 val |= WINCONx_BPPMODE_24BPP_xBGR; decon_win_set_pixfmt()
304 val |= WINCONx_BURSTLEN_16WORD; decon_win_set_pixfmt()
307 val |= WINCONx_BPPMODE_24BPP_RGBx; decon_win_set_pixfmt()
308 val |= WINCONx_BURSTLEN_16WORD; decon_win_set_pixfmt()
311 val |= WINCONx_BPPMODE_24BPP_BGRx; decon_win_set_pixfmt()
312 val |= WINCONx_BURSTLEN_16WORD; decon_win_set_pixfmt()
315 val |= WINCONx_BPPMODE_32BPP_ARGB | WINCONx_BLD_PIX | decon_win_set_pixfmt()
317 val |= WINCONx_BURSTLEN_16WORD; decon_win_set_pixfmt()
320 val |= WINCONx_BPPMODE_32BPP_ABGR | WINCONx_BLD_PIX | decon_win_set_pixfmt()
322 val |= WINCONx_BURSTLEN_16WORD; decon_win_set_pixfmt()
325 val |= WINCONx_BPPMODE_32BPP_RGBA | WINCONx_BLD_PIX | decon_win_set_pixfmt()
327 val |= WINCONx_BURSTLEN_16WORD; decon_win_set_pixfmt()
330 val |= WINCONx_BPPMODE_32BPP_BGRA | WINCONx_BLD_PIX | decon_win_set_pixfmt()
332 val |= WINCONx_BURSTLEN_16WORD; decon_win_set_pixfmt()
337 val |= WINCONx_BPPMODE_24BPP_xRGB; decon_win_set_pixfmt()
338 val |= WINCONx_BURSTLEN_16WORD; decon_win_set_pixfmt()
354 val &= ~WINCONx_BURSTLEN_MASK; decon_win_set_pixfmt()
355 val |= WINCONx_BURSTLEN_8WORD; decon_win_set_pixfmt()
358 writel(val, ctx->regs + WINCON(win)); decon_win_set_pixfmt()
383 u32 bits, val; decon_shadow_protect_win() local
387 val = readl(ctx->regs + SHADOWCON); decon_shadow_protect_win()
389 val |= bits; decon_shadow_protect_win()
391 val &= ~bits; decon_shadow_protect_win()
392 writel(val, ctx->regs + SHADOWCON); decon_shadow_protect_win()
401 unsigned long val, alpha; decon_win_commit() local
433 val = (unsigned long)plane->dma_addr[0]; decon_win_commit()
434 writel(val, ctx->regs + VIDW_BUF_START(win)); decon_win_commit()
447 (unsigned long)val); decon_win_commit()
460 val = VIDOSDxA_TOPLEFT_X(plane->crtc_x) | decon_win_commit()
462 writel(val, ctx->regs + VIDOSD_A(win)); decon_win_commit()
471 val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y); decon_win_commit()
473 writel(val, ctx->regs + VIDOSD_B(win)); decon_win_commit()
498 val = readl(ctx->regs + WINCON(win)); decon_win_commit()
499 val |= WINCONx_TRIPLE_BUF_MODE; decon_win_commit()
500 val |= WINCONx_ENWIN; decon_win_commit()
501 writel(val, ctx->regs + WINCON(win)); decon_win_commit()
506 val = readl(ctx->regs + DECON_UPDATE); decon_win_commit()
507 val |= DECON_UPDATE_STANDALONE_F; decon_win_commit()
508 writel(val, ctx->regs + DECON_UPDATE); decon_win_commit()
517 u32 val; decon_win_disable() local
534 val = readl(ctx->regs + WINCON(win)); decon_win_disable()
535 val &= ~WINCONx_ENWIN; decon_win_disable()
536 writel(val, ctx->regs + WINCON(win)); decon_win_disable()
541 val = readl(ctx->regs + DECON_UPDATE); decon_win_disable()
542 val |= DECON_UPDATE_STANDALONE_F; decon_win_disable()
543 writel(val, ctx->regs + DECON_UPDATE); decon_win_disable()
591 u32 val; decon_init() local
595 val = VIDOUTCON0_DISP_IF_0_ON; decon_init()
597 val |= VIDOUTCON0_RGBIF; decon_init()
598 writel(val, ctx->regs + VIDOUTCON0); decon_init()
728 u32 val, clear_bit; decon_irq_handler() local
730 val = readl(ctx->regs + VIDINTCON1); decon_irq_handler()
733 if (val & clear_bit) decon_irq_handler()
/linux-4.1.27/drivers/media/i2c/smiapp/
H A Dsmiapp-regs.c72 * Read a 8/16/32-bit i2c register. The value is returned in 'val'.
76 u16 len, u32 *val) ____smiapp_read()
108 *val = 0; ____smiapp_read()
112 *val = (data[0] << 24) + (data[1] << 16) + (data[2] << 8) + ____smiapp_read()
116 *val = (data[0] << 8) + data[1]; ____smiapp_read()
119 *val = data[0]; ____smiapp_read()
135 u16 len, u32 *val) ____smiapp_read_8only()
140 *val = 0; ____smiapp_read_8only()
148 *val |= val8 << ((len - i - 1) << 3); ____smiapp_read_8only()
155 * Read a 8/16/32-bit i2c register. The value is returned in 'val'.
158 static int __smiapp_read(struct smiapp_sensor *sensor, u32 reg, u32 *val, __smiapp_read() argument
170 rval = ____smiapp_read(sensor, SMIAPP_REG_ADDR(reg), len, val); __smiapp_read()
173 val); __smiapp_read()
178 *val = float_to_u32_mul_1000000(client, *val); __smiapp_read()
183 int smiapp_read_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 *val) smiapp_read_no_quirk() argument
186 sensor, reg, val, smiapp_read_no_quirk()
191 int smiapp_read(struct smiapp_sensor *sensor, u32 reg, u32 *val) smiapp_read() argument
195 *val = 0; smiapp_read()
196 rval = smiapp_call_quirk(sensor, reg_access, false, &reg, val); smiapp_read()
202 return smiapp_read_no_quirk(sensor, reg, val); smiapp_read()
205 int smiapp_read_8only(struct smiapp_sensor *sensor, u32 reg, u32 *val) smiapp_read_8only() argument
209 *val = 0; smiapp_read_8only()
210 rval = smiapp_call_quirk(sensor, reg_access, false, &reg, val); smiapp_read_8only()
216 return __smiapp_read(sensor, reg, val, true); smiapp_read_8only()
219 int smiapp_write_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 val) smiapp_write_no_quirk() argument
245 data[2] = val; smiapp_write_no_quirk()
248 data[2] = val >> 8; smiapp_write_no_quirk()
249 data[3] = val; smiapp_write_no_quirk()
252 data[2] = val >> 24; smiapp_write_no_quirk()
253 data[3] = val >> 16; smiapp_write_no_quirk()
254 data[4] = val >> 8; smiapp_write_no_quirk()
255 data[5] = val; smiapp_write_no_quirk()
280 "wrote 0x%x to offset 0x%x error %d\n", val, offset, r); smiapp_write_no_quirk()
289 int smiapp_write(struct smiapp_sensor *sensor, u32 reg, u32 val) smiapp_write() argument
293 rval = smiapp_call_quirk(sensor, reg_access, true, &reg, &val); smiapp_write()
299 return smiapp_write_no_quirk(sensor, reg, val); smiapp_write()
75 ____smiapp_read(struct smiapp_sensor *sensor, u16 reg, u16 len, u32 *val) ____smiapp_read() argument
134 ____smiapp_read_8only(struct smiapp_sensor *sensor, u16 reg, u16 len, u32 *val) ____smiapp_read_8only() argument
/linux-4.1.27/drivers/staging/comedi/drivers/
H A Dc6xdigio.c73 unsigned int val, unsigned int status) c6xdigio_write_data()
75 outb_p(val, dev->iobase + C6XDIGIO_DATA_REG); c6xdigio_write_data()
84 unsigned int val; c6xdigio_get_encoder_bits() local
86 val = inb(dev->iobase + C6XDIGIO_STATUS_REG); c6xdigio_get_encoder_bits()
87 val >>= 3; c6xdigio_get_encoder_bits()
88 val &= 0x07; c6xdigio_get_encoder_bits()
90 *bits = val; c6xdigio_get_encoder_bits()
96 unsigned int chan, unsigned int val) c6xdigio_pwm_write()
101 if (val > 498) c6xdigio_pwm_write()
102 val = 498; c6xdigio_pwm_write()
103 if (val < 2) c6xdigio_pwm_write()
104 val = 2; c6xdigio_pwm_write()
106 bits = (val >> 0) & 0x03; c6xdigio_pwm_write()
108 bits = (val >> 2) & 0x03; c6xdigio_pwm_write()
110 bits = (val >> 4) & 0x03; c6xdigio_pwm_write()
112 bits = (val >> 6) & 0x03; c6xdigio_pwm_write()
114 bits = (val >> 8) & 0x03; c6xdigio_pwm_write()
124 unsigned int val = 0; c6xdigio_encoder_read() local
130 val |= (bits << 0); c6xdigio_encoder_read()
133 val |= (bits << 3); c6xdigio_encoder_read()
136 val |= (bits << 6); c6xdigio_encoder_read()
139 val |= (bits << 9); c6xdigio_encoder_read()
142 val |= (bits << 12); c6xdigio_encoder_read()
145 val |= (bits << 15); c6xdigio_encoder_read()
148 val |= (bits << 18); c6xdigio_encoder_read()
151 val |= (bits << 21); c6xdigio_encoder_read()
155 return val; c6xdigio_encoder_read()
164 unsigned int val = (s->state >> (16 * chan)) & 0xffff; c6xdigio_pwm_insn_write() local
168 val = data[i]; c6xdigio_pwm_insn_write()
169 c6xdigio_pwm_write(dev, chan, val); c6xdigio_pwm_insn_write()
179 s->state |= (val << (16 * chan)); c6xdigio_pwm_insn_write()
190 unsigned int val; c6xdigio_pwm_insn_read() local
193 val = (s->state >> (16 * chan)) & 0xffff; c6xdigio_pwm_insn_read()
196 data[i] = val; c6xdigio_pwm_insn_read()
207 unsigned int val; c6xdigio_encoder_insn_read() local
211 val = c6xdigio_encoder_read(dev, chan); c6xdigio_encoder_insn_read()
214 data[i] = comedi_offset_munge(s, val); c6xdigio_encoder_insn_read()
72 c6xdigio_write_data(struct comedi_device *dev, unsigned int val, unsigned int status) c6xdigio_write_data() argument
95 c6xdigio_pwm_write(struct comedi_device *dev, unsigned int chan, unsigned int val) c6xdigio_pwm_write() argument
/linux-4.1.27/drivers/rapidio/
H A Drio-sysfs.c148 u8 val; rio_read_config() local
149 rio_read_config_8(dev, off, &val); rio_read_config()
150 data[off - init_off] = val; rio_read_config()
156 u16 val; rio_read_config() local
157 rio_read_config_16(dev, off, &val); rio_read_config()
158 data[off - init_off] = (val >> 8) & 0xff; rio_read_config()
159 data[off - init_off + 1] = val & 0xff; rio_read_config()
165 u32 val; rio_read_config() local
166 rio_read_config_32(dev, off, &val); rio_read_config()
167 data[off - init_off] = (val >> 24) & 0xff; rio_read_config()
168 data[off - init_off + 1] = (val >> 16) & 0xff; rio_read_config()
169 data[off - init_off + 2] = (val >> 8) & 0xff; rio_read_config()
170 data[off - init_off + 3] = val & 0xff; rio_read_config()
176 u16 val; rio_read_config() local
177 rio_read_config_16(dev, off, &val); rio_read_config()
178 data[off - init_off] = (val >> 8) & 0xff; rio_read_config()
179 data[off - init_off + 1] = val & 0xff; rio_read_config()
185 u8 val; rio_read_config() local
186 rio_read_config_8(dev, off, &val); rio_read_config()
187 data[off - init_off] = val; rio_read_config()
220 u16 val = data[off - init_off + 1]; rio_write_config() local
221 val |= (u16) data[off - init_off] << 8; rio_write_config()
222 rio_write_config_16(dev, off, val); rio_write_config()
228 u32 val = data[off - init_off + 3]; rio_write_config() local
229 val |= (u32) data[off - init_off + 2] << 8; rio_write_config()
230 val |= (u32) data[off - init_off + 1] << 16; rio_write_config()
231 val |= (u32) data[off - init_off] << 24; rio_write_config()
232 rio_write_config_32(dev, off, val); rio_write_config()
238 u16 val = data[off - init_off + 1]; rio_write_config() local
239 val |= (u16) data[off - init_off] << 8; rio_write_config()
240 rio_write_config_16(dev, off, val); rio_write_config()
308 long val; bus_scan_store() local
311 if (kstrtol(buf, 0, &val) < 0) bus_scan_store()
314 if (val == RIO_MPORT_ANY) { bus_scan_store()
319 if (val < 0 || val >= RIO_MAX_MPORTS) bus_scan_store()
322 rc = rio_mport_scan((int)val); bus_scan_store()
/linux-4.1.27/arch/mips/boot/compressed/
H A Ddbg.c25 void puthex(unsigned long long val) puthex() argument
31 buf[i] = "0123456789ABCDEF"[val & 0x0F]; puthex()
32 val >>= 4; puthex()
/linux-4.1.27/arch/mn10300/unit-asb2364/
H A Dleds.c39 void peripheral_leds7x4_display_dec(unsigned int val, unsigned int points) peripheral_leds7x4_display_dec() argument
43 leds = asb2364_led_hex_tbl[(val/1000) % 10]; peripheral_leds7x4_display_dec()
45 leds |= asb2364_led_hex_tbl[(val/100) % 10]; peripheral_leds7x4_display_dec()
47 leds |= asb2364_led_hex_tbl[(val/10) % 10]; peripheral_leds7x4_display_dec()
49 leds |= asb2364_led_hex_tbl[val % 10]; peripheral_leds7x4_display_dec()
55 void peripheral_leds7x4_display_hex(unsigned int val, unsigned int points) peripheral_leds7x4_display_hex() argument
59 leds = asb2364_led_hex_tbl[(val/1000) % 10]; peripheral_leds7x4_display_hex()
61 leds |= asb2364_led_hex_tbl[(val/100) % 10]; peripheral_leds7x4_display_hex()
63 leds |= asb2364_led_hex_tbl[(val/10) % 10]; peripheral_leds7x4_display_hex()
65 leds |= asb2364_led_hex_tbl[val % 10]; peripheral_leds7x4_display_hex()
94 void peripheral_leds7x4_display_dec(unsigned int val, unsigned int points) { } peripheral_leds7x4_display_hex() argument
95 void peripheral_leds7x4_display_hex(unsigned int val, unsigned int points) { } peripheral_leds_display_exception() argument

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