1#ifndef __ASM_ARM_CP15_H
2#define __ASM_ARM_CP15_H
3
4#include <asm/barrier.h>
5
6/*
7 * CR1 bits (CP#15 CR1)
8 */
9#define CR_M	(1 << 0)	/* MMU enable				*/
10#define CR_A	(1 << 1)	/* Alignment abort enable		*/
11#define CR_C	(1 << 2)	/* Dcache enable			*/
12#define CR_W	(1 << 3)	/* Write buffer enable			*/
13#define CR_P	(1 << 4)	/* 32-bit exception handler		*/
14#define CR_D	(1 << 5)	/* 32-bit data address range		*/
15#define CR_L	(1 << 6)	/* Implementation defined		*/
16#define CR_B	(1 << 7)	/* Big endian				*/
17#define CR_S	(1 << 8)	/* System MMU protection		*/
18#define CR_R	(1 << 9)	/* ROM MMU protection			*/
19#define CR_F	(1 << 10)	/* Implementation defined		*/
20#define CR_Z	(1 << 11)	/* Implementation defined		*/
21#define CR_I	(1 << 12)	/* Icache enable			*/
22#define CR_V	(1 << 13)	/* Vectors relocated to 0xffff0000	*/
23#define CR_RR	(1 << 14)	/* Round Robin cache replacement	*/
24#define CR_L4	(1 << 15)	/* LDR pc can set T bit			*/
25#define CR_DT	(1 << 16)
26#ifdef CONFIG_MMU
27#define CR_HA	(1 << 17)	/* Hardware management of Access Flag   */
28#else
29#define CR_BR	(1 << 17)	/* MPU Background region enable (PMSA)  */
30#endif
31#define CR_IT	(1 << 18)
32#define CR_ST	(1 << 19)
33#define CR_FI	(1 << 21)	/* Fast interrupt (lower latency mode)	*/
34#define CR_U	(1 << 22)	/* Unaligned access operation		*/
35#define CR_XP	(1 << 23)	/* Extended page tables			*/
36#define CR_VE	(1 << 24)	/* Vectored interrupts			*/
37#define CR_EE	(1 << 25)	/* Exception (Big) Endian		*/
38#define CR_TRE	(1 << 28)	/* TEX remap enable			*/
39#define CR_AFE	(1 << 29)	/* Access flag enable			*/
40#define CR_TE	(1 << 30)	/* Thumb exception enable		*/
41
42#ifndef __ASSEMBLY__
43
44#if __LINUX_ARM_ARCH__ >= 4
45#define vectors_high()	(get_cr() & CR_V)
46#else
47#define vectors_high()	(0)
48#endif
49
50#ifdef CONFIG_CPU_CP15
51
52extern unsigned long cr_alignment;	/* defined in entry-armv.S */
53
54static inline unsigned long get_cr(void)
55{
56	unsigned long val;
57	asm("mrc p15, 0, %0, c1, c0, 0	@ get CR" : "=r" (val) : : "cc");
58	return val;
59}
60
61static inline void set_cr(unsigned long val)
62{
63	asm volatile("mcr p15, 0, %0, c1, c0, 0	@ set CR"
64	  : : "r" (val) : "cc");
65	isb();
66}
67
68static inline unsigned int get_auxcr(void)
69{
70	unsigned int val;
71	asm("mrc p15, 0, %0, c1, c0, 1	@ get AUXCR" : "=r" (val));
72	return val;
73}
74
75static inline void set_auxcr(unsigned int val)
76{
77	asm volatile("mcr p15, 0, %0, c1, c0, 1	@ set AUXCR"
78	  : : "r" (val));
79	isb();
80}
81
82#define CPACC_FULL(n)		(3 << (n * 2))
83#define CPACC_SVC(n)		(1 << (n * 2))
84#define CPACC_DISABLE(n)	(0 << (n * 2))
85
86static inline unsigned int get_copro_access(void)
87{
88	unsigned int val;
89	asm("mrc p15, 0, %0, c1, c0, 2 @ get copro access"
90	  : "=r" (val) : : "cc");
91	return val;
92}
93
94static inline void set_copro_access(unsigned int val)
95{
96	asm volatile("mcr p15, 0, %0, c1, c0, 2 @ set copro access"
97	  : : "r" (val) : "cc");
98	isb();
99}
100
101#else /* ifdef CONFIG_CPU_CP15 */
102
103/*
104 * cr_alignment is tightly coupled to cp15 (at least in the minds of the
105 * developers). Yielding 0 for machines without a cp15 (and making it
106 * read-only) is fine for most cases and saves quite some #ifdeffery.
107 */
108#define cr_alignment	UL(0)
109
110static inline unsigned long get_cr(void)
111{
112	return 0;
113}
114
115#endif /* ifdef CONFIG_CPU_CP15 / else */
116
117#endif /* ifndef __ASSEMBLY__ */
118
119#endif
120