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Searched refs:uart (Results 1 – 200 of 386) sorted by relevance

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/linux-4.1.27/sound/drivers/
Dserial-u16550.c172 static inline void snd_uart16550_add_timer(struct snd_uart16550 *uart) in snd_uart16550_add_timer() argument
174 if (!uart->timer_running) { in snd_uart16550_add_timer()
176 mod_timer(&uart->buffer_timer, jiffies + (HZ + 255) / 256); in snd_uart16550_add_timer()
177 uart->timer_running = 1; in snd_uart16550_add_timer()
181 static inline void snd_uart16550_del_timer(struct snd_uart16550 *uart) in snd_uart16550_del_timer() argument
183 if (uart->timer_running) { in snd_uart16550_del_timer()
184 del_timer(&uart->buffer_timer); in snd_uart16550_del_timer()
185 uart->timer_running = 0; in snd_uart16550_del_timer()
190 static inline void snd_uart16550_buffer_output(struct snd_uart16550 *uart) in snd_uart16550_buffer_output() argument
192 unsigned short buff_out = uart->buff_out; in snd_uart16550_buffer_output()
[all …]
/linux-4.1.27/drivers/tty/serial/
Dbfin_uart.c70 static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart);
72 static void bfin_serial_tx_chars(struct bfin_serial_port *uart);
81 struct bfin_serial_port *uart = (struct bfin_serial_port *)port; in bfin_serial_get_mctrl() local
82 if (uart->cts_pin < 0) in bfin_serial_get_mctrl()
86 if (UART_GET_CTS(uart)) in bfin_serial_get_mctrl()
94 struct bfin_serial_port *uart = (struct bfin_serial_port *)port; in bfin_serial_set_mctrl() local
95 if (uart->rts_pin < 0) in bfin_serial_set_mctrl()
100 UART_ENABLE_RTS(uart); in bfin_serial_set_mctrl()
102 UART_DISABLE_RTS(uart); in bfin_serial_set_mctrl()
110 struct bfin_serial_port *uart = dev_id; in bfin_serial_mctrl_cts_int() local
[all …]
Dmen_z135_uart.c140 static inline void men_z135_reg_set(struct men_z135_port *uart, in men_z135_reg_set() argument
143 struct uart_port *port = &uart->port; in men_z135_reg_set()
147 spin_lock_irqsave(&uart->lock, flags); in men_z135_reg_set()
153 spin_unlock_irqrestore(&uart->lock, flags); in men_z135_reg_set()
162 static inline void men_z135_reg_clr(struct men_z135_port *uart, in men_z135_reg_clr() argument
165 struct uart_port *port = &uart->port; in men_z135_reg_clr()
169 spin_lock_irqsave(&uart->lock, flags); in men_z135_reg_clr()
175 spin_unlock_irqrestore(&uart->lock, flags); in men_z135_reg_clr()
185 static void men_z135_handle_modem_status(struct men_z135_port *uart) in men_z135_handle_modem_status() argument
189 msr = (uart->stat_reg >> 8) & 0xff; in men_z135_handle_modem_status()
[all …]
Dtimbuart.c67 struct timbuart_port *uart = in timbuart_start_tx() local
71 tasklet_schedule(&uart->tasklet); in timbuart_start_tx()
133 struct timbuart_port *uart = in timbuart_handle_tx_port() local
152 *ier |= uart->last_ier & TXFLAGS; in timbuart_handle_tx_port()
189 struct timbuart_port *uart = (struct timbuart_port *)arg; in timbuart_tasklet() local
192 spin_lock(&uart->port.lock); in timbuart_tasklet()
194 isr = ioread32(uart->port.membase + TIMBUART_ISR); in timbuart_tasklet()
195 dev_dbg(uart->port.dev, "%s ISR: %x\n", __func__, isr); in timbuart_tasklet()
197 if (!uart->usedma) in timbuart_tasklet()
198 timbuart_handle_tx_port(&uart->port, isr, &ier); in timbuart_tasklet()
[all …]
Dvt8500_serial.c109 struct uart_port uart; member
139 uart); in vt8500_stop_tx()
149 uart); in vt8500_stop_rx()
159 uart); in vt8500_enable_ms()
240 uart); in vt8500_start_tx()
318 container_of(port, struct vt8500_port, uart); in vt8500_set_baud_rate()
342 container_of(port, struct vt8500_port, uart); in vt8500_startup()
361 container_of(port, struct vt8500_port, uart); in vt8500_shutdown()
366 vt8500_write(&vt8500_port->uart, 0, VT8500_URIER); in vt8500_shutdown()
367 vt8500_write(&vt8500_port->uart, 0x880, VT8500_URFCR); in vt8500_shutdown()
[all …]
Darc_uart.c83 #define UART_SET_DATA(uart, val) UART_REG_SET(uart, R_DATA, val) argument
84 #define UART_GET_DATA(uart) UART_REG_GET(uart, R_DATA) argument
86 #define UART_SET_BAUDH(uart, val) UART_REG_SET(uart, R_BAUDH, val) argument
87 #define UART_SET_BAUDL(uart, val) UART_REG_SET(uart, R_BAUDL, val) argument
89 #define UART_CLR_STATUS(uart, val) UART_REG_CLR(uart, R_STS, val) argument
90 #define UART_GET_STATUS(uart) UART_REG_GET(uart, R_STS) argument
92 #define UART_ALL_IRQ_DISABLE(uart) UART_REG_CLR(uart, R_STS, RXIENB|TXIENB) argument
93 #define UART_RX_IRQ_DISABLE(uart) UART_REG_CLR(uart, R_STS, RXIENB) argument
94 #define UART_TX_IRQ_DISABLE(uart) UART_REG_CLR(uart, R_STS, TXIENB) argument
96 #define UART_ALL_IRQ_ENABLE(uart) UART_REG_OR(uart, R_STS, RXIENB|TXIENB) argument
[all …]
D68328serial.c215 m68328_uart *uart = &uart_addr[info->line]; in rs_stop() local
222 uart->ustcnt &= ~USTCNT_TXEN; in rs_stop()
247 m68328_uart *uart = &uart_addr[info->line]; in rs_start() local
254 if (info->xmit_cnt && info->xmit_buf && !(uart->ustcnt & USTCNT_TXEN)) { in rs_start()
256 uart->ustcnt |= USTCNT_TXEN | USTCNT_TX_INTR_MASK; in rs_start()
258 uart->ustcnt |= USTCNT_TXEN; in rs_start()
266 m68328_uart *uart = &uart_addr[info->line]; in receive_chars() local
305 } while((rx = uart->urx.w) & URX_DATA_READY); in receive_chars()
313 m68328_uart *uart = &uart_addr[info->line]; in transmit_chars() local
317 uart->utx.b.txdata = info->x_char; in transmit_chars()
[all …]
Dtilegx.c46 struct uart_port uart; member
87 struct tty_port *port = &tile_uart->uart.state->port; in handle_receive()
106 spin_unlock(&tile_uart->uart.lock); in handle_receive()
108 spin_lock(&tile_uart->uart.lock); in handle_receive()
143 port = &tile_uart->uart; in handle_transmit()
186 tile_uart = container_of(port, struct tile_uart_port, uart); in tilegx_interrupt()
214 tile_uart = container_of(port, struct tile_uart_port, uart); in tilegx_tx_empty()
264 tile_uart = container_of(port, struct tile_uart_port, uart); in tilegx_start_tx()
306 tile_uart = container_of(port, struct tile_uart_port, uart); in tilegx_stop_rx()
336 tile_uart = container_of(port, struct tile_uart_port, uart); in tilegx_startup()
[all …]
Dserial_txx9.c1023 struct uart_txx9_port *uart; in serial_txx9_register_port() local
1028 uart = &serial_txx9_ports[i]; in serial_txx9_register_port()
1029 if (uart_match_port(&uart->port, port)) { in serial_txx9_register_port()
1030 uart_remove_one_port(&serial_txx9_reg, &uart->port); in serial_txx9_register_port()
1037 uart = &serial_txx9_ports[i]; in serial_txx9_register_port()
1038 if (!(uart->port.iobase || uart->port.mapbase)) in serial_txx9_register_port()
1043 uart->port.iobase = port->iobase; in serial_txx9_register_port()
1044 uart->port.membase = port->membase; in serial_txx9_register_port()
1045 uart->port.irq = port->irq; in serial_txx9_register_port()
1046 uart->port.uartclk = port->uartclk; in serial_txx9_register_port()
[all …]
Dsccnxp.c112 struct uart_driver uart; member
459 for (i = 0; i < s->uart.nr; i++) { in sccnxp_handle_events()
921 s->uart.owner = THIS_MODULE; in sccnxp_probe()
922 s->uart.dev_name = "ttySC"; in sccnxp_probe()
923 s->uart.major = SCCNXP_MAJOR; in sccnxp_probe()
924 s->uart.minor = SCCNXP_MINOR; in sccnxp_probe()
925 s->uart.nr = s->chip->nr; in sccnxp_probe()
927 s->uart.cons = &s->console; in sccnxp_probe()
928 s->uart.cons->device = uart_console_device; in sccnxp_probe()
929 s->uart.cons->write = sccnxp_console_write; in sccnxp_probe()
[all …]
Dmax310x.c268 struct uart_driver uart; member
718 if (s->uart.nr > 1) { in max310x_ist()
724 val = ((1 << s->uart.nr) - 1) & ~val; in max310x_ist()
1012 for (i = 0; i < s->uart.nr; i++) { in max310x_suspend()
1013 uart_suspend_port(&s->uart, &s->p[i].port); in max310x_suspend()
1025 for (i = 0; i < s->uart.nr; i++) { in max310x_resume()
1027 uart_resume_port(&s->uart, &s->p[i].port); in max310x_resume()
1163 s->uart.owner = THIS_MODULE; in max310x_probe()
1164 s->uart.dev_name = "ttyMAX"; in max310x_probe()
1165 s->uart.major = MAX310X_MAJOR; in max310x_probe()
[all …]
Dsc16is7xx.c310 struct uart_driver uart; member
636 for (i = 0; i < s->uart.nr; ++i) in sc16is7xx_ist()
1078 s->uart.owner = THIS_MODULE; in sc16is7xx_probe()
1079 s->uart.dev_name = "ttySC"; in sc16is7xx_probe()
1080 s->uart.nr = devtype->nr_uart; in sc16is7xx_probe()
1081 ret = uart_register_driver(&s->uart); in sc16is7xx_probe()
1131 uart_add_one_port(&s->uart, &s->p[i].port); in sc16is7xx_probe()
1142 for (i = 0; i < s->uart.nr; i++) in sc16is7xx_probe()
1143 uart_remove_one_port(&s->uart, &s->p[i].port); in sc16is7xx_probe()
1153 uart_unregister_driver(&s->uart); in sc16is7xx_probe()
[all …]
Dioc3_serial.c314 struct ioc3_uartregs __iomem *uart; in set_baud() local
339 uart = port->ip_uart_regs; in set_baud()
340 lcr = readb(&uart->iu_lcr); in set_baud()
342 writeb(lcr | UART_LCR_DLAB, &uart->iu_lcr); in set_baud()
343 writeb((unsigned char)divisor, &uart->iu_dll); in set_baud()
344 writeb((unsigned char)(divisor >> 8), &uart->iu_dlm); in set_baud()
345 writeb((unsigned char)prediv, &uart->iu_scr); in set_baud()
346 writeb((unsigned char)lcr, &uart->iu_lcr); in set_baud()
384 struct ioc3_uartregs __iomem *uart; in port_init() local
418 uart = port->ip_uart_regs; in port_init()
[all …]
Datmel_serial.c140 struct uart_port uart; /* uart */ member
209 to_atmel_uart_port(struct uart_port *uart) in to_atmel_uart_port() argument
211 return container_of(uart, struct atmel_uart_port, uart); in to_atmel_uart_port()
723 struct uart_port *port = &atmel_port->uart; in atmel_complete_tx_dma()
1671 int usart, uart; in atmel_get_ip_name() local
1674 uart = 0x44424755; in atmel_get_ip_name()
1681 } else if (name == uart) { in atmel_get_ip_name()
2258 struct uart_port *port = &atmel_port->uart; in atmel_init_port()
2336 struct uart_port *port = &atmel_ports[co->index].uart; in atmel_console_write()
2410 struct uart_port *port = &atmel_ports[co->index].uart; in atmel_console_setup()
[all …]
Dioc4_serial.c713 struct ioc4_uartregs __iomem *uart; in set_baud() local
728 uart = port->ip_uart_regs; in set_baud()
729 lcr = readb(&uart->i4u_lcr); in set_baud()
730 writeb(lcr | UART_LCR_DLAB, &uart->i4u_lcr); in set_baud()
731 writeb((unsigned char)divisor, &uart->i4u_dll); in set_baud()
732 writeb((unsigned char)(divisor >> 8), &uart->i4u_dlm); in set_baud()
733 writeb(lcr, &uart->i4u_lcr); in set_baud()
831 struct ioc4_uartregs __iomem *uart; in port_init() local
853 uart = port->ip_uart_regs; in port_init()
854 writeb(0, &uart->i4u_lcr); in port_init()
[all …]
Dm32r_sio.h34 unsigned int uart; member
DMakefile54 obj-$(CONFIG_SERIAL_ETRAXFS) += etraxfs-uart.o
89 obj-$(CONFIG_SERIAL_EFM32_UART) += efm32-uart.o
/linux-4.1.27/arch/mn10300/kernel/
Dmn10300-serial.c157 .uart.ops = &mn10300_serial_ops,
158 .uart.membase = (void __iomem *) &SC0CTR,
159 .uart.mapbase = (unsigned long) &SC0CTR,
160 .uart.iotype = UPIO_MEM,
161 .uart.irq = 0,
162 .uart.uartclk = 0, /* MN10300_IOCLK, */
163 .uart.fifosize = 1,
164 .uart.flags = UPF_BOOT_AUTOCONF,
165 .uart.line = 0,
166 .uart.type = PORT_MN10300,
[all …]
Dgdb-io-ttysm.c157 gdbstub_port->uart.timeout = (2 * bits * HZ) / baud; in gdbstub_io_set_baud()
158 gdbstub_port->uart.timeout += HZ / 50; in gdbstub_io_set_baud()
/linux-4.1.27/arch/arm/mach-omap2/
Dserial.c110 struct omap_uart_state *uart) in omap_serial_fill_uart_tx_rx_pads() argument
112 uart->default_omap_uart_pads[0].name = rx_pad_name; in omap_serial_fill_uart_tx_rx_pads()
113 uart->default_omap_uart_pads[0].flags = OMAP_DEVICE_PAD_REMUX | in omap_serial_fill_uart_tx_rx_pads()
115 uart->default_omap_uart_pads[0].enable = OMAP_PIN_INPUT | in omap_serial_fill_uart_tx_rx_pads()
117 uart->default_omap_uart_pads[0].idle = OMAP_PIN_INPUT | OMAP_MUX_MODE0; in omap_serial_fill_uart_tx_rx_pads()
118 uart->default_omap_uart_pads[1].name = tx_pad_name; in omap_serial_fill_uart_tx_rx_pads()
119 uart->default_omap_uart_pads[1].enable = OMAP_PIN_OUTPUT | in omap_serial_fill_uart_tx_rx_pads()
121 bdata->pads = uart->default_omap_uart_pads; in omap_serial_fill_uart_tx_rx_pads()
122 bdata->pads_cnt = ARRAY_SIZE(uart->default_omap_uart_pads); in omap_serial_fill_uart_tx_rx_pads()
126 struct omap_uart_state *uart) in omap_serial_check_wakeup() argument
[all …]
/linux-4.1.27/Documentation/devicetree/bindings/serial/
Dsirf-uart.txt4 - compatible : Should be "sirf,prima2-uart", "sirf, prima2-usp-uart",
5 "sirf,atlas7-uart" or "sirf,atlas7-bt-uart" which means
6 uart located in BT module and used for BT.
8 - interrupts : Should contain uart interrupt
10 - clocks : Should contain uart clock number
13 - sirf,uart-has-rtscts: we have hardware flow controller pins in hardware
14 - rts-gpios: RTS pin for USP-based UART if sirf,uart-has-rtscts is true
15 - cts-gpios: CTS pin for USP-based UART if sirf,uart-has-rtscts is true
19 uart0: uart@b0050000 {
21 compatible = "sirf,prima2-uart";
[all …]
Dfsl-imx-uart.txt4 - compatible : Should be "fsl,<soc>-uart"
6 - interrupts : Should contain uart interrupt
9 - fsl,uart-has-rtscts : Indicate the uart has rts and cts
10 - fsl,irda-mode : Indicate the uart supports irda mode
11 - fsl,dte-mode : Indicate the uart works in DTE mode. The uart works
14 Note: Each uart controller should have an alias correctly numbered
24 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
27 fsl,uart-has-rtscts;
Dmtk-uart.txt5 * "mediatek,mt8135-uart" for MT8135 compatible UARTS
6 * "mediatek,mt8127-uart" for MT8127 compatible UARTS
7 * "mediatek,mt8173-uart" for MT8173 compatible UARTS
8 * "mediatek,mt6589-uart" for MT6589 compatible UARTS
9 * "mediatek,mt6582-uart" for MT6582 compatible UARTS
10 * "mediatek,mt6577-uart" for all compatible UARTS (MT8173, MT6589, MT6582,
22 compatible = "mediatek,mt6589-uart", "mediatek,mt6577-uart";
Dsamsung_uart.txt8 - "samsung,exynos4210-uart" - Exynos4210 SoC,
9 - "samsung,s3c2410-uart" - compatible with ports present on S3C2410 SoC,
10 - "samsung,s3c2412-uart" - compatible with ports present on S3C2412 SoC,
11 - "samsung,s3c2440-uart" - compatible with ports present on S3C2440 SoC,
12 - "samsung,s3c6400-uart" - compatible with ports present on S3C6400 SoC,
13 - "samsung,s5pv210-uart" - compatible with ports present on S5PV210 SoC.
22 - "uart" - controller bus clock,
33 - samsung,uart-fifosize: The fifo size supported by the UART channel
49 compatible = "samsung,s3c6400-uart";
53 clock-names = "uart", "clk_uart_baud2",
[all …]
Domap_serial.txt4 - compatible : should be "ti,omap2-uart" for OMAP2 controllers
5 - compatible : should be "ti,omap3-uart" for OMAP3 controllers
6 - compatible : should be "ti,omap4-uart" for OMAP4 controllers
8 - interrupts or interrupts-extended : Should contain the uart interrupt
12 - ti,hwmods : Must be "uart<n>", n being the instance number (1-based)
23 compatible = "ti,omap3-uart";
Defm32-uart.txt4 - compatible : Should be "energymicro,efm32-uart"
6 - interrupts : Should contain uart interrupt
15 uart@0x4000c400 {
16 compatible = "energymicro,efm32-uart";
Dsnps-dw-apb-uart.txt4 - compatible : "snps,dw-apb-uart"
6 - interrupts : should contain uart interrupt.
39 uart@80230000 {
40 compatible = "snps,dw-apb-uart";
54 uart@80230000 {
55 compatible = "snps,dw-apb-uart";
65 uart@80230000 {
66 compatible = "snps,dw-apb-uart";
D8250.txt11 - For Tegra20, must contain "nvidia,tegra20-uart"
12 - For other Tegra, must contain '"nvidia,<chip>-uart",
13 "nvidia,tegra20-uart"' where <chip> is tegra30, tegra114, tegra124,
15 - "nxp,lpc3220-uart"
16 - "ralink,rt2880-uart"
25 - interrupts : should contain uart interrupt.
60 uart@80230000 {
Dcdns,uart.txt4 - compatible : should be "cdns,uart-r1p8", or "xlnx,xuartps"
14 uart@e0000000 {
15 compatible = "cdns,uart-r1p8";
Dvt8500-uart.txt4 - compatible: should be "via,vt8500-uart" (for VIA/WonderMedia chips up to and
5 including WM8850/WM8950), or "wm,wm8880-uart" (for WM8880 and later)
23 compatible = "via,vt8500-uart";
Dqca,ar9330-uart.txt5 - compatible: Must be "qca,ar9330-uart"
28 uart0: uart@18020000 {
29 compatible = "qca,ar9330-uart";
Dqcom,msm-uart.txt9 - compatible: Should contain "qcom,msm-uart"
17 A uart device at 0xa9c00000 with interrupt 11.
20 compatible = "qcom,msm-uart";
Dcirrus,clps711x-uart.txt4 - compatible: Should be "cirrus,clps711x-uart".
22 uart1: uart@80000480 {
23 compatible = "cirrus,clps711x-uart";
Dmrvl-serial.txt4 - compatible : should be "mrvl,mmp-uart" or "mrvl,pxa-uart".
Daltera_uart.txt4 - compatible : should be "ALTR,uart-1.0" <DEPRECATED>
5 - compatible : should be "altr,uart-1.0"
Daxis,etraxfs-uart.txt4 - compatible : "axis,etraxfs-uart"
15 compatible = "axis,etraxfs-uart";
Dcavium-uart.txt3 - compatible: "cavium,octeon-3860-uart"
15 compatible = "cavium,octeon-3860-uart","ns16550";
Dbrcm,bcm6345-uart.txt5 - compatible: "brcm,bcm6345-uart"
17 compatible = "brcm,bcm6345-uart";
Darc-uart.txt4 - compatible : "snps,arc-uart"
13 compatible = "snps,arc-uart";
Dfsl-lpuart.txt10 - interrupts : Should contain uart interrupt
12 - clock-names : should contain: "ipg" - the uart clock
Dsprd-uart.txt4 - compatible: must be "sprd,sc9836-uart"
/linux-4.1.27/drivers/tty/serial/8250/
D8250_pnp.c440 struct uart_8250_port uart, *port; in serial_pnp_probe() local
449 memset(&uart, 0, sizeof(uart)); in serial_pnp_probe()
451 uart.port.irq = pnp_irq(dev, 0); in serial_pnp_probe()
453 uart.port.iobase = pnp_port_start(dev, 2); in serial_pnp_probe()
454 uart.port.iotype = UPIO_PORT; in serial_pnp_probe()
456 uart.port.iobase = pnp_port_start(dev, 0); in serial_pnp_probe()
457 uart.port.iotype = UPIO_PORT; in serial_pnp_probe()
459 uart.port.mapbase = pnp_mem_start(dev, 0); in serial_pnp_probe()
460 uart.port.iotype = UPIO_MEM; in serial_pnp_probe()
461 uart.port.flags = UPF_IOREMAP; in serial_pnp_probe()
[all …]
D8250_hp300.c160 struct uart_8250_port uart; in hpdca_init_one() local
169 memset(&uart, 0, sizeof(uart)); in hpdca_init_one()
172 uart.port.iotype = UPIO_MEM; in hpdca_init_one()
173 uart.port.flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF; in hpdca_init_one()
174 uart.port.irq = d->ipl; in hpdca_init_one()
175 uart.port.uartclk = HPDCA_BAUD_BASE * 16; in hpdca_init_one()
176 uart.port.mapbase = (d->resource.start + UART_OFFSET); in hpdca_init_one()
177 uart.port.membase = (char *)(uart.port.mapbase + DIO_VIRADDRBASE); in hpdca_init_one()
178 uart.port.regshift = 1; in hpdca_init_one()
179 uart.port.dev = &d->dev; in hpdca_init_one()
[all …]
D8250_gsc.c29 struct uart_8250_port uart; in serial_init_chip() local
56 memset(&uart, 0, sizeof(uart)); in serial_init_chip()
57 uart.port.iotype = UPIO_MEM; in serial_init_chip()
59 uart.port.uartclk = (dev->id.sversion != 0xad) ? in serial_init_chip()
61 uart.port.mapbase = address; in serial_init_chip()
62 uart.port.membase = ioremap_nocache(address, 16); in serial_init_chip()
63 uart.port.irq = dev->irq; in serial_init_chip()
64 uart.port.flags = UPF_BOOT_AUTOCONF; in serial_init_chip()
65 uart.port.dev = &dev->dev; in serial_init_chip()
67 err = serial8250_register_8250_port(&uart); in serial_init_chip()
[all …]
D8250_mtk.c155 struct uart_8250_port uart = {}; in mtk8250_probe() local
166 uart.port.membase = devm_ioremap(&pdev->dev, regs->start, in mtk8250_probe()
168 if (!uart.port.membase) in mtk8250_probe()
176 err = mtk8250_probe_of(pdev, &uart.port, data); in mtk8250_probe()
182 spin_lock_init(&uart.port.lock); in mtk8250_probe()
183 uart.port.mapbase = regs->start; in mtk8250_probe()
184 uart.port.irq = irq->start; in mtk8250_probe()
185 uart.port.pm = mtk8250_do_pm; in mtk8250_probe()
186 uart.port.type = PORT_16550; in mtk8250_probe()
187 uart.port.flags = UPF_BOOT_AUTOCONF | UPF_FIXED_PORT; in mtk8250_probe()
[all …]
D8250_acorn.c46 struct uart_8250_port uart; in serial_card_probe() local
65 memset(&uart, 0, sizeof(struct uart_8250_port)); in serial_card_probe()
66 uart.port.irq = ec->irq; in serial_card_probe()
67 uart.port.flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ; in serial_card_probe()
68 uart.port.uartclk = type->uartclk; in serial_card_probe()
69 uart.port.iotype = UPIO_MEM; in serial_card_probe()
70 uart.port.regshift = 2; in serial_card_probe()
71 uart.port.dev = &ec->dev; in serial_card_probe()
74 uart.port.membase = info->vaddr + type->offset[i]; in serial_card_probe()
75 uart.port.mapbase = bus_addr + type->offset[i]; in serial_card_probe()
[all …]
D8250_fintek.c146 struct uart_8250_port uart; in fintek_8250_probe() local
165 memset(&uart, 0, sizeof(uart)); in fintek_8250_probe()
168 uart.port.irq = pnp_irq(dev, 0); in fintek_8250_probe()
169 uart.port.iobase = pnp_port_start(dev, 0); in fintek_8250_probe()
170 uart.port.iotype = UPIO_PORT; in fintek_8250_probe()
171 uart.port.rs485_config = fintek_8250_rs485_config; in fintek_8250_probe()
173 uart.port.flags |= UPF_SKIP_TEST | UPF_BOOT_AUTOCONF; in fintek_8250_probe()
175 uart.port.flags |= UPF_SHARE_IRQ; in fintek_8250_probe()
176 uart.port.uartclk = 1843200; in fintek_8250_probe()
177 uart.port.dev = &dev->dev; in fintek_8250_probe()
[all …]
D8250_dw.c404 struct uart_8250_port uart = {}; in dw8250_probe() local
421 spin_lock_init(&uart.port.lock); in dw8250_probe()
422 uart.port.mapbase = regs->start; in dw8250_probe()
423 uart.port.irq = irq; in dw8250_probe()
424 uart.port.handle_irq = dw8250_handle_irq; in dw8250_probe()
425 uart.port.pm = dw8250_do_pm; in dw8250_probe()
426 uart.port.type = PORT_8250; in dw8250_probe()
427 uart.port.flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_FIXED_PORT; in dw8250_probe()
428 uart.port.dev = &pdev->dev; in dw8250_probe()
430 uart.port.membase = devm_ioremap(&pdev->dev, regs->start, in dw8250_probe()
[all …]
D8250_core.c3676 struct uart_8250_port uart; in serial8250_probe() local
3679 memset(&uart, 0, sizeof(uart)); in serial8250_probe()
3685 uart.port.iobase = p->iobase; in serial8250_probe()
3686 uart.port.membase = p->membase; in serial8250_probe()
3687 uart.port.irq = p->irq; in serial8250_probe()
3688 uart.port.irqflags = p->irqflags; in serial8250_probe()
3689 uart.port.uartclk = p->uartclk; in serial8250_probe()
3690 uart.port.regshift = p->regshift; in serial8250_probe()
3691 uart.port.iotype = p->iotype; in serial8250_probe()
3692 uart.port.flags = p->flags; in serial8250_probe()
[all …]
Dserial_cs.c107 static void quirk_setup_brainboxes_0104(struct pcmcia_device *link, struct uart_8250_port *uart) in quirk_setup_brainboxes_0104() argument
109 uart->port.uartclk = 14745600; in quirk_setup_brainboxes_0104()
345 struct uart_8250_port uart; in setup_serial() local
348 memset(&uart, 0, sizeof(uart)); in setup_serial()
349 uart.port.iobase = iobase; in setup_serial()
350 uart.port.irq = irq; in setup_serial()
351 uart.port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ; in setup_serial()
352 uart.port.uartclk = 1843200; in setup_serial()
353 uart.port.dev = &handle->dev; in setup_serial()
355 uart.port.flags |= UPF_BUGGY_UART; in setup_serial()
[all …]
/linux-4.1.27/drivers/firmware/
Dpcdp.c23 setup_serial_console(struct pcdp_uart *uart) in setup_serial_console() argument
30 mmio = (uart->addr.space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY); in setup_serial_console()
32 mmio ? "mmio" : "io", uart->addr.address); in setup_serial_console()
33 if (uart->baud) { in setup_serial_console()
34 p += sprintf(p, ",%llu", uart->baud); in setup_serial_console()
35 if (uart->bits) { in setup_serial_console()
36 switch (uart->parity) { in setup_serial_console()
41 p += sprintf(p, "%c%d", parity, uart->bits); in setup_serial_console()
90 struct pcdp_uart *uart; in efi_setup_pcdp_console() local
112 for (i = 0, uart = pcdp->uart; i < pcdp->num_uarts; i++, uart++) { in efi_setup_pcdp_console()
[all …]
/linux-4.1.27/drivers/misc/ibmasm/
Duart.c36 struct uart_8250_port uart; in ibmasm_register_uart() local
50 memset(&uart, 0, sizeof(uart)); in ibmasm_register_uart()
51 uart.port.irq = sp->irq; in ibmasm_register_uart()
52 uart.port.uartclk = 3686400; in ibmasm_register_uart()
53 uart.port.flags = UPF_SHARE_IRQ; in ibmasm_register_uart()
54 uart.port.iotype = UPIO_MEM; in ibmasm_register_uart()
55 uart.port.membase = iomem_base; in ibmasm_register_uart()
57 sp->serial_line = serial8250_register_8250_port(&uart); in ibmasm_register_uart()
DMakefile14 ibmasm-$(CONFIG_SERIAL_8250) += uart.o
/linux-4.1.27/arch/arm/mach-davinci/include/mach/
Duncompress.h30 u32 *uart; variable
35 if (!uart) in putc()
38 while (!(uart[UART_LSR] & UART_LSR_THRE)) in putc()
40 uart[UART_TX] = c; in putc()
45 if (!uart) in flush()
48 while (!(uart[UART_LSR] & UART_LSR_THRE)) in flush()
54 uart = (u32 *)phys; in set_uart_info()
/linux-4.1.27/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/
Dserial.txt4 - fsl,cpm1-smc-uart
5 - fsl,cpm2-smc-uart
6 - fsl,cpm1-scc-uart
7 - fsl,cpm2-scc-uart
8 - fsl,qe-uart
23 compatible = "fsl,mpc8272-scc-uart",
24 "fsl,cpm2-scc-uart";
/linux-4.1.27/arch/powerpc/boot/dts/
Dcm5200.dts31 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
35 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
39 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
51 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
Da4m072.dts47 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
53 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
59 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
73 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
Dpdm360ng.dts141 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
145 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
149 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
153 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
157 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
165 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
173 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
196 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
Duc101.dts51 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
55 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
71 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
Dmucmc52.dts54 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
58 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
74 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
Do2d.dtsi58 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
62 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
Dpcm030.dts41 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
55 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
Da3m071.dts44 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
66 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
Dmotionpro.dts36 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
54 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
Ddigsy_mtc.dts53 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
57 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
Dmedia5200.dts66 // PSC6 in uart mode
68 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
139 uart@3,0 {
Dpcm032.dts45 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
59 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
Dep8248e.dts135 compatible = "fsl,mpc8248-smc-uart",
136 "fsl,cpm2-smc-uart";
148 compatible = "fsl,mpc8248-scc-uart",
149 "fsl,cpm2-scc-uart";
Dmpc866ads.dts142 compatible = "fsl,mpc866-smc-uart",
143 "fsl,cpm1-smc-uart";
153 compatible = "fsl,mpc866-smc-uart",
154 "fsl,cpm1-smc-uart";
Dlite5200.dts176 compatible = "fsl,mpc5200-psc-uart";
198 // PSC4 in uart mode example
200 // compatible = "fsl,mpc5200-psc-uart";
206 // PSC5 in uart mode example
208 // compatible = "fsl,mpc5200-psc-uart";
Dep88xc.dts178 compatible = "fsl,mpc885-smc-uart",
179 "fsl,cpm1-smc-uart";
191 compatible = "fsl,mpc885-scc-uart",
192 "fsl,cpm1-scc-uart";
Dmpc885ads.dts183 compatible = "fsl,mpc885-smc-uart",
184 "fsl,cpm1-smc-uart";
194 compatible = "fsl,mpc885-smc-uart",
195 "fsl,cpm1-smc-uart";
Dpq2fads.dts155 compatible = "fsl,mpc8280-scc-uart",
156 "fsl,cpm2-scc-uart";
166 compatible = "fsl,mpc8280-scc-uart",
167 "fsl,cpm2-scc-uart";
Dtqm5200.dts114 compatible = "fsl,mpc5200-psc-uart";
120 compatible = "fsl,mpc5200-psc-uart";
126 compatible = "fsl,mpc5200-psc-uart";
Dmpc8272ads.dts156 compatible = "fsl,mpc8272-scc-uart",
157 "fsl,cpm2-scc-uart";
167 compatible = "fsl,mpc8272-scc-uart",
168 "fsl,cpm2-scc-uart";
Dksi8560.dts252 compatible = "fsl,mpc8560-scc-uart",
253 "fsl,cpm2-scc-uart";
264 compatible = "fsl,mpc8560-scc-uart",
265 "fsl,cpm2-scc-uart";
Dlite5200b.dts44 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
Dtqm8560.dts270 compatible = "fsl,mpc8560-scc-uart",
271 "fsl,cpm2-scc-uart";
282 compatible = "fsl,mpc8560-scc-uart",
283 "fsl,cpm2-scc-uart";
/linux-4.1.27/arch/arm/boot/dts/
Defm32gg.dtsi97 uart0: uart@4000c000 { /* USART0 */
98 compatible = "efm32,uart";
105 uart1: uart@4000c400 { /* USART1 */
106 compatible = "efm32,uart";
113 uart2: uart@4000c800 { /* USART2 */
114 compatible = "efm32,uart";
121 uart3: uart@4000e000 { /* UART0 */
122 compatible = "efm32,uart";
129 uart4: uart@4000e400 { /* UART1 */
130 compatible = "efm32,uart";
Dimx31.dtsi55 compatible = "fsl,imx31-uart", "fsl,imx21-uart";
64 compatible = "fsl,imx31-uart", "fsl,imx21-uart";
73 compatible = "fsl,imx31-uart", "fsl,imx21-uart";
82 compatible = "fsl,imx31-uart", "fsl,imx21-uart";
99 compatible = "fsl,imx31-uart", "fsl,imx21-uart";
Dpxa2xx.dtsi78 ffuart: uart@40100000 {
79 compatible = "mrvl,pxa-uart";
85 btuart: uart@40200000 {
86 compatible = "mrvl,pxa-uart";
92 stuart: uart@40700000 {
93 compatible = "mrvl,pxa-uart";
99 hwuart: uart@41100000 {
100 compatible = "mrvl,pxa-uart";
Dhip01.dtsi49 uart0: uart@10001000 {
50 compatible = "snps,dw-apb-uart";
59 uart1: uart@10002000 {
60 compatible = "snps,dw-apb-uart";
69 uart2: uart@10003000 {
70 compatible = "snps,dw-apb-uart";
79 uart3: uart@10006000 {
80 compatible = "snps,dw-apb-uart";
Ds3c2416.dtsi52 compatible = "samsung,s3c2440-uart";
53 clock-names = "uart", "clk_uart_baud2",
60 compatible = "samsung,s3c2440-uart";
61 clock-names = "uart", "clk_uart_baud2",
68 compatible = "samsung,s3c2440-uart";
69 clock-names = "uart", "clk_uart_baud2",
76 compatible = "samsung,s3c2440-uart";
79 clock-names = "uart", "clk_uart_baud2",
Dmt8127.dtsi111 compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart";
119 compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart";
127 compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart";
135 compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart";
Dmt8135.dtsi134 compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
142 compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
150 compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
158 compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
Ds3c64xx.dtsi119 compatible = "samsung,s3c6400-uart";
123 clock-names = "uart", "clk_uart_baud2",
131 compatible = "samsung,s3c6400-uart";
135 clock-names = "uart", "clk_uart_baud2",
143 compatible = "samsung,s3c6400-uart";
147 clock-names = "uart", "clk_uart_baud2",
155 compatible = "samsung,s3c6400-uart";
159 clock-names = "uart", "clk_uart_baud2",
Dpxa168.dtsi59 uart1: uart@d4017000 {
60 compatible = "mrvl,mmp-uart";
68 uart2: uart@d4018000 {
69 compatible = "mrvl,mmp-uart";
77 uart3: uart@d4026000 {
78 compatible = "mrvl,mmp-uart";
Dbcm11351.dtsi63 uart@3e000000 {
64 compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
73 uart@3e001000 {
74 compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
83 uart@3e002000 {
84 compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
93 uart@3e003000 {
94 compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
Dpxa910.dtsi71 uart1: uart@d4017000 {
72 compatible = "mrvl,mmp-uart";
80 uart2: uart@d4018000 {
81 compatible = "mrvl,mmp-uart";
89 uart3: uart@d4036000 {
90 compatible = "mrvl,mmp-uart";
Dmmp2.dtsi135 uart1: uart@d4030000 {
136 compatible = "mrvl,mmp-uart";
144 uart2: uart@d4017000 {
145 compatible = "mrvl,mmp-uart";
153 uart3: uart@d4018000 {
154 compatible = "mrvl,mmp-uart";
162 uart4: uart@d4016000 {
163 compatible = "mrvl,mmp-uart";
Dbcm21664.dtsi63 uart@3e000000 {
64 compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart";
73 uart@3e001000 {
74 compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart";
83 uart@3e002000 {
84 compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart";
Dexynos5410.dtsi195 compatible = "samsung,exynos4210-uart";
199 clock-names = "uart", "clk_uart_baud0";
204 compatible = "samsung,exynos4210-uart";
208 clock-names = "uart", "clk_uart_baud0";
213 compatible = "samsung,exynos4210-uart";
217 clock-names = "uart", "clk_uart_baud0";
Dexynos5.dtsi61 compatible = "samsung,exynos4210-uart";
67 compatible = "samsung,exynos4210-uart";
73 compatible = "samsung,exynos4210-uart";
79 compatible = "samsung,exynos4210-uart";
Dexynos5260.dtsi240 compatible = "samsung,exynos4210-uart";
244 clock-names = "uart", "clk_uart_baud0";
249 compatible = "samsung,exynos4210-uart";
253 clock-names = "uart", "clk_uart_baud0";
258 compatible = "samsung,exynos4210-uart";
262 clock-names = "uart", "clk_uart_baud0";
267 compatible = "samsung,exynos4210-uart";
271 clock-names = "uart", "clk_uart_baud0";
Datlas7.dtsi219 uart0: uart@18010000 {
221 compatible = "sirf,atlas7-uart";
230 uart1: uart@18020000 {
232 compatible = "sirf,atlas7-uart";
239 uart2: uart@18030000 {
241 compatible = "sirf,atlas7-uart";
250 uart3: uart@18040000 {
252 compatible = "sirf,atlas7-uart";
261 uart4: uart@18050000 {
263 compatible = "sirf,atlas7-uart";
[all …]
Domap-zoom-common.dtsi16 uart@3,0 {
52 uart@3,1 {
63 uart@3,2 {
74 uart@3,3 {
Dste-ccu9540.dts24 uart@80120000 {
28 uart@80121000 {
32 uart@80007000 {
Dvt8500.dtsi132 compatible = "via,vt8500-uart";
140 compatible = "via,vt8500-uart";
148 compatible = "via,vt8500-uart";
156 compatible = "via,vt8500-uart";
Ds3c24xx.dtsi53 compatible = "samsung,s3c2410-uart";
60 compatible = "samsung,s3c2410-uart";
67 compatible = "samsung,s3c2410-uart";
Dwm8505.dtsi229 compatible = "via,vt8500-uart";
237 compatible = "via,vt8500-uart";
245 compatible = "via,vt8500-uart";
253 compatible = "via,vt8500-uart";
261 compatible = "via,vt8500-uart";
269 compatible = "via,vt8500-uart";
Dimx50.dtsi126 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
309 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
319 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
372 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
390 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
Dimx27.dtsi163 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
173 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
183 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
193 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
397 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
407 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
Dste-ccu8540.dts35 uart@80120000 {
42 uart@80121000 {
46 uart@80007000 {
Dmt6592.dtsi113 compatible = "mediatek,mt6577-uart";
121 compatible = "mediatek,mt6577-uart";
129 compatible = "mediatek,mt6577-uart";
137 compatible = "mediatek,mt6577-uart";
Dmt6589.dtsi111 compatible = "mediatek,mt6577-uart";
119 compatible = "mediatek,mt6577-uart";
127 compatible = "mediatek,mt6577-uart";
135 compatible = "mediatek,mt6577-uart";
Dwm8750.dtsi269 compatible = "via,vt8500-uart";
277 compatible = "via,vt8500-uart";
285 compatible = "via,vt8500-uart";
293 compatible = "via,vt8500-uart";
301 compatible = "via,vt8500-uart";
309 compatible = "via,vt8500-uart";
Datlas6.dtsi224 uart0: uart@b0050000 {
226 compatible = "sirf,prima2-uart";
235 uart1: uart@b0060000 {
237 compatible = "sirf,prima2-uart";
245 uart2: uart@b0070000 {
247 compatible = "sirf,prima2-uart";
397 uart {
403 uart {
409 uart {
415 uart {
[all …]
Dimx25.dtsi122 compatible = "fsl,imx25-uart", "fsl,imx21-uart";
131 compatible = "fsl,imx25-uart", "fsl,imx21-uart";
213 compatible = "fsl,imx25-uart", "fsl,imx21-uart";
222 compatible = "fsl,imx25-uart", "fsl,imx21-uart";
260 compatible = "fsl,imx25-uart", "fsl,imx21-uart";
Dimx6sl.dtsi191 compatible = "fsl,imx6sl-uart",
192 "fsl,imx6q-uart", "fsl,imx21-uart";
204 compatible = "fsl,imx6sl-uart",
205 "fsl,imx6q-uart", "fsl,imx21-uart";
217 compatible = "fsl,imx6sl-uart",
218 "fsl,imx6q-uart", "fsl,imx21-uart";
278 compatible = "fsl,imx6sl-uart",
279 "fsl,imx6q-uart", "fsl,imx21-uart";
291 compatible = "fsl,imx6sl-uart",
292 "fsl,imx6q-uart", "fsl,imx21-uart";
Dprima2.dtsi230 uart0: uart@b0050000 {
232 compatible = "sirf,prima2-uart";
241 uart1: uart@b0060000 {
243 compatible = "sirf,prima2-uart";
250 uart2: uart@b0070000 {
252 compatible = "sirf,prima2-uart";
411 uart {
417 uart {
423 uart {
429 uart {
[all …]
Daxm55xx.dtsi115 serial0: uart@2010080000 {
124 serial1: uart@2010081000 {
133 serial2: uart@2010082000 {
142 serial3: uart@2010083000 {
Dimx27-phytec-phycard-s-rdk.dts150 fsl,uart-has-rtscts;
157 fsl,uart-has-rtscts;
164 fsl,uart-has-rtscts;
Demev2.dtsi141 compatible = "renesas,em-uart";
149 compatible = "renesas,em-uart";
157 compatible = "renesas,em-uart";
165 compatible = "renesas,em-uart";
Dpicoxcell-pc3x2.dtsi197 uart0: uart@30000 {
198 compatible = "snps,dw-apb-uart";
207 uart1: uart@40000 {
208 compatible = "snps,dw-apb-uart";
Dimx35.dtsi88 compatible = "fsl,imx35-uart", "fsl,imx21-uart";
97 compatible = "fsl,imx35-uart", "fsl,imx21-uart";
154 compatible = "fsl,imx35-uart", "fsl,imx21-uart";
Datlas7-evb.dts71 uart6: uart@11000000 {
73 sirf,uart-has-rtscts;
Dmeson.dtsi86 compatible = "amlogic,meson-uart";
94 compatible = "amlogic,meson-uart";
102 compatible = "amlogic,meson-uart";
110 compatible = "amlogic,meson-uart";
Dwm8850.dtsi256 compatible = "via,vt8500-uart";
264 compatible = "via,vt8500-uart";
272 compatible = "via,vt8500-uart";
280 compatible = "via,vt8500-uart";
Dimx53.dtsi213 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
494 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
504 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
587 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
617 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
Dam4372.dtsi147 compatible = "ti,am4372-uart","ti,omap2-uart";
154 compatible = "ti,am4372-uart","ti,omap2-uart";
162 compatible = "ti,am4372-uart","ti,omap2-uart";
170 compatible = "ti,am4372-uart","ti,omap2-uart";
178 compatible = "ti,am4372-uart","ti,omap2-uart";
186 compatible = "ti,am4372-uart","ti,omap2-uart";
Dtegra30.dtsi370 * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
375 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
388 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
401 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
414 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
427 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
Dbcm-cygnus.dtsi172 compatible = "snps,dw-apb-uart";
183 compatible = "snps,dw-apb-uart";
194 compatible = "snps,dw-apb-uart";
205 compatible = "snps,dw-apb-uart";
Dlpc32xx.dtsi136 compatible = "nxp,lpc3220-uart";
145 compatible = "nxp,lpc3220-uart";
154 compatible = "nxp,lpc3220-uart";
163 compatible = "nxp,lpc3220-uart";
Dtegra114.dtsi255 * is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable
260 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
273 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
286 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
299 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
Dcx92755.dtsi90 uart0: uart@f0000740 {
98 uart1: uart@f0000760 {
106 uart2: uart@f0000780 {
Ds5pv210.dtsi330 compatible = "samsung,s5pv210-uart";
334 clock-names = "uart", "clk_uart_baud0",
342 compatible = "samsung,s5pv210-uart";
346 clock-names = "uart", "clk_uart_baud0",
354 compatible = "samsung,s5pv210-uart";
358 clock-names = "uart", "clk_uart_baud0",
366 compatible = "samsung,s5pv210-uart";
370 clock-names = "uart", "clk_uart_baud0",
Dexynos4415.dtsi414 compatible = "samsung,exynos4210-uart";
418 clock-names = "uart", "clk_uart_baud0";
423 compatible = "samsung,exynos4210-uart";
427 clock-names = "uart", "clk_uart_baud0";
432 compatible = "samsung,exynos4210-uart";
436 clock-names = "uart", "clk_uart_baud0";
441 compatible = "samsung,exynos4210-uart";
445 clock-names = "uart", "clk_uart_baud0";
Ddm816x.dtsi345 uart1: uart@48020000 {
346 compatible = "ti,omap3-uart";
355 uart2: uart@48022000 {
356 compatible = "ti,omap3-uart";
365 uart3: uart@48024000 {
366 compatible = "ti,omap3-uart";
Dimx27-eukrea-mbimxsd27-baseboard.dts143 fsl,uart-has-rtscts;
150 fsl,uart-has-rtscts;
157 fsl,uart-has-rtscts;
Dintegrator.dtsi76 uart@16000000 {
81 uart@17000000 {
Dimx1-apf9328.dts37 fsl,uart-has-rtscts;
44 fsl,uart-has-rtscts;
Dexynos5440.dtsi108 compatible = "samsung,exynos4210-uart";
112 clock-names = "uart", "clk_uart_baud0";
116 compatible = "samsung,exynos4210-uart";
120 clock-names = "uart", "clk_uart_baud0";
Dbcm63138.dtsi118 compatible = "brcm,bcm6345-uart";
127 compatible = "brcm,bcm6345-uart";
Dimx1-ads.dts69 fsl,uart-has-rtscts;
76 fsl,uart-has-rtscts;
Dversatile-ab.dts124 uart0: uart@101f1000 {
132 uart1: uart@101f2000 {
140 uart2: uart@101f3000 {
Dste-href.dtsi28 uart@80120000 {
35 uart@80121000 {
42 uart@80007000 {
Dimx1.dtsi98 compatible = "fsl,imx1-uart";
108 compatible = "fsl,imx1-uart";
138 compatible = "fsl,imx1-uart";
Dpicoxcell-pc3x3.dtsi291 uart0: uart@30000 {
292 compatible = "snps,dw-apb-uart";
301 uart1: uart@40000 {
302 compatible = "snps,dw-apb-uart";
Dimx51.dtsi191 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
397 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
407 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
Dsun9i-a80.dtsi496 compatible = "snps,dw-apb-uart";
507 compatible = "snps,dw-apb-uart";
518 compatible = "snps,dw-apb-uart";
529 compatible = "snps,dw-apb-uart";
540 compatible = "snps,dw-apb-uart";
551 compatible = "snps,dw-apb-uart";
623 compatible = "snps,dw-apb-uart";
Dexynos4.dtsi424 compatible = "samsung,exynos4210-uart";
428 clock-names = "uart", "clk_uart_baud0";
433 compatible = "samsung,exynos4210-uart";
437 clock-names = "uart", "clk_uart_baud0";
442 compatible = "samsung,exynos4210-uart";
446 clock-names = "uart", "clk_uart_baud0";
451 compatible = "samsung,exynos4210-uart";
455 clock-names = "uart", "clk_uart_baud0";
Dimx35-eukrea-mbimxsd35-baseboard.dts142 fsl,uart-has-rtscts;
149 fsl,uart-has-rtscts;
Dprima2-evb.dts23 uart@b0060000 {
Domap2.dtsi153 compatible = "ti,omap2-uart";
163 compatible = "ti,omap2-uart";
173 compatible = "ti,omap2-uart";
Dimx25-eukrea-mbimxsd25-baseboard.dts164 fsl,uart-has-rtscts;
171 fsl,uart-has-rtscts;
Dimx6sx.dtsi277 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
979 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
991 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1003 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1015 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1151 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
/linux-4.1.27/arch/x86/include/asm/
Dserial.h24 { .uart = 0, BASE_BAUD, 0x3F8, 4, STD_COMX_FLAGS }, /* ttyS0 */ \
25 { .uart = 0, BASE_BAUD, 0x2F8, 3, STD_COMX_FLAGS }, /* ttyS1 */ \
26 { .uart = 0, BASE_BAUD, 0x3E8, 4, STD_COMX_FLAGS }, /* ttyS2 */ \
27 { .uart = 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS }, /* ttyS3 */
/linux-4.1.27/arch/arm64/boot/dts/mediatek/
Dmt8173.dtsi151 compatible = "mediatek,mt8173-uart",
152 "mediatek,mt6577-uart";
160 compatible = "mediatek,mt8173-uart",
161 "mediatek,mt6577-uart";
169 compatible = "mediatek,mt8173-uart",
170 "mediatek,mt6577-uart";
178 compatible = "mediatek,mt8173-uart",
179 "mediatek,mt6577-uart";
/linux-4.1.27/arch/arm/plat-samsung/
Dinit.c117 int uart; in s3c24xx_init_uartdevs() local
121 for (uart = 0; uart < no; uart++, cfg++, cfgptr++) { in s3c24xx_init_uartdevs()
126 s3c24xx_uart_devs[uart] = platdev; in s3c24xx_init_uartdevs()
/linux-4.1.27/arch/mips/sgi-ip27/
Dip27-console.c35 struct ioc3_uartregs *uart = console_uart(); in prom_putchar() local
37 while ((uart->iu_lsr & 0x20) == 0); in prom_putchar()
38 uart->iu_thr = c; in prom_putchar()
/linux-4.1.27/arch/arm64/boot/dts/sprd/
Dsharkl64.dtsi27 compatible = "sprd,sc9836-uart";
35 compatible = "sprd,sc9836-uart";
43 compatible = "sprd,sc9836-uart";
51 compatible = "sprd,sc9836-uart";
/linux-4.1.27/Documentation/devicetree/bindings/dma/
Dqcom_bam_dma.txt19 uart-bam: dma@f9984000 = {
34 compatible = "qcom,msm-uart";
42 dmas = <&uart-bam 0>, <&uart-bam 1>;
/linux-4.1.27/Documentation/devicetree/bindings/powerpc/fsl/
Dmpc5121-psc.txt7 are specified by fsl,mpc5121-psc-uart nodes in the
11 fsl,mpc5121-psc-uart nodes
15 - compatible : Should contain "fsl,mpc5121-psc-uart" and "fsl,mpc5121-psc"
46 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
56 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
/linux-4.1.27/sound/drivers/mpu401/
DMakefile7 snd-mpu401-uart-objs := mpu401_uart.o
9 obj-$(CONFIG_SND_MPU401_UART) += snd-mpu401-uart.o
/linux-4.1.27/drivers/char/mwave/
Dmwavedd.c433 struct uart_8250_port uart; in register_serial_portandirq() local
465 memset(&uart, 0, sizeof(uart)); in register_serial_portandirq()
467 uart.port.uartclk = 1843200; in register_serial_portandirq()
468 uart.port.iobase = port; in register_serial_portandirq()
469 uart.port.irq = irq; in register_serial_portandirq()
470 uart.port.iotype = UPIO_PORT; in register_serial_portandirq()
471 uart.port.flags = UPF_SHARE_IRQ; in register_serial_portandirq()
472 return serial8250_register_8250_port(&uart); in register_serial_portandirq()
DREADME28 If the mwave's uart irq has not been setup and stored in bios by the
30 irq used by the mwave uart to be configured.
33 If the uart io range has not been setup and stored in bios by the
35 io range used by the mwave uart to be configured.
/linux-4.1.27/arch/mips/boot/compressed/
DMakefile32 targets := head.o decompress.o string.o dbg.o uart-16550.o uart-alchemy.o
39 vmlinuzobjs-$(CONFIG_SYS_SUPPORTS_ZBOOT_UART16550) += $(obj)/uart-16550.o
40 vmlinuzobjs-$(CONFIG_MIPS_ALCHEMY) += $(obj)/uart-alchemy.o
/linux-4.1.27/arch/mips/include/asm/octeon/
Dcvmx-ciu-defs.h1300 uint64_t uart:2; member
1308 uint64_t uart:2;
1346 uint64_t uart:2; member
1354 uint64_t uart:2;
1389 uint64_t uart:2; member
1397 uint64_t uart:2;
1428 uint64_t uart:2; member
1436 uint64_t uart:2;
1472 uint64_t uart:2; member
1480 uint64_t uart:2;
[all …]
/linux-4.1.27/arch/powerpc/boot/
Dcuboot-hotfoot.c29 u32 uart = mfdcr(DCRN_CPC0_UCR) & 0x7f; in hotfoot_fixups() local
37 dt_fixup_clock("/plb/opb/serial@ef600300", bd.bi_procfreq / uart); in hotfoot_fixups()
38 dt_fixup_clock("/plb/opb/serial@ef600400", bd.bi_procfreq / uart); in hotfoot_fixups()
/linux-4.1.27/Documentation/devicetree/bindings/pinctrl/
Dfsl,imx27-pinctrl.txt75 uart {
76 pinctrl_uart1: uart-1 {
109 uart {
110 pinctrl_uart1: uart-1 {
Dpinctrl-sirf.txt30 uart {
36 uart {
44 uart2: uart@0xb0070000 {
Dabilis,tb10x-iomux.txt62 uart@FF100000 {
63 compatible = "snps,dw-apb-uart";
/linux-4.1.27/arch/mips/boot/dts/ralink/
Drt3883.dtsi49 compatible = "ralink,rt3883-uart", "ralink,rt2880-uart", "ns16550a";
Dmt7620a.dtsi49 compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
Drt3050.dtsi49 compatible = "ralink,rt3052-uart", "ralink,rt2880-uart", "ns16550a";
/linux-4.1.27/Documentation/devicetree/bindings/clock/
Dimx27-clock.txt21 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
Dsamsung,s3c2443-clock.txt33 - "ext_uart" - external uart clock - optional,
48 compatible = "samsung,s3c2440-uart";
51 clock-names = "uart", "clk_uart_baud2",
Dimx6q-clock.txt25 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
Dimx31-clock.txt85 compatible = "fsl,imx31-uart", "fsl,imx21-uart";
Dexynos5250-clock.txt36 compatible = "samsung,exynos4210-uart";
40 clock-names = "uart", "clk_uart_baud0";
Dexynos5410-clock.txt40 compatible = "samsung,exynos4210-uart";
44 clock-names = "uart", "clk_uart_baud0";
Dexynos5420-clock.txt37 compatible = "samsung,exynos4210-uart";
41 clock-names = "uart", "clk_uart_baud0";
Dexynos4-clock.txt38 compatible = "samsung,exynos4210-uart";
42 clock-names = "uart", "clk_uart_baud0";
Dexynos3250-clock.txt52 compatible = "samsung,exynos4210-uart";
56 clock-names = "uart", "clk_uart_baud0";
Dimx25-clock.txt155 compatible = "fsl,imx25-uart", "fsl,imx21-uart";
Dsamsung,s3c2412-clock.txt43 compatible = "samsung,s3c2412-uart";
46 clock-names = "uart", "clk_uart_baud2", "clk_uart_baud3";
Dsamsung,s3c2410-clock.txt44 compatible = "samsung,s3c2440-uart";
47 clock-names = "uart", "clk_uart_baud2";
Dsamsung,s5pv210-clock.txt69 compatible = "samsung,s5pv210-uart";
73 clock-names = "uart", "clk_uart_baud0",
Dsamsung,s3c64xx-clock.txt68 compatible = "samsung,s3c6400-uart";
72 clock-names = "uart", "clk_uart_baud2",
Dbrcm,kona-ccu.txt47 uart@3e002000 {
48 compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
Demev2-clock.txt55 uart@e1020000 {
56 compatible = "renesas,em-uart";
Dclock-bindings.txt116 uart@a000 {
117 compatible = "fsl,imx-uart";
148 uart@a000 {
149 compatible = "fsl,imx-uart";
/linux-4.1.27/arch/arm64/boot/dts/arm/
Dfoundation-v8.dts201 v2m_serial0: uart@090000 {
209 v2m_serial1: uart@0a0000 {
217 v2m_serial2: uart@0b0000 {
225 v2m_serial3: uart@0c0000 {
Drtsm_ve-motherboard.dtsi115 v2m_serial0: uart@090000 {
123 v2m_serial1: uart@0a0000 {
131 v2m_serial2: uart@0b0000 {
139 v2m_serial3: uart@0c0000 {
/linux-4.1.27/arch/blackfin/include/asm/
Dbfin_serial.h269 #define port_membase(uart) (((struct bfin_serial_port *)(uart))->port.membase) argument
382 #define get_lsr_cache(uart) (((struct bfin_serial_port *)(uart))->lsr) argument
383 #define put_lsr_cache(uart, v) (((struct bfin_serial_port *)(uart))->lsr = (v)) argument
/linux-4.1.27/arch/arm64/boot/dts/exynos/
Dexynos7.dtsi189 compatible = "samsung,exynos4210-uart";
194 clock-names = "uart", "clk_uart_baud0";
199 compatible = "samsung,exynos4210-uart";
204 clock-names = "uart", "clk_uart_baud0";
209 compatible = "samsung,exynos4210-uart";
214 clock-names = "uart", "clk_uart_baud0";
219 compatible = "samsung,exynos4210-uart";
224 clock-names = "uart", "clk_uart_baud0";
/linux-4.1.27/arch/arm/mach-s3c24xx/include/mach/
Dmap.h38 #define S3C_VA_UARTx(uart) (S3C_VA_UART + ((uart * S3C_UART_OFFSET))) argument
/linux-4.1.27/Documentation/sound/alsa/
Dserial-u16550.txt26 /sbin/setserial /dev/ttyS0 uart none
31 /sbin/setserial /dev/ttyS0 uart none
41 /sbin/setserial /dev/ttyS0 uart none
51 /sbin/setserial /dev/ttyS0 uart none
67 /sbin/setserial /dev/ttyS0 uart none
/linux-4.1.27/drivers/clk/mxs/
Dclk-imx23.c92 clk32k, dri, pwm, filt, uart, ssp, gpmi, spdif, emi, saif, enumerator
101 cpu, hbus, xbus, emi, uart, enumerator
151 clks[uart] = mxs_clk_gate("uart", "ref_xtal", XTAL, 31); in mx23_clocks_init()
Dclk-imx28.c145 clk32k_div, rtc, lradc, spdif_div, clk32k, pwm, uart, ssp0, enumerator
155 cpu, hbus, xbus, emi, uart, enumerator
218 clks[uart] = mxs_clk_gate("uart", "ref_xtal", XTAL, 31); in mx28_clocks_init()
/linux-4.1.27/arch/arm/mach-iop33x/
DMakefile5 obj-y := irq.o uart.o
/linux-4.1.27/drivers/staging/speakup/
Dserialio.h15 unsigned int uart; /* unused */ member
/linux-4.1.27/drivers/ipack/devices/
DKconfig2 tristate "IndustryPack IP-OCTAL uart support"
/linux-4.1.27/arch/tile/gxio/
DMakefile9 obj-$(CONFIG_TILE_GXIO_UART) += uart.o iorpc_uart.o
/linux-4.1.27/drivers/net/hamradio/
Dbaycom_ser_fdx.c374 enum uart { c_uart_unknown, c_uart_8250, enum
380 static enum uart ser12_check_uart(unsigned int iobase) in ser12_check_uart()
383 enum uart u; in ser12_check_uart()
384 enum uart uart_tab[] = in ser12_check_uart()
416 enum uart u; in ser12_open()
Dbaycom_ser_hdx.c433 enum uart { c_uart_unknown, c_uart_8250, enum
439 static enum uart ser12_check_uart(unsigned int iobase) in ser12_check_uart()
442 enum uart u; in ser12_check_uart()
443 enum uart uart_tab[] = in ser12_check_uart()
475 enum uart u; in ser12_open()
/linux-4.1.27/arch/mips/bcm63xx/
DMakefile3 dev-pcmcia.o dev-rng.o dev-spi.o dev-hsspi.o dev-uart.o \
/linux-4.1.27/arch/cris/boot/dts/
Detraxfs.dtsi32 compatible = "axis,etraxfs-uart";
/linux-4.1.27/drivers/usb/serial/
Dssu100.c89 unsigned short uart, in ssu100_getregister() argument
95 uart, data, sizeof(*data), 300); in ssu100_getregister()
101 unsigned short uart, in ssu100_setregister() argument
108 QT_SET_GET_REGISTER, 0x40, value, uart, in ssu100_setregister()
/linux-4.1.27/arch/arm/include/debug/
Dtegra.S54 #define checkuart(rp, rv, lhu, bit, uart) \ argument
72 ldr rp, =TEGRA_UART##uart##_BASE ; \

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