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Searched refs:timer_base (Results 1 – 18 of 18) sorted by relevance

/linux-4.1.27/arch/arm/mach-imx/
Dtime.c85 static void __iomem *timer_base; variable
92 __raw_writel(0, timer_base + V2_IR); in gpt_irq_disable()
94 tmp = __raw_readl(timer_base + MXC_TCTL); in gpt_irq_disable()
95 __raw_writel(tmp & ~MX1_2_TCTL_IRQEN, timer_base + MXC_TCTL); in gpt_irq_disable()
102 __raw_writel(1<<0, timer_base + V2_IR); in gpt_irq_enable()
104 __raw_writel(__raw_readl(timer_base + MXC_TCTL) | MX1_2_TCTL_IRQEN, in gpt_irq_enable()
105 timer_base + MXC_TCTL); in gpt_irq_enable()
113 __raw_writel(0, timer_base + MX1_2_TSTAT); in gpt_irq_acknowledge()
116 timer_base + MX1_2_TSTAT); in gpt_irq_acknowledge()
118 __raw_writel(V2_TSTAT_OF1, timer_base + V2_TSTAT); in gpt_irq_acknowledge()
[all …]
Depit.c62 static void __iomem *timer_base; variable
68 val = __raw_readl(timer_base + EPITCR); in epit_irq_disable()
70 __raw_writel(val, timer_base + EPITCR); in epit_irq_disable()
77 val = __raw_readl(timer_base + EPITCR); in epit_irq_enable()
79 __raw_writel(val, timer_base + EPITCR); in epit_irq_enable()
84 __raw_writel(EPITSR_OCIF, timer_base + EPITSR); in epit_irq_acknowledge()
91 return clocksource_mmio_init(timer_base + EPITCNR, "epit", c, 200, 32, in epit_clocksource_init()
102 tcmp = __raw_readl(timer_base + EPITCNR); in epit_set_next_event()
104 __raw_writel(tcmp - evt, timer_base + EPITCMPR); in epit_set_next_event()
208 timer_base = base; in epit_timer_init()
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/linux-4.1.27/arch/arm/plat-orion/
Dtime.c50 static void __iomem *timer_base; variable
66 return ~readl(timer_base + TIMER0_VAL_OFF); in orion_read_sched_clock()
95 writel(delta, timer_base + TIMER1_VAL_OFF); in orion_clkevt_next_event()
100 u = readl(timer_base + TIMER_CTRL_OFF); in orion_clkevt_next_event()
102 writel(u, timer_base + TIMER_CTRL_OFF); in orion_clkevt_next_event()
120 writel(ticks_per_jiffy - 1, timer_base + TIMER1_RELOAD_OFF); in orion_clkevt_mode()
121 writel(ticks_per_jiffy - 1, timer_base + TIMER1_VAL_OFF); in orion_clkevt_mode()
132 u = readl(timer_base + TIMER_CTRL_OFF); in orion_clkevt_mode()
134 timer_base + TIMER_CTRL_OFF); in orion_clkevt_mode()
139 u = readl(timer_base + TIMER_CTRL_OFF); in orion_clkevt_mode()
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/linux-4.1.27/drivers/clocksource/
Dsun4i_timer.c42 static void __iomem *timer_base; variable
53 u32 old = readl(timer_base + TIMER_CNTVAL_REG(1)); in sun4i_clkevt_sync()
55 while ((old - readl(timer_base + TIMER_CNTVAL_REG(1))) < TIMER_SYNC_TICKS) in sun4i_clkevt_sync()
61 u32 val = readl(timer_base + TIMER_CTL_REG(timer)); in sun4i_clkevt_time_stop()
62 writel(val & ~TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(timer)); in sun4i_clkevt_time_stop()
68 writel(delay, timer_base + TIMER_INTVAL_REG(timer)); in sun4i_clkevt_time_setup()
73 u32 val = readl(timer_base + TIMER_CTL_REG(timer)); in sun4i_clkevt_time_start()
81 timer_base + TIMER_CTL_REG(timer)); in sun4i_clkevt_time_start()
128 writel(0x1, timer_base + TIMER_IRQ_ST_REG); in sun4i_timer_interrupt()
143 return ~readl(timer_base + TIMER_CNTVAL_REG(1)); in sun4i_timer_sched_read()
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Dtime-orion.c37 static void __iomem *timer_base; variable
44 return ~readl(timer_base + TIMER0_VAL); in orion_read_sched_clock()
56 writel(delta, timer_base + TIMER1_VAL); in orion_clkevt_next_event()
57 atomic_io_modify(timer_base + TIMER_CTRL, in orion_clkevt_next_event()
68 writel(ticks_per_jiffy - 1, timer_base + TIMER1_RELOAD); in orion_clkevt_mode()
69 writel(ticks_per_jiffy - 1, timer_base + TIMER1_VAL); in orion_clkevt_mode()
70 atomic_io_modify(timer_base + TIMER_CTRL, in orion_clkevt_mode()
75 atomic_io_modify(timer_base + TIMER_CTRL, in orion_clkevt_mode()
107 timer_base = of_iomap(np, 0); in orion_timer_init()
108 if (!timer_base) in orion_timer_init()
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Dmeson6_timer.c39 static void __iomem *timer_base; variable
43 return (u64)readl(timer_base + TIMER_ISA_VAL(CSD_ID)); in meson6_timer_sched_read()
48 u32 val = readl(timer_base + TIMER_ISA_MUX); in meson6_clkevt_time_stop()
50 writel(val & ~TIMER_ENABLE_BIT(timer), timer_base + TIMER_ISA_MUX); in meson6_clkevt_time_stop()
55 writel(delay, timer_base + TIMER_ISA_VAL(timer)); in meson6_clkevt_time_setup()
60 u32 val = readl(timer_base + TIMER_ISA_MUX); in meson6_clkevt_time_start()
67 writel(val | TIMER_ENABLE_BIT(timer), timer_base + TIMER_ISA_MUX); in meson6_clkevt_time_start()
130 timer_base = of_io_request_and_map(node, 0, "meson6-timer"); in meson6_timer_init()
131 if (IS_ERR(timer_base)) in meson6_timer_init()
139 val = readl(timer_base + TIMER_ISA_MUX); in meson6_timer_init()
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Dtime-armada-370-xp.c77 static void __iomem *timer_base, *local_base; variable
97 return ~readl(timer_base + TIMER0_VAL_OFF); in armada_370_xp_read_sched_clock()
231 timer0_ctrl_reg = readl(timer_base + TIMER_CTRL_OFF); in armada_370_xp_timer_suspend()
238 writel(0xffffffff, timer_base + TIMER0_VAL_OFF); in armada_370_xp_timer_resume()
239 writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF); in armada_370_xp_timer_resume()
240 writel(timer0_ctrl_reg, timer_base + TIMER_CTRL_OFF); in armada_370_xp_timer_resume()
254 timer_base = of_iomap(np, 0); in armada_370_xp_timer_common_init()
255 WARN_ON(!timer_base); in armada_370_xp_timer_common_init()
265 atomic_io_modify(timer_base + TIMER_CTRL_OFF, clr | set, set); in armada_370_xp_timer_common_init()
280 writel(0xffffffff, timer_base + TIMER0_VAL_OFF); in armada_370_xp_timer_common_init()
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Dpxa_timer.c52 #define timer_readl(reg) readl_relaxed(timer_base + (reg))
53 #define timer_writel(val, reg) writel_relaxed((val), timer_base + (reg))
55 static void __iomem *timer_base; variable
177 clocksource_mmio_init(timer_base + OSCR, "oscr0", clock_tick_rate, 200, in pxa_timer_common_init()
189 timer_base = of_iomap(np, 0); in pxa_timer_dt_init()
190 if (!timer_base) in pxa_timer_dt_init()
219 timer_base = base; in pxa_timer_nodt_init()
Dvf_pit_timer.c165 void __iomem *timer_base; in pit_timer_init() local
169 timer_base = of_iomap(np, 0); in pit_timer_init()
170 BUG_ON(!timer_base); in pit_timer_init()
177 clksrc_base = timer_base + PITn_OFFSET(2); in pit_timer_init()
178 clkevt_base = timer_base + PITn_OFFSET(3); in pit_timer_init()
192 __raw_writel(~PITMCR_MDIS, timer_base + PITMCR); in pit_timer_init()
Dbcm_kona_timer.c71 kona_timer_get_counter(void __iomem *timer_base, uint32_t *msw, uint32_t *lsw) in kona_timer_get_counter() argument
88 *msw = readl(timer_base + KONA_GPTIMER_STCHI_OFFSET); in kona_timer_get_counter()
89 *lsw = readl(timer_base + KONA_GPTIMER_STCLO_OFFSET); in kona_timer_get_counter()
90 if (*msw == readl(timer_base + KONA_GPTIMER_STCHI_OFFSET)) in kona_timer_get_counter()
Dtimer-sun5i.c322 void __iomem *timer_base; in sun5i_timer_init() local
326 timer_base = of_io_request_and_map(node, 0, of_node_full_name(node)); in sun5i_timer_init()
327 if (!timer_base) in sun5i_timer_init()
342 sun5i_setup_clocksource(node, timer_base, clk, irq); in sun5i_timer_init()
343 sun5i_setup_clockevent(node, timer_base, clk, irq); in sun5i_timer_init()
/linux-4.1.27/arch/cris/arch-v32/kernel/
Dtime.c173 static void __iomem *timer_base; variable
183 REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl); in crisv32_clkevt_mode()
194 REG_WR(timer, timer_base, rw_tmr0_div, evt); in crisv32_clkevt_next_event()
195 REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl); in crisv32_clkevt_next_event()
198 REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl); in crisv32_clkevt_next_event()
213 intr = REG_RD(timer, timer_base, r_masked_intr); in crisv32_timer_interrupt()
217 REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl); in crisv32_timer_interrupt()
218 REG_WR(timer, timer_base, rw_ack_intr, ack); in crisv32_timer_interrupt()
248 return REG_RD(timer, timer_base, r_time); in crisv32_timer_sched_clock()
259 REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl); in crisv32_timer_init()
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/linux-4.1.27/arch/mips/loongson1/common/
Dtime.c38 static void __iomem *timer_base; variable
43 __raw_writel(period, timer_base + PWM_HRC); in ls1x_pwmtimer_set_period()
44 __raw_writel(period, timer_base + PWM_LRC); in ls1x_pwmtimer_set_period()
49 __raw_writel(0x0, timer_base + PWM_CNT); in ls1x_pwmtimer_restart()
50 __raw_writel(INT_EN | CNT_EN, timer_base + PWM_CTRL); in ls1x_pwmtimer_restart()
55 timer_base = ioremap(LS1X_TIMER_BASE, 0xf); in ls1x_pwmtimer_init()
56 if (!timer_base) in ls1x_pwmtimer_init()
89 count = __raw_readl(timer_base + PWM_CNT); in ls1x_clocksource_read()
138 __raw_writel(INT_EN | CNT_EN, timer_base + PWM_CTRL); in ls1x_clockevent_set_mode()
142 __raw_writel(__raw_readl(timer_base + PWM_CTRL) & ~CNT_EN, in ls1x_clockevent_set_mode()
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/linux-4.1.27/sound/pci/ctxfi/
Dcttimer.c35 struct ct_timer *timer_base; member
295 struct ct_timer *atimer = ti->timer_base; in ct_xfitimer_start()
310 struct ct_timer *atimer = ti->timer_base; in ct_xfitimer_stop()
348 ti->timer_base = atimer; in ct_timer_instance_new()
363 if (ti->timer_base->ops->prepare) in ct_timer_prepare()
364 ti->timer_base->ops->prepare(ti); in ct_timer_prepare()
371 struct ct_timer *atimer = ti->timer_base; in ct_timer_start()
377 struct ct_timer *atimer = ti->timer_base; in ct_timer_stop()
383 struct ct_timer *atimer = ti->timer_base; in ct_timer_instance_free()
/linux-4.1.27/arch/arm/plat-orion/include/plat/
Dtime.h14 void orion_time_set_base(void __iomem *timer_base);
/linux-4.1.27/drivers/staging/comedi/drivers/
Ddt3000.c365 static int dt3k_ns_to_timer(unsigned int timer_base, unsigned int *nanosec, in dt3k_ns_to_timer() argument
374 base = timer_base * (prescale + 1); in dt3k_ns_to_timer()
394 base = timer_base * (1 << prescale); in dt3k_ns_to_timer()
Daddi_apci_3120.c282 unsigned int timer_base = devpriv->osc_base * prescale; in apci3120_ns_to_timer() local
287 divisor = DIV_ROUND_UP(ns, timer_base); in apci3120_ns_to_timer()
290 divisor = ns / timer_base; in apci3120_ns_to_timer()
294 divisor = DIV_ROUND_CLOSEST(ns, timer_base); in apci3120_ns_to_timer()
Dme4000.c1377 unsigned long timer_base = pci_resource_start(pcidev, 3); in me4000_auto_attach() local
1379 if (!timer_base) in me4000_auto_attach()
1382 dev->pacer = comedi_8254_init(timer_base, 0, I8254_IO8, 0); in me4000_auto_attach()