39 static void __iomem *timer_base;  variable
43 	return (u64)readl(timer_base + TIMER_ISA_VAL(CSD_ID));  in meson6_timer_sched_read()
48 	u32 val = readl(timer_base + TIMER_ISA_MUX);  in meson6_clkevt_time_stop()
50 	writel(val & ~TIMER_ENABLE_BIT(timer), timer_base + TIMER_ISA_MUX);  in meson6_clkevt_time_stop()
55 	writel(delay, timer_base + TIMER_ISA_VAL(timer));  in meson6_clkevt_time_setup()
60 	u32 val = readl(timer_base + TIMER_ISA_MUX);  in meson6_clkevt_time_start()
67 	writel(val | TIMER_ENABLE_BIT(timer), timer_base + TIMER_ISA_MUX);  in meson6_clkevt_time_start()
130 	timer_base = of_io_request_and_map(node, 0, "meson6-timer");  in meson6_timer_init()
131 	if (IS_ERR(timer_base))  in meson6_timer_init()
139 	val = readl(timer_base + TIMER_ISA_MUX);  in meson6_timer_init()
142 	writel(val, timer_base + TIMER_ISA_MUX);  in meson6_timer_init()
145 	clocksource_mmio_init(timer_base + TIMER_ISA_VAL(CSD_ID), node->name,  in meson6_timer_init()
151 	writel(val, timer_base + TIMER_ISA_MUX);  in meson6_timer_init()