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Searched refs:ramfc (Results 1 – 11 of 11) sorted by relevance

/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
Dg84.c214 nv_wo32(base->ramfc, 0x08, lower_32_bits(args->v0.offset)); in g84_fifo_chan_ctor_dma()
215 nv_wo32(base->ramfc, 0x0c, upper_32_bits(args->v0.offset)); in g84_fifo_chan_ctor_dma()
216 nv_wo32(base->ramfc, 0x10, lower_32_bits(args->v0.offset)); in g84_fifo_chan_ctor_dma()
217 nv_wo32(base->ramfc, 0x14, upper_32_bits(args->v0.offset)); in g84_fifo_chan_ctor_dma()
218 nv_wo32(base->ramfc, 0x3c, 0x003f6078); in g84_fifo_chan_ctor_dma()
219 nv_wo32(base->ramfc, 0x44, 0x01003fff); in g84_fifo_chan_ctor_dma()
220 nv_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4); in g84_fifo_chan_ctor_dma()
221 nv_wo32(base->ramfc, 0x4c, 0xffffffff); in g84_fifo_chan_ctor_dma()
222 nv_wo32(base->ramfc, 0x60, 0x7fffffff); in g84_fifo_chan_ctor_dma()
223 nv_wo32(base->ramfc, 0x78, 0x00000000); in g84_fifo_chan_ctor_dma()
[all …]
Dnv40.c133 nv_wo32(priv->ramfc, chan->ramfc + ctx, nv_engctx(engctx)->addr); in nv40_fifo_context_attach()
169 nv_wo32(priv->ramfc, chan->ramfc + ctx, 0x00000000); in nv40_fifo_context_detach()
212 chan->ramfc = chan->base.chid * 128; in nv40_fifo_chan_ctor()
214 nv_wo32(priv->ramfc, chan->ramfc + 0x00, args->v0.offset); in nv40_fifo_chan_ctor()
215 nv_wo32(priv->ramfc, chan->ramfc + 0x04, args->v0.offset); in nv40_fifo_chan_ctor()
216 nv_wo32(priv->ramfc, chan->ramfc + 0x0c, chan->base.pushgpu->addr >> 4); in nv40_fifo_chan_ctor()
217 nv_wo32(priv->ramfc, chan->ramfc + 0x18, 0x30000000 | in nv40_fifo_chan_ctor()
224 nv_wo32(priv->ramfc, chan->ramfc + 0x3c, 0x0001ffff); in nv40_fifo_chan_ctor()
283 nvkm_gpuobj_ref(imem->ramfc, &priv->ramfc); in nv40_fifo_ctor()
331 priv->ramfc->addr) >> 16) | in nv40_fifo_init()
Dnv10.c87 chan->ramfc = chan->base.chid * 32; in nv10_fifo_chan_ctor()
89 nv_wo32(priv->ramfc, chan->ramfc + 0x00, args->v0.offset); in nv10_fifo_chan_ctor()
90 nv_wo32(priv->ramfc, chan->ramfc + 0x04, args->v0.offset); in nv10_fifo_chan_ctor()
91 nv_wo32(priv->ramfc, chan->ramfc + 0x0c, chan->base.pushgpu->addr >> 4); in nv10_fifo_chan_ctor()
92 nv_wo32(priv->ramfc, chan->ramfc + 0x14, in nv10_fifo_chan_ctor()
157 nvkm_gpuobj_ref(imem->ramfc, &priv->ramfc); in nv10_fifo_ctor()
Dnv17.c94 chan->ramfc = chan->base.chid * 64; in nv17_fifo_chan_ctor()
96 nv_wo32(priv->ramfc, chan->ramfc + 0x00, args->v0.offset); in nv17_fifo_chan_ctor()
97 nv_wo32(priv->ramfc, chan->ramfc + 0x04, args->v0.offset); in nv17_fifo_chan_ctor()
98 nv_wo32(priv->ramfc, chan->ramfc + 0x0c, chan->base.pushgpu->addr >> 4); in nv17_fifo_chan_ctor()
99 nv_wo32(priv->ramfc, chan->ramfc + 0x14, in nv17_fifo_chan_ctor()
164 nvkm_gpuobj_ref(imem->ramfc, &priv->ramfc); in nv17_fifo_ctor()
193 nv_wr32(priv, NV03_PFIFO_RAMFC, priv->ramfc->addr >> 8 | 0x00010000); in nv17_fifo_init()
Dnv50.c231 nv_wo32(base->ramfc, 0x08, lower_32_bits(args->v0.offset)); in nv50_fifo_chan_ctor_dma()
232 nv_wo32(base->ramfc, 0x0c, upper_32_bits(args->v0.offset)); in nv50_fifo_chan_ctor_dma()
233 nv_wo32(base->ramfc, 0x10, lower_32_bits(args->v0.offset)); in nv50_fifo_chan_ctor_dma()
234 nv_wo32(base->ramfc, 0x14, upper_32_bits(args->v0.offset)); in nv50_fifo_chan_ctor_dma()
235 nv_wo32(base->ramfc, 0x3c, 0x003f6078); in nv50_fifo_chan_ctor_dma()
236 nv_wo32(base->ramfc, 0x44, 0x01003fff); in nv50_fifo_chan_ctor_dma()
237 nv_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4); in nv50_fifo_chan_ctor_dma()
238 nv_wo32(base->ramfc, 0x4c, 0xffffffff); in nv50_fifo_chan_ctor_dma()
239 nv_wo32(base->ramfc, 0x60, 0x7fffffff); in nv50_fifo_chan_ctor_dma()
240 nv_wo32(base->ramfc, 0x78, 0x00000000); in nv50_fifo_chan_ctor_dma()
[all …]
Dnv04.c144 chan->ramfc = chan->base.chid * 32; in nv04_fifo_chan_ctor()
146 nv_wo32(priv->ramfc, chan->ramfc + 0x00, args->v0.offset); in nv04_fifo_chan_ctor()
147 nv_wo32(priv->ramfc, chan->ramfc + 0x04, args->v0.offset); in nv04_fifo_chan_ctor()
148 nv_wo32(priv->ramfc, chan->ramfc + 0x08, chan->base.pushgpu->addr >> 4); in nv04_fifo_chan_ctor()
149 nv_wo32(priv->ramfc, chan->ramfc + 0x10, in nv04_fifo_chan_ctor()
167 nv_wo32(priv->ramfc, chan->ramfc + c->ctxp, 0x00000000); in nv04_fifo_chan_dtor()
197 struct nvkm_gpuobj *fctx = priv->ramfc; in nv04_fifo_chan_fini()
200 u32 data = chan->ramfc; in nv04_fifo_chan_fini()
574 nvkm_gpuobj_ref(imem->ramfc, &priv->ramfc); in nv04_fifo_ctor()
590 nvkm_gpuobj_ref(NULL, &priv->ramfc); in nv04_fifo_dtor()
[all …]
Dnv04.h147 struct nvkm_gpuobj *ramfc; member
157 u32 ramfc; member
Dnv50.h13 struct nvkm_gpuobj *ramfc; member
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/
Dnv04.h18 struct nvkm_gpuobj *ramfc; member
Dnv04.c125 nvkm_gpuobj_ref(NULL, &priv->ramfc); in nv04_instmem_dtor()
168 NVOBJ_FLAG_ZERO_ALLOC, &priv->ramfc); in nv04_instmem_ctor()
Dnv40.c117 NVOBJ_FLAG_ZERO_ALLOC, &priv->ramfc); in nv40_instmem_ctor()