231 	nv_wo32(base->ramfc, 0x08, lower_32_bits(args->v0.offset));  in nv50_fifo_chan_ctor_dma()
232 	nv_wo32(base->ramfc, 0x0c, upper_32_bits(args->v0.offset));  in nv50_fifo_chan_ctor_dma()
233 	nv_wo32(base->ramfc, 0x10, lower_32_bits(args->v0.offset));  in nv50_fifo_chan_ctor_dma()
234 	nv_wo32(base->ramfc, 0x14, upper_32_bits(args->v0.offset));  in nv50_fifo_chan_ctor_dma()
235 	nv_wo32(base->ramfc, 0x3c, 0x003f6078);  in nv50_fifo_chan_ctor_dma()
236 	nv_wo32(base->ramfc, 0x44, 0x01003fff);  in nv50_fifo_chan_ctor_dma()
237 	nv_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4);  in nv50_fifo_chan_ctor_dma()
238 	nv_wo32(base->ramfc, 0x4c, 0xffffffff);  in nv50_fifo_chan_ctor_dma()
239 	nv_wo32(base->ramfc, 0x60, 0x7fffffff);  in nv50_fifo_chan_ctor_dma()
240 	nv_wo32(base->ramfc, 0x78, 0x00000000);  in nv50_fifo_chan_ctor_dma()
241 	nv_wo32(base->ramfc, 0x7c, 0x30000001);  in nv50_fifo_chan_ctor_dma()
242 	nv_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |  in nv50_fifo_chan_ctor_dma()
297 	nv_wo32(base->ramfc, 0x3c, 0x403f6078);  in nv50_fifo_chan_ctor_ind()
298 	nv_wo32(base->ramfc, 0x44, 0x01003fff);  in nv50_fifo_chan_ctor_ind()
299 	nv_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4);  in nv50_fifo_chan_ctor_ind()
300 	nv_wo32(base->ramfc, 0x50, lower_32_bits(ioffset));  in nv50_fifo_chan_ctor_ind()
301 	nv_wo32(base->ramfc, 0x54, upper_32_bits(ioffset) | (ilength << 16));  in nv50_fifo_chan_ctor_ind()
302 	nv_wo32(base->ramfc, 0x60, 0x7fffffff);  in nv50_fifo_chan_ctor_ind()
303 	nv_wo32(base->ramfc, 0x78, 0x00000000);  in nv50_fifo_chan_ctor_ind()
304 	nv_wo32(base->ramfc, 0x7c, 0x30000001);  in nv50_fifo_chan_ctor_ind()
305 	nv_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |  in nv50_fifo_chan_ctor_ind()
326 	struct nvkm_gpuobj *ramfc = base->ramfc;  in nv50_fifo_chan_init()  local
334 	nv_wr32(priv, 0x002600 + (chid * 4), 0x80000000 | ramfc->addr >> 12);  in nv50_fifo_chan_init()
404 			      0x1000, NVOBJ_FLAG_ZERO_ALLOC, &base->ramfc);  in nv50_fifo_context_ctor()
432 	nvkm_gpuobj_ref(NULL, &base->ramfc);  in nv50_fifo_context_dtor()