214 	nv_wo32(base->ramfc, 0x08, lower_32_bits(args->v0.offset));  in g84_fifo_chan_ctor_dma()
215 	nv_wo32(base->ramfc, 0x0c, upper_32_bits(args->v0.offset));  in g84_fifo_chan_ctor_dma()
216 	nv_wo32(base->ramfc, 0x10, lower_32_bits(args->v0.offset));  in g84_fifo_chan_ctor_dma()
217 	nv_wo32(base->ramfc, 0x14, upper_32_bits(args->v0.offset));  in g84_fifo_chan_ctor_dma()
218 	nv_wo32(base->ramfc, 0x3c, 0x003f6078);  in g84_fifo_chan_ctor_dma()
219 	nv_wo32(base->ramfc, 0x44, 0x01003fff);  in g84_fifo_chan_ctor_dma()
220 	nv_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4);  in g84_fifo_chan_ctor_dma()
221 	nv_wo32(base->ramfc, 0x4c, 0xffffffff);  in g84_fifo_chan_ctor_dma()
222 	nv_wo32(base->ramfc, 0x60, 0x7fffffff);  in g84_fifo_chan_ctor_dma()
223 	nv_wo32(base->ramfc, 0x78, 0x00000000);  in g84_fifo_chan_ctor_dma()
224 	nv_wo32(base->ramfc, 0x7c, 0x30000001);  in g84_fifo_chan_ctor_dma()
225 	nv_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |  in g84_fifo_chan_ctor_dma()
228 	nv_wo32(base->ramfc, 0x88, base->cache->addr >> 10);  in g84_fifo_chan_ctor_dma()
229 	nv_wo32(base->ramfc, 0x98, nv_gpuobj(base)->addr >> 12);  in g84_fifo_chan_ctor_dma()
292 	nv_wo32(base->ramfc, 0x3c, 0x403f6078);  in g84_fifo_chan_ctor_ind()
293 	nv_wo32(base->ramfc, 0x44, 0x01003fff);  in g84_fifo_chan_ctor_ind()
294 	nv_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4);  in g84_fifo_chan_ctor_ind()
295 	nv_wo32(base->ramfc, 0x50, lower_32_bits(ioffset));  in g84_fifo_chan_ctor_ind()
296 	nv_wo32(base->ramfc, 0x54, upper_32_bits(ioffset) | (ilength << 16));  in g84_fifo_chan_ctor_ind()
297 	nv_wo32(base->ramfc, 0x60, 0x7fffffff);  in g84_fifo_chan_ctor_ind()
298 	nv_wo32(base->ramfc, 0x78, 0x00000000);  in g84_fifo_chan_ctor_ind()
299 	nv_wo32(base->ramfc, 0x7c, 0x30000001);  in g84_fifo_chan_ctor_ind()
300 	nv_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |  in g84_fifo_chan_ctor_ind()
303 	nv_wo32(base->ramfc, 0x88, base->cache->addr >> 10);  in g84_fifo_chan_ctor_ind()
304 	nv_wo32(base->ramfc, 0x98, nv_gpuobj(base)->addr >> 12);  in g84_fifo_chan_ctor_ind()
315 	struct nvkm_gpuobj *ramfc = base->ramfc;  in g84_fifo_chan_init()  local
323 	nv_wr32(priv, 0x002600 + (chid * 4), 0x80000000 | ramfc->addr >> 8);  in g84_fifo_chan_init()
397 			      0x100, NVOBJ_FLAG_ZERO_ALLOC, &base->ramfc);  in g84_fifo_context_ctor()