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Searched refs:pll_clk (Results 1 – 31 of 31) sorted by relevance

/linux-4.1.27/drivers/clk/socfpga/
Dclk-pll.c89 struct socfpga_pll *pll_clk; in __socfpga_pll_init() local
99 pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL); in __socfpga_pll_init()
100 if (WARN_ON(!pll_clk)) in __socfpga_pll_init()
106 pll_clk->hw.reg = clk_mgr_base_addr + reg; in __socfpga_pll_init()
120 pll_clk->hw.hw.init = &init; in __socfpga_pll_init()
122 pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA; in __socfpga_pll_init()
126 clk = clk_register(NULL, &pll_clk->hw.hw); in __socfpga_pll_init()
128 kfree(pll_clk); in __socfpga_pll_init()
/linux-4.1.27/arch/sh/kernel/cpu/sh2a/
Dclock-sh7269.c50 static struct clk pll_clk = { variable
67 .parent = &pll_clk,
82 .parent = &pll_clk,
89 &pll_clk,
109 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
145 CLKDEV_CON_ID("pll_clk", &pll_clk),
Dclock-sh7264.c54 static struct clk pll_clk = { variable
63 &pll_clk,
81 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
111 CLKDEV_CON_ID("pll_clk", &pll_clk),
/linux-4.1.27/arch/sh/kernel/cpu/sh4a/
Dclock-sh7722.c94 static struct clk pll_clk = { variable
103 &pll_clk,
121 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
150 [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
186 CLKDEV_CON_ID("pll_clk", &pll_clk),
238 pll_clk.parent = &dll_clk; in arch_clk_init()
240 pll_clk.parent = &extal_clk; in arch_clk_init()
Dclock-sh7366.c91 static struct clk pll_clk = { variable
100 &pll_clk,
121 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
137 [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
200 CLKDEV_CON_ID("pll_clk", &pll_clk),
263 pll_clk.parent = &dll_clk; in arch_clk_init()
265 pll_clk.parent = &extal_clk; in arch_clk_init()
Dclock-sh7757.c40 static struct clk pll_clk = { variable
48 &pll_clk,
66 SH_CLK_DIV4(&pll_clk, FRQCR, _bit, _mask, _flags)
108 CLKDEV_CON_ID("pll_clk", &pll_clk),
Dclock-shx3.c39 static struct clk pll_clk = { variable
47 &pll_clk,
65 SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)
106 CLKDEV_CON_ID("pll_clk", &pll_clk),
Dclock-sh7723.c95 static struct clk pll_clk = { variable
104 &pll_clk,
124 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
150 [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
211 CLKDEV_CON_ID("pll_clk", &pll_clk),
286 pll_clk.parent = &dll_clk; in arch_clk_init()
288 pll_clk.parent = &extal_clk; in arch_clk_init()
Dclock-sh7343.c88 static struct clk pll_clk = { variable
97 &pll_clk,
118 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
134 [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
202 CLKDEV_CON_ID("pll_clk", &pll_clk),
270 pll_clk.parent = &dll_clk; in arch_clk_init()
272 pll_clk.parent = &extal_clk; in arch_clk_init()
Dclock-sh7785.c43 static struct clk pll_clk = { variable
51 &pll_clk,
70 SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)
122 CLKDEV_CON_ID("pll_clk", &pll_clk),
Dclock-sh7724.c97 static struct clk pll_clk = { variable
114 .parent = &pll_clk,
131 &pll_clk,
163 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
276 CLKDEV_CON_ID("pll_clk", &pll_clk),
360 pll_clk.parent = &fll_clk; in arch_clk_init()
362 pll_clk.parent = &extal_clk; in arch_clk_init()
Dclock-sh7786.c45 static struct clk pll_clk = { variable
53 &pll_clk,
71 SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)
131 CLKDEV_CON_ID("pll_clk", &pll_clk),
Dclock-sh7734.c45 static struct clk pll_clk = { variable
53 &pll_clk,
73 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
184 CLKDEV_CON_ID("pll_clk", &pll_clk),
/linux-4.1.27/drivers/clk/
Dclk-moxart.c59 struct clk *clk, *pll_clk; in moxart_of_apb_clk_init() local
81 pll_clk = of_clk_get(node, 0); in moxart_of_apb_clk_init()
82 if (IS_ERR(pll_clk)) { in moxart_of_apb_clk_init()
Dclk-vt8500.c654 struct clk_pll *pll_clk; in vtwm_pll_clk_init() local
667 pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL); in vtwm_pll_clk_init()
668 if (WARN_ON(!pll_clk)) in vtwm_pll_clk_init()
671 pll_clk->reg = pmc_base + reg; in vtwm_pll_clk_init()
672 pll_clk->lock = &_lock; in vtwm_pll_clk_init()
673 pll_clk->type = pll_type; in vtwm_pll_clk_init()
684 pll_clk->hw.init = &init; in vtwm_pll_clk_init()
686 clk = clk_register(NULL, &pll_clk->hw); in vtwm_pll_clk_init()
688 kfree(pll_clk); in vtwm_pll_clk_init()
Dclk-asm9260.c271 const char *ref_clk, *pll_clk = "pll"; in asm9260_acc_init() local
285 clk = clk_register_fixed_rate_with_accuracy(NULL, pll_clk, in asm9260_acc_init()
295 mc->parent_names[1] = pll_clk; in asm9260_acc_init()
/linux-4.1.27/drivers/clk/samsung/
Dclk-pll.c1159 struct samsung_pll_clock *pll_clk, in _samsung_clk_register_pll() argument
1170 __func__, pll_clk->name); in _samsung_clk_register_pll()
1174 init.name = pll_clk->name; in _samsung_clk_register_pll()
1175 init.flags = pll_clk->flags; in _samsung_clk_register_pll()
1176 init.parent_names = &pll_clk->parent_name; in _samsung_clk_register_pll()
1179 if (pll_clk->rate_table) { in _samsung_clk_register_pll()
1181 for (len = 0; pll_clk->rate_table[len].rate != 0; ) in _samsung_clk_register_pll()
1185 pll->rate_table = kmemdup(pll_clk->rate_table, in _samsung_clk_register_pll()
1191 __func__, pll_clk->name); in _samsung_clk_register_pll()
1194 switch (pll_clk->type) { in _samsung_clk_register_pll()
[all …]
/linux-4.1.27/drivers/clk/rockchip/
Dclk-pll.c342 struct clk *pll_clk, *mux_clk; in rockchip_clk_register_pll() local
415 pll_clk = clk_register(NULL, &pll->hw); in rockchip_clk_register_pll()
416 if (IS_ERR(pll_clk)) { in rockchip_clk_register_pll()
418 __func__, name, PTR_ERR(pll_clk)); in rockchip_clk_register_pll()
419 mux_clk = pll_clk; in rockchip_clk_register_pll()
441 clk_unregister(pll_clk); in rockchip_clk_register_pll()
/linux-4.1.27/drivers/clk/ti/
Dfapll.c495 struct clk *pll_clk) in ti_fapll_synth_setup() argument
519 synth->clk_pll = pll_clk; in ti_fapll_synth_setup()
535 struct clk *pll_clk; in ti_fapll_setup() local
590 pll_clk = clk_register(NULL, &fd->hw); in ti_fapll_setup()
591 if (IS_ERR(pll_clk)) in ti_fapll_setup()
594 fd->outputs.clks[0] = pll_clk; in ti_fapll_setup()
634 pll_clk); in ti_fapll_setup()
/linux-4.1.27/drivers/cpufreq/
Dls1x-cpufreq.c27 struct clk *pll_clk; /* PLL clk */ member
81 pll_freq = clk_get_rate(ls1x_cpufreq.pll_clk) / 1000; in ls1x_cpufreq_init()
175 ls1x_cpufreq.pll_clk = clk; in ls1x_cpufreq_probe()
/linux-4.1.27/Documentation/devicetree/bindings/video/
Dexynos_dsim.txt13 - clock-names: should include "bus_clk"and "pll_clk" entries
19 - samsung,pll-clock-frequency: specifies frequency of the "pll_clk" clock
51 clock-names = "bus_clk", "pll_clk";
/linux-4.1.27/sound/soc/codecs/
Dtas2552.c142 int sample_rate, pll_clk; in tas2552_hw_params() local
167 pll_clk = TAS2552_245MHZ_CLK; in tas2552_hw_params()
169 pll_clk = TAS2552_225MHZ_CLK; in tas2552_hw_params()
176 j = (pll_clk * 2 * (1 << p)) / tas2552->mclk; in tas2552_hw_params()
177 d = (pll_clk * 2 * (1 << p)) % tas2552->mclk; in tas2552_hw_params()
Dlm49453.c1205 u16 pll_clk = 0; in lm49453_set_dai_sysclk() local
1212 pll_clk = 0; in lm49453_set_dai_sysclk()
1217 pll_clk = BIT(4); in lm49453_set_dai_sysclk()
1223 snd_soc_update_bits(codec, LM49453_P0_PMC_SETUP_REG, BIT(4), pll_clk); in lm49453_set_dai_sysclk()
/linux-4.1.27/drivers/clk/spear/
Dclk-vco-pll.c279 spinlock_t *lock, struct clk **pll_clk, in clk_register_vco_pll() argument
350 if (pll_clk) in clk_register_vco_pll()
351 *pll_clk = tpll_clk; in clk_register_vco_pll()
Dclk.h127 spinlock_t *lock, struct clk **pll_clk,
/linux-4.1.27/arch/blackfin/mach-bf609/
Dclock.c285 static struct clk pll_clk = { variable
357 .parent = &pll_clk,
380 CLK(pll_clk, NULL, "PLLCLK"),
/linux-4.1.27/drivers/gpu/drm/exynos/
Dexynos_drm_dsi.c280 struct clk *pll_clk; member
434 clk_set_rate(dsi->pll_clk, dsi->pll_clk_rate); in exynos_dsi_set_pll()
436 fin = clk_get_rate(dsi->pll_clk); in exynos_dsi_set_pll()
1311 ret = clk_prepare_enable(dsi->pll_clk); in exynos_dsi_poweron()
1326 clk_disable_unprepare(dsi->pll_clk); in exynos_dsi_poweron()
1353 clk_disable_unprepare(dsi->pll_clk); in exynos_dsi_poweroff()
1716 dsi->pll_clk = devm_clk_get(dev, "pll_clk"); in exynos_dsi_probe()
1717 if (IS_ERR(dsi->pll_clk)) { in exynos_dsi_probe()
1719 ret = PTR_ERR(dsi->pll_clk); in exynos_dsi_probe()
/linux-4.1.27/arch/arm/boot/dts/
Dexynos3250.dtsi267 clock-names = "bus_clk", "pll_clk";
Dexynos4415.dtsi265 clock-names = "bus_clk", "pll_clk";
Dexynos4.dtsi170 clock-names = "bus_clk", "pll_clk";
Dexynos5420.dtsi555 clock-names = "bus_clk", "pll_clk";