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Searched refs:layers (Results 1 – 99 of 99) sorted by relevance

/linux-4.1.27/drivers/edac/
Dtile_edac.c128 struct edac_mc_layer layers[2]; in tile_edac_mc_probe() local
138 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in tile_edac_mc_probe()
139 layers[0].size = TILE_EDAC_NR_CSROWS; in tile_edac_mc_probe()
140 layers[0].is_virt_csrow = true; in tile_edac_mc_probe()
141 layers[1].type = EDAC_MC_LAYER_CHANNEL; in tile_edac_mc_probe()
142 layers[1].size = TILE_EDAC_NR_CHANS; in tile_edac_mc_probe()
143 layers[1].is_virt_csrow = false; in tile_edac_mc_probe()
144 mci = edac_mc_alloc(pdev->id, ARRAY_SIZE(layers), layers, in tile_edac_mc_probe()
Dpasemi_edac.c195 struct edac_mc_layer layers[2]; in pasemi_edac_probe() local
212 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in pasemi_edac_probe()
213 layers[0].size = PASEMI_EDAC_NR_CSROWS; in pasemi_edac_probe()
214 layers[0].is_virt_csrow = true; in pasemi_edac_probe()
215 layers[1].type = EDAC_MC_LAYER_CHANNEL; in pasemi_edac_probe()
216 layers[1].size = PASEMI_EDAC_NR_CHANS; in pasemi_edac_probe()
217 layers[1].is_virt_csrow = false; in pasemi_edac_probe()
218 mci = edac_mc_alloc(system_mmc_id++, ARRAY_SIZE(layers), layers, in pasemi_edac_probe()
Dhighbank_mc_edac.c160 struct edac_mc_layer layers[2]; in highbank_mc_probe() local
174 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in highbank_mc_probe()
175 layers[0].size = 1; in highbank_mc_probe()
176 layers[0].is_virt_csrow = true; in highbank_mc_probe()
177 layers[1].type = EDAC_MC_LAYER_CHANNEL; in highbank_mc_probe()
178 layers[1].size = 1; in highbank_mc_probe()
179 layers[1].is_virt_csrow = false; in highbank_mc_probe()
180 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, in highbank_mc_probe()
Damd76x_edac.c239 struct edac_mc_layer layers[2]; in amd76x_probe1() local
248 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in amd76x_probe1()
249 layers[0].size = AMD76X_NR_CSROWS; in amd76x_probe1()
250 layers[0].is_virt_csrow = true; in amd76x_probe1()
251 layers[1].type = EDAC_MC_LAYER_CHANNEL; in amd76x_probe1()
252 layers[1].size = 1; in amd76x_probe1()
253 layers[1].is_virt_csrow = false; in amd76x_probe1()
254 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0); in amd76x_probe1()
Dr82600_edac.c273 struct edac_mc_layer layers[2]; in r82600_probe1() local
287 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in r82600_probe1()
288 layers[0].size = R82600_NR_CSROWS; in r82600_probe1()
289 layers[0].is_virt_csrow = true; in r82600_probe1()
290 layers[1].type = EDAC_MC_LAYER_CHANNEL; in r82600_probe1()
291 layers[1].size = R82600_NR_CHANS; in r82600_probe1()
292 layers[1].is_virt_csrow = false; in r82600_probe1()
293 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0); in r82600_probe1()
Di82860_edac.c189 struct edac_mc_layer layers[2]; in i82860_probe1() local
202 layers[0].type = EDAC_MC_LAYER_CHANNEL; in i82860_probe1()
203 layers[0].size = 2; in i82860_probe1()
204 layers[0].is_virt_csrow = true; in i82860_probe1()
205 layers[1].type = EDAC_MC_LAYER_SLOT; in i82860_probe1()
206 layers[1].size = 8; in i82860_probe1()
207 layers[1].is_virt_csrow = true; in i82860_probe1()
208 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0); in i82860_probe1()
Dcell_edac.c172 struct edac_mc_layer layers[2]; in cell_edac_probe() local
202 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in cell_edac_probe()
203 layers[0].size = 1; in cell_edac_probe()
204 layers[0].is_virt_csrow = true; in cell_edac_probe()
205 layers[1].type = EDAC_MC_LAYER_CHANNEL; in cell_edac_probe()
206 layers[1].size = num_chans; in cell_edac_probe()
207 layers[1].is_virt_csrow = false; in cell_edac_probe()
208 mci = edac_mc_alloc(pdev->id, ARRAY_SIZE(layers), layers, in cell_edac_probe()
Daltera_edac.c256 struct edac_mc_layer layers[2]; in altr_sdram_probe() local
304 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in altr_sdram_probe()
305 layers[0].size = 1; in altr_sdram_probe()
306 layers[0].is_virt_csrow = true; in altr_sdram_probe()
307 layers[1].type = EDAC_MC_LAYER_CHANNEL; in altr_sdram_probe()
308 layers[1].size = 1; in altr_sdram_probe()
309 layers[1].is_virt_csrow = false; in altr_sdram_probe()
310 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, in altr_sdram_probe()
Die31200_edac.c333 struct edac_mc_layer layers[2]; in ie31200_probe1() local
347 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in ie31200_probe1()
348 layers[0].size = IE31200_DIMMS; in ie31200_probe1()
349 layers[0].is_virt_csrow = true; in ie31200_probe1()
350 layers[1].type = EDAC_MC_LAYER_CHANNEL; in ie31200_probe1()
351 layers[1].size = nr_channels; in ie31200_probe1()
352 layers[1].is_virt_csrow = false; in ie31200_probe1()
353 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, in ie31200_probe1()
414 dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, in ie31200_probe1()
424 dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, in ie31200_probe1()
Di3200_edac.c343 struct edac_mc_layer layers[2]; in i3200_probe1() local
358 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in i3200_probe1()
359 layers[0].size = I3200_DIMMS; in i3200_probe1()
360 layers[0].is_virt_csrow = true; in i3200_probe1()
361 layers[1].type = EDAC_MC_LAYER_CHANNEL; in i3200_probe1()
362 layers[1].size = nr_channels; in i3200_probe1()
363 layers[1].is_virt_csrow = false; in i3200_probe1()
364 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, in i3200_probe1()
398 struct dimm_info *dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, in i3200_probe1()
Di82443bxgx_edac.c237 struct edac_mc_layer layers[2]; in i82443bxgx_edacmc_probe1() local
251 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in i82443bxgx_edacmc_probe1()
252 layers[0].size = I82443BXGX_NR_CSROWS; in i82443bxgx_edacmc_probe1()
253 layers[0].is_virt_csrow = true; in i82443bxgx_edacmc_probe1()
254 layers[1].type = EDAC_MC_LAYER_CHANNEL; in i82443bxgx_edacmc_probe1()
255 layers[1].size = I82443BXGX_NR_CHANS; in i82443bxgx_edacmc_probe1()
256 layers[1].is_virt_csrow = false; in i82443bxgx_edacmc_probe1()
257 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0); in i82443bxgx_edacmc_probe1()
Dsynopsys_edac.c439 struct edac_mc_layer layers[2]; in synps_edac_mc_probe() local
455 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in synps_edac_mc_probe()
456 layers[0].size = SYNPS_EDAC_NR_CSROWS; in synps_edac_mc_probe()
457 layers[0].is_virt_csrow = true; in synps_edac_mc_probe()
458 layers[1].type = EDAC_MC_LAYER_CHANNEL; in synps_edac_mc_probe()
459 layers[1].size = SYNPS_EDAC_NR_CHANS; in synps_edac_mc_probe()
460 layers[1].is_virt_csrow = false; in synps_edac_mc_probe()
462 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, in synps_edac_mc_probe()
Dx38_edac.c325 struct edac_mc_layer layers[2]; in x38_probe1() local
341 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in x38_probe1()
342 layers[0].size = X38_RANKS; in x38_probe1()
343 layers[0].is_virt_csrow = true; in x38_probe1()
344 layers[1].type = EDAC_MC_LAYER_CHANNEL; in x38_probe1()
345 layers[1].size = x38_channel_num; in x38_probe1()
346 layers[1].is_virt_csrow = false; in x38_probe1()
347 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0); in x38_probe1()
Di3000_edac.c316 struct edac_mc_layer layers[2]; in i3000_probe1() local
359 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in i3000_probe1()
360 layers[0].size = I3000_RANKS / nr_channels; in i3000_probe1()
361 layers[0].is_virt_csrow = true; in i3000_probe1()
362 layers[1].type = EDAC_MC_LAYER_CHANNEL; in i3000_probe1()
363 layers[1].size = nr_channels; in i3000_probe1()
364 layers[1].is_virt_csrow = false; in i3000_probe1()
365 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0); in i3000_probe1()
Di82875p_edac.c393 struct edac_mc_layer layers[2]; in i82875p_probe1() local
408 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in i82875p_probe1()
409 layers[0].size = I82875P_NR_CSROWS(nr_chans); in i82875p_probe1()
410 layers[0].is_virt_csrow = true; in i82875p_probe1()
411 layers[1].type = EDAC_MC_LAYER_CHANNEL; in i82875p_probe1()
412 layers[1].size = nr_chans; in i82875p_probe1()
413 layers[1].is_virt_csrow = false; in i82875p_probe1()
414 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt)); in i82875p_probe1()
Docteon_edac-lmc.c228 struct edac_mc_layer layers[1]; in octeon_lmc_edac_probe() local
233 layers[0].type = EDAC_MC_LAYER_CHANNEL; in octeon_lmc_edac_probe()
234 layers[0].size = 1; in octeon_lmc_edac_probe()
235 layers[0].is_virt_csrow = false; in octeon_lmc_edac_probe()
246 mci = edac_mc_alloc(mc, ARRAY_SIZE(layers), layers, sizeof(struct octeon_lmc_pvt)); in octeon_lmc_edac_probe()
278 mci = edac_mc_alloc(mc, ARRAY_SIZE(layers), layers, sizeof(struct octeon_lmc_pvt)); in octeon_lmc_edac_probe()
Dedac_mc.c59 edac_layer_name[mci->layers[i].type], in edac_dimm_info_location()
263 struct edac_mc_layer *layers, in edac_mc_alloc() argument
285 tot_dimms *= layers[i].size; in edac_mc_alloc()
286 if (layers[i].is_virt_csrow) in edac_mc_alloc()
287 tot_csrows *= layers[i].size; in edac_mc_alloc()
289 tot_channels *= layers[i].size; in edac_mc_alloc()
291 if (layers[i].type == EDAC_MC_LAYER_CHIP_SELECT) in edac_mc_alloc()
303 count *= layers[i].size; in edac_mc_alloc()
339 mci->layers = layer; in edac_mc_alloc()
340 memcpy(mci->layers, layers, sizeof(*layer) * n_layers); in edac_mc_alloc()
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De7xxx_edac.c426 struct edac_mc_layer layers[2]; in e7xxx_probe1() local
445 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in e7xxx_probe1()
446 layers[0].size = E7XXX_NR_CSROWS; in e7xxx_probe1()
447 layers[0].is_virt_csrow = true; in e7xxx_probe1()
448 layers[1].type = EDAC_MC_LAYER_CHANNEL; in e7xxx_probe1()
449 layers[1].size = drc_chan + 1; in e7xxx_probe1()
450 layers[1].is_virt_csrow = false; in e7xxx_probe1()
451 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt)); in e7xxx_probe1()
Di82975x_edac.c476 struct edac_mc_layer layers[2]; in i82975x_probe1() local
545 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in i82975x_probe1()
546 layers[0].size = I82975X_NR_DIMMS; in i82975x_probe1()
547 layers[0].is_virt_csrow = true; in i82975x_probe1()
548 layers[1].type = EDAC_MC_LAYER_CHANNEL; in i82975x_probe1()
549 layers[1].size = I82975X_NR_CSROWS(chans); in i82975x_probe1()
550 layers[1].is_virt_csrow = false; in i82975x_probe1()
551 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt)); in i82975x_probe1()
Di7300_edac.c799 dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, in i7300_init_csrows()
1027 struct edac_mc_layer layers[3]; in i7300_init_one() local
1045 layers[0].type = EDAC_MC_LAYER_BRANCH; in i7300_init_one()
1046 layers[0].size = MAX_BRANCHES; in i7300_init_one()
1047 layers[0].is_virt_csrow = false; in i7300_init_one()
1048 layers[1].type = EDAC_MC_LAYER_CHANNEL; in i7300_init_one()
1049 layers[1].size = MAX_CH_PER_BRANCH; in i7300_init_one()
1050 layers[1].is_virt_csrow = true; in i7300_init_one()
1051 layers[2].type = EDAC_MC_LAYER_SLOT; in i7300_init_one()
1052 layers[2].size = MAX_SLOTS; in i7300_init_one()
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Di5400_edac.c1190 for (channel = 0; channel < mci->layers[0].size * mci->layers[1].size; in i5400_init_dimms()
1192 for (slot = 0; slot < mci->layers[2].size; slot++) { in i5400_init_dimms()
1199 dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, in i5400_init_dimms()
1265 struct edac_mc_layer layers[3]; in i5400_probe1() local
1283 layers[0].type = EDAC_MC_LAYER_BRANCH; in i5400_probe1()
1284 layers[0].size = MAX_BRANCHES; in i5400_probe1()
1285 layers[0].is_virt_csrow = false; in i5400_probe1()
1286 layers[1].type = EDAC_MC_LAYER_CHANNEL; in i5400_probe1()
1287 layers[1].size = CHANNELS_PER_BRANCH; in i5400_probe1()
1288 layers[1].is_virt_csrow = false; in i5400_probe1()
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Dghes_edac.c104 struct dimm_info *dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, in ghes_edac_dmidecode()
433 struct edac_mc_layer layers[1]; in ghes_edac_register() local
446 layers[0].type = EDAC_MC_LAYER_ALL_MEM; in ghes_edac_register()
447 layers[0].size = num_dimm; in ghes_edac_register()
448 layers[0].is_virt_csrow = true; in ghes_edac_register()
455 mci = edac_mc_alloc(ghes_edac_mc_num, ARRAY_SIZE(layers), layers, in ghes_edac_register()
509 struct dimm_info *dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, in ghes_edac_register()
Dppc4xx_edac.c1236 struct edac_mc_layer layers[2]; in ppc4xx_edac_probe() local
1282 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in ppc4xx_edac_probe()
1283 layers[0].size = ppc4xx_edac_nr_csrows; in ppc4xx_edac_probe()
1284 layers[0].is_virt_csrow = true; in ppc4xx_edac_probe()
1285 layers[1].type = EDAC_MC_LAYER_CHANNEL; in ppc4xx_edac_probe()
1286 layers[1].size = ppc4xx_edac_nr_chans; in ppc4xx_edac_probe()
1287 layers[1].is_virt_csrow = false; in ppc4xx_edac_probe()
1288 mci = edac_mc_alloc(ppc4xx_edac_instance, ARRAY_SIZE(layers), layers, in ppc4xx_edac_probe()
Di5000_edac.c1285 dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, in i5000_init_csrows()
1365 struct edac_mc_layer layers[3]; in i5000_probe1() local
1399 layers[0].type = EDAC_MC_LAYER_BRANCH; in i5000_probe1()
1400 layers[0].size = MAX_BRANCHES; in i5000_probe1()
1401 layers[0].is_virt_csrow = false; in i5000_probe1()
1402 layers[1].type = EDAC_MC_LAYER_CHANNEL; in i5000_probe1()
1403 layers[1].size = num_channels / MAX_BRANCHES; in i5000_probe1()
1404 layers[1].is_virt_csrow = false; in i5000_probe1()
1405 layers[2].type = EDAC_MC_LAYER_SLOT; in i5000_probe1()
1406 layers[2].size = num_dimms_per_channel; in i5000_probe1()
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Dmv64x60_edac.c703 struct edac_mc_layer layers[2]; in mv64x60_mc_err_probe() local
712 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in mv64x60_mc_err_probe()
713 layers[0].size = 1; in mv64x60_mc_err_probe()
714 layers[0].is_virt_csrow = true; in mv64x60_mc_err_probe()
715 layers[1].type = EDAC_MC_LAYER_CHANNEL; in mv64x60_mc_err_probe()
716 layers[1].size = 1; in mv64x60_mc_err_probe()
717 layers[1].is_virt_csrow = false; in mv64x60_mc_err_probe()
718 mci = edac_mc_alloc(edac_mc_idx, ARRAY_SIZE(layers), layers, in mv64x60_mc_err_probe()
Dcpc925_edac.c939 struct edac_mc_layer layers[2]; in cpc925_probe() local
977 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in cpc925_probe()
978 layers[0].size = CPC925_NR_CSROWS; in cpc925_probe()
979 layers[0].is_virt_csrow = true; in cpc925_probe()
980 layers[1].type = EDAC_MC_LAYER_CHANNEL; in cpc925_probe()
981 layers[1].size = nr_channels; in cpc925_probe()
982 layers[1].is_virt_csrow = false; in cpc925_probe()
983 mci = edac_mc_alloc(edac_mc_idx, ARRAY_SIZE(layers), layers, in cpc925_probe()
Di5100_edac.c863 dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, in i5100_init_csrows()
997 struct edac_mc_layer layers[2]; in i5100_init_one() local
1058 layers[0].type = EDAC_MC_LAYER_CHANNEL; in i5100_init_one()
1059 layers[0].size = 2; in i5100_init_one()
1060 layers[0].is_virt_csrow = false; in i5100_init_one()
1061 layers[1].type = EDAC_MC_LAYER_SLOT; in i5100_init_one()
1062 layers[1].size = ranksperch; in i5100_init_one()
1063 layers[1].is_virt_csrow = true; in i5100_init_one()
1064 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, in i5100_init_one()
De752x_edac.c1262 struct edac_mc_layer layers[2]; in e752x_probe1() local
1289 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in e752x_probe1()
1290 layers[0].size = E752X_NR_CSROWS; in e752x_probe1()
1291 layers[0].is_virt_csrow = true; in e752x_probe1()
1292 layers[1].type = EDAC_MC_LAYER_CHANNEL; in e752x_probe1()
1293 layers[1].size = drc_chan + 1; in e752x_probe1()
1294 layers[1].is_virt_csrow = false; in e752x_probe1()
1295 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt)); in e752x_probe1()
Dmpc85xx_edac.c1008 struct edac_mc_layer layers[2]; in mpc85xx_mc_err_probe() local
1017 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in mpc85xx_mc_err_probe()
1018 layers[0].size = 4; in mpc85xx_mc_err_probe()
1019 layers[0].is_virt_csrow = true; in mpc85xx_mc_err_probe()
1020 layers[1].type = EDAC_MC_LAYER_CHANNEL; in mpc85xx_mc_err_probe()
1021 layers[1].size = 1; in mpc85xx_mc_err_probe()
1022 layers[1].is_virt_csrow = false; in mpc85xx_mc_err_probe()
1023 mci = edac_mc_alloc(edac_mc_idx, ARRAY_SIZE(layers), layers, in mpc85xx_mc_err_probe()
Di7core_edac.c600 dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, in get_dimm_config()
2197 struct edac_mc_layer layers[2]; in i7core_register_mci() local
2201 layers[0].type = EDAC_MC_LAYER_CHANNEL; in i7core_register_mci()
2202 layers[0].size = NUM_CHANS; in i7core_register_mci()
2203 layers[0].is_virt_csrow = false; in i7core_register_mci()
2204 layers[1].type = EDAC_MC_LAYER_SLOT; in i7core_register_mci()
2205 layers[1].size = MAX_DIMMS; in i7core_register_mci()
2206 layers[1].is_virt_csrow = true; in i7core_register_mci()
2207 mci = edac_mc_alloc(i7core_dev->socket, ARRAY_SIZE(layers), layers, in i7core_register_mci()
Dsb_edac.c916 dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, in get_dimm_config()
2268 struct edac_mc_layer layers[2]; in sbridge_register_mci() local
2279 layers[0].type = EDAC_MC_LAYER_CHANNEL; in sbridge_register_mci()
2280 layers[0].size = NUM_CHANNELS; in sbridge_register_mci()
2281 layers[0].is_virt_csrow = false; in sbridge_register_mci()
2282 layers[1].type = EDAC_MC_LAYER_SLOT; in sbridge_register_mci()
2283 layers[1].size = MAX_DIMMS; in sbridge_register_mci()
2284 layers[1].is_virt_csrow = true; in sbridge_register_mci()
2285 mci = edac_mc_alloc(sbridge_dev->mc, ARRAY_SIZE(layers), layers, in sbridge_register_mci()
Dedac_mc_sysfs.c643 cnt *= mci->layers[i].size; in mci_reset_counters_store()
786 edac_layer_name[mci->layers[i].type], in mci_max_location_show()
787 mci->layers[i].size - 1); in mci_max_location_show()
938 edac_layer_name[mci->layers[i].type]); in edac_create_debug_nodes()
1034 edac_layer_name[mci->layers[lay].type], in edac_create_sysfs_mci_device()
Damd64_edac.c2771 struct edac_mc_layer layers[2]; in init_one_instance() local
2806 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; in init_one_instance()
2807 layers[0].size = pvt->csels[0].b_cnt; in init_one_instance()
2808 layers[0].is_virt_csrow = true; in init_one_instance()
2809 layers[1].type = EDAC_MC_LAYER_CHANNEL; in init_one_instance()
2816 layers[1].size = 2; in init_one_instance()
2817 layers[1].is_virt_csrow = false; in init_one_instance()
2819 mci = edac_mc_alloc(nid, ARRAY_SIZE(layers), layers, 0); in init_one_instance()
Dedac_core.h447 struct edac_mc_layer *layers,
/linux-4.1.27/lib/
Didr.c49 static int idr_max(int layers) in idr_max() argument
51 int bits = min_t(int, layers * IDR_BITS, MAX_IDR_SHIFT); in idr_max()
230 l = idp->layers; in sub_alloc()
245 if (id > idr_max(idp->layers)) { in sub_alloc()
294 int layers, v, id; in idr_get_empty_slot() local
300 layers = idp->layers; in idr_get_empty_slot()
305 layers = 1; in idr_get_empty_slot()
311 while (id > idr_max(layers)) { in idr_get_empty_slot()
312 layers++; in idr_get_empty_slot()
340 new->layer = layers-1; in idr_get_empty_slot()
[all …]
/linux-4.1.27/drivers/media/dvb-frontends/
Dtc90522.c210 int layers; in tc90522s_get_frontend() local
219 layers = 0; in tc90522s_get_frontend()
243 layers = (v > 0) ? 2 : 1; in tc90522s_get_frontend()
291 stats->len = layers; in tc90522s_get_frontend()
294 for (i = 0; i < layers; i++) in tc90522s_get_frontend()
297 for (i = 0; i < layers; i++) { in tc90522s_get_frontend()
305 stats->len = layers; in tc90522s_get_frontend()
307 for (i = 0; i < layers; i++) in tc90522s_get_frontend()
310 for (i = 0; i < layers; i++) { in tc90522s_get_frontend()
343 int layers; in tc90522t_get_frontend() local
[all …]
/linux-4.1.27/include/linux/
Dedac.h500 #define EDAC_DIMM_OFF(layers, nlayers, layer0, layer1, layer2) ({ \ argument
505 __i = (layer1) + ((layers[1]).size * (layer0)); \
507 __i = (layer2) + ((layers[2]).size * ((layer1) + \
508 ((layers[1]).size * (layer0)))); \
533 #define EDAC_DIMM_PTR(layers, var, nlayers, layer0, layer1, layer2) ({ \ argument
535 int ___i = EDAC_DIMM_OFF(layers, nlayers, layer0, layer1, layer2); \
716 struct edac_mc_layer *layers; member
Didr.h45 int layers; /* only valid w/o concurrent changes */ member
/linux-4.1.27/drivers/parisc/
Dpdc_stable.c372 for (i = 0; i < 6 && devpath->layers[i]; i++) in pdcspath_layer_read()
373 out += sprintf(out, "%u ", devpath->layers[i]); in pdcspath_layer_read()
395 unsigned int layers[6]; /* device-specific info (ctlr#, unit#, ...) */ in pdcspath_layer_write() local
408 memset(&layers, 0, sizeof(layers)); in pdcspath_layer_write()
413 layers[0] = simple_strtoul(in, NULL, 10); in pdcspath_layer_write()
414 DPRINTK("%s: layer[0]: %d\n", __func__, layers[0]); in pdcspath_layer_write()
420 layers[i] = simple_strtoul(temp, NULL, 10); in pdcspath_layer_write()
421 DPRINTK("%s: layer[%d]: %d\n", __func__, i, layers[i]); in pdcspath_layer_write()
429 memcpy(&entry->devpath.layers, &layers, sizeof(layers)); in pdcspath_layer_write()
/linux-4.1.27/drivers/gpu/drm/atmel-hlcdc/
Datmel_hlcdc_dc.h61 const struct atmel_hlcdc_layer_desc *layers; member
138 struct atmel_hlcdc_layer *layers[ATMEL_HLCDC_MAX_LAYERS]; member
Datmel_hlcdc_dc.c132 .layers = atmel_hlcdc_sama5d3_layers,
190 struct atmel_hlcdc_layer *layer = dc->layers[i]; in atmel_hlcdc_dc_irq_handler()
252 dc->layers[planes->primary->layer.desc->id] = in atmel_hlcdc_dc_modeset_init()
256 dc->layers[planes->cursor->layer.desc->id] = in atmel_hlcdc_dc_modeset_init()
260 dc->layers[planes->overlays[i]->layer.desc->id] = in atmel_hlcdc_dc_modeset_init()
438 if (dc->layers[i]) in atmel_hlcdc_dc_irq_postinstall()
Datmel_hlcdc_plane.c986 const struct atmel_hlcdc_layer_desc *descs = dc->desc->layers; in atmel_hlcdc_create_planes()
/linux-4.1.27/Documentation/scsi/
Dufs.txt48 UFS communication architecture consists of following layers,
63 layers. Device level configurations involve handling of query
70 the higher layers through Service Access Points. UTP defines 3
71 service access points for higher layers.
88 * UIO_SAP: To issue commands to Unipro layers.
Dscsi_eh.txt150 Note that this does not mean lower layers are quiescent. If a LLDD
151 completed a scmd with error status, the LLDD and lower layers are
153 has timed out, unless hostt->eh_timed_out() made lower layers forget
155 active as long as lower layers are concerned and completion could
201 lower layers and lower layers are ready to process or fail the scmd
366 that lower layers have forgotten about the scmd and we can
375 and STU doesn't make lower layers forget about those
377 if STU succeeds leaving lower layers in an inconsistent
429 On completion, the handler should have made lower layers forget about
471 - Know that timed out scmds are still active on lower layers. Make
[all …]
Dbnx2fc.txt7 automatically with the upper storage layers.
Dscsi_mid_low_api.txt35 The SCSI mid level isolates an LLD from other layers such as the SCSI
109 that are shared with the mid level and other layers.
215 upper layers with this sequence:
308 across the various SCSI layers which use them. Previously such instances
324 across the various SCSI layers which use them. Previously such instances
Dosst.txt116 Via the SCSI emulation layers usb-storage and ide-scsi, you can also use the
Dlibsas.txt348 upper layers (Command set drivers) and user space.
/linux-4.1.27/drivers/nfc/st21nfcb/
DKconfig7 NCI logic and hooks into the NFC kernel APIs. Physical layers will
/linux-4.1.27/drivers/nfc/st21nfca/
DKconfig8 HCI logic and hooks into the NFC kernel APIs. Physical layers will
/linux-4.1.27/Documentation/driver-model/
Doverview.txt39 Common data fields have been moved out of individual bus layers into a common
40 data structure. These fields must still be accessed by the bus layers,
43 Other bus layers are encouraged to do what has been done for the PCI layer.
/linux-4.1.27/Documentation/networking/caif/
DLinux-CAIF.txt73 to the called function (except for framing layers' receive function)
146 - All layers embed the same structure "struct cflayer"
164 receive of packets is handled as by the rest of the layers: the 'dn->transmit()'
/linux-4.1.27/drivers/nfc/nxp-nci/
DKconfig8 This is a driver based on the NCI NFC kernel layers and
/linux-4.1.27/drivers/char/tpm/st33zp24/
DKconfig6 TPM1.2 logic and hooks into the TPM kernel APIs. Physical layers will
/linux-4.1.27/drivers/nfc/pn544/
DKconfig8 This is a driver based on the HCI NFC kernel layers and
/linux-4.1.27/drivers/nfc/microread/
DKconfig9 the NFC kernel APIs. Physical layers will register against it.
/linux-4.1.27/drivers/staging/lustre/lustre/obdclass/
Dlu_object.c202 struct list_head *layers; in lu_object_alloc() local
222 layers = &top->lo_header->loh_layers; in lu_object_alloc()
231 list_for_each_entry(scan, layers, lo_linkage) { in lu_object_alloc()
247 list_for_each_entry_reverse(scan, layers, lo_linkage) { in lu_object_alloc()
269 struct list_head *layers; in lu_object_free() local
273 layers = &o->lo_header->loh_layers; in lu_object_free()
278 list_for_each_entry_reverse(scan, layers, lo_linkage) { in lu_object_free()
290 list_splice_init(layers, &splice); in lu_object_free()
/linux-4.1.27/arch/parisc/include/uapi/asm/
Dpdc.h354 unsigned int layers[6];/* device-specific layer-info */ member
/linux-4.1.27/Documentation/networking/
Dieee802154.txt8 two layers: Medium Access Control (MAC) and Physical (PHY). And there
9 are mainly two options available for upper layers:
Doperstates.txt81 however, if different layers of the driver manipulate the same flag,
Dip-sysctl.txt91 queued for each unresolved address by other network layers.
98 unresolved address by other network layers.
Dcan.txt133 disk or tape streamer device. Instead, you have abstraction layers
/linux-4.1.27/Documentation/ABI/testing/
Dsysfs-class-net-statistics7 This value might not be relevant with all MAC layers.
50 but dropped, that are not forwarded to the upper layers for
Dsysfs-class-mtd146 an error, 0 is returned. Higher layers (e.g., UBI) use this
Dsysfs-driver-hid-roccat-ryos153 layers.
/linux-4.1.27/arch/parisc/include/asm/
Dpdc.h189 unsigned int layers[6]; /* device-specific info (ctlr #, unit # ...) */ member
/linux-4.1.27/Documentation/video4linux/
DREADME.pvrusb226 This driver has a strong separation of layers. They are very
45 The most important shearing layer is between the top 2 layers. A
171 pvrusb2-ioread.[ch] - This module layers on top of pvrusb2-io.[ch]
DREADME.davinci-vpbe33 provides v4l2 device interface to manage VID0 and VID1 layers.
/linux-4.1.27/net/bluetooth/
DKconfig23 Linux Bluetooth subsystem consist of several layers:
/linux-4.1.27/drivers/staging/lustre/
DREADME.txt59 between the layers (or not).
/linux-4.1.27/Documentation/ABI/stable/
Dfirewire-cdev36 link layers, reception of inbound requests to such
/linux-4.1.27/Documentation/isdn/
DHiSax.cert26 These tests included all layers 1-3 and as well all functional tests for
/linux-4.1.27/Documentation/filesystems/
Doverlayfs.txt162 Multiple lower layers
165 Multiple lower layers can now be given using the the colon (":") as a
Dsysfs.txt306 The following interface layers currently exist in sysfs:
Dxfs-self-describing-metadata.txt183 error for the higher layers to catch.
/linux-4.1.27/arch/parisc/kernel/
Dfirmware.c1148 PAGE0->mem_cons.spa, __pa(PAGE0->mem_cons.dp.layers), in pdc_iodc_print()
1175 PAGE0->mem_kbd.spa, __pa(PAGE0->mem_kbd.dp.layers), in pdc_iodc_getc()
/linux-4.1.27/Documentation/development-process/
D4.Coding57 * Abstraction layers
60 abstraction layers in the name of flexibility and information hiding.
78 Abstraction layers which hide access to hardware - often to allow the bulk
80 frowned upon. Such layers obscure the code and may impose a performance
/linux-4.1.27/Documentation/nfc/
Dnfc-hci.txt136 layers such as an llc to store the frame for re-emission, this function must
266 must be reported such that upper layers don't stay ignorant that something
/linux-4.1.27/Documentation/device-mapper/
Dthin-provisioning.txt143 completion may have already been acknowledged to upper IO layers
145 (e.g. fsck) be performed on those layers when repair of the pool is
/linux-4.1.27/Documentation/block/
Dbiodoc.txt52 1.3 Direct access/bypass to lower layers for diagnostics and special
281 to the device bypassing some of the intermediate i/o layers.
285 multiple levels without having to pass through upper layers makes
399 passed around different types of subsystems or layers, maybe even
429 * main unit of I/O for the block layer and lower layers (ie drivers)
506 structure fields and a quick reference about the layers which are
886 I/O scheduler, a.k.a. elevator, is implemented in two layers. Generic dispatch
/linux-4.1.27/Documentation/spi/
Dspidev20 they need to access kernel interfaces (such as IRQ handlers or other layers
Dspi-summary423 clean (and small, and "optional") layers over spi_async().
/linux-4.1.27/Documentation/fb/
Dviafb.txt168 multi-head since SAMM support multi monitor at driver layers, thus fbcon
/linux-4.1.27/Documentation/devicetree/bindings/arm/
Dtopology.txt105 per cluster. A system can contain several layers of
/linux-4.1.27/Documentation/usb/
DWUSB-Design-overview.txt258 higher layers will enable the higher layers to use the reservations upon
/linux-4.1.27/Documentation/wimax/
DREADME.i2400m101 abstraction layers are used, so to port to another OS, the Linux kernel
/linux-4.1.27/Documentation/timers/
Dtimekeeping.txt46 are various quirks and layers in the timekeeping code for e.g. synchronizing
Dhighres.txt148 clock source and the clock event device layers provide notification functions
/linux-4.1.27/Documentation/
DChanges229 enable it to operate over diverse media layers. If you use PPP,
DHOWTO122 - Subsystem shim-layers (for compatibility?)
DSubmittingPatches412 layers of maintainers, we've introduced a "sign-off" procedure on
Dkernel-parameters.txt212 debug layers and levels.
/linux-4.1.27/Documentation/hid/
Dhid-transport.txt17 and quirks are handled by all layers depending on the quirk.
/linux-4.1.27/Documentation/powerpc/
Deeh-pci-error-recovery.txt99 slots. In principle, layers far above the device driver probably
/linux-4.1.27/Documentation/ioctl/
Dcdrom.txt880 EINVAL physical.layer_num exceeds number of layers
/linux-4.1.27/Documentation/rapidio/
Drapidio.txt84 one or more common service layers for all participating RapidIO devices. These
/linux-4.1.27/Documentation/PCI/
Dpci-error-recovery.txt361 higher layers. The device driver should then clean up all of its
/linux-4.1.27/Documentation/filesystems/caching/
Dnetfs-api.txt114 function is recursive. Too many layers will run the kernel out of stack.
/linux-4.1.27/
DCREDITS540 D: gadget layers, SPI subsystem, GPIO subsystem, and more than a few