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Searched refs:icache (Results 1 – 52 of 52) sorted by relevance

/linux-4.1.27/arch/mips/mm/
Dc-octeon.c197 c->icache.linesz = 2 << ((config1 >> 19) & 7); in probe_octeon()
198 c->icache.sets = 64 << ((config1 >> 22) & 7); in probe_octeon()
199 c->icache.ways = 1 + ((config1 >> 16) & 7); in probe_octeon()
200 c->icache.flags |= MIPS_CACHE_VTAG; in probe_octeon()
202 c->icache.sets * c->icache.ways * c->icache.linesz; in probe_octeon()
203 c->icache.waybit = ffs(icache_size / c->icache.ways) - 1; in probe_octeon()
217 c->icache.linesz = 2 << ((config1 >> 19) & 7); in probe_octeon()
218 c->icache.sets = 8; in probe_octeon()
219 c->icache.ways = 37; in probe_octeon()
220 c->icache.flags |= MIPS_CACHE_VTAG; in probe_octeon()
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Dc-r4k.c231 unsigned long end = start + current_cpu_data.icache.waysize; in tx49_blast_icache32()
232 unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; in tx49_blast_icache32()
233 unsigned long ws_end = current_cpu_data.icache.ways << in tx49_blast_icache32()
234 current_cpu_data.icache.waybit; in tx49_blast_icache32()
260 unsigned long indexmask = current_cpu_data.icache.waysize - 1; in tx49_blast_icache32_page_indexed()
263 unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; in tx49_blast_icache32_page_indexed()
264 unsigned long ws_end = current_cpu_data.icache.ways << in tx49_blast_icache32_page_indexed()
265 current_cpu_data.icache.waybit; in tx49_blast_icache32_page_indexed()
966 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); in probe_pcache()
967 c->icache.ways = 2; in probe_pcache()
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Dc-tx39.c296 unsigned long ic_lsize = current_cpu_data.icache.linesz; in tx39_flush_cache_sigtramp()
324 current_cpu_data.icache.linesz = 16; in tx39_probe_cache()
327 current_cpu_data.icache.ways = 1; in tx39_probe_cache()
333 current_cpu_data.icache.ways = 2; in tx39_probe_cache()
340 current_cpu_data.icache.ways = 1; in tx39_probe_cache()
418 current_cpu_data.icache.waysize = icache_size / current_cpu_data.icache.ways; in tx39_cache_init()
421 current_cpu_data.icache.sets = in tx39_cache_init()
422 current_cpu_data.icache.waysize / current_cpu_data.icache.linesz; in tx39_cache_init()
429 current_cpu_data.icache.waybit = 0; in tx39_cache_init()
433 icache_size >> 10, current_cpu_data.icache.linesz); in tx39_cache_init()
/linux-4.1.27/arch/sh/kernel/cpu/sh5/
Dprobe.c42 boot_cpu_data.icache.ways = 4; in cpu_probe()
43 boot_cpu_data.icache.sets = 256; in cpu_probe()
44 boot_cpu_data.icache.linesz = L1_CACHE_BYTES; in cpu_probe()
45 boot_cpu_data.icache.way_incr = (1 << 13); in cpu_probe()
46 boot_cpu_data.icache.entry_shift = 5; in cpu_probe()
47 boot_cpu_data.icache.way_size = boot_cpu_data.icache.sets * in cpu_probe()
48 boot_cpu_data.icache.linesz; in cpu_probe()
49 boot_cpu_data.icache.entry_mask = 0x1fe0; in cpu_probe()
50 boot_cpu_data.icache.flags = 0; in cpu_probe()
62 boot_cpu_data.dcache = boot_cpu_data.icache; in cpu_probe()
/linux-4.1.27/arch/sh/kernel/cpu/sh4/
Dprobe.c38 boot_cpu_data.icache.way_incr = (1 << 13); in cpu_probe()
39 boot_cpu_data.icache.entry_shift = 5; in cpu_probe()
40 boot_cpu_data.icache.sets = 256; in cpu_probe()
41 boot_cpu_data.icache.ways = 1; in cpu_probe()
42 boot_cpu_data.icache.linesz = L1_CACHE_BYTES; in cpu_probe()
70 boot_cpu_data.icache.ways = 4; in cpu_probe()
174 boot_cpu_data.icache.ways = 2; in cpu_probe()
179 boot_cpu_data.icache.ways = 2; in cpu_probe()
195 boot_cpu_data.icache.ways = 2; in cpu_probe()
205 if (boot_cpu_data.icache.ways > 1) { in cpu_probe()
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/linux-4.1.27/arch/sh/kernel/cpu/
Dinit.c212 l1i_cache_shape = CACHE_DESC_SHAPE(current_cpu_data.icache); in detect_cache_shape()
309 current_cpu_data.icache.entry_mask = current_cpu_data.icache.way_incr - in cpu_init()
310 current_cpu_data.icache.linesz; in cpu_init()
312 current_cpu_data.icache.way_size = current_cpu_data.icache.sets * in cpu_init()
313 current_cpu_data.icache.linesz; in cpu_init()
Dproc.c110 if (c->icache.flags & SH_CACHE_COMBINED) { in show_cpuinfo()
112 show_cacheinfo(m, "cache", c->icache); in show_cpuinfo()
115 show_cacheinfo(m, "icache", c->icache); in show_cpuinfo()
/linux-4.1.27/arch/mips/include/asm/
Dr4kcache.h612 __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, )
615 __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, )
616 __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I_Loongson2, 32, loongson2_)
619 __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, )
622 __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 128, )
650 __BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16)
653 __BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32)
656 __BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
682 __BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, )
716 __BUILD_PROT_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I)
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Dcpu-features.h147 #define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
153 #define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC)
175 #define cpu_icache_snoops_remote_store (cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE)
379 #define cpu_icache_line_size() cpu_data[0].icache.linesz
Dcpu-info.h61 struct cache_desc icache; /* Primary I-cache */ member
/linux-4.1.27/arch/mn10300/mm/
DKconfig.cache44 The icache and dcache are disabled.
95 Set if we need the dcache flushing before the icache is invalidated.
100 Set if we need the icache to be invalidated, even if the dcache is in
113 icache using the cache tag registers to make breakpoints work.
122 icache using automatic purge registers to make breakpoints work.
130 Set if the debugger needs to invalidate the icache using the cache
139 Set if the debugger needs to invalidate the icache using automatic
147 invalidate the icache to make breakpoints work.
Dcache-dbg-flush-by-tag.S26 # Flush the entire data cache back to RAM and invalidate the icache
81 # Invalidate one particular cacheline if it's in the icache
109 # now go and do the icache
Dcache-dbg-inv.S28 # Invalidate the entire icache
36 # we only need to invalidate the icache in this cache mode
Dcache-dbg-flush-by-reg.S25 # Flush the entire data cache back to RAM and invalidate the icache
74 # secondly, invalidate the icache if it is enabled
DMakefile9 cacheflush-$(CONFIG_MN10300_CACHE_INV_ICACHE) += cache-inv-icache.o
10 cacheflush-$(CONFIG_MN10300_CACHE_FLUSH_ICACHE) += cache-flush-icache.o
Dcache.inc20 # On some cores it is necessary to disable the icache whilst we do this.
35 # disable the icache
Dcache-inv-by-reg.S53 # Invalidate the entire icache
Dcache-inv-by-tag.S61 # Invalidate the entire icache
/linux-4.1.27/arch/avr32/kernel/
Dcpu.c283 boot_cpu_data.icache.ways = 1 << SYSREG_BFEXT(IASS, config1); in setup_processor()
284 boot_cpu_data.icache.sets = 1 << SYSREG_BFEXT(ISET, config1); in setup_processor()
285 boot_cpu_data.icache.linesz = 1 << (tmp + 1); in setup_processor()
341 icache_size = boot_cpu_data.icache.ways * in c_show()
342 boot_cpu_data.icache.sets * in c_show()
343 boot_cpu_data.icache.linesz; in c_show()
367 boot_cpu_data.icache.ways, in c_show()
368 boot_cpu_data.icache.sets, in c_show()
369 boot_cpu_data.icache.linesz); in c_show()
/linux-4.1.27/arch/sh/mm/
Dcache.c254 boot_cpu_data.icache.ways, in emit_cache_params()
255 boot_cpu_data.icache.sets, in emit_cache_params()
256 boot_cpu_data.icache.way_incr); in emit_cache_params()
258 boot_cpu_data.icache.entry_mask, in emit_cache_params()
259 boot_cpu_data.icache.alias_mask, in emit_cache_params()
260 boot_cpu_data.icache.n_aliases); in emit_cache_params()
293 compute_alias(&boot_cpu_data.icache); in cpu_cache_init()
Dcache-shx3.c27 if (boot_cpu_data.dcache.n_aliases || boot_cpu_data.icache.n_aliases) { in shx3_cache_init()
30 boot_cpu_data.icache.n_aliases = 0; in shx3_cache_init()
Dcache-sh4.c74 cpu_data->icache.entry_mask); in sh4_flush_icache_range()
77 n = boot_cpu_data.icache.n_aliases; in sh4_flush_icache_range()
78 for (i = 0; i < cpu_data->icache.ways; i++) { in sh4_flush_icache_range()
81 icacheaddr += cpu_data->icache.way_incr; in sh4_flush_icache_range()
Dcache-debugfs.c52 cache = &current_cpu_data.icache; in cache_seq_show()
/linux-4.1.27/arch/frv/lib/
Dcache.S40 # Invalidate a range of dcache and icache
61 # Invalidate a range of icache
81 # Write back and invalidate a range of dcache and icache
/linux-4.1.27/Documentation/devicetree/bindings/nios2/
Dnios2.txt18 - icache-line-size: Contains instruction line size.
20 - icache-size: Contains instruction cache size.
47 icache-line-size = <32>;
49 icache-size = <32768>;
/linux-4.1.27/arch/frv/kernel/
Dsleep.S84 # preload and lock into icache that code which may have to run
126 # - we want it to be be cacheline aligned so we can lock it into the icache easily
206 # locked in icache.
277 # unlock the icache which was locked before going to sleep
302 # Preload into icache.
363 # Unlock from icache
/linux-4.1.27/arch/sh/kernel/cpu/sh2/
Dprobe.c31 boot_cpu_data.icache = boot_cpu_data.dcache; in cpu_probe()
/linux-4.1.27/arch/powerpc/kernel/
Dcacheinfo.c366 struct cache *dcache, *icache; in cache_do_one_devnode_split() local
372 icache = new_cache(CACHE_TYPE_INSTRUCTION, level, node); in cache_do_one_devnode_split()
374 if (!dcache || !icache) in cache_do_one_devnode_split()
377 dcache->next_local = icache; in cache_do_one_devnode_split()
382 release_cache(icache); in cache_do_one_devnode_split()
/linux-4.1.27/arch/unicore32/boot/compressed/
Dhead.S92 mov r0, #0x1c @ en icache and wb dcache
145 movc p0.c5, r0, #20 @ icache invalidate all
/linux-4.1.27/arch/tile/include/uapi/arch/
DKbuild6 header-y += icache.h
/linux-4.1.27/arch/sh/kernel/cpu/sh2a/
Dprobe.c59 boot_cpu_data.icache = boot_cpu_data.dcache; in cpu_probe()
/linux-4.1.27/arch/arc/mm/
Dcache_arc700.c91 PR_CACHE(&cpuinfo_arc700[c].icache, CONFIG_ARC_HAS_ICACHE, "I-Cache"); in arc_cache_mumbojumbo()
114 p_ic = &cpuinfo_arc700[cpu].icache; in read_decode_cache_bcr()
159 struct cpuinfo_arc_cache *ic = &cpuinfo_arc700[cpu].icache; in arc_cache_init()
/linux-4.1.27/arch/microblaze/boot/dts/
Dsystem.dts70 xlnx,allow-icache-wr = <0x1>;
96 xlnx,icache-always-used = <0x1>;
97 xlnx,icache-line-len = <0x4>;
98 xlnx,icache-use-fsl = <0x1>;
126 xlnx,use-icache = <0x1>;
/linux-4.1.27/arch/nios2/boot/dts/
D3c120_devboard.dts40 icache-line-size = <32>;
42 icache-size = <32768>;
/linux-4.1.27/arch/mn10300/kernel/
Dsmp-low.S96 # Jump here after RTI to suppress the icache lookahead
/linux-4.1.27/arch/avr32/include/asm/
Dprocessor.h67 struct cache_info icache; member
/linux-4.1.27/arch/sh/kernel/cpu/sh3/
Dprobe.c108 boot_cpu_data.icache = boot_cpu_data.dcache; in cpu_probe()
/linux-4.1.27/arch/sh/include/asm/
Dprocessor.h81 struct cache_info icache; /* Primary I-cache */ member
/linux-4.1.27/arch/avr32/mm/
Dcache.c82 linesz = boot_cpu_data.icache.linesz; in invalidate_icache_region()
/linux-4.1.27/arch/arc/include/asm/
Darcregs.h318 struct cpuinfo_arc_cache icache, dcache; member
/linux-4.1.27/tools/perf/util/
Dparse-events.l211 L1-icache|l1-i|l1i|L1-instruction |
/linux-4.1.27/arch/mips/include/asm/octeon/
Dcvmx-mio-defs.h1864 uint64_t icache:24; member
1866 uint64_t icache:24;
1896 uint64_t icache:24; member
1898 uint64_t icache:24;
1919 uint64_t icache:24; member
1921 uint64_t icache:24;
1941 uint64_t icache:24; member
1943 uint64_t icache:24;
1961 uint64_t icache:24; member
1963 uint64_t icache:24;
/linux-4.1.27/arch/mips/kernel/
Dpm-cps.c460 cps_gen_cache_routine(&p, &l, &r, &cpu_data[cpu].icache, in cps_gen_entry_code()
Dtraps.c632 current_cpu_data.icache.linesz); in simulate_rdhwr()
/linux-4.1.27/arch/arm/mach-omap2/
Dsram243x.S249 mcrr p15, 1, r8, r4, c12 @ preload into icache
Dsram242x.S249 mcrr p15, 1, r8, r4, c12 @ preload into icache
/linux-4.1.27/arch/powerpc/platforms/44x/
DKconfig356 This option enables a work around for an icache bug on 476
/linux-4.1.27/Documentation/frv/
Dkernel-ABI.txt106 SCR2 MMU Save for EAR0 (destroyed by icache insns
/linux-4.1.27/arch/blackfin/
DKconfig896 bool "Locate icache flush funcs in L1 Inst Memory"
899 If enabled, the Blackfin icache flushing functions are linked
/linux-4.1.27/Documentation/
Dcachetlb.txt373 If the icache does not snoop stores then this routine will need
DCodingStyle754 icache footprint for the CPU and simply because there is less memory
/linux-4.1.27/arch/mips/kvm/
Demulate.c2359 current_cpu_data.icache.linesz); in kvm_mips_handle_ri()