1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1996 David S. Miller (davem@davemloft.net) 7 * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org) 8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 9 */ 10#include <linux/cpu_pm.h> 11#include <linux/hardirq.h> 12#include <linux/init.h> 13#include <linux/highmem.h> 14#include <linux/kernel.h> 15#include <linux/linkage.h> 16#include <linux/preempt.h> 17#include <linux/sched.h> 18#include <linux/smp.h> 19#include <linux/mm.h> 20#include <linux/module.h> 21#include <linux/bitops.h> 22 23#include <asm/bcache.h> 24#include <asm/bootinfo.h> 25#include <asm/cache.h> 26#include <asm/cacheops.h> 27#include <asm/cpu.h> 28#include <asm/cpu-features.h> 29#include <asm/cpu-type.h> 30#include <asm/io.h> 31#include <asm/page.h> 32#include <asm/pgtable.h> 33#include <asm/r4kcache.h> 34#include <asm/sections.h> 35#include <asm/mmu_context.h> 36#include <asm/war.h> 37#include <asm/cacheflush.h> /* for run_uncached() */ 38#include <asm/traps.h> 39#include <asm/dma-coherence.h> 40#include <asm/mips-cm.h> 41 42/* 43 * Special Variant of smp_call_function for use by cache functions: 44 * 45 * o No return value 46 * o collapses to normal function call on UP kernels 47 * o collapses to normal function call on systems with a single shared 48 * primary cache. 49 * o doesn't disable interrupts on the local CPU 50 */ 51static inline void r4k_on_each_cpu(void (*func) (void *info), void *info) 52{ 53 preempt_disable(); 54 55 /* 56 * The Coherent Manager propagates address-based cache ops to other 57 * cores but not index-based ops. However, r4k_on_each_cpu is used 58 * in both cases so there is no easy way to tell what kind of op is 59 * executed to the other cores. The best we can probably do is 60 * to restrict that call when a CM is not present because both 61 * CM-based SMP protocols (CMP & CPS) restrict index-based cache ops. 62 */ 63 if (!mips_cm_present()) 64 smp_call_function_many(&cpu_foreign_map, func, info, 1); 65 func(info); 66 preempt_enable(); 67} 68 69#if defined(CONFIG_MIPS_CMP) || defined(CONFIG_MIPS_CPS) 70#define cpu_has_safe_index_cacheops 0 71#else 72#define cpu_has_safe_index_cacheops 1 73#endif 74 75/* 76 * Must die. 77 */ 78static unsigned long icache_size __read_mostly; 79static unsigned long dcache_size __read_mostly; 80static unsigned long scache_size __read_mostly; 81 82/* 83 * Dummy cache handling routines for machines without boardcaches 84 */ 85static void cache_noop(void) {} 86 87static struct bcache_ops no_sc_ops = { 88 .bc_enable = (void *)cache_noop, 89 .bc_disable = (void *)cache_noop, 90 .bc_wback_inv = (void *)cache_noop, 91 .bc_inv = (void *)cache_noop 92}; 93 94struct bcache_ops *bcops = &no_sc_ops; 95 96#define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010) 97#define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020) 98 99#define R4600_HIT_CACHEOP_WAR_IMPL \ 100do { \ 101 if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) \ 102 *(volatile unsigned long *)CKSEG1; \ 103 if (R4600_V1_HIT_CACHEOP_WAR) \ 104 __asm__ __volatile__("nop;nop;nop;nop"); \ 105} while (0) 106 107static void (*r4k_blast_dcache_page)(unsigned long addr); 108 109static inline void r4k_blast_dcache_page_dc32(unsigned long addr) 110{ 111 R4600_HIT_CACHEOP_WAR_IMPL; 112 blast_dcache32_page(addr); 113} 114 115static inline void r4k_blast_dcache_page_dc64(unsigned long addr) 116{ 117 blast_dcache64_page(addr); 118} 119 120static inline void r4k_blast_dcache_page_dc128(unsigned long addr) 121{ 122 blast_dcache128_page(addr); 123} 124 125static void r4k_blast_dcache_page_setup(void) 126{ 127 unsigned long dc_lsize = cpu_dcache_line_size(); 128 129 switch (dc_lsize) { 130 case 0: 131 r4k_blast_dcache_page = (void *)cache_noop; 132 break; 133 case 16: 134 r4k_blast_dcache_page = blast_dcache16_page; 135 break; 136 case 32: 137 r4k_blast_dcache_page = r4k_blast_dcache_page_dc32; 138 break; 139 case 64: 140 r4k_blast_dcache_page = r4k_blast_dcache_page_dc64; 141 break; 142 case 128: 143 r4k_blast_dcache_page = r4k_blast_dcache_page_dc128; 144 break; 145 default: 146 break; 147 } 148} 149 150#ifndef CONFIG_EVA 151#define r4k_blast_dcache_user_page r4k_blast_dcache_page 152#else 153 154static void (*r4k_blast_dcache_user_page)(unsigned long addr); 155 156static void r4k_blast_dcache_user_page_setup(void) 157{ 158 unsigned long dc_lsize = cpu_dcache_line_size(); 159 160 if (dc_lsize == 0) 161 r4k_blast_dcache_user_page = (void *)cache_noop; 162 else if (dc_lsize == 16) 163 r4k_blast_dcache_user_page = blast_dcache16_user_page; 164 else if (dc_lsize == 32) 165 r4k_blast_dcache_user_page = blast_dcache32_user_page; 166 else if (dc_lsize == 64) 167 r4k_blast_dcache_user_page = blast_dcache64_user_page; 168} 169 170#endif 171 172static void (* r4k_blast_dcache_page_indexed)(unsigned long addr); 173 174static void r4k_blast_dcache_page_indexed_setup(void) 175{ 176 unsigned long dc_lsize = cpu_dcache_line_size(); 177 178 if (dc_lsize == 0) 179 r4k_blast_dcache_page_indexed = (void *)cache_noop; 180 else if (dc_lsize == 16) 181 r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed; 182 else if (dc_lsize == 32) 183 r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed; 184 else if (dc_lsize == 64) 185 r4k_blast_dcache_page_indexed = blast_dcache64_page_indexed; 186 else if (dc_lsize == 128) 187 r4k_blast_dcache_page_indexed = blast_dcache128_page_indexed; 188} 189 190void (* r4k_blast_dcache)(void); 191EXPORT_SYMBOL(r4k_blast_dcache); 192 193static void r4k_blast_dcache_setup(void) 194{ 195 unsigned long dc_lsize = cpu_dcache_line_size(); 196 197 if (dc_lsize == 0) 198 r4k_blast_dcache = (void *)cache_noop; 199 else if (dc_lsize == 16) 200 r4k_blast_dcache = blast_dcache16; 201 else if (dc_lsize == 32) 202 r4k_blast_dcache = blast_dcache32; 203 else if (dc_lsize == 64) 204 r4k_blast_dcache = blast_dcache64; 205 else if (dc_lsize == 128) 206 r4k_blast_dcache = blast_dcache128; 207} 208 209/* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */ 210#define JUMP_TO_ALIGN(order) \ 211 __asm__ __volatile__( \ 212 "b\t1f\n\t" \ 213 ".align\t" #order "\n\t" \ 214 "1:\n\t" \ 215 ) 216#define CACHE32_UNROLL32_ALIGN JUMP_TO_ALIGN(10) /* 32 * 32 = 1024 */ 217#define CACHE32_UNROLL32_ALIGN2 JUMP_TO_ALIGN(11) 218 219static inline void blast_r4600_v1_icache32(void) 220{ 221 unsigned long flags; 222 223 local_irq_save(flags); 224 blast_icache32(); 225 local_irq_restore(flags); 226} 227 228static inline void tx49_blast_icache32(void) 229{ 230 unsigned long start = INDEX_BASE; 231 unsigned long end = start + current_cpu_data.icache.waysize; 232 unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; 233 unsigned long ws_end = current_cpu_data.icache.ways << 234 current_cpu_data.icache.waybit; 235 unsigned long ws, addr; 236 237 CACHE32_UNROLL32_ALIGN2; 238 /* I'm in even chunk. blast odd chunks */ 239 for (ws = 0; ws < ws_end; ws += ws_inc) 240 for (addr = start + 0x400; addr < end; addr += 0x400 * 2) 241 cache32_unroll32(addr|ws, Index_Invalidate_I); 242 CACHE32_UNROLL32_ALIGN; 243 /* I'm in odd chunk. blast even chunks */ 244 for (ws = 0; ws < ws_end; ws += ws_inc) 245 for (addr = start; addr < end; addr += 0x400 * 2) 246 cache32_unroll32(addr|ws, Index_Invalidate_I); 247} 248 249static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page) 250{ 251 unsigned long flags; 252 253 local_irq_save(flags); 254 blast_icache32_page_indexed(page); 255 local_irq_restore(flags); 256} 257 258static inline void tx49_blast_icache32_page_indexed(unsigned long page) 259{ 260 unsigned long indexmask = current_cpu_data.icache.waysize - 1; 261 unsigned long start = INDEX_BASE + (page & indexmask); 262 unsigned long end = start + PAGE_SIZE; 263 unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; 264 unsigned long ws_end = current_cpu_data.icache.ways << 265 current_cpu_data.icache.waybit; 266 unsigned long ws, addr; 267 268 CACHE32_UNROLL32_ALIGN2; 269 /* I'm in even chunk. blast odd chunks */ 270 for (ws = 0; ws < ws_end; ws += ws_inc) 271 for (addr = start + 0x400; addr < end; addr += 0x400 * 2) 272 cache32_unroll32(addr|ws, Index_Invalidate_I); 273 CACHE32_UNROLL32_ALIGN; 274 /* I'm in odd chunk. blast even chunks */ 275 for (ws = 0; ws < ws_end; ws += ws_inc) 276 for (addr = start; addr < end; addr += 0x400 * 2) 277 cache32_unroll32(addr|ws, Index_Invalidate_I); 278} 279 280static void (* r4k_blast_icache_page)(unsigned long addr); 281 282static void r4k_blast_icache_page_setup(void) 283{ 284 unsigned long ic_lsize = cpu_icache_line_size(); 285 286 if (ic_lsize == 0) 287 r4k_blast_icache_page = (void *)cache_noop; 288 else if (ic_lsize == 16) 289 r4k_blast_icache_page = blast_icache16_page; 290 else if (ic_lsize == 32 && current_cpu_type() == CPU_LOONGSON2) 291 r4k_blast_icache_page = loongson2_blast_icache32_page; 292 else if (ic_lsize == 32) 293 r4k_blast_icache_page = blast_icache32_page; 294 else if (ic_lsize == 64) 295 r4k_blast_icache_page = blast_icache64_page; 296 else if (ic_lsize == 128) 297 r4k_blast_icache_page = blast_icache128_page; 298} 299 300#ifndef CONFIG_EVA 301#define r4k_blast_icache_user_page r4k_blast_icache_page 302#else 303 304static void (*r4k_blast_icache_user_page)(unsigned long addr); 305 306static void __cpuinit r4k_blast_icache_user_page_setup(void) 307{ 308 unsigned long ic_lsize = cpu_icache_line_size(); 309 310 if (ic_lsize == 0) 311 r4k_blast_icache_user_page = (void *)cache_noop; 312 else if (ic_lsize == 16) 313 r4k_blast_icache_user_page = blast_icache16_user_page; 314 else if (ic_lsize == 32) 315 r4k_blast_icache_user_page = blast_icache32_user_page; 316 else if (ic_lsize == 64) 317 r4k_blast_icache_user_page = blast_icache64_user_page; 318} 319 320#endif 321 322static void (* r4k_blast_icache_page_indexed)(unsigned long addr); 323 324static void r4k_blast_icache_page_indexed_setup(void) 325{ 326 unsigned long ic_lsize = cpu_icache_line_size(); 327 328 if (ic_lsize == 0) 329 r4k_blast_icache_page_indexed = (void *)cache_noop; 330 else if (ic_lsize == 16) 331 r4k_blast_icache_page_indexed = blast_icache16_page_indexed; 332 else if (ic_lsize == 32) { 333 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x()) 334 r4k_blast_icache_page_indexed = 335 blast_icache32_r4600_v1_page_indexed; 336 else if (TX49XX_ICACHE_INDEX_INV_WAR) 337 r4k_blast_icache_page_indexed = 338 tx49_blast_icache32_page_indexed; 339 else if (current_cpu_type() == CPU_LOONGSON2) 340 r4k_blast_icache_page_indexed = 341 loongson2_blast_icache32_page_indexed; 342 else 343 r4k_blast_icache_page_indexed = 344 blast_icache32_page_indexed; 345 } else if (ic_lsize == 64) 346 r4k_blast_icache_page_indexed = blast_icache64_page_indexed; 347} 348 349void (* r4k_blast_icache)(void); 350EXPORT_SYMBOL(r4k_blast_icache); 351 352static void r4k_blast_icache_setup(void) 353{ 354 unsigned long ic_lsize = cpu_icache_line_size(); 355 356 if (ic_lsize == 0) 357 r4k_blast_icache = (void *)cache_noop; 358 else if (ic_lsize == 16) 359 r4k_blast_icache = blast_icache16; 360 else if (ic_lsize == 32) { 361 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x()) 362 r4k_blast_icache = blast_r4600_v1_icache32; 363 else if (TX49XX_ICACHE_INDEX_INV_WAR) 364 r4k_blast_icache = tx49_blast_icache32; 365 else if (current_cpu_type() == CPU_LOONGSON2) 366 r4k_blast_icache = loongson2_blast_icache32; 367 else 368 r4k_blast_icache = blast_icache32; 369 } else if (ic_lsize == 64) 370 r4k_blast_icache = blast_icache64; 371 else if (ic_lsize == 128) 372 r4k_blast_icache = blast_icache128; 373} 374 375static void (* r4k_blast_scache_page)(unsigned long addr); 376 377static void r4k_blast_scache_page_setup(void) 378{ 379 unsigned long sc_lsize = cpu_scache_line_size(); 380 381 if (scache_size == 0) 382 r4k_blast_scache_page = (void *)cache_noop; 383 else if (sc_lsize == 16) 384 r4k_blast_scache_page = blast_scache16_page; 385 else if (sc_lsize == 32) 386 r4k_blast_scache_page = blast_scache32_page; 387 else if (sc_lsize == 64) 388 r4k_blast_scache_page = blast_scache64_page; 389 else if (sc_lsize == 128) 390 r4k_blast_scache_page = blast_scache128_page; 391} 392 393static void (* r4k_blast_scache_page_indexed)(unsigned long addr); 394 395static void r4k_blast_scache_page_indexed_setup(void) 396{ 397 unsigned long sc_lsize = cpu_scache_line_size(); 398 399 if (scache_size == 0) 400 r4k_blast_scache_page_indexed = (void *)cache_noop; 401 else if (sc_lsize == 16) 402 r4k_blast_scache_page_indexed = blast_scache16_page_indexed; 403 else if (sc_lsize == 32) 404 r4k_blast_scache_page_indexed = blast_scache32_page_indexed; 405 else if (sc_lsize == 64) 406 r4k_blast_scache_page_indexed = blast_scache64_page_indexed; 407 else if (sc_lsize == 128) 408 r4k_blast_scache_page_indexed = blast_scache128_page_indexed; 409} 410 411static void (* r4k_blast_scache)(void); 412 413static void r4k_blast_scache_setup(void) 414{ 415 unsigned long sc_lsize = cpu_scache_line_size(); 416 417 if (scache_size == 0) 418 r4k_blast_scache = (void *)cache_noop; 419 else if (sc_lsize == 16) 420 r4k_blast_scache = blast_scache16; 421 else if (sc_lsize == 32) 422 r4k_blast_scache = blast_scache32; 423 else if (sc_lsize == 64) 424 r4k_blast_scache = blast_scache64; 425 else if (sc_lsize == 128) 426 r4k_blast_scache = blast_scache128; 427} 428 429static inline void local_r4k___flush_cache_all(void * args) 430{ 431 switch (current_cpu_type()) { 432 case CPU_LOONGSON2: 433 case CPU_LOONGSON3: 434 case CPU_R4000SC: 435 case CPU_R4000MC: 436 case CPU_R4400SC: 437 case CPU_R4400MC: 438 case CPU_R10000: 439 case CPU_R12000: 440 case CPU_R14000: 441 case CPU_R16000: 442 /* 443 * These caches are inclusive caches, that is, if something 444 * is not cached in the S-cache, we know it also won't be 445 * in one of the primary caches. 446 */ 447 r4k_blast_scache(); 448 break; 449 450 default: 451 r4k_blast_dcache(); 452 r4k_blast_icache(); 453 break; 454 } 455} 456 457static void r4k___flush_cache_all(void) 458{ 459 r4k_on_each_cpu(local_r4k___flush_cache_all, NULL); 460} 461 462static inline int has_valid_asid(const struct mm_struct *mm) 463{ 464#ifdef CONFIG_MIPS_MT_SMP 465 int i; 466 467 for_each_online_cpu(i) 468 if (cpu_context(i, mm)) 469 return 1; 470 471 return 0; 472#else 473 return cpu_context(smp_processor_id(), mm); 474#endif 475} 476 477static void r4k__flush_cache_vmap(void) 478{ 479 r4k_blast_dcache(); 480} 481 482static void r4k__flush_cache_vunmap(void) 483{ 484 r4k_blast_dcache(); 485} 486 487static inline void local_r4k_flush_cache_range(void * args) 488{ 489 struct vm_area_struct *vma = args; 490 int exec = vma->vm_flags & VM_EXEC; 491 492 if (!(has_valid_asid(vma->vm_mm))) 493 return; 494 495 r4k_blast_dcache(); 496 if (exec) 497 r4k_blast_icache(); 498} 499 500static void r4k_flush_cache_range(struct vm_area_struct *vma, 501 unsigned long start, unsigned long end) 502{ 503 int exec = vma->vm_flags & VM_EXEC; 504 505 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) 506 r4k_on_each_cpu(local_r4k_flush_cache_range, vma); 507} 508 509static inline void local_r4k_flush_cache_mm(void * args) 510{ 511 struct mm_struct *mm = args; 512 513 if (!has_valid_asid(mm)) 514 return; 515 516 /* 517 * Kludge alert. For obscure reasons R4000SC and R4400SC go nuts if we 518 * only flush the primary caches but R1x000 behave sane ... 519 * R4000SC and R4400SC indexed S-cache ops also invalidate primary 520 * caches, so we can bail out early. 521 */ 522 if (current_cpu_type() == CPU_R4000SC || 523 current_cpu_type() == CPU_R4000MC || 524 current_cpu_type() == CPU_R4400SC || 525 current_cpu_type() == CPU_R4400MC) { 526 r4k_blast_scache(); 527 return; 528 } 529 530 r4k_blast_dcache(); 531} 532 533static void r4k_flush_cache_mm(struct mm_struct *mm) 534{ 535 if (!cpu_has_dc_aliases) 536 return; 537 538 r4k_on_each_cpu(local_r4k_flush_cache_mm, mm); 539} 540 541struct flush_cache_page_args { 542 struct vm_area_struct *vma; 543 unsigned long addr; 544 unsigned long pfn; 545}; 546 547static inline void local_r4k_flush_cache_page(void *args) 548{ 549 struct flush_cache_page_args *fcp_args = args; 550 struct vm_area_struct *vma = fcp_args->vma; 551 unsigned long addr = fcp_args->addr; 552 struct page *page = pfn_to_page(fcp_args->pfn); 553 int exec = vma->vm_flags & VM_EXEC; 554 struct mm_struct *mm = vma->vm_mm; 555 int map_coherent = 0; 556 pgd_t *pgdp; 557 pud_t *pudp; 558 pmd_t *pmdp; 559 pte_t *ptep; 560 void *vaddr; 561 562 /* 563 * If ownes no valid ASID yet, cannot possibly have gotten 564 * this page into the cache. 565 */ 566 if (!has_valid_asid(mm)) 567 return; 568 569 addr &= PAGE_MASK; 570 pgdp = pgd_offset(mm, addr); 571 pudp = pud_offset(pgdp, addr); 572 pmdp = pmd_offset(pudp, addr); 573 ptep = pte_offset(pmdp, addr); 574 575 /* 576 * If the page isn't marked valid, the page cannot possibly be 577 * in the cache. 578 */ 579 if (!(pte_present(*ptep))) 580 return; 581 582 if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) 583 vaddr = NULL; 584 else { 585 /* 586 * Use kmap_coherent or kmap_atomic to do flushes for 587 * another ASID than the current one. 588 */ 589 map_coherent = (cpu_has_dc_aliases && 590 page_mapped(page) && !Page_dcache_dirty(page)); 591 if (map_coherent) 592 vaddr = kmap_coherent(page, addr); 593 else 594 vaddr = kmap_atomic(page); 595 addr = (unsigned long)vaddr; 596 } 597 598 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) { 599 vaddr ? r4k_blast_dcache_page(addr) : 600 r4k_blast_dcache_user_page(addr); 601 if (exec && !cpu_icache_snoops_remote_store) 602 r4k_blast_scache_page(addr); 603 } 604 if (exec) { 605 if (vaddr && cpu_has_vtag_icache && mm == current->active_mm) { 606 int cpu = smp_processor_id(); 607 608 if (cpu_context(cpu, mm) != 0) 609 drop_mmu_context(mm, cpu); 610 } else 611 vaddr ? r4k_blast_icache_page(addr) : 612 r4k_blast_icache_user_page(addr); 613 } 614 615 if (vaddr) { 616 if (map_coherent) 617 kunmap_coherent(); 618 else 619 kunmap_atomic(vaddr); 620 } 621} 622 623static void r4k_flush_cache_page(struct vm_area_struct *vma, 624 unsigned long addr, unsigned long pfn) 625{ 626 struct flush_cache_page_args args; 627 628 args.vma = vma; 629 args.addr = addr; 630 args.pfn = pfn; 631 632 r4k_on_each_cpu(local_r4k_flush_cache_page, &args); 633} 634 635static inline void local_r4k_flush_data_cache_page(void * addr) 636{ 637 r4k_blast_dcache_page((unsigned long) addr); 638} 639 640static void r4k_flush_data_cache_page(unsigned long addr) 641{ 642 if (in_atomic()) 643 local_r4k_flush_data_cache_page((void *)addr); 644 else 645 r4k_on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr); 646} 647 648struct flush_icache_range_args { 649 unsigned long start; 650 unsigned long end; 651}; 652 653static inline void local_r4k_flush_icache_range(unsigned long start, unsigned long end) 654{ 655 if (!cpu_has_ic_fills_f_dc) { 656 if (end - start >= dcache_size) { 657 r4k_blast_dcache(); 658 } else { 659 R4600_HIT_CACHEOP_WAR_IMPL; 660 protected_blast_dcache_range(start, end); 661 } 662 } 663 664 if (end - start > icache_size) 665 r4k_blast_icache(); 666 else { 667 switch (boot_cpu_type()) { 668 case CPU_LOONGSON2: 669 protected_loongson2_blast_icache_range(start, end); 670 break; 671 672 default: 673 protected_blast_icache_range(start, end); 674 break; 675 } 676 } 677#ifdef CONFIG_EVA 678 /* 679 * Due to all possible segment mappings, there might cache aliases 680 * caused by the bootloader being in non-EVA mode, and the CPU switching 681 * to EVA during early kernel init. It's best to flush the scache 682 * to avoid having secondary cores fetching stale data and lead to 683 * kernel crashes. 684 */ 685 bc_wback_inv(start, (end - start)); 686 __sync(); 687#endif 688} 689 690static inline void local_r4k_flush_icache_range_ipi(void *args) 691{ 692 struct flush_icache_range_args *fir_args = args; 693 unsigned long start = fir_args->start; 694 unsigned long end = fir_args->end; 695 696 local_r4k_flush_icache_range(start, end); 697} 698 699static void r4k_flush_icache_range(unsigned long start, unsigned long end) 700{ 701 struct flush_icache_range_args args; 702 703 args.start = start; 704 args.end = end; 705 706 r4k_on_each_cpu(local_r4k_flush_icache_range_ipi, &args); 707 instruction_hazard(); 708} 709 710#if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_DMA_MAYBE_COHERENT) 711 712static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size) 713{ 714 /* Catch bad driver code */ 715 BUG_ON(size == 0); 716 717 preempt_disable(); 718 if (cpu_has_inclusive_pcaches) { 719 if (size >= scache_size) 720 r4k_blast_scache(); 721 else 722 blast_scache_range(addr, addr + size); 723 preempt_enable(); 724 __sync(); 725 return; 726 } 727 728 /* 729 * Either no secondary cache or the available caches don't have the 730 * subset property so we have to flush the primary caches 731 * explicitly 732 */ 733 if (cpu_has_safe_index_cacheops && size >= dcache_size) { 734 r4k_blast_dcache(); 735 } else { 736 R4600_HIT_CACHEOP_WAR_IMPL; 737 blast_dcache_range(addr, addr + size); 738 } 739 preempt_enable(); 740 741 bc_wback_inv(addr, size); 742 __sync(); 743} 744 745static void r4k_dma_cache_inv(unsigned long addr, unsigned long size) 746{ 747 /* Catch bad driver code */ 748 BUG_ON(size == 0); 749 750 preempt_disable(); 751 if (cpu_has_inclusive_pcaches) { 752 if (size >= scache_size) 753 r4k_blast_scache(); 754 else { 755 /* 756 * There is no clearly documented alignment requirement 757 * for the cache instruction on MIPS processors and 758 * some processors, among them the RM5200 and RM7000 759 * QED processors will throw an address error for cache 760 * hit ops with insufficient alignment. Solved by 761 * aligning the address to cache line size. 762 */ 763 blast_inv_scache_range(addr, addr + size); 764 } 765 preempt_enable(); 766 __sync(); 767 return; 768 } 769 770 if (cpu_has_safe_index_cacheops && size >= dcache_size) { 771 r4k_blast_dcache(); 772 } else { 773 R4600_HIT_CACHEOP_WAR_IMPL; 774 blast_inv_dcache_range(addr, addr + size); 775 } 776 preempt_enable(); 777 778 bc_inv(addr, size); 779 __sync(); 780} 781#endif /* CONFIG_DMA_NONCOHERENT || CONFIG_DMA_MAYBE_COHERENT */ 782 783/* 784 * While we're protected against bad userland addresses we don't care 785 * very much about what happens in that case. Usually a segmentation 786 * fault will dump the process later on anyway ... 787 */ 788static void local_r4k_flush_cache_sigtramp(void * arg) 789{ 790 unsigned long ic_lsize = cpu_icache_line_size(); 791 unsigned long dc_lsize = cpu_dcache_line_size(); 792 unsigned long sc_lsize = cpu_scache_line_size(); 793 unsigned long addr = (unsigned long) arg; 794 795 R4600_HIT_CACHEOP_WAR_IMPL; 796 if (dc_lsize) 797 protected_writeback_dcache_line(addr & ~(dc_lsize - 1)); 798 if (!cpu_icache_snoops_remote_store && scache_size) 799 protected_writeback_scache_line(addr & ~(sc_lsize - 1)); 800 if (ic_lsize) 801 protected_flush_icache_line(addr & ~(ic_lsize - 1)); 802 if (MIPS4K_ICACHE_REFILL_WAR) { 803 __asm__ __volatile__ ( 804 ".set push\n\t" 805 ".set noat\n\t" 806 ".set "MIPS_ISA_LEVEL"\n\t" 807#ifdef CONFIG_32BIT 808 "la $at,1f\n\t" 809#endif 810#ifdef CONFIG_64BIT 811 "dla $at,1f\n\t" 812#endif 813 "cache %0,($at)\n\t" 814 "nop; nop; nop\n" 815 "1:\n\t" 816 ".set pop" 817 : 818 : "i" (Hit_Invalidate_I)); 819 } 820 if (MIPS_CACHE_SYNC_WAR) 821 __asm__ __volatile__ ("sync"); 822} 823 824static void r4k_flush_cache_sigtramp(unsigned long addr) 825{ 826 r4k_on_each_cpu(local_r4k_flush_cache_sigtramp, (void *) addr); 827} 828 829static void r4k_flush_icache_all(void) 830{ 831 if (cpu_has_vtag_icache) 832 r4k_blast_icache(); 833} 834 835struct flush_kernel_vmap_range_args { 836 unsigned long vaddr; 837 int size; 838}; 839 840static inline void local_r4k_flush_kernel_vmap_range(void *args) 841{ 842 struct flush_kernel_vmap_range_args *vmra = args; 843 unsigned long vaddr = vmra->vaddr; 844 int size = vmra->size; 845 846 /* 847 * Aliases only affect the primary caches so don't bother with 848 * S-caches or T-caches. 849 */ 850 if (cpu_has_safe_index_cacheops && size >= dcache_size) 851 r4k_blast_dcache(); 852 else { 853 R4600_HIT_CACHEOP_WAR_IMPL; 854 blast_dcache_range(vaddr, vaddr + size); 855 } 856} 857 858static void r4k_flush_kernel_vmap_range(unsigned long vaddr, int size) 859{ 860 struct flush_kernel_vmap_range_args args; 861 862 args.vaddr = (unsigned long) vaddr; 863 args.size = size; 864 865 r4k_on_each_cpu(local_r4k_flush_kernel_vmap_range, &args); 866} 867 868static inline void rm7k_erratum31(void) 869{ 870 const unsigned long ic_lsize = 32; 871 unsigned long addr; 872 873 /* RM7000 erratum #31. The icache is screwed at startup. */ 874 write_c0_taglo(0); 875 write_c0_taghi(0); 876 877 for (addr = INDEX_BASE; addr <= INDEX_BASE + 4096; addr += ic_lsize) { 878 __asm__ __volatile__ ( 879 ".set push\n\t" 880 ".set noreorder\n\t" 881 ".set mips3\n\t" 882 "cache\t%1, 0(%0)\n\t" 883 "cache\t%1, 0x1000(%0)\n\t" 884 "cache\t%1, 0x2000(%0)\n\t" 885 "cache\t%1, 0x3000(%0)\n\t" 886 "cache\t%2, 0(%0)\n\t" 887 "cache\t%2, 0x1000(%0)\n\t" 888 "cache\t%2, 0x2000(%0)\n\t" 889 "cache\t%2, 0x3000(%0)\n\t" 890 "cache\t%1, 0(%0)\n\t" 891 "cache\t%1, 0x1000(%0)\n\t" 892 "cache\t%1, 0x2000(%0)\n\t" 893 "cache\t%1, 0x3000(%0)\n\t" 894 ".set pop\n" 895 : 896 : "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill)); 897 } 898} 899 900static inline int alias_74k_erratum(struct cpuinfo_mips *c) 901{ 902 unsigned int imp = c->processor_id & PRID_IMP_MASK; 903 unsigned int rev = c->processor_id & PRID_REV_MASK; 904 int present = 0; 905 906 /* 907 * Early versions of the 74K do not update the cache tags on a 908 * vtag miss/ptag hit which can occur in the case of KSEG0/KUSEG 909 * aliases. In this case it is better to treat the cache as always 910 * having aliases. Also disable the synonym tag update feature 911 * where available. In this case no opportunistic tag update will 912 * happen where a load causes a virtual address miss but a physical 913 * address hit during a D-cache look-up. 914 */ 915 switch (imp) { 916 case PRID_IMP_74K: 917 if (rev <= PRID_REV_ENCODE_332(2, 4, 0)) 918 present = 1; 919 if (rev == PRID_REV_ENCODE_332(2, 4, 0)) 920 write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND); 921 break; 922 case PRID_IMP_1074K: 923 if (rev <= PRID_REV_ENCODE_332(1, 1, 0)) { 924 present = 1; 925 write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND); 926 } 927 break; 928 default: 929 BUG(); 930 } 931 932 return present; 933} 934 935static void b5k_instruction_hazard(void) 936{ 937 __sync(); 938 __sync(); 939 __asm__ __volatile__( 940 " nop; nop; nop; nop; nop; nop; nop; nop\n" 941 " nop; nop; nop; nop; nop; nop; nop; nop\n" 942 " nop; nop; nop; nop; nop; nop; nop; nop\n" 943 " nop; nop; nop; nop; nop; nop; nop; nop\n" 944 : : : "memory"); 945} 946 947static char *way_string[] = { NULL, "direct mapped", "2-way", 948 "3-way", "4-way", "5-way", "6-way", "7-way", "8-way" 949}; 950 951static void probe_pcache(void) 952{ 953 struct cpuinfo_mips *c = ¤t_cpu_data; 954 unsigned int config = read_c0_config(); 955 unsigned int prid = read_c0_prid(); 956 int has_74k_erratum = 0; 957 unsigned long config1; 958 unsigned int lsize; 959 960 switch (current_cpu_type()) { 961 case CPU_R4600: /* QED style two way caches? */ 962 case CPU_R4700: 963 case CPU_R5000: 964 case CPU_NEVADA: 965 icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); 966 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); 967 c->icache.ways = 2; 968 c->icache.waybit = __ffs(icache_size/2); 969 970 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); 971 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); 972 c->dcache.ways = 2; 973 c->dcache.waybit= __ffs(dcache_size/2); 974 975 c->options |= MIPS_CPU_CACHE_CDEX_P; 976 break; 977 978 case CPU_R5432: 979 case CPU_R5500: 980 icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); 981 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); 982 c->icache.ways = 2; 983 c->icache.waybit= 0; 984 985 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); 986 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); 987 c->dcache.ways = 2; 988 c->dcache.waybit = 0; 989 990 c->options |= MIPS_CPU_CACHE_CDEX_P | MIPS_CPU_PREFETCH; 991 break; 992 993 case CPU_TX49XX: 994 icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); 995 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); 996 c->icache.ways = 4; 997 c->icache.waybit= 0; 998 999 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); 1000 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); 1001 c->dcache.ways = 4; 1002 c->dcache.waybit = 0; 1003 1004 c->options |= MIPS_CPU_CACHE_CDEX_P; 1005 c->options |= MIPS_CPU_PREFETCH; 1006 break; 1007 1008 case CPU_R4000PC: 1009 case CPU_R4000SC: 1010 case CPU_R4000MC: 1011 case CPU_R4400PC: 1012 case CPU_R4400SC: 1013 case CPU_R4400MC: 1014 case CPU_R4300: 1015 icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); 1016 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); 1017 c->icache.ways = 1; 1018 c->icache.waybit = 0; /* doesn't matter */ 1019 1020 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); 1021 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); 1022 c->dcache.ways = 1; 1023 c->dcache.waybit = 0; /* does not matter */ 1024 1025 c->options |= MIPS_CPU_CACHE_CDEX_P; 1026 break; 1027 1028 case CPU_R10000: 1029 case CPU_R12000: 1030 case CPU_R14000: 1031 case CPU_R16000: 1032 icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29)); 1033 c->icache.linesz = 64; 1034 c->icache.ways = 2; 1035 c->icache.waybit = 0; 1036 1037 dcache_size = 1 << (12 + ((config & R10K_CONF_DC) >> 26)); 1038 c->dcache.linesz = 32; 1039 c->dcache.ways = 2; 1040 c->dcache.waybit = 0; 1041 1042 c->options |= MIPS_CPU_PREFETCH; 1043 break; 1044 1045 case CPU_VR4133: 1046 write_c0_config(config & ~VR41_CONF_P4K); 1047 case CPU_VR4131: 1048 /* Workaround for cache instruction bug of VR4131 */ 1049 if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U || 1050 c->processor_id == 0x0c82U) { 1051 config |= 0x00400000U; 1052 if (c->processor_id == 0x0c80U) 1053 config |= VR41_CONF_BP; 1054 write_c0_config(config); 1055 } else 1056 c->options |= MIPS_CPU_CACHE_CDEX_P; 1057 1058 icache_size = 1 << (10 + ((config & CONF_IC) >> 9)); 1059 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); 1060 c->icache.ways = 2; 1061 c->icache.waybit = __ffs(icache_size/2); 1062 1063 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6)); 1064 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); 1065 c->dcache.ways = 2; 1066 c->dcache.waybit = __ffs(dcache_size/2); 1067 break; 1068 1069 case CPU_VR41XX: 1070 case CPU_VR4111: 1071 case CPU_VR4121: 1072 case CPU_VR4122: 1073 case CPU_VR4181: 1074 case CPU_VR4181A: 1075 icache_size = 1 << (10 + ((config & CONF_IC) >> 9)); 1076 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); 1077 c->icache.ways = 1; 1078 c->icache.waybit = 0; /* doesn't matter */ 1079 1080 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6)); 1081 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); 1082 c->dcache.ways = 1; 1083 c->dcache.waybit = 0; /* does not matter */ 1084 1085 c->options |= MIPS_CPU_CACHE_CDEX_P; 1086 break; 1087 1088 case CPU_RM7000: 1089 rm7k_erratum31(); 1090 1091 icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); 1092 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); 1093 c->icache.ways = 4; 1094 c->icache.waybit = __ffs(icache_size / c->icache.ways); 1095 1096 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); 1097 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); 1098 c->dcache.ways = 4; 1099 c->dcache.waybit = __ffs(dcache_size / c->dcache.ways); 1100 1101 c->options |= MIPS_CPU_CACHE_CDEX_P; 1102 c->options |= MIPS_CPU_PREFETCH; 1103 break; 1104 1105 case CPU_LOONGSON2: 1106 icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); 1107 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); 1108 if (prid & 0x3) 1109 c->icache.ways = 4; 1110 else 1111 c->icache.ways = 2; 1112 c->icache.waybit = 0; 1113 1114 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); 1115 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); 1116 if (prid & 0x3) 1117 c->dcache.ways = 4; 1118 else 1119 c->dcache.ways = 2; 1120 c->dcache.waybit = 0; 1121 break; 1122 1123 case CPU_LOONGSON3: 1124 config1 = read_c0_config1(); 1125 lsize = (config1 >> 19) & 7; 1126 if (lsize) 1127 c->icache.linesz = 2 << lsize; 1128 else 1129 c->icache.linesz = 0; 1130 c->icache.sets = 64 << ((config1 >> 22) & 7); 1131 c->icache.ways = 1 + ((config1 >> 16) & 7); 1132 icache_size = c->icache.sets * 1133 c->icache.ways * 1134 c->icache.linesz; 1135 c->icache.waybit = 0; 1136 1137 lsize = (config1 >> 10) & 7; 1138 if (lsize) 1139 c->dcache.linesz = 2 << lsize; 1140 else 1141 c->dcache.linesz = 0; 1142 c->dcache.sets = 64 << ((config1 >> 13) & 7); 1143 c->dcache.ways = 1 + ((config1 >> 7) & 7); 1144 dcache_size = c->dcache.sets * 1145 c->dcache.ways * 1146 c->dcache.linesz; 1147 c->dcache.waybit = 0; 1148 break; 1149 1150 case CPU_CAVIUM_OCTEON3: 1151 /* For now lie about the number of ways. */ 1152 c->icache.linesz = 128; 1153 c->icache.sets = 16; 1154 c->icache.ways = 8; 1155 c->icache.flags |= MIPS_CACHE_VTAG; 1156 icache_size = c->icache.sets * c->icache.ways * c->icache.linesz; 1157 1158 c->dcache.linesz = 128; 1159 c->dcache.ways = 8; 1160 c->dcache.sets = 8; 1161 dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz; 1162 c->options |= MIPS_CPU_PREFETCH; 1163 break; 1164 1165 default: 1166 if (!(config & MIPS_CONF_M)) 1167 panic("Don't know how to probe P-caches on this cpu."); 1168 1169 /* 1170 * So we seem to be a MIPS32 or MIPS64 CPU 1171 * So let's probe the I-cache ... 1172 */ 1173 config1 = read_c0_config1(); 1174 1175 lsize = (config1 >> 19) & 7; 1176 1177 /* IL == 7 is reserved */ 1178 if (lsize == 7) 1179 panic("Invalid icache line size"); 1180 1181 c->icache.linesz = lsize ? 2 << lsize : 0; 1182 1183 c->icache.sets = 32 << (((config1 >> 22) + 1) & 7); 1184 c->icache.ways = 1 + ((config1 >> 16) & 7); 1185 1186 icache_size = c->icache.sets * 1187 c->icache.ways * 1188 c->icache.linesz; 1189 c->icache.waybit = __ffs(icache_size/c->icache.ways); 1190 1191 if (config & 0x8) /* VI bit */ 1192 c->icache.flags |= MIPS_CACHE_VTAG; 1193 1194 /* 1195 * Now probe the MIPS32 / MIPS64 data cache. 1196 */ 1197 c->dcache.flags = 0; 1198 1199 lsize = (config1 >> 10) & 7; 1200 1201 /* DL == 7 is reserved */ 1202 if (lsize == 7) 1203 panic("Invalid dcache line size"); 1204 1205 c->dcache.linesz = lsize ? 2 << lsize : 0; 1206 1207 c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7); 1208 c->dcache.ways = 1 + ((config1 >> 7) & 7); 1209 1210 dcache_size = c->dcache.sets * 1211 c->dcache.ways * 1212 c->dcache.linesz; 1213 c->dcache.waybit = __ffs(dcache_size/c->dcache.ways); 1214 1215 c->options |= MIPS_CPU_PREFETCH; 1216 break; 1217 } 1218 1219 /* 1220 * Processor configuration sanity check for the R4000SC erratum 1221 * #5. With page sizes larger than 32kB there is no possibility 1222 * to get a VCE exception anymore so we don't care about this 1223 * misconfiguration. The case is rather theoretical anyway; 1224 * presumably no vendor is shipping his hardware in the "bad" 1225 * configuration. 1226 */ 1227 if ((prid & PRID_IMP_MASK) == PRID_IMP_R4000 && 1228 (prid & PRID_REV_MASK) < PRID_REV_R4400 && 1229 !(config & CONF_SC) && c->icache.linesz != 16 && 1230 PAGE_SIZE <= 0x8000) 1231 panic("Improper R4000SC processor configuration detected"); 1232 1233 /* compute a couple of other cache variables */ 1234 c->icache.waysize = icache_size / c->icache.ways; 1235 c->dcache.waysize = dcache_size / c->dcache.ways; 1236 1237 c->icache.sets = c->icache.linesz ? 1238 icache_size / (c->icache.linesz * c->icache.ways) : 0; 1239 c->dcache.sets = c->dcache.linesz ? 1240 dcache_size / (c->dcache.linesz * c->dcache.ways) : 0; 1241 1242 /* 1243 * R1x000 P-caches are odd in a positive way. They're 32kB 2-way 1244 * virtually indexed so normally would suffer from aliases. So 1245 * normally they'd suffer from aliases but magic in the hardware deals 1246 * with that for us so we don't need to take care ourselves. 1247 */ 1248 switch (current_cpu_type()) { 1249 case CPU_20KC: 1250 case CPU_25KF: 1251 case CPU_SB1: 1252 case CPU_SB1A: 1253 case CPU_XLR: 1254 c->dcache.flags |= MIPS_CACHE_PINDEX; 1255 break; 1256 1257 case CPU_R10000: 1258 case CPU_R12000: 1259 case CPU_R14000: 1260 case CPU_R16000: 1261 break; 1262 1263 case CPU_74K: 1264 case CPU_1074K: 1265 has_74k_erratum = alias_74k_erratum(c); 1266 /* Fall through. */ 1267 case CPU_M14KC: 1268 case CPU_M14KEC: 1269 case CPU_24K: 1270 case CPU_34K: 1271 case CPU_1004K: 1272 case CPU_INTERAPTIV: 1273 case CPU_P5600: 1274 case CPU_PROAPTIV: 1275 case CPU_M5150: 1276 case CPU_QEMU_GENERIC: 1277 if (!(read_c0_config7() & MIPS_CONF7_IAR) && 1278 (c->icache.waysize > PAGE_SIZE)) 1279 c->icache.flags |= MIPS_CACHE_ALIASES; 1280 if (!has_74k_erratum && (read_c0_config7() & MIPS_CONF7_AR)) { 1281 /* 1282 * Effectively physically indexed dcache, 1283 * thus no virtual aliases. 1284 */ 1285 c->dcache.flags |= MIPS_CACHE_PINDEX; 1286 break; 1287 } 1288 default: 1289 if (has_74k_erratum || c->dcache.waysize > PAGE_SIZE) 1290 c->dcache.flags |= MIPS_CACHE_ALIASES; 1291 } 1292 1293 switch (current_cpu_type()) { 1294 case CPU_20KC: 1295 /* 1296 * Some older 20Kc chips doesn't have the 'VI' bit in 1297 * the config register. 1298 */ 1299 c->icache.flags |= MIPS_CACHE_VTAG; 1300 break; 1301 1302 case CPU_ALCHEMY: 1303 c->icache.flags |= MIPS_CACHE_IC_F_DC; 1304 break; 1305 1306 case CPU_LOONGSON2: 1307 /* 1308 * LOONGSON2 has 4 way icache, but when using indexed cache op, 1309 * one op will act on all 4 ways 1310 */ 1311 c->icache.ways = 1; 1312 } 1313 1314 printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n", 1315 icache_size >> 10, 1316 c->icache.flags & MIPS_CACHE_VTAG ? "VIVT" : "VIPT", 1317 way_string[c->icache.ways], c->icache.linesz); 1318 1319 printk("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n", 1320 dcache_size >> 10, way_string[c->dcache.ways], 1321 (c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT", 1322 (c->dcache.flags & MIPS_CACHE_ALIASES) ? 1323 "cache aliases" : "no aliases", 1324 c->dcache.linesz); 1325} 1326 1327/* 1328 * If you even _breathe_ on this function, look at the gcc output and make sure 1329 * it does not pop things on and off the stack for the cache sizing loop that 1330 * executes in KSEG1 space or else you will crash and burn badly. You have 1331 * been warned. 1332 */ 1333static int probe_scache(void) 1334{ 1335 unsigned long flags, addr, begin, end, pow2; 1336 unsigned int config = read_c0_config(); 1337 struct cpuinfo_mips *c = ¤t_cpu_data; 1338 1339 if (config & CONF_SC) 1340 return 0; 1341 1342 begin = (unsigned long) &_stext; 1343 begin &= ~((4 * 1024 * 1024) - 1); 1344 end = begin + (4 * 1024 * 1024); 1345 1346 /* 1347 * This is such a bitch, you'd think they would make it easy to do 1348 * this. Away you daemons of stupidity! 1349 */ 1350 local_irq_save(flags); 1351 1352 /* Fill each size-multiple cache line with a valid tag. */ 1353 pow2 = (64 * 1024); 1354 for (addr = begin; addr < end; addr = (begin + pow2)) { 1355 unsigned long *p = (unsigned long *) addr; 1356 __asm__ __volatile__("nop" : : "r" (*p)); /* whee... */ 1357 pow2 <<= 1; 1358 } 1359 1360 /* Load first line with zero (therefore invalid) tag. */ 1361 write_c0_taglo(0); 1362 write_c0_taghi(0); 1363 __asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */ 1364 cache_op(Index_Store_Tag_I, begin); 1365 cache_op(Index_Store_Tag_D, begin); 1366 cache_op(Index_Store_Tag_SD, begin); 1367 1368 /* Now search for the wrap around point. */ 1369 pow2 = (128 * 1024); 1370 for (addr = begin + (128 * 1024); addr < end; addr = begin + pow2) { 1371 cache_op(Index_Load_Tag_SD, addr); 1372 __asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */ 1373 if (!read_c0_taglo()) 1374 break; 1375 pow2 <<= 1; 1376 } 1377 local_irq_restore(flags); 1378 addr -= begin; 1379 1380 scache_size = addr; 1381 c->scache.linesz = 16 << ((config & R4K_CONF_SB) >> 22); 1382 c->scache.ways = 1; 1383 c->scache.waybit = 0; /* does not matter */ 1384 1385 return 1; 1386} 1387 1388static void __init loongson2_sc_init(void) 1389{ 1390 struct cpuinfo_mips *c = ¤t_cpu_data; 1391 1392 scache_size = 512*1024; 1393 c->scache.linesz = 32; 1394 c->scache.ways = 4; 1395 c->scache.waybit = 0; 1396 c->scache.waysize = scache_size / (c->scache.ways); 1397 c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways); 1398 pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n", 1399 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz); 1400 1401 c->options |= MIPS_CPU_INCLUSIVE_CACHES; 1402} 1403 1404static void __init loongson3_sc_init(void) 1405{ 1406 struct cpuinfo_mips *c = ¤t_cpu_data; 1407 unsigned int config2, lsize; 1408 1409 config2 = read_c0_config2(); 1410 lsize = (config2 >> 4) & 15; 1411 if (lsize) 1412 c->scache.linesz = 2 << lsize; 1413 else 1414 c->scache.linesz = 0; 1415 c->scache.sets = 64 << ((config2 >> 8) & 15); 1416 c->scache.ways = 1 + (config2 & 15); 1417 1418 scache_size = c->scache.sets * 1419 c->scache.ways * 1420 c->scache.linesz; 1421 /* Loongson-3 has 4 cores, 1MB scache for each. scaches are shared */ 1422 scache_size *= 4; 1423 c->scache.waybit = 0; 1424 pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n", 1425 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz); 1426 if (scache_size) 1427 c->options |= MIPS_CPU_INCLUSIVE_CACHES; 1428 return; 1429} 1430 1431extern int r5k_sc_init(void); 1432extern int rm7k_sc_init(void); 1433extern int mips_sc_init(void); 1434 1435static void setup_scache(void) 1436{ 1437 struct cpuinfo_mips *c = ¤t_cpu_data; 1438 unsigned int config = read_c0_config(); 1439 int sc_present = 0; 1440 1441 /* 1442 * Do the probing thing on R4000SC and R4400SC processors. Other 1443 * processors don't have a S-cache that would be relevant to the 1444 * Linux memory management. 1445 */ 1446 switch (current_cpu_type()) { 1447 case CPU_R4000SC: 1448 case CPU_R4000MC: 1449 case CPU_R4400SC: 1450 case CPU_R4400MC: 1451 sc_present = run_uncached(probe_scache); 1452 if (sc_present) 1453 c->options |= MIPS_CPU_CACHE_CDEX_S; 1454 break; 1455 1456 case CPU_R10000: 1457 case CPU_R12000: 1458 case CPU_R14000: 1459 case CPU_R16000: 1460 scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16); 1461 c->scache.linesz = 64 << ((config >> 13) & 1); 1462 c->scache.ways = 2; 1463 c->scache.waybit= 0; 1464 sc_present = 1; 1465 break; 1466 1467 case CPU_R5000: 1468 case CPU_NEVADA: 1469#ifdef CONFIG_R5000_CPU_SCACHE 1470 r5k_sc_init(); 1471#endif 1472 return; 1473 1474 case CPU_RM7000: 1475#ifdef CONFIG_RM7000_CPU_SCACHE 1476 rm7k_sc_init(); 1477#endif 1478 return; 1479 1480 case CPU_LOONGSON2: 1481 loongson2_sc_init(); 1482 return; 1483 1484 case CPU_LOONGSON3: 1485 loongson3_sc_init(); 1486 return; 1487 1488 case CPU_CAVIUM_OCTEON3: 1489 case CPU_XLP: 1490 /* don't need to worry about L2, fully coherent */ 1491 return; 1492 1493 default: 1494 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 | 1495 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R1 | 1496 MIPS_CPU_ISA_M64R2 | MIPS_CPU_ISA_M64R6)) { 1497#ifdef CONFIG_MIPS_CPU_SCACHE 1498 if (mips_sc_init ()) { 1499 scache_size = c->scache.ways * c->scache.sets * c->scache.linesz; 1500 printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n", 1501 scache_size >> 10, 1502 way_string[c->scache.ways], c->scache.linesz); 1503 } 1504#else 1505 if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT)) 1506 panic("Dunno how to handle MIPS32 / MIPS64 second level cache"); 1507#endif 1508 return; 1509 } 1510 sc_present = 0; 1511 } 1512 1513 if (!sc_present) 1514 return; 1515 1516 /* compute a couple of other cache variables */ 1517 c->scache.waysize = scache_size / c->scache.ways; 1518 1519 c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways); 1520 1521 printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n", 1522 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz); 1523 1524 c->options |= MIPS_CPU_INCLUSIVE_CACHES; 1525} 1526 1527void au1x00_fixup_config_od(void) 1528{ 1529 /* 1530 * c0_config.od (bit 19) was write only (and read as 0) 1531 * on the early revisions of Alchemy SOCs. It disables the bus 1532 * transaction overlapping and needs to be set to fix various errata. 1533 */ 1534 switch (read_c0_prid()) { 1535 case 0x00030100: /* Au1000 DA */ 1536 case 0x00030201: /* Au1000 HA */ 1537 case 0x00030202: /* Au1000 HB */ 1538 case 0x01030200: /* Au1500 AB */ 1539 /* 1540 * Au1100 errata actually keeps silence about this bit, so we set it 1541 * just in case for those revisions that require it to be set according 1542 * to the (now gone) cpu table. 1543 */ 1544 case 0x02030200: /* Au1100 AB */ 1545 case 0x02030201: /* Au1100 BA */ 1546 case 0x02030202: /* Au1100 BC */ 1547 set_c0_config(1 << 19); 1548 break; 1549 } 1550} 1551 1552/* CP0 hazard avoidance. */ 1553#define NXP_BARRIER() \ 1554 __asm__ __volatile__( \ 1555 ".set noreorder\n\t" \ 1556 "nop; nop; nop; nop; nop; nop;\n\t" \ 1557 ".set reorder\n\t") 1558 1559static void nxp_pr4450_fixup_config(void) 1560{ 1561 unsigned long config0; 1562 1563 config0 = read_c0_config(); 1564 1565 /* clear all three cache coherency fields */ 1566 config0 &= ~(0x7 | (7 << 25) | (7 << 28)); 1567 config0 |= (((_page_cachable_default >> _CACHE_SHIFT) << 0) | 1568 ((_page_cachable_default >> _CACHE_SHIFT) << 25) | 1569 ((_page_cachable_default >> _CACHE_SHIFT) << 28)); 1570 write_c0_config(config0); 1571 NXP_BARRIER(); 1572} 1573 1574static int cca = -1; 1575 1576static int __init cca_setup(char *str) 1577{ 1578 get_option(&str, &cca); 1579 1580 return 0; 1581} 1582 1583early_param("cca", cca_setup); 1584 1585static void coherency_setup(void) 1586{ 1587 if (cca < 0 || cca > 7) 1588 cca = read_c0_config() & CONF_CM_CMASK; 1589 _page_cachable_default = cca << _CACHE_SHIFT; 1590 1591 pr_debug("Using cache attribute %d\n", cca); 1592 change_c0_config(CONF_CM_CMASK, cca); 1593 1594 /* 1595 * c0_status.cu=0 specifies that updates by the sc instruction use 1596 * the coherency mode specified by the TLB; 1 means cachable 1597 * coherent update on write will be used. Not all processors have 1598 * this bit and; some wire it to zero, others like Toshiba had the 1599 * silly idea of putting something else there ... 1600 */ 1601 switch (current_cpu_type()) { 1602 case CPU_R4000PC: 1603 case CPU_R4000SC: 1604 case CPU_R4000MC: 1605 case CPU_R4400PC: 1606 case CPU_R4400SC: 1607 case CPU_R4400MC: 1608 clear_c0_config(CONF_CU); 1609 break; 1610 /* 1611 * We need to catch the early Alchemy SOCs with 1612 * the write-only co_config.od bit and set it back to one on: 1613 * Au1000 rev DA, HA, HB; Au1100 AB, BA, BC, Au1500 AB 1614 */ 1615 case CPU_ALCHEMY: 1616 au1x00_fixup_config_od(); 1617 break; 1618 1619 case PRID_IMP_PR4450: 1620 nxp_pr4450_fixup_config(); 1621 break; 1622 } 1623} 1624 1625static void r4k_cache_error_setup(void) 1626{ 1627 extern char __weak except_vec2_generic; 1628 extern char __weak except_vec2_sb1; 1629 1630 switch (current_cpu_type()) { 1631 case CPU_SB1: 1632 case CPU_SB1A: 1633 set_uncached_handler(0x100, &except_vec2_sb1, 0x80); 1634 break; 1635 1636 default: 1637 set_uncached_handler(0x100, &except_vec2_generic, 0x80); 1638 break; 1639 } 1640} 1641 1642void r4k_cache_init(void) 1643{ 1644 extern void build_clear_page(void); 1645 extern void build_copy_page(void); 1646 struct cpuinfo_mips *c = ¤t_cpu_data; 1647 1648 probe_pcache(); 1649 setup_scache(); 1650 1651 r4k_blast_dcache_page_setup(); 1652 r4k_blast_dcache_page_indexed_setup(); 1653 r4k_blast_dcache_setup(); 1654 r4k_blast_icache_page_setup(); 1655 r4k_blast_icache_page_indexed_setup(); 1656 r4k_blast_icache_setup(); 1657 r4k_blast_scache_page_setup(); 1658 r4k_blast_scache_page_indexed_setup(); 1659 r4k_blast_scache_setup(); 1660#ifdef CONFIG_EVA 1661 r4k_blast_dcache_user_page_setup(); 1662 r4k_blast_icache_user_page_setup(); 1663#endif 1664 1665 /* 1666 * Some MIPS32 and MIPS64 processors have physically indexed caches. 1667 * This code supports virtually indexed processors and will be 1668 * unnecessarily inefficient on physically indexed processors. 1669 */ 1670 if (c->dcache.linesz) 1671 shm_align_mask = max_t( unsigned long, 1672 c->dcache.sets * c->dcache.linesz - 1, 1673 PAGE_SIZE - 1); 1674 else 1675 shm_align_mask = PAGE_SIZE-1; 1676 1677 __flush_cache_vmap = r4k__flush_cache_vmap; 1678 __flush_cache_vunmap = r4k__flush_cache_vunmap; 1679 1680 flush_cache_all = cache_noop; 1681 __flush_cache_all = r4k___flush_cache_all; 1682 flush_cache_mm = r4k_flush_cache_mm; 1683 flush_cache_page = r4k_flush_cache_page; 1684 flush_cache_range = r4k_flush_cache_range; 1685 1686 __flush_kernel_vmap_range = r4k_flush_kernel_vmap_range; 1687 1688 flush_cache_sigtramp = r4k_flush_cache_sigtramp; 1689 flush_icache_all = r4k_flush_icache_all; 1690 local_flush_data_cache_page = local_r4k_flush_data_cache_page; 1691 flush_data_cache_page = r4k_flush_data_cache_page; 1692 flush_icache_range = r4k_flush_icache_range; 1693 local_flush_icache_range = local_r4k_flush_icache_range; 1694 1695#if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_DMA_MAYBE_COHERENT) 1696 if (coherentio) { 1697 _dma_cache_wback_inv = (void *)cache_noop; 1698 _dma_cache_wback = (void *)cache_noop; 1699 _dma_cache_inv = (void *)cache_noop; 1700 } else { 1701 _dma_cache_wback_inv = r4k_dma_cache_wback_inv; 1702 _dma_cache_wback = r4k_dma_cache_wback_inv; 1703 _dma_cache_inv = r4k_dma_cache_inv; 1704 } 1705#endif 1706 1707 build_clear_page(); 1708 build_copy_page(); 1709 1710 /* 1711 * We want to run CMP kernels on core with and without coherent 1712 * caches. Therefore, do not use CONFIG_MIPS_CMP to decide whether 1713 * or not to flush caches. 1714 */ 1715 local_r4k___flush_cache_all(NULL); 1716 1717 coherency_setup(); 1718 board_cache_error_setup = r4k_cache_error_setup; 1719 1720 /* 1721 * Per-CPU overrides 1722 */ 1723 switch (current_cpu_type()) { 1724 case CPU_BMIPS4350: 1725 case CPU_BMIPS4380: 1726 /* No IPI is needed because all CPUs share the same D$ */ 1727 flush_data_cache_page = r4k_blast_dcache_page; 1728 break; 1729 case CPU_BMIPS5000: 1730 /* We lose our superpowers if L2 is disabled */ 1731 if (c->scache.flags & MIPS_CACHE_NOT_PRESENT) 1732 break; 1733 1734 /* I$ fills from D$ just by emptying the write buffers */ 1735 flush_cache_page = (void *)b5k_instruction_hazard; 1736 flush_cache_range = (void *)b5k_instruction_hazard; 1737 flush_cache_sigtramp = (void *)b5k_instruction_hazard; 1738 local_flush_data_cache_page = (void *)b5k_instruction_hazard; 1739 flush_data_cache_page = (void *)b5k_instruction_hazard; 1740 flush_icache_range = (void *)b5k_instruction_hazard; 1741 local_flush_icache_range = (void *)b5k_instruction_hazard; 1742 1743 /* Cache aliases are handled in hardware; allow HIGHMEM */ 1744 current_cpu_data.dcache.flags &= ~MIPS_CACHE_ALIASES; 1745 1746 /* Optimization: an L2 flush implicitly flushes the L1 */ 1747 current_cpu_data.options |= MIPS_CPU_INCLUSIVE_CACHES; 1748 break; 1749 } 1750} 1751 1752static int r4k_cache_pm_notifier(struct notifier_block *self, unsigned long cmd, 1753 void *v) 1754{ 1755 switch (cmd) { 1756 case CPU_PM_ENTER_FAILED: 1757 case CPU_PM_EXIT: 1758 coherency_setup(); 1759 break; 1760 } 1761 1762 return NOTIFY_OK; 1763} 1764 1765static struct notifier_block r4k_cache_pm_notifier_block = { 1766 .notifier_call = r4k_cache_pm_notifier, 1767}; 1768 1769int __init r4k_cache_init_pm(void) 1770{ 1771 return cpu_pm_register_notifier(&r4k_cache_pm_notifier_block); 1772} 1773arch_initcall(r4k_cache_init_pm); 1774