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Searched refs:gpu_addr (Results 1 – 55 of 55) sorted by relevance

/linux-4.1.27/drivers/gpu/drm/radeon/
Dr600_dma.c144 upper_32_bits(rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFF); in r600_dma_resume()
146 ((rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFFFFFFFC)); in r600_dma_resume()
151 WREG32(DMA_RB_BASE, ring->gpu_addr >> 8); in r600_dma_resume()
237 u64 gpu_addr; in r600_dma_ring_test() local
244 gpu_addr = rdev->wb.gpu_addr + index; in r600_dma_ring_test()
255 radeon_ring_write(ring, lower_32_bits(gpu_addr)); in r600_dma_ring_test()
256 radeon_ring_write(ring, upper_32_bits(gpu_addr) & 0xff); in r600_dma_ring_test()
291 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in r600_dma_fence_ring_emit()
318 u64 addr = semaphore->gpu_addr; in r600_dma_semaphore_ring_emit()
344 u64 gpu_addr; in r600_dma_ib_test() local
[all …]
Duvd_v2_2.c43 uint64_t addr = rdev->fence_drv[fence->ring].gpu_addr; in uvd_v2_2_fence_emit()
77 uint64_t addr = semaphore->gpu_addr; in uvd_v2_2_semaphore_emit()
113 addr = rdev->uvd.gpu_addr >> 3; in uvd_v2_2_resume()
129 addr = (rdev->uvd.gpu_addr >> 28) & 0xF; in uvd_v2_2_resume()
133 addr = (rdev->uvd.gpu_addr >> 32) & 0xFF; in uvd_v2_2_resume()
Dcik_sdma.c155 radeon_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */ in cik_sdma_ring_ib_execute()
156 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr)); in cik_sdma_ring_ib_execute()
204 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in cik_sdma_fence_ring_emit()
233 u64 addr = semaphore->gpu_addr; in cik_sdma_semaphore_ring_emit()
401 upper_32_bits(rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); in cik_sdma_gfx_resume()
403 ((rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC)); in cik_sdma_gfx_resume()
408 WREG32(SDMA0_GFX_RB_BASE + reg_offset, ring->gpu_addr >> 8); in cik_sdma_gfx_resume()
409 WREG32(SDMA0_GFX_RB_BASE_HI + reg_offset, ring->gpu_addr >> 40); in cik_sdma_gfx_resume()
652 u64 gpu_addr; in cik_sdma_ring_test() local
659 gpu_addr = rdev->wb.gpu_addr + index; in cik_sdma_ring_test()
[all …]
Duvd_v4_2.c44 addr = rdev->uvd.gpu_addr >> 3; in uvd_v4_2_resume()
60 addr = (rdev->uvd.gpu_addr >> 28) & 0xF; in uvd_v4_2_resume()
64 addr = (rdev->uvd.gpu_addr >> 32) & 0xFF; in uvd_v4_2_resume()
Dr600_blit.c77 set_render_target(drm_radeon_private_t *dev_priv, int format, int w, int h, u64 gpu_addr) in set_render_target() argument
97 OUT_RING(gpu_addr >> 8); in set_render_target()
104 OUT_RING(gpu_addr >> 8); in set_render_target()
160 u64 gpu_addr; in set_shaders() local
178 gpu_addr = dev_priv->gart_buffers_offset + dev_priv->blit_vb->offset; in set_shaders()
187 OUT_RING(gpu_addr >> 8); in set_shaders()
200 OUT_RING((gpu_addr + 256) >> 8); in set_shaders()
216 R600_SH_ACTION_ENA, 512, gpu_addr); in set_shaders()
220 set_vtx_resource(drm_radeon_private_t *dev_priv, u64 gpu_addr) in set_vtx_resource() argument
226 sq_vtx_constant_word2 = (((gpu_addr >> 32) & 0xff) | (16 << 8)); in set_vtx_resource()
[all …]
Dvce_v1_0.c103 WREG32(VCE_RB_BASE_LO, ring->gpu_addr); in vce_v1_0_start()
104 WREG32(VCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in vce_v1_0_start()
110 WREG32(VCE_RB_BASE_LO2, ring->gpu_addr); in vce_v1_0_start()
111 WREG32(VCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in vce_v1_0_start()
Dradeon_semaphore.c51 (*semaphore)->gpu_addr = radeon_sa_bo_gpu_addr((*semaphore)->sa_bo); in radeon_semaphore_create()
69 ring->last_semaphore_signal_addr = semaphore->gpu_addr; in radeon_semaphore_emit_signal()
86 ring->last_semaphore_wait_addr = semaphore->gpu_addr; in radeon_semaphore_emit_wait()
Duvd_v1_0.c85 uint64_t addr = rdev->fence_drv[fence->ring].gpu_addr; in uvd_v1_0_fence_emit()
121 addr = (rdev->uvd.gpu_addr >> 3) + 16; in uvd_v1_0_resume()
137 addr = (rdev->uvd.gpu_addr >> 28) & 0xF; in uvd_v1_0_resume()
141 addr = (rdev->uvd.gpu_addr >> 32) & 0xFF; in uvd_v1_0_resume()
363 WREG32(UVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) | in uvd_v1_0_start()
373 WREG32(UVD_RBC_RB_BASE, ring->gpu_addr); in uvd_v1_0_start()
486 radeon_ring_write(ring, ib->gpu_addr); in uvd_v1_0_ib_execute()
Devergreen_dma.c45 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in evergreen_dma_fence_ring_emit()
89 radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0)); in evergreen_dma_ring_ib_execute()
90 radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF)); in evergreen_dma_ring_ib_execute()
Dradeon_trace.h176 __field(uint64_t, gpu_addr)
182 __entry->gpu_addr = sem->gpu_addr;
186 __entry->waiters, __entry->gpu_addr)
Dradeon_object.h135 extern int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr);
137 u64 max_offset, u64 *gpu_addr);
165 return sa_bo->manager->gpu_addr + sa_bo->soffset; in radeon_sa_bo_gpu_addr()
Dni_dma.c145 radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0)); in cayman_dma_ring_ib_execute()
146 radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF)); in cayman_dma_ring_ib_execute()
223 upper_32_bits(rdev->wb.gpu_addr + wb_offset) & 0xFF); in cayman_dma_resume()
225 ((rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC)); in cayman_dma_resume()
230 WREG32(DMA_RB_BASE + reg_offset, ring->gpu_addr >> 8); in cayman_dma_resume()
Dradeon_fence.c812 rdev->fence_drv[ring].gpu_addr = rdev->wb.gpu_addr + in radeon_fence_driver_start_ring()
819 rdev->fence_drv[ring].gpu_addr = rdev->uvd.gpu_addr + index; in radeon_fence_driver_start_ring()
832 rdev->fence_drv[ring].gpu_addr = rdev->wb.gpu_addr + index; in radeon_fence_driver_start_ring()
837 ring, rdev->fence_drv[ring].gpu_addr, rdev->fence_drv[ring].cpu_addr); in radeon_fence_driver_start_ring()
857 rdev->fence_drv[ring].gpu_addr = 0; in radeon_fence_driver_init_ring()
Dradeon_kfd.c39 uint64_t gpu_addr; member
45 void **mem_obj, uint64_t *gpu_addr,
199 void **mem_obj, uint64_t *gpu_addr, in alloc_gtt_mem() argument
207 BUG_ON(gpu_addr == NULL); in alloc_gtt_mem()
230 &(*mem)->gpu_addr); in alloc_gtt_mem()
235 *gpu_addr = (*mem)->gpu_addr; in alloc_gtt_mem()
Dradeon_vce.c144 &rdev->vce.gpu_addr); in radeon_vce_init()
342 dummy = ib.gpu_addr + 1024; in radeon_vce_get_create_msg()
409 dummy = ib.gpu_addr + 1024; in radeon_vce_get_destroy_msg()
682 uint64_t addr = semaphore->gpu_addr; in radeon_vce_semaphore_emit()
705 radeon_ring_write(ring, ib->gpu_addr); in radeon_vce_ib_execute()
706 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr)); in radeon_vce_ib_execute()
721 uint64_t addr = rdev->fence_drv[fence->ring].gpu_addr; in radeon_vce_fence_emit()
Dradeon_object.c323 u64 *gpu_addr) in radeon_bo_pin_restricted() argument
332 if (gpu_addr) in radeon_bo_pin_restricted()
333 *gpu_addr = radeon_bo_gpu_offset(bo); in radeon_bo_pin_restricted()
365 if (gpu_addr != NULL) in radeon_bo_pin_restricted()
366 *gpu_addr = radeon_bo_gpu_offset(bo); in radeon_bo_pin_restricted()
377 int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr) in radeon_bo_pin() argument
379 return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr); in radeon_bo_pin()
Dradeon_gart.c151 uint64_t gpu_addr; in radeon_gart_table_vram_pin() local
158 RADEON_GEM_DOMAIN_VRAM, &gpu_addr); in radeon_gart_table_vram_pin()
167 rdev->gart.table_addr = gpu_addr; in radeon_gart_table_vram_pin()
Duvd_v3_1.c45 uint64_t addr = semaphore->gpu_addr; in uvd_v3_1_semaphore_emit()
Dradeon_ib.c77 ib->gpu_addr = ib->sa_bo->soffset + RADEON_VA_IB_OFFSET; in radeon_ib_get()
79 ib->gpu_addr = radeon_sa_bo_gpu_addr(ib->sa_bo); in radeon_ib_get()
Dradeon_sa.c112 r = radeon_bo_pin(sa_manager->bo, sa_manager->domain, &sa_manager->gpu_addr); in radeon_sa_bo_manager_start()
407 uint64_t soffset = i->soffset + sa_manager->gpu_addr; in radeon_sa_bo_dump_debug_info()
408 uint64_t eoffset = i->eoffset + sa_manager->gpu_addr; in radeon_sa_bo_dump_debug_info()
Dradeon_uvd.c159 &rdev->uvd.gpu_addr); in radeon_uvd_init()
581 (start >> 28) != (p->rdev->uvd.gpu_addr >> 28)) { in radeon_uvd_cs_reloc()
736 uint64_t addr = rdev->uvd.gpu_addr + offs; in radeon_uvd_get_create_msg()
772 uint64_t addr = rdev->uvd.gpu_addr + offs; in radeon_uvd_get_destroy_msg()
Dvce_v2_0.c145 uint64_t addr = rdev->vce.gpu_addr; in vce_v2_0_resume()
Dradeon_ring.c396 &ring->gpu_addr); in radeon_ring_init()
414 ring->next_rptr_gpu_addr = rdev->wb.gpu_addr + index; in radeon_ring_init()
Dr600.c1289 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12); in r600_mc_program()
1470 RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr); in r600_vram_scratch_init()
2699 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC)); in r600_cp_resume()
2700 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); in r600_cp_resume()
2701 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); in r600_cp_resume()
2713 WREG32(CP_RB_BASE, ring->gpu_addr >> 8); in r600_cp_resume()
2828 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in r600_fence_ring_emit()
2881 uint64_t addr = semaphore->gpu_addr; in r600_semaphore_ring_emit()
3304 (ib->gpu_addr & 0xFFFFFFFC)); in r600_ring_ib_execute()
3305 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF); in r600_ring_ib_execute()
[all …]
Dradeon.h357 uint64_t gpu_addr; member
547 uint64_t gpu_addr; member
593 uint64_t gpu_addr; member
839 uint64_t gpu_addr; member
862 uint64_t gpu_addr; member
986 uint64_t gpu_addr; member
1142 uint64_t gpu_addr; member
1677 uint64_t gpu_addr; member
1719 uint64_t gpu_addr; member
2253 u64 gpu_addr; member
Dni.c1387 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in cayman_fence_ring_emit()
1430 (ib->gpu_addr & 0xFFFFFFFC)); in cayman_ring_ib_execute()
1431 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF); in cayman_ring_ib_execute()
1666 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); in cayman_cp_resume()
1683 addr = rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET; in cayman_cp_resume()
1691 WREG32(cp_rb_base[i], ring->gpu_addr >> 8); in cayman_cp_resume()
Dsi.c3372 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in si_fence_ring_emit()
3435 (ib->gpu_addr & 0xFFFFFFFC)); in si_ring_ib_execute()
3436 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); in si_ring_ib_execute()
3658 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); in si_cp_resume()
3676 WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC); in si_cp_resume()
3677 WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); in si_cp_resume()
3689 WREG32(CP_RB0_BASE, ring->gpu_addr >> 8); in si_cp_resume()
3707 WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC); in si_cp_resume()
3708 WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF); in si_cp_resume()
3713 WREG32(CP_RB1_BASE, ring->gpu_addr >> 8); in si_cp_resume()
[all …]
Dcik.c3941 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in cik_fence_gfx_ring_emit()
3982 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in cik_fence_compute_ring_emit()
4013 uint64_t addr = semaphore->gpu_addr; in cik_semaphore_ring_emit()
4155 (ib->gpu_addr & 0xFFFFFFFC)); in cik_ring_ib_execute()
4156 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); in cik_ring_ib_execute()
4458 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); in cik_cp_gfx_resume()
4476 WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC); in cik_cp_gfx_resume()
4477 WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); in cik_cp_gfx_resume()
4488 rb_addr = ring->gpu_addr >> 8; in cik_cp_gfx_resume()
5043 hqd_gpu_addr = rdev->ring[idx].gpu_addr >> 8; in cik_cp_compute_resume()
[all …]
Devergreen.c2934 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12); in evergreen_mc_program()
3000 (ib->gpu_addr & 0xFFFFFFFC)); in evergreen_ring_ib_execute()
3001 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF); in evergreen_ring_ib_execute()
3144 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC)); in evergreen_cp_resume()
3145 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); in evergreen_cp_resume()
3146 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); in evergreen_cp_resume()
3158 WREG32(CP_RB_BASE, ring->gpu_addr >> 8); in evergreen_cp_resume()
Dr100.c1177 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr); in r100_cp_init()
1178 WREG32(RADEON_CP_RB_BASE, ring->gpu_addr); in r100_cp_init()
1187 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2)); in r100_cp_init()
1188 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET); in r100_cp_init()
3687 radeon_ring_write(ring, ib->gpu_addr); in r100_ring_ib_execute()
Dradeon_device.c480 &rdev->wb.gpu_addr); in radeon_wb_init()
Drv770.c1048 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12); in rv770_mc_program()
/linux-4.1.27/drivers/gpu/drm/mgag200/
Dmgag200_cursor.c53 u64 gpu_addr; in mga_crtc_cursor_set() local
225 gpu_addr = mdev->cursor.pixels_1_gpu_addr; in mga_crtc_cursor_set()
227 gpu_addr = mdev->cursor.pixels_2_gpu_addr; in mga_crtc_cursor_set()
228 WREG_DAC(MGA1064_CURSOR_BASE_ADR_LOW, (u8)((gpu_addr>>10) & 0xff)); in mga_crtc_cursor_set()
229 WREG_DAC(MGA1064_CURSOR_BASE_ADR_HI, (u8)((gpu_addr>>18) & 0x3f)); in mga_crtc_cursor_set()
Dmgag200_ttm.c355 int mgag200_bo_pin(struct mgag200_bo *bo, u32 pl_flag, u64 *gpu_addr) in mgag200_bo_pin() argument
361 if (gpu_addr) in mgag200_bo_pin()
362 *gpu_addr = mgag200_bo_gpu_offset(bo); in mgag200_bo_pin()
374 if (gpu_addr) in mgag200_bo_pin()
375 *gpu_addr = mgag200_bo_gpu_offset(bo); in mgag200_bo_pin()
Dmgag200_drv.h302 int mgag200_bo_pin(struct mgag200_bo *bo, u32 pl_flag, u64 *gpu_addr);
Dmgag200_mode.c732 u64 gpu_addr; in mga_crtc_do_set_base() local
754 ret = mgag200_bo_pin(bo, TTM_PL_FLAG_VRAM, &gpu_addr); in mga_crtc_do_set_base()
769 mga_set_start_address(crtc, (u32)gpu_addr); in mga_crtc_do_set_base()
/linux-4.1.27/drivers/gpu/drm/qxl/
Dqxl_object.c227 int qxl_bo_pin(struct qxl_bo *bo, u32 domain, u64 *gpu_addr) in qxl_bo_pin() argument
234 if (gpu_addr) in qxl_bo_pin()
235 *gpu_addr = qxl_bo_gpu_offset(bo); in qxl_bo_pin()
242 if (gpu_addr != NULL) in qxl_bo_pin()
243 *gpu_addr = qxl_bo_gpu_offset(bo); in qxl_bo_pin()
Dqxl_object.h98 extern int qxl_bo_pin(struct qxl_bo *bo, u32 domain, u64 *gpu_addr);
/linux-4.1.27/drivers/gpu/drm/cirrus/
Dcirrus_ttm.c359 int cirrus_bo_pin(struct cirrus_bo *bo, u32 pl_flag, u64 *gpu_addr) in cirrus_bo_pin() argument
365 if (gpu_addr) in cirrus_bo_pin()
366 *gpu_addr = cirrus_bo_gpu_offset(bo); in cirrus_bo_pin()
377 if (gpu_addr) in cirrus_bo_pin()
378 *gpu_addr = cirrus_bo_gpu_offset(bo); in cirrus_bo_pin()
Dcirrus_mode.c139 u64 gpu_addr; in cirrus_crtc_do_set_base() local
161 ret = cirrus_bo_pin(bo, TTM_PL_FLAG_VRAM, &gpu_addr); in cirrus_crtc_do_set_base()
175 cirrus_set_start_address(crtc, (u32)gpu_addr); in cirrus_crtc_do_set_base()
Dcirrus_drv.h264 int cirrus_bo_pin(struct cirrus_bo *bo, u32 pl_flag, u64 *gpu_addr);
/linux-4.1.27/drivers/gpu/drm/ast/
Dast_ttm.c355 int ast_bo_pin(struct ast_bo *bo, u32 pl_flag, u64 *gpu_addr) in ast_bo_pin() argument
361 if (gpu_addr) in ast_bo_pin()
362 *gpu_addr = ast_bo_gpu_offset(bo); in ast_bo_pin()
373 if (gpu_addr) in ast_bo_pin()
374 *gpu_addr = ast_bo_gpu_offset(bo); in ast_bo_pin()
Dast_mode.c517 u64 gpu_addr; in ast_crtc_do_set_base() local
539 ret = ast_bo_pin(bo, TTM_PL_FLAG_VRAM, &gpu_addr); in ast_crtc_do_set_base()
553 ast_set_start_address_crt1(crtc, (u32)gpu_addr); in ast_crtc_do_set_base()
913 uint64_t gpu_addr; in ast_cursor_init() local
925 ret = ast_bo_pin(bo, TTM_PL_FLAG_VRAM, &gpu_addr); in ast_cursor_init()
936 ast->cursor_cache_gpu_addr = gpu_addr; in ast_cursor_init()
1144 uint64_t gpu_addr; in ast_cursor_set() local
1196 gpu_addr = ast->cursor_cache_gpu_addr; in ast_cursor_set()
1197 gpu_addr += (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE)*ast->next_cursor; in ast_cursor_set()
1198 gpu_addr >>= 3; in ast_cursor_set()
[all …]
Dast_drv.h363 int ast_bo_pin(struct ast_bo *bo, u32 pl_flag, u64 *gpu_addr);
/linux-4.1.27/drivers/gpu/drm/amd/amdkfd/
Dkfd_kernel_queue.c84 kq->pq_gpu_addr = kq->pq->gpu_addr; in initialize()
97 kq->rptr_gpu_addr = kq->rptr_mem->gpu_addr; in initialize()
106 kq->wptr_gpu_addr = kq->wptr_mem->gpu_addr; in initialize()
154 kq->fence_gpu_addr = kq->fence_mem_obj->gpu_addr; in initialize()
Dkfd_kernel_queue_vi.c45 kq->eop_gpu_addr = kq->eop_mem->gpu_addr; in initialize_vi()
Dkfd_mqd_manager_cik.c55 addr = (*mqd_mem_obj)->gpu_addr; in init_mqd()
130 *gart_addr = (*mqd_mem_obj)->gpu_addr; in init_mqd_sdma()
307 addr = (*mqd_mem_obj)->gpu_addr; in init_mqd_hiq()
Dkfd_device.c428 (*mem_obj)->gpu_addr = kfd_gtt_sa_calc_gpu_addr( in kfd_gtt_sa_allocate()
438 (uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr); in kfd_gtt_sa_allocate()
Dkfd_priv.h122 uint64_t gpu_addr; member
Dkfd_device_queue_manager.c500 dqm->pipelines_addr = dqm->pipeline_mem->gpu_addr; in init_pipelines()
753 dqm->fence_gpu_addr = dqm->fence_mem->gpu_addr; in start_cpsch()
Dkfd_packet_manager.c109 *rl_gpu_buffer = pm->ib_buffer_obj->gpu_addr; in pm_allocate_runlist_ib()
/linux-4.1.27/drivers/gpu/drm/bochs/
Dbochs_mm.c290 int bochs_bo_pin(struct bochs_bo *bo, u32 pl_flag, u64 *gpu_addr) in bochs_bo_pin() argument
296 if (gpu_addr) in bochs_bo_pin()
297 *gpu_addr = bochs_bo_gpu_offset(bo); in bochs_bo_pin()
309 if (gpu_addr) in bochs_bo_pin()
310 *gpu_addr = bochs_bo_gpu_offset(bo); in bochs_bo_pin()
Dbochs_kms.c47 u64 gpu_addr = 0; in bochs_crtc_mode_set_base() local
71 ret = bochs_bo_pin(bo, TTM_PL_FLAG_VRAM, &gpu_addr); in bochs_crtc_mode_set_base()
78 bochs_hw_setbase(bochs, x, y, gpu_addr); in bochs_crtc_mode_set_base()
Dbochs.h154 int bochs_bo_pin(struct bochs_bo *bo, u32 pl_flag, u64 *gpu_addr);
/linux-4.1.27/drivers/gpu/drm/amd/include/
Dkgd_kfd_interface.h126 void **mem_obj, uint64_t *gpu_addr,