3941 	u64 addr = rdev->fence_drv[fence->ring].gpu_addr;  in cik_fence_gfx_ring_emit()
3982 	u64 addr = rdev->fence_drv[fence->ring].gpu_addr;  in cik_fence_compute_ring_emit()
4013 	uint64_t addr = semaphore->gpu_addr;  in cik_semaphore_ring_emit()
4155 			  (ib->gpu_addr & 0xFFFFFFFC));  in cik_ring_ib_execute()
4156 	radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);  in cik_ring_ib_execute()
4458 	WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);  in cik_cp_gfx_resume()
4476 	WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);  in cik_cp_gfx_resume()
4477 	WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);  in cik_cp_gfx_resume()
4488 	rb_addr = ring->gpu_addr >> 8;  in cik_cp_gfx_resume()
5043 		hqd_gpu_addr = rdev->ring[idx].gpu_addr >> 8;  in cik_cp_compute_resume()
5069 			wb_gpu_addr = rdev->wb.gpu_addr + CIK_WB_CP1_WPTR_OFFSET;  in cik_cp_compute_resume()
5071 			wb_gpu_addr = rdev->wb.gpu_addr + CIK_WB_CP2_WPTR_OFFSET;  in cik_cp_compute_resume()
5080 			wb_gpu_addr = rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET;  in cik_cp_compute_resume()
5082 			wb_gpu_addr = rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET;  in cik_cp_compute_resume()
5685 	       rdev->vram_scratch.gpu_addr >> 12);  in cik_mc_program()
7382 	WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);  in cik_irq_init()
7392 	WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);  in cik_irq_init()
7403 	WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);  in cik_irq_init()
7404 	WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);  in cik_irq_init()