Searched refs:chid (Results 1 - 60 of 60) sorted by relevance

/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
H A Dnv04.c60 u32 context, chid = chan->base.chid; nv04_fifo_object_attach() local
84 context |= chid << 24; nv04_fifo_object_attach()
87 ret = nvkm_ramht_insert(priv->ramht, chid, handle, context); nv04_fifo_object_attach()
105 nv_engctx(object)->addr = nvkm_fifo_chan(parent)->chid; nv04_fifo_context_attach()
139 args->v0.chid = chan->base.chid; nv04_fifo_chan_ctor()
144 chan->ramfc = chan->base.chid * 32; nv04_fifo_chan_ctor()
178 u32 mask = 1 << chan->base.chid; nv04_fifo_chan_init()
201 u32 chid; nv04_fifo_chan_fini() local
208 chid = nv_rd32(priv, NV03_PFIFO_CACHE1_PUSH1) & priv->base.max; nv04_fifo_chan_fini()
209 if (chid == chan->base.chid) { nv04_fifo_chan_fini()
236 nv_mask(priv, NV04_PFIFO_MODE, 1 << chan->base.chid, 0); nv04_fifo_chan_fini()
357 nv04_fifo_swmthd(struct nv04_fifo_priv *priv, u32 chid, u32 addr, u32 data) nv04_fifo_swmthd() argument
368 if (likely(chid >= priv->base.min && chid <= priv->base.max)) nv04_fifo_swmthd()
369 chan = (void *)priv->base.channel[chid]; nv04_fifo_swmthd()
410 struct nv04_fifo_priv *priv, u32 chid, u32 get) nv04_fifo_cache_error()
430 if (!nv04_fifo_swmthd(priv, chid, mthd, data)) { nv04_fifo_cache_error()
432 nvkm_client_name_for_fifo_chid(&priv->base, chid); nv04_fifo_cache_error()
435 chid, client_name, (mthd >> 13) & 7, mthd & 0x1ffc, nv04_fifo_cache_error()
456 struct nv04_fifo_priv *priv, u32 chid) nv04_fifo_dma_pusher()
464 client_name = nvkm_client_name_for_fifo_chid(&priv->base, chid); nv04_fifo_dma_pusher()
474 chid, client_name, ho_get, dma_get, ho_put, dma_put, nv04_fifo_dma_pusher()
488 chid, client_name, dma_get, dma_put, state, nv04_fifo_dma_pusher()
507 u32 reassign, chid, get, sem; nv04_fifo_intr() local
512 chid = nv_rd32(priv, NV03_PFIFO_CACHE1_PUSH1) & priv->base.max; nv04_fifo_intr()
516 nv04_fifo_cache_error(device, priv, chid, get); nv04_fifo_intr()
521 nv04_fifo_dma_pusher(device, priv, chid); nv04_fifo_intr()
409 nv04_fifo_cache_error(struct nvkm_device *device, struct nv04_fifo_priv *priv, u32 chid, u32 get) nv04_fifo_cache_error() argument
455 nv04_fifo_dma_pusher(struct nvkm_device *device, struct nv04_fifo_priv *priv, u32 chid) nv04_fifo_dma_pusher() argument
H A Dbase.c95 for (chan->chid = priv->min; chan->chid < priv->max; chan->chid++) { nvkm_fifo_channel_create_()
96 if (!priv->channel[chan->chid]) { nvkm_fifo_channel_create_()
97 priv->channel[chan->chid] = nv_object(chan); nvkm_fifo_channel_create_()
103 if (chan->chid == priv->max) { nvkm_fifo_channel_create_()
109 addr + size * chan->chid; nvkm_fifo_channel_create_()
125 priv->channel[chan->chid] = NULL; nvkm_fifo_channel_destroy()
225 return nvkm_fifo_chan(object)->chid; nvkm_fifo_chid()
233 nvkm_client_name_for_fifo_chid(struct nvkm_fifo *fifo, u32 chid) nvkm_client_name_for_fifo_chid() argument
239 if (chid >= fifo->min && chid <= fifo->max) nvkm_client_name_for_fifo_chid()
240 chan = (void *)fifo->channel[chid]; nvkm_client_name_for_fifo_chid()
279 priv->chid = nvkm_fifo_chid; nvkm_fifo_create_()
H A Dnv40.c73 u32 context, chid = chan->base.chid; nv40_fifo_object_attach() local
96 context |= chid << 23; nv40_fifo_object_attach()
99 ret = nvkm_ramht_insert(priv->ramht, chid, handle, context); nv40_fifo_object_attach()
131 if ((nv_rd32(priv, 0x003204) & priv->base.max) == chan->base.chid) nv40_fifo_context_attach()
167 if ((nv_rd32(priv, 0x003204) & priv->base.max) == chan->base.chid) nv40_fifo_context_detach()
206 args->v0.chid = chan->base.chid; nv40_fifo_chan_ctor()
212 chan->ramfc = chan->base.chid * 128; nv40_fifo_chan_ctor()
H A Dgk104.c191 nv_wr32(priv, 0x002634, chan->base.chid); gk104_fifo_context_detach()
192 if (!nv_wait(priv, 0x002634, 0xffffffff, chan->base.chid)) { gk104_fifo_context_detach()
194 chan->base.chid, nvkm_client_name(chan)); gk104_fifo_context_detach()
254 args->v0.chid = chan->base.chid; gk104_fifo_chan_ctor()
260 usermem = chan->base.chid * 0x200; gk104_fifo_chan_ctor()
277 nv_wo32(base, 0xe8, chan->base.chid); gk104_fifo_chan_ctor()
291 u32 chid = chan->base.chid; gk104_fifo_chan_init() local
298 nv_mask(priv, 0x800004 + (chid * 8), 0x000f0000, chan->engine << 16); gk104_fifo_chan_init()
299 nv_wr32(priv, 0x800000 + (chid * 8), 0x80000000 | base->addr >> 12); gk104_fifo_chan_init()
302 nv_mask(priv, 0x800004 + (chid * 8), 0x00000400, 0x00000400); gk104_fifo_chan_init()
304 nv_mask(priv, 0x800004 + (chid * 8), 0x00000400, 0x00000400); gk104_fifo_chan_init()
315 u32 chid = chan->base.chid; gk104_fifo_chan_fini() local
318 nv_mask(priv, 0x800004 + (chid * 8), 0x00000800, 0x00000800); gk104_fifo_chan_fini()
322 nv_wr32(priv, 0x800000 + (chid * 8), 0x00000000); gk104_fifo_chan_fini()
466 u32 chid = chan->base.chid; gk104_fifo_recover() local
470 nv_subdev(engine)->name, chid); gk104_fifo_recover()
472 nv_mask(priv, 0x800004 + (chid * 0x08), 0x00000800, 0x00000800); gk104_fifo_recover()
482 gk104_fifo_swmthd(struct gk104_fifo_priv *priv, u32 chid, u32 mthd, u32 data) gk104_fifo_swmthd() argument
490 if (likely(chid >= priv->base.min && chid <= priv->base.max)) gk104_fifo_swmthd()
491 chan = (void *)priv->base.channel[chid]; gk104_fifo_swmthd()
554 u32 chid = load ? next : prev; gk104_fifo_intr_sched_ctxsw() local
558 if (!(chan = (void *)priv->base.channel[chid])) gk104_fifo_intr_sched_ctxsw()
828 u32 chid = nv_rd32(priv, 0x040120 + (unit * 0x2000)) & 0xfff; gk104_fifo_intr_pbdma_0() local
834 if (!gk104_fifo_swmthd(priv, chid, mthd, data)) gk104_fifo_intr_pbdma_0()
845 unit, chid, gk104_fifo_intr_pbdma_0()
846 nvkm_client_name_for_fifo_chid(&priv->base, chid), gk104_fifo_intr_pbdma_0()
867 u32 chid = nv_rd32(priv, 0x040120 + (unit * 0x2000)) & 0xfff; gk104_fifo_intr_pbdma_1() local
873 nv_error(priv, "PBDMA%d: ch %d %08x %08x\n", unit, chid, gk104_fifo_intr_pbdma_1()
H A Dgf100.c166 nv_wr32(priv, 0x002634, chan->base.chid); gf100_fifo_context_detach()
167 if (!nv_wait(priv, 0x002634, 0xffffffff, chan->base.chid)) { gf100_fifo_context_detach()
169 chan->base.chid, nvkm_client_name(chan)); gf100_fifo_context_detach()
218 args->v0.chid = chan->base.chid; gf100_fifo_chan_ctor()
223 usermem = chan->base.chid * 0x1000; gf100_fifo_chan_ctor()
256 u32 chid = chan->base.chid; gf100_fifo_chan_init() local
263 nv_wr32(priv, 0x003000 + (chid * 8), 0xc0000000 | base->addr >> 12); gf100_fifo_chan_init()
266 nv_wr32(priv, 0x003004 + (chid * 8), 0x001f0001); gf100_fifo_chan_init()
280 u32 chid = chan->base.chid; gf100_fifo_chan_fini() local
283 nv_mask(priv, 0x003004 + (chid * 8), 0x00000001, 0x00000000); gf100_fifo_chan_fini()
289 nv_wr32(priv, 0x003000 + (chid * 8), 0x00000000); gf100_fifo_chan_fini()
441 u32 chid = chan->base.chid; gf100_fifo_recover() local
445 nv_subdev(engine)->name, chid); gf100_fifo_recover()
447 nv_mask(priv, 0x003004 + (chid * 0x08), 0x00000001, 0x00000000); gf100_fifo_recover()
457 gf100_fifo_swmthd(struct gf100_fifo_priv *priv, u32 chid, u32 mthd, u32 data) gf100_fifo_swmthd() argument
465 if (likely(chid >= priv->base.min && chid <= priv->base.max)) gf100_fifo_swmthd()
466 chan = (void *)priv->base.channel[chid]; gf100_fifo_swmthd()
501 u32 chid = (stat & 0x0000007f); gf100_fifo_intr_sched_ctxsw() local
505 if (!(chan = (void *)priv->base.channel[chid])) gf100_fifo_intr_sched_ctxsw()
686 u32 chid = nv_rd32(priv, 0x040120 + (unit * 0x2000)) & 0x7f; gf100_fifo_intr_pbdma() local
692 if (!gf100_fifo_swmthd(priv, chid, mthd, data)) gf100_fifo_intr_pbdma()
702 unit, chid, gf100_fifo_intr_pbdma()
703 nvkm_client_name_for_fifo_chid(&priv->base, chid), gf100_fifo_intr_pbdma()
H A Dnv50.c138 chan->base.chid, nvkm_client_name(chan)); nv50_fifo_context_detach()
219 args->v0.chid = chan->base.chid; nv50_fifo_chan_ctor_dma()
282 args->v0.chid = chan->base.chid; nv50_fifo_chan_ctor_ind()
327 u32 chid = chan->base.chid; nv50_fifo_chan_init() local
334 nv_wr32(priv, 0x002600 + (chid * 4), 0x80000000 | ramfc->addr >> 12); nv50_fifo_chan_init()
344 u32 chid = chan->base.chid; nv50_fifo_chan_fini() local
347 nv_mask(priv, 0x002600 + (chid * 4), 0x80000000, 0x00000000); nv50_fifo_chan_fini()
349 nv_wr32(priv, 0x002600 + (chid * 4), 0x00000000); nv50_fifo_chan_fini()
H A Dnv10.c82 args->v0.chid = chan->base.chid; nv10_fifo_chan_ctor()
87 chan->ramfc = chan->base.chid * 32; nv10_fifo_chan_ctor()
H A Dnv17.c89 args->v0.chid = chan->base.chid; nv17_fifo_chan_ctor()
94 chan->ramfc = chan->base.chid * 64; nv17_fifo_chan_ctor()
H A Dg84.c112 chan->base.chid, nvkm_client_name(chan)); g84_fifo_context_detach()
202 args->v0.chid = chan->base.chid; g84_fifo_chan_ctor_dma()
277 args->v0.chid = chan->base.chid; g84_fifo_chan_ctor_ind()
316 u32 chid = chan->base.chid; g84_fifo_chan_init() local
323 nv_wr32(priv, 0x002600 + (chid * 4), 0x80000000 | ramfc->addr >> 8); g84_fifo_chan_init()
/linux-4.1.27/drivers/gpu/drm/nouveau/include/nvkm/core/
H A Dramht.h10 int nvkm_ramht_insert(struct nvkm_ramht *, int chid, u32 handle, u32 context);
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dnv20.h12 int chid; member in struct:nv20_gr_chan
H A Dnv20.c53 chan->chid = nvkm_fifo_chan(parent)->chid; nv20_gr_context_ctor()
55 nv_wo32(chan, 0x0000, 0x00000001 | (chan->chid << 24)); nv20_gr_context_ctor()
113 nv_wo32(priv->ctxtab, chan->chid * 4, nv_gpuobj(chan)->addr >> 4); nv20_gr_context_init()
122 int chid = -1; nv20_gr_context_fini() local
126 chid = (nv_rd32(priv, 0x400148) & 0x1f000000) >> 24; nv20_gr_context_fini()
127 if (chan->chid == chid) { nv20_gr_context_fini()
136 nv_wo32(priv->ctxtab, chan->chid * 4, 0x00000000); nv20_gr_context_fini()
199 u32 chid = (addr & 0x01f00000) >> 20; nv20_gr_intr() local
206 engctx = nvkm_engctx_get(engine, chid); nv20_gr_intr()
229 chid, nvkm_client_name(engctx), subc, class, mthd, nv20_gr_intr()
H A Dnv2a.c24 chan->chid = nvkm_fifo_chan(parent)->chid; nv2a_gr_context_ctor()
26 nv_wo32(chan, 0x0000, 0x00000001 | (chan->chid << 24)); nv2a_gr_context_ctor()
H A Dnv25.c48 chan->chid = nvkm_fifo_chan(parent)->chid; nv25_gr_context_ctor()
50 nv_wo32(chan, 0x0028, 0x00000001 | (chan->chid << 24)); nv25_gr_context_ctor()
H A Dnv34.c50 chan->chid = nvkm_fifo_chan(parent)->chid; nv34_gr_context_ctor()
52 nv_wo32(chan, 0x0028, 0x00000001 | (chan->chid << 24)); nv34_gr_context_ctor()
H A Dnv35.c50 chan->chid = nvkm_fifo_chan(parent)->chid; nv35_gr_context_ctor()
52 nv_wo32(chan, 0x0028, 0x00000001 | (chan->chid << 24)); nv35_gr_context_ctor()
H A Dnv10.c397 int chid; member in struct:nv10_gr_chan
610 int chid = nv_rd32(priv, 0x400148) >> 24; nv10_gr_channel() local
611 if (chid < ARRAY_SIZE(priv->chan)) nv10_gr_channel()
612 chan = priv->chan[chid]; nv10_gr_channel()
865 nv10_gr_load_dma_vtxbuf(struct nv10_gr_chan *chan, int chid, u32 inst) nv10_gr_load_dma_vtxbuf() argument
913 0x2c000000 | chid << 20 | subchan << 16 | 0x18c); nv10_gr_load_dma_vtxbuf()
935 nv10_gr_load_context(struct nv10_gr_chan *chan, int chid) nv10_gr_load_context() argument
953 nv10_gr_load_dma_vtxbuf(chan, chid, inst); nv10_gr_load_context()
956 nv_mask(priv, NV10_PGRAPH_CTX_USER, 0xff000000, chid << 24); nv10_gr_load_context()
989 int chid; nv10_gr_context_switch() local
1000 chid = (nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR) >> 20) & 0x1f; nv10_gr_context_switch()
1001 next = priv->chan[chid]; nv10_gr_context_switch()
1003 nv10_gr_load_context(next, chid); nv10_gr_context_switch()
1037 if (priv->chan[fifo->chid]) { nv10_gr_context_ctor()
1038 *pobject = nv_object(priv->chan[fifo->chid]); nv10_gr_context_ctor()
1063 NV_WRITE_CTX(NV10_PGRAPH_CTX_USER, chan->chid << 24); nv10_gr_context_ctor()
1067 priv->chan[fifo->chid] = chan; nv10_gr_context_ctor()
1068 chan->chid = fifo->chid; nv10_gr_context_ctor()
1081 priv->chan[chan->chid] = NULL; nv10_gr_context_dtor()
1162 u32 chid = (addr & 0x01f00000) >> 20; nv10_gr_intr() local
1171 chan = priv->chan[chid]; nv10_gr_intr()
1204 chid, nvkm_client_name(chan), subc, class, mthd, nv10_gr_intr()
H A Dnv04.c357 int chid; member in struct:nv04_gr_chan
1039 int chid = nv_rd32(priv, NV04_PGRAPH_CTX_USER) >> 24; nv04_gr_channel() local
1040 if (chid < ARRAY_SIZE(priv->chan)) nv04_gr_channel()
1041 chan = priv->chan[chid]; nv04_gr_channel()
1047 nv04_gr_load_context(struct nv04_gr_chan *chan, int chid) nv04_gr_load_context() argument
1056 nv_mask(priv, NV04_PGRAPH_CTX_USER, 0xff000000, chid << 24); nv04_gr_load_context()
1081 int chid; nv04_gr_context_switch() local
1092 chid = (nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR) >> 24) & 0x0f; nv04_gr_context_switch()
1093 next = priv->chan[chid]; nv04_gr_context_switch()
1095 nv04_gr_load_context(next, chid); nv04_gr_context_switch()
1130 if (priv->chan[fifo->chid]) { nv04_gr_context_ctor()
1131 *pobject = nv_object(priv->chan[fifo->chid]); nv04_gr_context_ctor()
1140 priv->chan[fifo->chid] = chan; nv04_gr_context_ctor()
1141 chan->chid = fifo->chid; nv04_gr_context_ctor()
1154 priv->chan[chan->chid] = NULL; nv04_gr_context_dtor()
1260 u32 chid = (addr & 0x0f000000) >> 24; nv04_gr_intr() local
1270 chan = priv->chan[chid]; nv04_gr_intr()
1303 chid, nvkm_client_name(chan), subc, class, mthd, nv04_gr_intr()
H A Dnv50.c574 int chid, u64 inst, struct nvkm_object *engctx) nv50_gr_trap_handler()
609 chid, inst, nv50_gr_trap_handler()
634 chid, inst, nv50_gr_trap_handler()
799 int chid; nv50_gr_intr() local
802 chid = pfifo->chid(pfifo, engctx); nv50_gr_intr()
820 if (!nv50_gr_trap_handler(priv, show, chid, (u64)inst << 12, nv50_gr_intr()
838 chid, (u64)inst << 12, nvkm_client_name(engctx), nv50_gr_intr()
573 nv50_gr_trap_handler(struct nv50_gr_priv *priv, u32 display, int chid, u64 inst, struct nvkm_object *engctx) nv50_gr_trap_handler() argument
H A Dnv30.c52 chan->chid = nvkm_fifo_chan(parent)->chid; nv30_gr_context_ctor()
54 nv_wo32(chan, 0x0028, 0x00000001 | (chan->chid << 24)); nv30_gr_context_ctor()
H A Dnv40.c301 int chid; nv40_gr_intr() local
304 chid = pfifo->chid(pfifo, engctx); nv40_gr_intr()
332 chid, inst << 4, nvkm_client_name(engctx), subc, nv40_gr_intr()
H A Dgf100.c1121 int chid; gf100_gr_intr() local
1129 chid = pfifo->chid(pfifo, engctx); gf100_gr_intr()
1145 chid, inst << 12, nvkm_client_name(engctx), gf100_gr_intr()
1156 chid, inst << 12, nvkm_client_name(engctx), subc, gf100_gr_intr()
1166 chid, inst << 12, nvkm_client_name(engctx), subc, gf100_gr_intr()
1173 nv_error(priv, "TRAP ch %d [0x%010llx %s]\n", chid, inst << 12, gf100_gr_intr()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A Dgf110.c80 u32 data = (chan->chid << 27) | (addr << 9) | 0x00000001; gf110_disp_dmac_object_attach()
81 return nvkm_ramht_insert(base->ramht, chan->chid, name, data); gf110_disp_dmac_object_attach()
96 int chid = dmac->base.chid; gf110_disp_dmac_init() local
104 nv_mask(priv, 0x6100a0, 0x00000001 << chid, 0x00000001 << chid); gf110_disp_dmac_init()
107 nv_wr32(priv, 0x610494 + (chid * 0x0010), dmac->push); gf110_disp_dmac_init()
108 nv_wr32(priv, 0x610498 + (chid * 0x0010), 0x00010000); gf110_disp_dmac_init()
109 nv_wr32(priv, 0x61049c + (chid * 0x0010), 0x00000001); gf110_disp_dmac_init()
110 nv_mask(priv, 0x610490 + (chid * 0x0010), 0x00000010, 0x00000010); gf110_disp_dmac_init()
111 nv_wr32(priv, 0x640000 + (chid * 0x1000), 0x00000000); gf110_disp_dmac_init()
112 nv_wr32(priv, 0x610490 + (chid * 0x0010), 0x00000013); gf110_disp_dmac_init()
115 if (!nv_wait(priv, 0x610490 + (chid * 0x10), 0x80000000, 0x00000000)) { gf110_disp_dmac_init()
117 nv_rd32(priv, 0x610490 + (chid * 0x10))); gf110_disp_dmac_init()
129 int chid = dmac->base.chid; gf110_disp_dmac_fini() local
132 nv_mask(priv, 0x610490 + (chid * 0x0010), 0x00001010, 0x00001000); gf110_disp_dmac_fini()
133 nv_mask(priv, 0x610490 + (chid * 0x0010), 0x00000003, 0x00000000); gf110_disp_dmac_fini()
134 if (!nv_wait(priv, 0x610490 + (chid * 0x10), 0x001e0000, 0x00000000)) { gf110_disp_dmac_fini()
136 nv_rd32(priv, 0x610490 + (chid * 0x10))); gf110_disp_dmac_fini()
142 nv_mask(priv, 0x610090, 0x00000001 << chid, 0x00000000); gf110_disp_dmac_fini()
143 nv_mask(priv, 0x6100a0, 0x00000001 << chid, 0x00000000); gf110_disp_dmac_fini()
355 .chid = 0,
449 .chid = 1,
530 .chid = 5,
544 int chid = pioc->base.chid; gf110_disp_pioc_init() local
552 nv_mask(priv, 0x6100a0, 0x00000001 << chid, 0x00000001 << chid); gf110_disp_pioc_init()
555 nv_wr32(priv, 0x610490 + (chid * 0x10), 0x00000001); gf110_disp_pioc_init()
556 if (!nv_wait(priv, 0x610490 + (chid * 0x10), 0x00030000, 0x00010000)) { gf110_disp_pioc_init()
558 nv_rd32(priv, 0x610490 + (chid * 0x10))); gf110_disp_pioc_init()
570 int chid = pioc->base.chid; gf110_disp_pioc_fini() local
572 nv_mask(priv, 0x610490 + (chid * 0x10), 0x00000001, 0x00000000); gf110_disp_pioc_fini()
573 if (!nv_wait(priv, 0x610490 + (chid * 0x10), 0x00030000, 0x00000000)) { gf110_disp_pioc_fini()
575 nv_rd32(priv, 0x610490 + (chid * 0x10))); gf110_disp_pioc_fini()
581 nv_mask(priv, 0x610090, 0x00000001 << chid, 0x00000000); gf110_disp_pioc_fini()
582 nv_mask(priv, 0x6100a0, 0x00000001 << chid, 0x00000000); gf110_disp_pioc_fini()
601 .chid = 9,
618 .chid = 13,
1153 gf110_disp_intr_error(struct nv50_disp_priv *priv, int chid) gf110_disp_intr_error() argument
1156 u32 mthd = nv_rd32(priv, 0x6101f0 + (chid * 12)); gf110_disp_intr_error()
1157 u32 data = nv_rd32(priv, 0x6101f4 + (chid * 12)); gf110_disp_intr_error()
1158 u32 unkn = nv_rd32(priv, 0x6101f8 + (chid * 12)); gf110_disp_intr_error()
1160 nv_error(priv, "chid %d mthd 0x%04x data 0x%08x " gf110_disp_intr_error()
1162 chid, (mthd & 0x0000ffc), data, mthd, unkn); gf110_disp_intr_error()
1164 if (chid == 0) { gf110_disp_intr_error()
1167 nv50_disp_mthd_chan(priv, NV_DBG_ERROR, chid - 0, gf110_disp_intr_error()
1174 if (chid <= 4) { gf110_disp_intr_error()
1177 nv50_disp_mthd_chan(priv, NV_DBG_ERROR, chid - 1, gf110_disp_intr_error()
1184 if (chid <= 8) { gf110_disp_intr_error()
1187 nv50_disp_mthd_chan(priv, NV_DBG_ERROR, chid - 5, gf110_disp_intr_error()
1195 nv_wr32(priv, 0x61009c, (1 << chid)); gf110_disp_intr_error()
1196 nv_wr32(priv, 0x6101f0 + (chid * 12), 0x90000000); gf110_disp_intr_error()
1209 int chid = __ffs(stat); stat &= ~(1 << chid); gf110_disp_intr() local
1210 nv50_disp_chan_uevent_send(priv, chid); gf110_disp_intr()
1211 nv_wr32(priv, 0x61008c, 1 << chid); gf110_disp_intr()
1218 int chid = ffs(stat) - 1; gf110_disp_intr() local
1219 if (chid >= 0) gf110_disp_intr()
1220 gf110_disp_intr_error(priv, chid); gf110_disp_intr()
H A Dnv50.c61 int chid = impl->chid + head; nv50_disp_chan_create_() local
64 if (base->chan & (1 << chid)) nv50_disp_chan_create_()
66 base->chan |= (1 << chid); nv50_disp_chan_create_()
74 chan->chid = chid; nv50_disp_chan_create_()
85 base->chan &= ~(1 << chan->chid); nv50_disp_chan_destroy()
106 nv50_disp_chan_uevent_send(struct nv50_disp_priv *priv, int chid) nv50_disp_chan_uevent_send() argument
111 nvkm_event_send(&priv->uevent, 1, chid, &rep, sizeof(rep)); nv50_disp_chan_uevent_send()
127 notify->index = dmac->base.chid; nv50_disp_chan_uevent_ctor()
161 0x640000 + (chan->chid * 0x1000); nv50_disp_chan_map()
171 return nv_rd32(priv, 0x640000 + (chan->chid * 0x1000) + addr); nv50_disp_chan_rd32()
179 nv_wr32(priv, 0x640000 + (chan->chid * 0x1000) + addr, data); nv50_disp_chan_wr32()
193 u32 chid = chan->chid; nv50_disp_dmac_object_attach() local
194 u32 data = (chid << 28) | (addr << 10) | chid; nv50_disp_dmac_object_attach()
195 return nvkm_ramht_insert(base->ramht, chid, name, data); nv50_disp_dmac_object_attach()
261 int chid = dmac->base.chid; nv50_disp_dmac_init() local
269 nv_mask(priv, 0x610028, 0x00010000 << chid, 0x00010000 << chid); nv50_disp_dmac_init()
272 nv_wr32(priv, 0x610204 + (chid * 0x0010), dmac->push); nv50_disp_dmac_init()
273 nv_wr32(priv, 0x610208 + (chid * 0x0010), 0x00010000); nv50_disp_dmac_init()
274 nv_wr32(priv, 0x61020c + (chid * 0x0010), chid); nv50_disp_dmac_init()
275 nv_mask(priv, 0x610200 + (chid * 0x0010), 0x00000010, 0x00000010); nv50_disp_dmac_init()
276 nv_wr32(priv, 0x640000 + (chid * 0x1000), 0x00000000); nv50_disp_dmac_init()
277 nv_wr32(priv, 0x610200 + (chid * 0x0010), 0x00000013); nv50_disp_dmac_init()
280 if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x80000000, 0x00000000)) { nv50_disp_dmac_init()
282 nv_rd32(priv, 0x610200 + (chid * 0x10))); nv50_disp_dmac_init()
294 int chid = dmac->base.chid; nv50_disp_dmac_fini() local
297 nv_mask(priv, 0x610200 + (chid * 0x0010), 0x00001010, 0x00001000); nv50_disp_dmac_fini()
298 nv_mask(priv, 0x610200 + (chid * 0x0010), 0x00000003, 0x00000000); nv50_disp_dmac_fini()
299 if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x001e0000, 0x00000000)) { nv50_disp_dmac_fini()
301 nv_rd32(priv, 0x610200 + (chid * 0x10))); nv50_disp_dmac_fini()
307 nv_mask(priv, 0x610028, 0x00010001 << chid, 0x00000000 << chid); nv50_disp_dmac_fini()
584 .chid = 0,
686 .chid = 1,
776 .chid = 3,
807 int chid = pioc->base.chid; nv50_disp_pioc_init() local
814 nv_wr32(priv, 0x610200 + (chid * 0x10), 0x00002000); nv50_disp_pioc_init()
815 if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x00000000, 0x00000000)) { nv50_disp_pioc_init()
817 nv_rd32(priv, 0x610200 + (chid * 0x10))); nv50_disp_pioc_init()
821 nv_wr32(priv, 0x610200 + (chid * 0x10), 0x00000001); nv50_disp_pioc_init()
822 if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x00030000, 0x00010000)) { nv50_disp_pioc_init()
824 nv_rd32(priv, 0x610200 + (chid * 0x10))); nv50_disp_pioc_init()
836 int chid = pioc->base.chid; nv50_disp_pioc_fini() local
838 nv_mask(priv, 0x610200 + (chid * 0x10), 0x00000001, 0x00000000); nv50_disp_pioc_fini()
839 if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x00030000, 0x00000000)) { nv50_disp_pioc_fini()
841 nv_rd32(priv, 0x610200 + (chid * 0x10))); nv50_disp_pioc_fini()
894 .chid = 5,
942 .chid = 7,
1326 nv50_disp_intr_error(struct nv50_disp_priv *priv, int chid) nv50_disp_intr_error() argument
1329 u32 data = nv_rd32(priv, 0x610084 + (chid * 0x08)); nv50_disp_intr_error()
1330 u32 addr = nv_rd32(priv, 0x610080 + (chid * 0x08)); nv50_disp_intr_error()
1345 nv_error(priv, "%s [%s] chid %d mthd 0x%04x data 0x%08x\n", nv50_disp_intr_error()
1347 chid, mthd, data); nv50_disp_intr_error()
1349 if (chid == 0) { nv50_disp_intr_error()
1352 nv50_disp_mthd_chan(priv, NV_DBG_ERROR, chid - 0, nv50_disp_intr_error()
1359 if (chid <= 2) { nv50_disp_intr_error()
1362 nv50_disp_mthd_chan(priv, NV_DBG_ERROR, chid - 1, nv50_disp_intr_error()
1369 if (chid <= 4) { nv50_disp_intr_error()
1372 nv50_disp_mthd_chan(priv, NV_DBG_ERROR, chid - 3, nv50_disp_intr_error()
1380 nv_wr32(priv, 0x610020, 0x00010000 << chid); nv50_disp_intr_error()
1381 nv_wr32(priv, 0x610080 + (chid * 0x08), 0x90000000); nv50_disp_intr_error()
1932 u32 chid = __ffs(intr0 & 0x001f0000) - 16; nv50_disp_intr() local
1933 nv50_disp_intr_error(priv, chid); nv50_disp_intr()
1934 intr0 &= ~(0x00010000 << chid); nv50_disp_intr()
1938 u32 chid = __ffs(intr0 & 0x0000001f); nv50_disp_intr() local
1939 nv50_disp_chan_uevent_send(priv, chid); nv50_disp_intr()
1940 intr0 &= ~(0x00000001 << chid); nv50_disp_intr()
H A Dnv50.h86 int chid; member in struct:nv50_disp_chan_impl
95 int chid; member in struct:nv50_disp_chan
/linux-4.1.27/drivers/usb/wusbcore/
H A Dwusbhc.c97 const struct wusb_ckhdid *chid; wusb_chid_show() local
101 chid = &wusbhc->wuie_host_info->CHID; wusb_chid_show()
103 chid = &wusb_ckhdid_zero; wusb_chid_show()
105 result += ckhdid_printf(buf, PAGE_SIZE, chid); wusb_chid_show()
124 struct wusb_ckhdid chid; wusb_chid_store() local
132 &chid.data[0] , &chid.data[1] , wusb_chid_store()
133 &chid.data[2] , &chid.data[3] , wusb_chid_store()
134 &chid.data[4] , &chid.data[5] , wusb_chid_store()
135 &chid.data[6] , &chid.data[7] , wusb_chid_store()
136 &chid.data[8] , &chid.data[9] , wusb_chid_store()
137 &chid.data[10], &chid.data[11], wusb_chid_store()
138 &chid.data[12], &chid.data[13], wusb_chid_store()
139 &chid.data[14], &chid.data[15]); wusb_chid_store()
145 result = wusbhc_chid_set(wusbhc, &chid); wusb_chid_store()
H A Dmmc.c267 int wusbhc_chid_set(struct wusbhc *wusbhc, const struct wusb_ckhdid *chid) wusbhc_chid_set() argument
271 if (memcmp(chid, &wusb_ckhdid_zero, sizeof(*chid)) == 0) wusbhc_chid_set()
272 chid = NULL; wusbhc_chid_set()
275 if (chid) { wusbhc_chid_set()
280 wusbhc->chid = *chid; wusbhc_chid_set()
285 if ((chid) && (wusbhc->uwb_rc == NULL)) { wusbhc_chid_set()
302 if (chid) wusbhc_chid_set()
H A Dcbaf.c110 struct wusb_ckhdid chid; member in struct:cbaf
256 hi->CHID = cbaf->chid; cbaf_send_host_info()
321 ckhdid_printf(pr_chid, sizeof(pr_chid), &cbaf->chid); cbaf_wusb_chid_show()
338 &cbaf->chid.data[0] , &cbaf->chid.data[1], cbaf_wusb_chid_store()
339 &cbaf->chid.data[2] , &cbaf->chid.data[3], cbaf_wusb_chid_store()
340 &cbaf->chid.data[4] , &cbaf->chid.data[5], cbaf_wusb_chid_store()
341 &cbaf->chid.data[6] , &cbaf->chid.data[7], cbaf_wusb_chid_store()
342 &cbaf->chid.data[8] , &cbaf->chid.data[9], cbaf_wusb_chid_store()
343 &cbaf->chid.data[10], &cbaf->chid.data[11], cbaf_wusb_chid_store()
344 &cbaf->chid.data[12], &cbaf->chid.data[13], cbaf_wusb_chid_store()
345 &cbaf->chid.data[14], &cbaf->chid.data[15]); cbaf_wusb_chid_store()
524 ccd->CHID = cbaf->chid; cbaf_cc_upload()
H A Dwusbhc.h181 * @chid WUSB Cluster Host ID: this is supposed to be a
254 struct wusb_ckhdid chid; member in struct:wusbhc
H A Ddevconnect.c1036 hi->CHID = wusbhc->chid; wusbhc_devconnect_start()
/linux-4.1.27/drivers/gpu/drm/nouveau/include/nvkm/engine/
H A Dfifo.h12 u16 chid; member in struct:nvkm_fifo_chan
81 int (*chid)(struct nvkm_fifo *, struct nvkm_object *); member in struct:nvkm_fifo
104 nvkm_client_name_for_fifo_chid(struct nvkm_fifo *fifo, u32 chid);
/linux-4.1.27/drivers/gpu/drm/nouveau/
H A Dnouveau_chan.h11 int chid; member in struct:nouveau_channel
H A Dnv84_fence.c78 u64 addr = chan->chid * 16; nv84_fence_emit()
93 u64 addr = prev->chid * 16; nv84_fence_sync()
107 return nouveau_bo_rd32(priv->bo, chan->chid * 16/4); nv84_fence_read()
123 nouveau_bo_wr32(priv->bo, chan->chid * 16 / 4, fctx->base.sequence); nv84_fence_context_del()
H A Dnouveau_chan.c230 chan->chid = retn->kepler.chid; nouveau_channel_ind()
232 chan->chid = retn->nv50.chid; nouveau_channel_ind()
271 chan->chid = retn->chid; nouveau_channel_dma()
H A Dnouveau_drm.h78 NVDRM_PUSH = 0xbbbb0000, /* |= client chid */
79 NVDRM_CHAN = 0xcccc0000, /* |= client chid */
H A Dnouveau_fence.c178 fctx->context = priv->context_base + chan->chid; nouveau_fence_context_new()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/core/
H A Dramht.c28 nvkm_ramht_hash(struct nvkm_ramht *ramht, int chid, u32 handle) nvkm_ramht_hash() argument
37 hash ^= chid << (ramht->bits - 4); nvkm_ramht_hash()
43 nvkm_ramht_insert(struct nvkm_ramht *ramht, int chid, u32 handle, u32 context) nvkm_ramht_insert() argument
48 co = ho = nvkm_ramht_hash(ramht, chid, handle); nvkm_ramht_insert()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/ce/
H A Dgt215.c92 int chid; gt215_ce_intr() local
95 chid = pfifo->chid(pfifo, engctx); gt215_ce_intr()
101 chid, inst << 12, nvkm_client_name(engctx), subc, gt215_ce_intr()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/cipher/
H A Dg84.c119 int chid; g84_cipher_intr() local
122 chid = pfifo->chid(pfifo, engctx); g84_cipher_intr()
128 chid, (u64)inst << 12, nvkm_client_name(engctx), g84_cipher_intr()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/
H A Dnv44.c107 int chid; nv44_mpeg_intr() local
110 chid = pfifo->chid(pfifo, engctx); nv44_mpeg_intr()
133 chid, inst << 4, nvkm_client_name(engctx), stat, nv44_mpeg_intr()
H A Dnv31.c230 pfifo->chid(pfifo, engctx), nv31_mpeg_intr()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/sec/
H A Dg98.c90 int chid; g98_sec_intr() local
93 chid = pfifo->chid(pfifo, engctx); g98_sec_intr()
99 chid, (u64)inst << 12, nvkm_client_name(engctx), g98_sec_intr()
/linux-4.1.27/drivers/gpu/drm/nouveau/include/nvif/
H A Dclass.h338 __u8 chid; member in struct:nv03_channel_dma_v0
352 __u8 chid; member in struct:nv50_channel_gpfifo_v0
369 __u16 chid; member in struct:kepler_channel_gpfifo_a_v0
/linux-4.1.27/drivers/gpu/host1x/
H A Ddev.h214 int chid) host1x_hw_channel_init()
216 return host->channel_op->init(channel, host, chid); host1x_hw_channel_init()
212 host1x_hw_channel_init(struct host1x *host, struct host1x_channel *channel, int chid) host1x_hw_channel_init() argument
/linux-4.1.27/drivers/s390/cio/
H A Dchsc.h32 u16 chid; member in struct:channel_path_desc_fmt1
H A Dchp.c363 rc = sprintf(buf, "%04x\n", chp->desc_fmt1.chid); chp_chid_show()
370 static DEVICE_ATTR(chid, 0444, chp_chid_show, NULL);
/linux-4.1.27/sound/pci/ca0106/
H A Dca0106_mixer.c555 #define CA_VOLUME(xname,chid,reg) \
564 .private_value = ((chid) << 8) | (reg) \
636 #define I2C_VOLUME(xname,chid) \
645 .private_value = chid \
/linux-4.1.27/sound/pci/emu10k1/
H A Demumixer.c491 #define EMU1010_SOURCE_OUTPUT(xname,chid) \
498 .private_value = chid \
552 #define EMU1010_SOURCE_INPUT(xname,chid) \
559 .private_value = chid \
620 #define EMU1010_ADC_PADS(xname,chid) \
627 .private_value = chid \
668 #define EMU1010_DAC_PADS(xname,chid) \
675 .private_value = chid \
1055 #define I2C_VOLUME(xname,chid) \
1064 .private_value = chid \
/linux-4.1.27/drivers/isdn/hisax/
H A Dl3ni1.c447 u_char chid; l3ni1_message_plus_chid() local
449 chid = (u_char)(pc->para.bchannel & 0x03) | 0x88; l3ni1_message_plus_chid()
453 *p++ = chid; l3ni1_message_plus_chid()
822 l3_debug(pc->st, "wrong chid len %d", *p); l3ni1_get_channel_id()
828 l3_debug(pc->st, "wrong chid %x", *p); l3ni1_get_channel_id()
1293 l3_debug(pc->st, "setup answer with wrong chid %x", id); l3ni1_call_proc()
1301 l3_debug(pc->st, "setup answer wrong chid (ret %d)", id); l3ni1_call_proc()
1332 l3_debug(pc->st, "setup answer with wrong chid %x", id); l3ni1_setup_ack()
1340 l3_debug(pc->st, "setup answer wrong chid (ret %d)", id); l3ni1_setup_ack()
1528 l3_debug(pc->st, "setup with wrong chid %x", l3ni1_setup()
1542 l3_debug(pc->st, "setup with wrong chid ret %d", id); l3ni1_setup()
2481 l3_debug(pc->st, "resume ack with wrong chid %x", id); l3ni1_resume_ack()
2489 l3_debug(pc->st, "resume ack without chid (ret %d)", id); l3ni1_resume_ack()
H A Dl3dss1.c872 l3_debug(pc->st, "wrong chid len %d", *p); l3dss1_get_channel_id()
878 l3_debug(pc->st, "wrong chid %x", *p); l3dss1_get_channel_id()
1439 l3_debug(pc->st, "setup answer with wrong chid %x", id); l3dss1_call_proc()
1447 l3_debug(pc->st, "setup answer wrong chid (ret %d)", id); l3dss1_call_proc()
1478 l3_debug(pc->st, "setup answer with wrong chid %x", id); l3dss1_setup_ack()
1486 l3_debug(pc->st, "setup answer wrong chid (ret %d)", id); l3dss1_setup_ack()
1674 l3_debug(pc->st, "setup with wrong chid %x", l3dss1_setup()
1688 l3_debug(pc->st, "setup with wrong chid ret %d", id); l3dss1_setup()
2621 l3_debug(pc->st, "resume ack with wrong chid %x", id); l3dss1_resume_ack()
2629 l3_debug(pc->st, "resume ack without chid (ret %d)", id); l3dss1_resume_ack()
/linux-4.1.27/drivers/net/wireless/hostap/
H A Dhostap_info.c221 req.channel = selected->chid; prism2_host_roaming()
H A Dhostap_proc.c360 le16_to_cpu(scanres->chid), prism2_scan_results_proc_show()
H A Dhostap_wlan.h229 __le16 chid; member in struct:hfa384x_scan_result
242 __le16 chid; member in struct:hfa384x_hostscan_result
H A Dhostap_ioctl.c659 req.channel = entry->chid; hostap_join_ap()
1838 chan = le16_to_cpu(scan->chid); __prism2_translate_scan()
/linux-4.1.27/drivers/staging/wlan-ng/
H A Dhfa384x.h639 u16 chid; member in struct:hfa384x_ScanResultSub
658 u16 chid; member in struct:hfa384x_ChInfoResultSub
674 u16 chid; member in struct:hfa384x_HScanResultSub
H A Dprism2sta.c1040 pr_debug("chid=%d anl=%d sl=%d bcnint=%d\n", prism2sta_inf_scanresults()
1041 sr->result[i].chid, prism2sta_inf_scanresults()
1048 joinreq.channel = sr->result[0].chid; prism2sta_inf_scanresults()
1135 chan = le16_to_cpu(result->chid) - 1; prism2sta_inf_chinforesults()
1141 chinforesult->chid = chan; prism2sta_inf_chinforesults()
H A Dprism2mgmt.c478 req->dschannel.data = le16_to_cpu(item->chid); prism2mgmt_scan_results()
/linux-4.1.27/drivers/s390/net/
H A Dctcm_main.c202 char chid[CTCM_ID_SIZE+1]; channel_remove() local
208 strncpy(chid, ch->id, CTCM_ID_SIZE); channel_remove()
239 chid, ok ? "OK" : "failed"); channel_remove()
H A Dqeth_core_mpc.h538 __u16 chid; member in struct:net_if_token
H A Dqeth_l2_main.c1435 snprintf(str[i], sizeof(str[i]), "NTOK_CHID=%04x", token->chid); qeth_bridge_emit_host_event()

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