Searched refs:PCI (Results 1 - 200 of 2710) sorted by relevance

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/linux-4.1.27/arch/sh/include/mach-sh03/mach/
H A Dsh03.h9 * Interface CTP/PCI-SH03 support
12 #define PA_PCI_IO (0xbe240000) /* PCI I/O space */
13 #define PA_PCI_MEM (0xbd000000) /* PCI MEM space */
15 #define PCIPAR (0xa4000cf8) /* PCI Config address */
16 #define PCIPDR (0xa4000cfc) /* PCI Config data */
H A Dio.h6 * IO functions for an Interface CTP/PCI-SH03
/linux-4.1.27/drivers/pci/pcie/
H A DMakefile2 # Makefile for PCI-Express PORT Driver
5 # Build PCI Express ASPM if needed
13 # Build PCI Express AER if needed
H A Dportdrv_core.c3 * Purpose: PCI Express Port Bus Driver's Core Functions
34 * release_pcie_device - free PCI Express port service device structure
68 * @dev: PCI Express port to handle
115 * The code below follows the PCI Express Base Specification 2.0 pcie_port_enable_msix()
119 * Number field in the PCI Express Capabilities register", where pcie_port_enable_msix()
141 * The code below follows Section 7.10.10 of the PCI Express pcie_port_enable_msix()
192 * init_service_irqs - initialize irqs for PCI Express port services
193 * @dev: PCI Express port to handle
245 * get_port_device_capability - discover capabilities of a PCI Express port
246 * @dev: PCI Express port to examine
248 * The capabilities are read from the port's PCI Express configuration registers
249 * as described in PCI Express Base Specification 1.0a sections 7.8.2, 7.8.9 and
319 * pcie_device_init - allocate and initialize PCI Express port service device
320 * @pdev: PCI Express port to associate the service device with
357 * pcie_port_device_register - register PCI Express port
358 * @dev: PCI Express port to register
368 /* Enable PCI Express port device */ pcie_port_device_register()
373 /* Get and check PCI Express port services */ pcie_port_device_register()
430 * @dev: PCI Express port to handle
452 * @dev: PCI Express port to handle
468 * pcie_port_device_remove - unregister PCI Express port service devices
469 * @dev: PCI Express port the service devices to unregister are associated with
471 * Remove PCI Express port service devices associated with given port and
482 * pcie_port_probe_service - probe driver for given PCI Express port service
483 * @dev: PCI Express port service device to probe against
485 * If PCI Express port service driver is registered with
513 * pcie_port_remove_service - detach driver from given PCI Express port service
514 * @dev: PCI Express port service device to handle
516 * If PCI Express port service driver is registered with
541 * pcie_port_shutdown_service - shut down given PCI Express port service
542 * @dev: PCI Express port service device to handle
544 * If PCI Express port service driver is registered with
552 * pcie_port_service_register - register PCI Express port service driver pcie_port_shutdown_service()
553 * @new: PCI Express port service driver to register pcie_port_shutdown_service()
571 * pcie_port_service_unregister - unregister PCI Express port service driver
572 * @drv: PCI Express port service driver to unregister
/linux-4.1.27/drivers/scsi/arcmsr/
H A DMakefile2 # Makefile for the ARECA PCI-X PCI-EXPRESS SATA RAID controllers SCSI driver.
/linux-4.1.27/drivers/scsi/qla2xxx/
H A Dqla_devtbl.h7 "QLA2340", "133MHz PCI-X to 2Gb FC, Single Channel", /* 0x100 */
8 "QLA2342", "133MHz PCI-X to 2Gb FC, Dual Channel", /* 0x101 */
9 "QLA2344", "133MHz PCI-X to 2Gb FC, Quad Channel", /* 0x102 */
13 "QLA2310", "Sun 66MHz PCI-X to 2Gb FC, Single Channel", /* 0x106 */
14 "QLA2332", "Sun 66MHz PCI-X to 2Gb FC, Single Channel", /* 0x107 */
17 "QLA2342", "Sun 133MHz PCI-X to 2Gb FC, Dual Channel", /* 0x10a */
19 "QLA2350", "133MHz PCI-X to 2Gb FC, Single Channel", /* 0x10c */
20 "QLA2352", "133MHz PCI-X to 2Gb FC, Dual Channel", /* 0x10d */
21 "QLA2352", "Sun 133MHz PCI-X to 2Gb FC, Dual Channel", /* 0x10e */
28 "QLA2360", "133MHz PCI-X to 2Gb FC, Single Channel", /* 0x115 */
29 "QLA2362", "133MHz PCI-X to 2Gb FC, Dual Channel", /* 0x116 */
30 "QLE2360", "PCI-Express to 2Gb FC, Single Channel", /* 0x117 */
31 "QLE2362", "PCI-Express to 2Gb FC, Dual Channel", /* 0x118 */
32 "QLA200", "133MHz PCI-X to 2Gb FC Optical", /* 0x119 */
35 "QLA200P", "133MHz PCI-X to 2Gb FC SFP", /* 0x11c */
54 "QLA210", "133MHz PCI-X to 2Gb FC, Single Channel", /* 0x12f */
55 "EMC 250", "133MHz PCI-X to 2Gb FC, Single Channel", /* 0x130 */
56 "HP A7538A", "HP 1p2g PCI-X to 2Gb FC, Single Channel", /* 0x131 */
57 "QLA210", "Sun 133MHz PCI-X to 2Gb FC, Single Channel", /* 0x132 */
58 "QLA2460", "PCI-X 2.0 to 4Gb FC, Single Channel", /* 0x133 */
59 "QLA2462", "PCI-X 2.0 to 4Gb FC, Dual Channel", /* 0x134 */
62 "QLE2460", "PCI-Express to 4Gb FC, Single Channel", /* 0x137 */
63 "QLE2462", "PCI-Express to 4Gb FC, Dual Channel", /* 0x138 */
64 "QME2462", "Dell BS PCI-Express to 4Gb FC, Dual Channel", /* 0x139 */
69 "QLE210", "PCI-Express to 2Gb FC, Single Channel", /* 0x13e */
70 "QLE220", "PCI-Express to 4Gb FC, Single Channel", /* 0x13f */
71 "QLA2460", "Sun PCI-X 2.0 to 4Gb FC, Single Channel", /* 0x140 */
72 "QLA2462", "Sun PCI-X 2.0 to 4Gb FC, Dual Channel", /* 0x141 */
73 "QLE2460", "Sun PCI-Express to 2Gb FC, Single Channel", /* 0x142 */
74 "QLE2462", "Sun PCI-Express to 4Gb FC, Single Channel", /* 0x143 */
76 "QLE2440", "PCI-Express to 4Gb FC, Single Channel", /* 0x145 */
77 "QLE2464", "PCI-Express to 4Gb FC, Quad Channel", /* 0x146 */
78 "QLA2440", "PCI-X 2.0 to 4Gb FC, Single Channel", /* 0x147 */
79 "HP AE369A", "PCI-X 2.0 to 4Gb FC, Dual Channel", /* 0x148 */
80 "QLA2340", "Sun 133MHz PCI-X to 2Gb FC, Single Channel", /* 0x149 */
85 "QLE220", "Sun PCI-Express to 4Gb FC, Single Channel", /* 0x14e */
89 "QME2462", "PCI-Express to 4Gb FC, Dual Channel Mezz HBA", /* 0x152 */
90 "QMH2462", "PCI-Express to 4Gb FC, Dual Channel Mezz HBA", /* 0x153 */
92 "QLE220", "PCI-Express to 4Gb FC, Single Channel", /* 0x155 */
93 "QLE220", "PCI-Express to 4Gb FC, Single Channel", /* 0x156 */
98 "QME2472", "Dell BS PCI-Express to 4Gb FC, Dual Channel", /* 0x15b */
/linux-4.1.27/arch/sh/boards/mach-sh03/
H A DMakefile2 # Makefile for the Interface (CTP/PCI-SH03) specific parts of the kernel
/linux-4.1.27/arch/x86/pci/
H A Dlegacy.c2 * legacy.c - traditional, old school PCI bus probing
10 * Discover remaining PCI buses in case there are peer host bridges.
11 * We use the number of last PCI bus provided by the PCI BIOS.
19 DBG("PCI: Peer bridge fixup\n"); pcibios_fixup_peer_bridges()
28 printk("PCI: System does not support PCI\n"); pci_legacy_init()
32 printk("PCI: Probing PCI hardware\n"); pci_legacy_init()
49 printk(KERN_INFO "PCI: Discovered peer bus %02x\n", busn); pcibios_scan_specific_bus()
H A Dinit.c28 * in case legacy PCI probing is used. otherwise detecting peer busses pci_arch_init()
36 "PCI: Fatal: No config space access function found\n"); pci_arch_init()
H A Dpcbios.c2 * BIOS32 and PCI BIOS handling.
17 /* PCI signature: "PCI " */
20 /* PCI service signature: "$PCI" */
23 /* PCI BIOS hardware mechanism flags */
47 printk(KERN_INFO "PCI : PCI BIOS area is rw and x. Use pci=nobios if you want it NX.\n"); set_bios_x()
57 * and the PCI BIOS specification.
157 DBG("PCI: BIOS probe returned s=%02x hw=%02x ver=%02x.%02x l=%02x\n", check_pcibios()
160 printk (KERN_ERR "PCI: BIOS BUG #%x[%08x] found\n", check_pcibios()
164 printk(KERN_INFO "PCI: PCI BIOS revision %x.%02x entry at 0x%lx, last bus=%d\n", check_pcibios()
312 * Try to find PCI BIOS.
345 printk("PCI: unsupported BIOS32 revision %d at 0x%p\n", pci_find_bios()
349 DBG("PCI: BIOS32 Service Directory structure at 0x%p\n", check); pci_find_bios()
351 printk("PCI: BIOS32 entry (0x%p) in high memory, " pci_find_bios()
356 DBG("PCI: BIOS32 Service Directory entry at 0x%lx\n", pci_find_bios()
395 DBG("PCI: Fetching IRQ routing table... "); pcibios_get_irq_routing_table()
415 printk(KERN_ERR "PCI: Error %02x when fetching IRQ routing table.\n", (ret >> 8) & 0xff); pcibios_get_irq_routing_table()
423 printk(KERN_INFO "PCI: Using BIOS Interrupt Routing Table\n"); pcibios_get_irq_routing_table()
/linux-4.1.27/drivers/staging/dgnc/
H A Ddgnc_pci.h19 #define PCIMAX 32 /* maximum number of PCI boards */
42 #define PCI_DEVICE_CLASSIC_4_PCI_NAME "ClassicBoard 4 PCI"
43 #define PCI_DEVICE_CLASSIC_8_PCI_NAME "ClassicBoard 8 PCI"
44 #define PCI_DEVICE_CLASSIC_4_422_PCI_NAME "ClassicBoard 4 422 PCI"
45 #define PCI_DEVICE_CLASSIC_8_422_PCI_NAME "ClassicBoard 8 422 PCI"
46 #define PCI_DEVICE_NEO_4_PCI_NAME "Neo 4 PCI"
47 #define PCI_DEVICE_NEO_8_PCI_NAME "Neo 8 PCI"
48 #define PCI_DEVICE_NEO_2DB9_PCI_NAME "Neo 2 - DB9 Universal PCI"
49 #define PCI_DEVICE_NEO_2DB9PRI_PCI_NAME "Neo 2 - DB9 Universal PCI - Powered Ring Indicator"
50 #define PCI_DEVICE_NEO_2RJ45_PCI_NAME "Neo 2 - RJ45 Universal PCI"
51 #define PCI_DEVICE_NEO_2RJ45PRI_PCI_NAME "Neo 2 - RJ45 Universal PCI - Powered Ring Indicator"
52 #define PCI_DEVICE_NEO_1_422_PCI_NAME "Neo 1 422 PCI"
53 #define PCI_DEVICE_NEO_1_422_485_PCI_NAME "Neo 1 422/485 PCI"
54 #define PCI_DEVICE_NEO_2_422_485_PCI_NAME "Neo 2 422/485 PCI"
56 #define PCI_DEVICE_NEO_EXPRESS_8_PCI_NAME "Neo 8 PCI Express"
57 #define PCI_DEVICE_NEO_EXPRESS_4_PCI_NAME "Neo 4 PCI Express"
58 #define PCI_DEVICE_NEO_EXPRESS_4RJ45_PCI_NAME "Neo 4 PCI Express RJ45"
59 #define PCI_DEVICE_NEO_EXPRESS_8RJ45_PCI_NAME "Neo 8 PCI Express RJ45"
60 #define PCI_DEVICE_NEO_EXPRESS_4_IBM_PCI_NAME "Neo 4 PCI Express IBM"
63 /* Size of Memory and I/O for PCI (4 K) */
/linux-4.1.27/include/uapi/linux/
H A Dpci.h4 * PCI defines and function prototypes
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
23 * The PCI interface treats multi-function devices as independent
36 #define PCIIOC_CONTROLLER (PCIIOC_BASE | 0x00) /* Get controller for PCI device. */
/linux-4.1.27/sound/pci/ice1712/
H A Dse.h6 "{ONKYO INC,SE-90PCI},"\
7 "{ONKYO INC,SE-200PCI},"
/linux-4.1.27/drivers/net/ethernet/qlogic/qlge/
H A DMakefile2 # Makefile for the Qlogic 10GbE PCI Express ethernet driver
/linux-4.1.27/include/linux/ssb/
H A Dssb_driver_pci.h11 /* PCI core registers. */
12 #define SSB_PCICORE_CTL 0x0000 /* PCI Control */
17 #define SSB_PCICORE_ARBCTL 0x0010 /* PCI Arbiter Control */
26 #define SSB_PCICORE_ISTAT_INTA 0x00000001 /* PCI INTA# */
27 #define SSB_PCICORE_ISTAT_INTB 0x00000002 /* PCI INTB# */
28 #define SSB_PCICORE_ISTAT_SERR 0x00000004 /* PCI SERR# (write to clear) */
29 #define SSB_PCICORE_ISTAT_PERR 0x00000008 /* PCI PERR# (write to clear) */
30 #define SSB_PCICORE_ISTAT_PME 0x00000010 /* PCI PME# */
32 #define SSB_PCICORE_IMASK_INTA 0x00000001 /* PCI INTA# */
33 #define SSB_PCICORE_IMASK_INTB 0x00000002 /* PCI INTB# */
34 #define SSB_PCICORE_IMASK_SERR 0x00000004 /* PCI SERR# */
35 #define SSB_PCICORE_IMASK_PERR 0x00000008 /* PCI PERR# */
36 #define SSB_PCICORE_IMASK_PME 0x00000010 /* PCI PME# */
37 #define SSB_PCICORE_MBOX 0x0028 /* Backplane to PCI Mailbox */
38 #define SSB_PCICORE_MBOX_F0_0 0x00000100 /* PCI function 0, INT 0 */
39 #define SSB_PCICORE_MBOX_F0_1 0x00000200 /* PCI function 0, INT 1 */
40 #define SSB_PCICORE_MBOX_F1_0 0x00000400 /* PCI function 1, INT 0 */
41 #define SSB_PCICORE_MBOX_F1_1 0x00000800 /* PCI function 1, INT 1 */
42 #define SSB_PCICORE_MBOX_F2_0 0x00001000 /* PCI function 2, INT 0 */
43 #define SSB_PCICORE_MBOX_F2_1 0x00002000 /* PCI function 2, INT 1 */
44 #define SSB_PCICORE_MBOX_F3_0 0x00004000 /* PCI function 3, INT 0 */
45 #define SSB_PCICORE_MBOX_F3_1 0x00008000 /* PCI function 3, INT 1 */
53 #define SSB_PCICORE_SBTOPCI0 0x0100 /* Backplane to PCI translation 0 (sbtopci0) */
55 #define SSB_PCICORE_SBTOPCI1 0x0104 /* Backplane to PCI translation 1 (sbtopci1) */
57 #define SSB_PCICORE_SBTOPCI2 0x0108 /* Backplane to PCI translation 2 (sbtopci2) */
59 #define SSB_PCICORE_PCICFG0 0x0400 /* PCI config space 0 (rev >= 8) */
60 #define SSB_PCICORE_PCICFG1 0x0500 /* PCI config space 1 (rev >= 8) */
61 #define SSB_PCICORE_PCICFG2 0x0600 /* PCI config space 2 (rev >= 8) */
62 #define SSB_PCICORE_PCICFG3 0x0700 /* PCI config space 3 (rev >= 8) */
80 #define SSB_PCICORE_BFL_NOPCI 0x00000400 /* Board leaves PCI floating */
H A Dssb_driver_gige.h13 #define SSB_GIGE_PCIIO 0x0000 /* PCI I/O Registers (1024 bytes) */
15 #define SSB_GIGE_PCICFG 0x0800 /* PCI config space (256 bytes) */
16 #define SSB_GIGE_SHIM_FLUSHSTAT 0x0C00 /* PCI to OCP: Flush status control (32bit) */
17 #define SSB_GIGE_SHIM_FLUSHRDA 0x0C04 /* PCI to OCP: Flush read address (32bit) */
18 #define SSB_GIGE_SHIM_FLUSHTO 0x0C08 /* PCI to OCP: Flush timeout counter (32bit) */
19 #define SSB_GIGE_SHIM_BARRIER 0x0C0C /* PCI to OCP: Barrier register (32bit) */
20 #define SSB_GIGE_SHIM_MAOCPSI 0x0C10 /* PCI to OCP: MaocpSI Control (32bit) */
21 #define SSB_GIGE_SHIM_SIOCPMA 0x0C14 /* PCI to OCP: SiocpMa Control (32bit) */
46 /* The PCI controller device. */
53 /* Check whether a PCI device is a SSB Gigabit Ethernet core. */
132 * because we can not unregister the PCI bridge. */ ssb_gige_exit()
/linux-4.1.27/arch/sh/drivers/pci/
H A Dfixups-cayman.c12 /* The complication here is that the PCI IRQ lines from the Cayman's 2 pcibios_map_platform_irq()
19 always bus 2, because a card containing a PCI-PCI bridge may be pcibios_map_platform_irq()
22 Also, the Cayman has an intermediate PCI bus that goes a custom pcibios_map_platform_irq()
26 The 1ary onboard PCI-PCI bridge is device 3 on bus 0 pcibios_map_platform_irq()
27 The 2ary onboard PCI-PCI bridge is device 0 on the 2ary bus of pcibios_map_platform_irq()
43 if (i > 3) panic("PCI path to root bus too long!\n"); pcibios_map_platform_irq()
52 /* Bus 0 (incl. PCI-PCI bridge itself) : perform the final pcibios_map_platform_irq()
60 panic("PCI expansion bus device found - not handled!\n"); pcibios_map_platform_irq()
70 /* IRQ for 2ary PCI-PCI bridge : unused */ pcibios_map_platform_irq()
H A Dpci-sh5.c9 * Support functions for the SH5 PCI hardware.
31 * sizing the PCI window.
66 printk("PCI INTERRUPT (at %08llx)!\n", regs->pc); pcish5_err_irq()
67 printk("PCI INT -> 0x%x\n", pci_int & 0xffff); pcish5_err_irq()
68 printk("PCI AIR -> 0x%x\n", pci_air); pcish5_err_irq()
69 printk("PCI CIR -> 0x%x\n", pci_cir); pcish5_err_irq()
75 printk("PCI ARB INTERRUPT!\n"); pcish5_err_irq()
76 printk("PCI AINT -> 0x%x\n", pci_aint); pcish5_err_irq()
77 printk("PCI AIR -> 0x%x\n", pci_air); pcish5_err_irq()
78 printk("PCI CIR -> 0x%x\n", pci_cir); pcish5_err_irq()
110 0, "PCI Error",NULL) < 0) { sh5pci_init()
116 0, "PCI SERR interrupt", NULL) < 0) { sh5pci_init()
158 ** used for the main bus, to the PCI internal address. sh5pci_init()
166 ** I/O addresses are mapped at internal PCI specific address sh5pci_init()
178 /* The SH5 has a HUGE 256K I/O region, which breaks the PCI spec. sh5pci_init()
186 /* Now we set up the mbars so the PCI bus can see the memory of sh5pci_init()
207 /* Enable the PCI interrupts on the device */ sh5pci_init()
H A Dpci-sh7751.c2 * Low-Level PCI Support for the SH7751
30 printk("PCI: Area %d is not configured for SDRAM. BCR1=0x%lx\n", __area_sdram_check()
39 printk("PCI: Area %d is not 32 bit SDRAM. BCR2=0x%lx\n", __area_sdram_check()
84 printk(KERN_NOTICE "PCI: Starting initialization.\n"); sh7751_pci_init()
92 pr_debug("PCI: This is not an SH7751(R) (%x)\n", id); sh7751_pci_init()
96 /* Set the BCR's to enable PCI access */ sh7751_pci_init()
120 * Make PCI and local address the same for easy 1 to 1 mapping sh7751_pci_init()
124 /* Set the values on window 0 PCI config registers */ sh7751_pci_init()
129 /* Set the local 16MB PCI memory space window to sh7751_pci_init()
130 * the lowest PCI mapped address sh7751_pci_init()
133 pr_debug("PCI: Setting upper bits of Memory window to 0x%x\n", word); sh7751_pci_init()
136 /* Make sure the MSB's of IO window are set to access PCI space sh7751_pci_init()
139 pr_debug("PCI: Setting upper bits of IO window to 0x%x\n", word); sh7751_pci_init()
142 /* Set PCI WCRx, BCRx's, copy from BSC locations */ sh7751_pci_init()
168 /* NOTE: I'm ignoring the PCI error IRQs for now.. sh7751_pci_init()
H A Dpci-sh7751.h2 * Low-Level PCI Support for SH7751 targets
28 #define SH7751_PCIREG_BASE 0xFE200000 /* PCI regs base address */
30 #define SH7751_PCICONF0 0x0 /* PCI Config Reg 0 */
33 #define SH7751_PCICONF1 0x4 /* PCI Config Reg 1 */
55 #define SH7751_PCICONF2 0x8 /* PCI Config Reg 2 */
60 #define SH7751_PCICONF3 0xC /* PCI Config Reg 3 */
68 #define SH7751_PCICONF4 0x10 /* PCI Config Reg 4 */
71 #define SH7751_PCICONF5 0x14 /* PCI Config Reg 5 */
76 #define SH7751_PCICONF6 0x18 /* PCI Config Reg 6 */
82 #define SH7751_PCICONF11 0x2C /* PCI Config Reg 11 */
86 #define SH7751_PCICONF13 0x34 /* PCI Config Reg 13 */
89 #define SH7751_PCICONF15 0x3C /* PCI Config Reg 15 */
91 #define SH7751_PCICONF16 0x40 /* PCI Config Reg 16 */
100 #define SH7751_PCICONF17 0x44 /* PCI Config Reg 17 */
107 /* SH7715 Internal PCI Registers */
H A Dcommon.c7 * These functions are used early on before PCI scanning is done
56 printk(KERN_INFO "PCI: Checking 66MHz capabilities...\n"); EARLY_PCI_OP()
76 "PCI: %02x:%02x not 66MHz capable.\n", EARLY_PCI_OP()
92 printk(KERN_DEBUG "PCI: re-enabling error IRQ.\n"); pcibios_enable_err()
101 printk(KERN_DEBUG "PCI: re-enabling system error IRQ.\n"); pcibios_enable_serr()
121 * A simple handler for the regular PCI status errors, called from IRQ
131 printk(KERN_DEBUG "PCI: master abort, pc=0x%08lx\n", addr); pcibios_handle_status_errors()
136 printk(KERN_DEBUG "PCI: target abort: "); pcibios_handle_status_errors()
146 printk(KERN_DEBUG "PCI: parity error detected: "); pcibios_handle_status_errors()
H A Dpci-sh7780.h2 * Low-Level PCI Support for SH7780 targets
23 #define SH7780_PCIREG_BASE 0xFE040000 /* PCI regs base address */
25 /* SH7780 PCI Config Registers */
26 #define SH7780_PCIIR 0x114 /* PCI Interrupt Register */
27 #define SH7780_PCIIMR 0x118 /* PCI Interrupt Mask Register */
H A Dfixups-snapgear.c13 * PCI initialization for the SnapGear boards
27 case 8: /* the PCI bridge */ break; pcibios_map_platform_irq()
35 printk("PCI: Mapping SnapGear IRQ for slot %d, pin %c to irq %d\n", pcibios_map_platform_irq()
H A Dfixups-sh03.c15 case 6: return evt2irq(0x240); /* PCI bridge */ pcibios_map_platform_irq()
17 printk(KERN_ERR "PCI: Bad IRQ mapping request " pcibios_map_platform_irq()
H A Dfixups-se7751.c19 printk("PCI: Bad IRQ mapping request for slot %d\n", slot); pcibios_map_platform_irq()
74 /* Set up standard PCI config registers */ pci_fixup_pcic()
76 PCIC_WRITE(SH7751_PCICONF2, 0x00000000); /* PCI Class code & Revision ID */ pci_fixup_pcic()
77 PCIC_WRITE(SH7751_PCICONF4, 0xab000001); /* PCI I/O address (local regs) */ pci_fixup_pcic()
78 PCIC_WRITE(SH7751_PCICONF5, 0x0c000000); /* PCI MEM address (local RAM) */ pci_fixup_pcic()
79 PCIC_WRITE(SH7751_PCICONF6, 0xd0000000); /* PCI MEM address (unused) */ pci_fixup_pcic()
80 PCIC_WRITE(SH7751_PCICONF11, 0x35051054); /* PCI Subsystem ID & Vendor ID */ pci_fixup_pcic()
83 PCIC_WRITE(SH7751_PCILAR0, 0x0c000000); /* MEM (direct map from PCI) */ pci_fixup_pcic()
97 * Set the MBR so PCI address is one-to-one with window, pci_fixup_pcic()
109 printk("SH7751 PCI: Finished initialization of the PCI controller\n"); pci_fixup_pcic()
H A Dpci-sh7780.c2 * Low-Level PCI Support for the SH7780
33 .name = "PCI IO",
38 .name = "PCI MEM 0",
43 .name = "PCI MEM 1",
51 .name = "PCI MEM 2",
125 printk(KERN_DEBUG "PCI: %s, addr=%08lx\n", sh7780_pci_err_irq()
133 * Handle the remaining PCI errors. sh7780_pci_err_irq()
138 printk(KERN_DEBUG "PCI: %s, addr=%08lx\n", sh7780_pci_err_irq()
152 printk(KERN_DEBUG "PCI: system error received: "); sh7780_pci_serr_irq()
171 /* Clear out PCI arbiter IRQs */ sh7780_pci_setup_irqs()
183 "PCI SERR interrupt", hose); sh7780_pci_setup_irqs()
185 printk(KERN_ERR "PCI: Failed hooking SERR IRQ\n"); sh7780_pci_setup_irqs()
190 * The PCI ERR IRQ needs to be IRQF_SHARED since all of the power sh7780_pci_setup_irqs()
196 "PCI ERR interrupt", hose); sh7780_pci_setup_irqs()
207 /* Unmask all of the PCI IRQs */ sh7780_pci_setup_irqs()
256 printk(KERN_NOTICE "PCI: Starting initialization.\n"); sh7780_pci_init()
276 printk(KERN_ERR "PCI: Unknown vendor ID 0x%04x.\n", id); sh7780_pci_init()
287 printk(KERN_ERR "PCI: Found an unsupported Renesas host " sh7780_pci_init()
292 printk(KERN_NOTICE "PCI: Found a Renesas %s host " sh7780_pci_init()
401 printk(KERN_NOTICE "PCI: Running at %dMHz.\n", sh7780_pci_init()
H A Dpci-sh4.h22 #define SH4_PCICR 0x100 /* PCI Control Register */
27 #define SH4_PCICR_PLUP 0x00000080 /* Enable PCI Pullup */
28 #define SH4_PCICR_ARBM 0x00000040 /* PCI Arbitration Mode */
32 #define SH4_PCICR_PRST 0x00000002 /* PCI Reset Assert */
34 #define SH4_PCILSR0 0x104 /* PCI Local Space Register0 */
35 #define SH4_PCILSR1 0x108 /* PCI Local Space Register1 */
36 #define SH4_PCILAR0 0x10C /* PCI Local Addr Register1 */
37 #define SH4_PCILAR1 0x110 /* PCI Local Addr Register1 */
38 #define SH4_PCIINT 0x114 /* PCI Interrupt Register */
51 #define SH4_PCIINTM 0x118 /* PCI Interrupt Mask */
71 #define SH4_PCICLR_CMDL 0x0000000F /* PCI Command at Error */
98 #define SH4_PCIDCR_PHLD 0x00000010 /* PCI Address Control*/
99 #define SH4_PCIDCR_IOSEL 0x00000008 /* PCI Address Space Type */
131 #define SH4_PCICLKR_PCSTP 0x00000002 /* PCI Clock Stop */
H A Dpci-sh5.h7 * Definitions for the SH5 PCI hardware.
29 #define PCISH5_ICR_CR 0x100 /* PCI control register values */
65 #define PCISH5_ICR_CSCR0 0x210 /* PCI cache snoop control register 0 */
66 #define PCISH5_ICR_CSCR1 0x214 /* PCI cache snoop control register 1 */
98 /* Set PCI config bits */
101 /* Set PCI command register */
H A Dfixups-titan.c12 * PCI initialization for the Titan boards
34 printk("PCI: Mapping TITAN IRQ for slot %d, pin %c to irq %d\n", pcibios_map_platform_irq()
H A Dfixups-dreamcast.c4 * PCI fixups for the Sega Dreamcast
11 * Dreamcast PCI: Supports SEGA Broadband Adaptor only.
37 printk(KERN_NOTICE "PCI: Fixing up device %s\n", pci_name(dev)); gapspci_fixup_resources()
74 printk("PCI: Failed resource fixup\n"); gapspci_fixup_resources()
H A Dfixups-r7780rp.c4 * Highlander R7780RP-1 PCI fixups
/linux-4.1.27/arch/mips/include/asm/
H A Dnile4.h32 #define NILE4_PCIW0 0x0060 /* PCI Address Window 0 [R/W] */
33 #define NILE4_PCIW1 0x0068 /* PCI Address Window 1 [R/W] */
49 #define NILE4_INTPPES 0x00A8 /* PCI Interrupt Control [R/W] */
62 * PCI-Bus Registers
65 #define NILE4_PCICTRL 0x00E0 /* PCI Control [R/W] */
66 #define NILE4_PCIARB 0x00E8 /* PCI Arbiter [R/W] */
67 #define NILE4_PCIINIT0 0x00F0 /* PCI Master (Initiator) 0 [R/W] */
68 #define NILE4_PCIINIT1 0x00F8 /* PCI Master (Initiator) 1 [R/W] */
69 #define NILE4_PCIERR 0x00B8 /* PCI Error [R/W] */
117 * PCI Configuration Space Registers
122 #define NILE4_VID 0x0200 /* PCI Vendor ID [R] */
123 #define NILE4_DID 0x0202 /* PCI Device ID [R] */
124 #define NILE4_PCICMD 0x0204 /* PCI Command [R/W] */
125 #define NILE4_PCISTS 0x0206 /* PCI Status [R/W] */
126 #define NILE4_REVID 0x0208 /* PCI Revision ID [R] */
127 #define NILE4_CLASS 0x0209 /* PCI Class Code [R] */
128 #define NILE4_CLSIZ 0x020C /* PCI Cache Line Size [R/W] */
129 #define NILE4_MLTIM 0x020D /* PCI Latency Timer [R/W] */
130 #define NILE4_HTYPE 0x020E /* PCI Header Type [R] */
132 #define NILE4_BARC 0x0210 /* PCI Base Address Register Control [R/W] */
133 #define NILE4_BAR0 0x0218 /* PCI Base Address Register 0 [R/W] */
134 #define NILE4_BAR1 0x0220 /* PCI Base Address Register 1 [R/W] */
135 #define NILE4_CIS 0x0228 /* PCI Cardbus CIS Pointer [R] */
137 #define NILE4_SSVID 0x022C /* PCI Sub-System Vendor ID [R/W] */
138 #define NILE4_SSID 0x022E /* PCI Sub-System ID [R/W] */
141 #define NILE4_INTLIN 0x023C /* PCI Interrupt Line [R/W] */
142 #define NILE4_INTPIN 0x023D /* PCI Interrupt Pin [R] */
143 #define NILE4_MINGNT 0x023E /* PCI Min_Gnt [R] (unimplemented) */
144 #define NILE4_MAXLAT 0x023F /* PCI Max_Lat [R] (unimplemented) */
145 #define NILE4_BAR2 0x0240 /* PCI Base Address Register 2 [R/W] */
146 #define NILE4_BAR3 0x0248 /* PCI Base Address Register 3 [R/W] */
147 #define NILE4_BAR4 0x0250 /* PCI Base Address Register 4 [R/W] */
148 #define NILE4_BAR5 0x0258 /* PCI Base Address Register 5 [R/W] */
149 #define NILE4_BAR6 0x0260 /* PCI Base Address Register 6 [R/W] */
150 #define NILE4_BAR7 0x0268 /* PCI Base Address Register 7 [R/W] */
151 #define NILE4_BAR8 0x0270 /* PCI Base Address Register 8 [R/W] */
152 #define NILE4_BARB 0x0278 /* PCI Base Address Register BOOT [R/W] */
189 #define NILE4_INT_INTA 8 /* PCI Interrupt Signal INTA# */
190 #define NILE4_INT_INTB 9 /* PCI Interrupt Signal INTB# */
191 #define NILE4_INT_INTC 10 /* PCI Interrupt Signal INTC# */
192 #define NILE4_INT_INTD 11 /* PCI Interrupt Signal INTD# */
193 #define NILE4_INT_INTE 12 /* PCI Interrupt Signal INTE# (ISA cascade) */
195 #define NILE4_INT_PCIS 14 /* PCI SERR# Interrupt */
196 #define NILE4_INT_PCIE 15 /* PCI Internal Error Interrupt */
258 * PCI Master Registers
261 #define NILE4_PCICMD_IACK 0 /* PCI Interrupt Acknowledge */
262 #define NILE4_PCICMD_IO 1 /* PCI I/O Space */
263 #define NILE4_PCICMD_MEM 3 /* PCI Memory Space */
264 #define NILE4_PCICMD_CFG 5 /* PCI Configuration Space */
268 * PCI Address Spaces
H A Dpci.h15 * specific PCI code and MIPS common PCI code. Should potentially put
23 * Each pci channel is a top-level PCI bus seem by CPU. A machine with
24 * multiple PCI channels may have multiple PCI host controllers or a
49 of the PCI controller */
55 * Used by boards to register their PCI busses before the actual scanning.
67 or architectures with incomplete PCI setup by the loader */
110 * The PCI address space does equal the physical memory address space. The
/linux-4.1.27/drivers/scsi/sym53c8xx_2/
H A DMakefile1 # Makefile for the NCR/SYMBIOS/LSI 53C8XX PCI SCSI controllers driver.
/linux-4.1.27/drivers/pci/pcie/aer/
H A DMakefile2 # Makefile for PCI-Express Root Port Advanced Error Reporting Driver
/linux-4.1.27/arch/sparc/include/asm/
H A Dpbm.h3 * pbm.h: PCI bus module pseudo driver software state
7 * pbm.h: U2P PCI bus module pseudo driver software state.
11 * To put things into perspective, consider sparc64 with a few PCI controllers.
15 * pci_bus - Linux PCI subsystem view of a PCI bus (including bridged buses)
16 * pbm - Arch-specific view of a PCI bus (sparc or sparc64)
33 /* Now things for the actual PCI bus probes. */
38 /* PCI devices which are not bridges have this placed in their pci_dev
39 * sysdata member. This makes OBP aware PCI device drivers easier to
H A Dpci_32.h10 * or architectures with incomplete PCI setup by the loader.
42 * On LEON PCI Memory space is mapped 1:1 with physical address space.
44 * I/O space is located at low 64Kbytes in PCI I/O space. The I/O addresses
46 * MMU to the PCI Host PCI I/O space window which are translated to the low
H A Dpci_64.h10 * or architectures with incomplete PCI setup by the loader.
19 /* The PCI address space does not equal the physical memory
25 /* PCI IOMMU mapping bypass support. */
27 /* PCI 64-bit addressing works for all slots on all controller
53 /* Return the index of the PCI controller for device PDEV. */
H A Dleon_pci.h10 /* PCI related definitions */
H A Dapb.h2 * apb.h: Advanced PCI Bridge Configuration Registers and Bits
/linux-4.1.27/arch/avr32/include/asm/
H A Dpci.h4 /* We don't support PCI yet, but some drivers require this file anyway */
/linux-4.1.27/drivers/pci/
H A Dsearch.c2 * PCI searching functions.
60 * PCIe-to-PCI/X bridges alias transactions from downstream pci_for_each_dma_alias()
61 * devices using the subordinate bus number (PCI Express to pci_for_each_dma_alias()
62 * PCI/PCI-X Bridge Spec, rev 1.0, sec 2.3). For all cases pci_for_each_dma_alias()
63 * where the upstream bus is PCI/X we alias to the bridge pci_for_each_dma_alias()
66 * when the secondary interface is PCI-X). pci_for_each_dma_alias()
123 * pci_find_bus - locate PCI bus from a given domain and bus number
124 * @domain: number of PCI domain to search
125 * @busnr: number of desired PCI bus
127 * Given a PCI bus number and domain number, the desired PCI bus is located
128 * in the global list of PCI buses. If the bus is found, a pointer to its
148 * pci_find_next_bus - begin or continue searching for a PCI bus
149 * @from: Previous PCI bus found, or %NULL for new search.
151 * Iterates through the list of known PCI buses. A new search is
172 * pci_get_slot - locate PCI device for a given PCI slot
173 * @bus: PCI bus on which desired PCI device resides
174 * @devfn: encodes number of PCI slot in which the desired PCI
178 * Given a PCI bus and slot/function number, the desired PCI device
179 * is located in the list of PCI devices.
206 * pci_get_domain_bus_and_slot - locate PCI device for a given PCI domain (segment), bus, and slot
207 * @domain: PCI domain/segment on which the PCI device resides.
208 * @bus: PCI bus on which desired PCI device resides
209 * @devfn: encodes number of PCI slot in which the desired PCI device
213 * Given a PCI domain, bus, and slot/function number, the desired PCI
214 * device is located in the list of PCI devices. If the device is
245 * pci_get_dev_by_id - begin or continue searching for a PCI device by id
247 * @from: Previous PCI device found in search, or %NULL for new search.
249 * Iterates through the list of known PCI devices. If a PCI device is found
279 * pci_get_subsys - begin or continue searching for a PCI device by vendor/subvendor/device/subdevice id
280 * @vendor: PCI vendor id to match, or %PCI_ANY_ID to match all vendor ids
281 * @device: PCI device id to match, or %PCI_ANY_ID to match all device ids
282 * @ss_vendor: PCI subsystem vendor id to match, or %PCI_ANY_ID to match all vendor ids
283 * @ss_device: PCI subsystem device id to match, or %PCI_ANY_ID to match all device ids
284 * @from: Previous PCI device found in search, or %NULL for new search.
286 * Iterates through the list of known PCI devices. If a PCI device is found
310 * pci_get_device - begin or continue searching for a PCI device by vendor/device id
311 * @vendor: PCI vendor id to match, or %PCI_ANY_ID to match all vendor ids
312 * @device: PCI device id to match, or %PCI_ANY_ID to match all device ids
313 * @from: Previous PCI device found in search, or %NULL for new search.
315 * Iterates through the list of known PCI devices. If a PCI device is
331 * pci_get_class - begin or continue searching for a PCI device by class
332 * @class: search for a PCI device with this class designation
333 * @from: Previous PCI device found in search, or %NULL for new search.
335 * Iterates through the list of known PCI devices. If a PCI device is
362 * that describe the type of PCI device the caller is trying to find.
H A Dhotplug-pci.c1 /* Core PCI functionality used only by PCI hotplug */
H A Drom.c7 * PCI ROM access routines
17 * pci_enable_rom - enable ROM decoding for a PCI device
18 * @pdev: PCI device to enable
21 * bit of the PCI ROM BAR. Note that some cards may share address decoders
44 * pci_disable_rom - disable ROM decoding for a PCI device
45 * @pdev: PCI device to disable
47 * Disable ROM decoding on a PCI device by turning off the last bit in the
61 * @pdev: target PCI device
63 * @size: size of PCI window
67 * The PCI window size could be much larger than the
79 /* Standard PCI ROMs start out with these bytes 55 AA */ pci_get_rom_size()
86 /* get the PCI data structure and check its signature */ pci_get_rom_size()
101 /* never return a size larger than the PCI resource window */ pci_get_rom_size()
107 * pci_map_rom - map a PCI ROM to kernel space
113 * Map a PCI ROM into kernel space. If ROM is boot video ROM,
165 * Try to find the true size of the ROM since sometimes the PCI window pci_map_rom()
H A Dpci.c2 * PCI Bus Services, see include/linux/pci.h for further explanation.
105 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
106 * @bus: pointer to PCI bus structure to search
108 * Given a PCI bus, returns the highest PCI bus number present in the set
109 * including the given PCI bus and its list of child PCI buses.
208 * @dev: PCI device to query
211 * Tell if a device supports a given PCI capability.
213 * device's PCI configuration space or 0 in case the device does not
222 * %PCI_CAP_ID_PCIX PCI-X
223 * %PCI_CAP_ID_EXP PCI Express
239 * @bus: the PCI bus to query
240 * @devfn: PCI device to query
247 * device's PCI configuration space or 0 in case the device does not
267 * @dev: PCI device to query
272 * within the device's PCI configuration space or 0 if the device does
319 * @dev: PCI device to query
323 * within the device's PCI configuration space or 0 if the device does
366 * @dev: PCI device to query
374 * NB. To be 100% safe against broken PCI devices, the caller should take
385 * @dev: PCI device to query
389 * Returns an address within the device's PCI configuration space
391 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
408 * @dev: PCI device structure contains resources to be searched
451 * @dev: the PCI device to operate on
477 * @dev: PCI device to have its BARs restored
536 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
537 * given PCI device
538 * @dev: PCI device to handle.
539 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
543 * -EIO if device does not support PCI PM or its PM capabilities register has a
608 /* see PCI PM 1.1 5.6.1 table 18 */ pci_raw_set_power_state()
621 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT pci_raw_set_power_state()
643 * pci_update_current_state - Read PCI power state of given device from its
644 * PCI PM registers and cache it
645 * @dev: PCI device to handle.
672 * @dev: PCI device to power up
685 * @dev: PCI device to handle.
706 * pci_wakeup - Wake up a PCI device
728 * __pci_start_power_transition - Start power transition of a PCI device
729 * @dev: PCI device to handle.
738 * PCI Express Base Specification Revision 2.0 Section __pci_start_power_transition()
757 * __pci_dev_set_current_state - Set current state of a PCI device
781 * __pci_complete_power_transition - Complete power transition of a PCI device
782 * @dev: PCI device to handle.
802 * pci_set_power_state - Set the power state of a PCI device
803 * @dev: PCI device to handle.
804 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
807 * the device's PCI PM registers.
811 * -EIO if device does not support PCI PM or its PM capabilities register has a
827 * If the device or the parent bridge do not support PCI PM, pci_set_power_state()
859 * pci_choose_state - Choose the power state of a PCI device
860 * @dev: PCI device to be suspended
864 * Returns PCI power state suitable for given device and given system
1007 * pci_save_state - save the PCI configuration space of a device before suspending
1008 * @dev: - PCI device that we're dealing with
1078 * pci_restore_state - Restore the saved state of a PCI device
1079 * @dev: - PCI device that we're dealing with
1086 /* PCI Express register must be restored first */ pci_restore_state()
1109 * @dev: PCI device that we're dealing with
1149 * @dev: PCI device that we're dealing with
1186 * @dev: PCI device that we're dealing with
1240 * @dev: PCI device to be resumed
1316 * @dev: PCI device to be initialized
1330 * @dev: PCI device to be initialized
1344 * @dev: PCI device to be initialized
1360 * Managed PCI resources. This manages device on/off, intx/msi/msix
1363 * when a device is enabled using managed PCI device enable interface.
1418 * @pdev: PCI device to be initialized
1443 * pcim_pin_device - Pin managed PCI device
1444 * @pdev: PCI device to pin
1446 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1463 * @dev: the PCI device being added
1476 * @dev: the PCI device being released
1485 * pcibios_disable_device - disable arch specific PCI resources for device dev pcibios_release_device()
1486 * @dev: the PCI device to disable pcibios_release_device()
1488 * Disables architecture specific PCI resources for the device. This pcibios_release_device()
1520 * @dev: PCI device to disable
1522 * NOTE: This function is a backend of PCI power management routines and is
1532 * pci_disable_device - Disable PCI device after use
1533 * @dev: PCI device to be disabled
1535 * Signal to the system that the PCI device is not in use by the system
1536 * anymore. This only involves disabling PCI bus-mastering, if active.
1582 * Sets the PCI reset state for the device.
1626 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1657 * pci_pme_capable - check the capability of PCI device to generate PME#
1658 * @dev: PCI device to handle.
1659 * @state: PCI state from which device will issue PME#.
1700 * pci_pme_active - enable or disable PCI device's PME# function
1701 * @dev: PCI device to handle.
1723 * PCI (as opposed to PCIe) PME requires that the device have pci_pme_active()
1737 * there are PCI Express Root Ports that don't bother to pci_pme_active()
1776 * __pci_enable_wake - enable PCI device as wakeup event source
1777 * @dev: PCI device affected
1778 * @state: PCI state from which device will issue wakeup events
1786 * Devices with legacy power management (no standard PCI PM capabilities)
1808 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don __pci_enable_wake()
1841 * @dev: PCI device to prepare
1846 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1862 * pci_target_state - find an appropriate low power state for a given PCI dev
1863 * @dev: PCI device
1910 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1937 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
1950 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
1951 * @dev: PCI device being suspended.
2067 * pci_pm_init - Initialize PM functions of given PCI device
2068 * @dev: PCI device to handle.
2084 /* find PCI PM capability in list */ pci_pm_init()
2146 * @dev: the PCI device
2189 * @dev: the PCI device
2199 "unable to preallocate PCI Express save buffer\n"); pci_allocate_cap_save_buffers()
2204 "unable to preallocate PCI-X save buffer\n"); pci_allocate_cap_save_buffers()
2220 * @dev: the PCI device
2264 * @dev: the PCI device
2298 * @dev: the PCI device
2335 * @acs_flags: required PCI ACS flags
2357 * Conventional PCI and PCI-X devices never support ACS, either pci_acs_enabled()
2366 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec, pci_acs_enabled()
2367 * but since their primary interface is PCI/X, we conservatively pci_acs_enabled()
2418 * Walk up a device tree from start to end testing PCI ACS support. If
2443 * @dev: the PCI device
2447 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
2450 * the PCI Express Base Specification, Revision 2.1)
2482 * @dev: the PCI device
2485 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
2486 * bridges all the way up to a PCI root bus.
2502 * pci_release_region - Release a PCI bar
2503 * @pdev: PCI device whose resources were previously reserved by pci_request_region
2506 * Releases the PCI I/O and memory resources previously reserved by a
2508 * after all use of the PCI regions has ceased.
2530 * __pci_request_region - Reserved PCI I/O and memory resource
2531 * @pdev: PCI device whose resources are to be reserved
2536 * Mark the PCI region associated with PCI device @pdev BR @bar as
2538 * address inside the PCI regions unless this call returns
2580 * pci_request_region - Reserve PCI I/O and memory resource
2581 * @pdev: PCI device whose resources are to be reserved
2585 * Mark the PCI region associated with PCI device @pdev BAR @bar as
2587 * address inside the PCI regions unless this call returns
2600 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
2601 * @pdev: PCI device whose resources are to be reserved
2605 * Mark the PCI region associated with PCI device @pdev BR @bar as
2607 * address inside the PCI regions unless this call returns
2625 * pci_release_selected_regions - Release selected PCI I/O and memory resources
2626 * @pdev: PCI device whose resources were previously reserved
2629 * Release selected PCI I/O and memory resources previously reserved.
2630 * Call this function only after all use of the PCI regions has ceased.
2663 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
2664 * @pdev: PCI device whose resources are to be reserved
2684 * pci_release_regions - Release reserved PCI I/O and memory resources
2685 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
2687 * Releases all PCI I/O and memory resources previously reserved by a
2689 * after all use of the PCI regions has ceased.
2699 * pci_request_regions - Reserved PCI I/O and memory resources
2700 * @pdev: PCI device whose resources are to be reserved
2703 * Mark all PCI regions associated with PCI device @pdev as
2705 * address inside the PCI regions unless this call returns
2718 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
2719 * @pdev: PCI device whose resources are to be reserved
2722 * Mark all PCI regions associated with PCI device @pdev as
2724 * address inside the PCI regions unless this call returns
2801 * pcibios_set_master - enable PCI bus-mastering for device dev
2802 * @dev: the PCI device to enable
2804 * Enables PCI bus-mastering for the device. This is the default
2829 * @dev: the PCI device to enable
2843 * @dev: the PCI device to disable
2853 * @dev: the PCI device for which MWI is to be enabled
2890 * pci_set_mwi - enables memory-write-invalidate PCI transaction
2891 * @dev: the PCI device for which MWI is enabled
2921 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
2922 * @dev: the PCI device for which MWI is enabled
2941 * @dev: the PCI device to disable
2943 * Disables PCI Memory-Write-Invalidate transaction on the device
2960 * pci_intx - enables/disables PCI INTx for device dev
2961 * @pdev: the PCI device to operate on
2962 * @enable: boolean: whether to enable or disable PCI INTx
2964 * Enables/disables PCI INTx for device dev
2993 * @dev: the PCI device to operate on
3078 * @dev: the PCI device to operate on
3092 * @dev: the PCI device to operate on
3106 * @dev: the PCI device to operate on
3151 * @dev: the PCI device to operate on
3219 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
3267 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double pci_reset_secondary_bus()
3276 * Trhfa for conventional PCI is 2^25 clock cycles. pci_reset_secondary_bus()
3291 * pci_reset_bridge_secondary_bus - Reset the secondary bus on a PCI bridge.
3442 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3 pci_dev_save_and_disable()
3470 * __pci_reset_function - reset a PCI device function
3471 * @dev: PCI device to reset
3474 * other functions in the same device. The PCI device must be responsive
3475 * to PCI config space in order to use this function.
3478 * Resetting the device will make the contents of PCI configuration space
3493 * __pci_reset_function_locked - reset a PCI device function while holding
3495 * @dev: PCI device to reset
3498 * other functions in the same device. The PCI device must be responsive
3499 * to PCI config space in order to use this function.
3503 * Resetting the device will make the contents of PCI configuration space
3519 * @dev: PCI device to reset
3522 * other functions in the same device. The PCI device must be responsive
3523 * to PCI config space in order to use this function.
3534 * pci_reset_function - quiesce and reset a PCI device function
3535 * @dev: PCI device to reset
3538 * other functions in the same device. The PCI device must be responsive
3539 * to PCI config space in order to use this function.
3541 * This function does not just reset the PCI portion of a device, but
3568 * pci_try_reset_function - quiesce and reset a PCI device function
3569 * @dev: PCI device to reset
3813 * pci_probe_reset_slot - probe whether a PCI slot can be reset
3814 * @slot: PCI slot to probe
3825 * pci_reset_slot - reset a PCI slot
3826 * @slot: PCI slot to reset
3828 * A PCI bus may host multiple slots, each slot may support a reset mechanism
3834 * through this function. PCI config space of all devices in the slot and
3858 * pci_try_reset_slot - Try to reset a PCI slot
3859 * @slot: PCI slot to reset
3906 * pci_probe_reset_bus - probe whether a PCI bus can be reset
3907 * @bus: PCI bus to probe
3918 * pci_reset_bus - reset a PCI bus
3919 * @bus: top level PCI bus to reset
3945 * pci_try_reset_bus - Try to reset a PCI bus
3946 * @bus: top level PCI bus to reset
3974 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
3975 * @dev: PCI device to query
3997 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
3998 * @dev: PCI device to query
4020 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
4021 * @dev: PCI device to query
4067 * pcie_get_readrq - get PCI Express read request size
4068 * @dev: PCI device to query
4084 * pcie_set_readrq - set PCI Express maximum memory read request
4085 * @dev: PCI device to query
4119 * pcie_get_mps - get PCI Express maximum payload size
4120 * @dev: PCI device to query
4135 * pcie_set_mps - set PCI Express maximum payload size
4136 * @dev: PCI device to query
4160 * pcie_get_minimum_link - determine minimum link settings of a PCI device
4161 * @dev: PCI device to query
4165 * This function will walk up the PCI device chain and determine the minimum
4204 * @dev: the PCI device for which BAR mask is made
4221 * @dev: the PCI device
4268 * @dev: the PCI device
4344 * @dev: the PCI device to get
4371 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n", pci_specified_resource_alignment()
4412 /* check if specified PCI is target device to reassign */ pci_reassigndev_resource_alignment()
4568 * pci_ext_cfg_avail - can we access extended PCI config space?
4570 * Returns 1 if we can access PCI extended config space (offsets
4627 printk(KERN_ERR "PCI: Unknown option `%s'\n", pci_setup()
H A Dslot.c54 "33 MHz PCI", /* 0x00 */
55 "66 MHz PCI", /* 0x01 */
56 "66 MHz PCI-X", /* 0x02 */
57 "100 MHz PCI-X", /* 0x03 */
58 "133 MHz PCI-X", /* 0x04 */
63 "66 MHz PCI-X 266", /* 0x09 */
64 "100 MHz PCI-X 266", /* 0x0a */
65 "133 MHz PCI-X 266", /* 0x0b */
71 "66 MHz PCI-X 533", /* 0x11 */
72 "100 MHz PCI-X 533", /* 0x12 */
73 "133 MHz PCI-X 533", /* 0x13 */
210 * pci_create_slot - create or increment refcount for physical PCI slot
216 * PCI slots have first class attributes such as address, speed, width,
243 * consist solely of a dddd:bb tuple, where dddd is the PCI domain of the
323 * pci_destroy_slot - decrement refcount for physical PCI slot
391 printk(KERN_ERR "PCI: Slot initialization failure\n"); pci_slot_init()
H A Dsetup-irq.c9 * Support routines for initializing a PCI subsystem.
35 time the interrupt line passes through a PCI-PCI bridge we must pdev_fixup_irq()
/linux-4.1.27/drivers/acpi/acpica/
H A Dhwpci.c3 * Module Name: hwpci - Obtain PCI bus, device, and function numbers
50 /* PCI configuration space values */
54 /* PCI header values */
86 * PARAMETERS: pci_id - Initial values for the PCI ID. May be
88 * root_pci_device - A handle to a PCI device object. This
89 * object must be a PCI Root Bridge having a
91 * pci_region - A handle to a PCI configuration space
96 * DESCRIPTION: This function derives a full PCI ID for a PCI device,
100 * The PCI hardware dynamically configures PCI bus numbers
111 * Function number PCI ID subfields as appropriate for the
134 /* Build a list of PCI devices, from pci_region up to root_pci_device */ acpi_hw_derive_pci_id()
140 /* Walk the list, updating the PCI device/function/bus numbers */ acpi_hw_derive_pci_id()
156 * PARAMETERS: root_pci_device - A handle to a PCI device object. This
157 * object is guaranteed to be a PCI Root
160 * pci_region - A handle to the PCI configuration space
162 * return_list_head - Where the PCI device list is returned
166 * DESCRIPTION: Builds a list of devices from the input PCI region up to the
167 * Root PCI device for this namespace subtree.
184 * a list of device nodes. Loop will exit when either the PCI device is acpi_hw_build_pci_list()
198 /* Finished when we reach the PCI root device (PNP0A03 or PNP0A08) */ acpi_hw_build_pci_list()
228 * PARAMETERS: pci_id - Initial values for the PCI ID. May be
235 * DESCRIPTION: Walk downward through the PCI device list, getting the device
236 * info for each, via the PCI configuration space and updating
237 * the PCI ID as necessary. Deletes the list during traversal.
260 * Descend down the namespace tree, collecting PCI device, function, acpi_hw_process_pci_list()
261 * and bus numbers. bus_number is only important for PCI bridges. acpi_hw_process_pci_list()
262 * Algorithm: As we descend the tree, use the last valid PCI device, acpi_hw_process_pci_list()
264 * to the PCI ID for the target device. acpi_hw_process_pci_list()
295 * DESCRIPTION: Free the entire PCI list.
316 * PARAMETERS: pci_id - Initial values for the PCI ID. May be
318 * pci_device - Handle for the PCI device object
319 * bus_number - Where a PCI bridge bus number is returned
320 * is_bridge - Return value, indicates if this PCI
321 * device is a PCI bridge
325 * DESCRIPTION: Get the device info for a single PCI device object. Get the
326 * _ADR (contains PCI device and function numbers), and for PCI
327 * bridge devices, get the bus number from PCI configuration
362 * From _ADR, get the PCI Device and Function and acpi_hw_get_pci_device_info()
363 * update the PCI ID. acpi_hw_get_pci_device_info()
377 * Get the bus numbers from PCI Config space: acpi_hw_get_pci_device_info()
379 * First, get the PCI header_type acpi_hw_get_pci_device_info()
/linux-4.1.27/arch/powerpc/platforms/52xx/
H A Dmpc52xx_pci.c2 * PCI code for the Freescale MPC52xx embedded CPU.
23 /* Structures mapping & Defines for PCI Unit */
64 u32 idr; /* PCI + 0x00 */
65 u32 scr; /* PCI + 0x04 */
66 u32 ccrir; /* PCI + 0x08 */
67 u32 cr1; /* PCI + 0x0C */
68 u32 bar0; /* PCI + 0x10 */
69 u32 bar1; /* PCI + 0x14 */
70 u8 reserved1[16]; /* PCI + 0x18 */
71 u32 ccpr; /* PCI + 0x28 */
72 u32 sid; /* PCI + 0x2C */
73 u32 erbar; /* PCI + 0x30 */
74 u32 cpr; /* PCI + 0x34 */
75 u8 reserved2[4]; /* PCI + 0x38 */
76 u32 cr2; /* PCI + 0x3C */
77 u8 reserved3[32]; /* PCI + 0x40 */
78 u32 gscr; /* PCI + 0x60 */
79 u32 tbatr0; /* PCI + 0x64 */
80 u32 tbatr1; /* PCI + 0x68 */
81 u32 tcr; /* PCI + 0x6C */
82 u32 iw0btar; /* PCI + 0x70 */
83 u32 iw1btar; /* PCI + 0x74 */
84 u32 iw2btar; /* PCI + 0x78 */
85 u8 reserved4[4]; /* PCI + 0x7C */
86 u32 iwcr; /* PCI + 0x80 */
87 u32 icr; /* PCI + 0x84 */
88 u32 isr; /* PCI + 0x88 */
89 u32 arb; /* PCI + 0x8C */
90 u8 reserved5[104]; /* PCI + 0x90 */
91 u32 car; /* PCI + 0xF8 */
92 u8 reserved6[4]; /* PCI + 0xFC */
103 /* PCI configuration access */
234 /* PCI setup */
309 /* Map IMMR onto PCI bus */ mpc52xx_pci_setup()
314 /* Map memory onto PCI bus */ mpc52xx_pci_setup()
322 /* Reset the exteral bus ( internal PCI controller is NOT resetted ) */ mpc52xx_pci_setup()
330 /* Make sure the PCI bridge is out of reset */ mpc52xx_pci_setup()
342 /* We don't rely on boot loader for PCI and resets all mpc52xx_pci_fixup_resources()
353 /* The PCI Host bridge of MPC52xx has a prefetch memory resource mpc52xx_pci_fixup_resources()
372 pr_debug("Adding MPC52xx PCI host bridge %s\n", node->full_name); mpc52xx_add_bridge()
388 /* There are some PCI quirks on the 52xx, register the hook to mpc52xx_add_bridge()
393 * tree are needed to configure the 52xx PCI controller. Rather mpc52xx_add_bridge()
411 /* Finish setting up PCI using values obtained by mpc52xx_add_bridge()
/linux-4.1.27/arch/x86/include/asm/
H A Dpci-functions.h2 * PCI BIOS function numbering for conventional PCI BIOS
H A Dcpu_device_id.h6 * Similar in spirit to pci_device_id and related PCI functions
H A Dpci-direct.h6 /* Direct PCI access. This is used for PCI accesses in early boot before
7 the PCI subsystem works. */
/linux-4.1.27/arch/alpha/kernel/
H A Dsys_sable.c66 * 0 PCI slot 0 34
70 * 4 PCI slot 1 35
71 * 5 PCI slot 2 36
137 2, 1, 0, 4, 5, -1, -1, -1, /* pseudo PCI */
170 * PCI Fixup configuration for ALPHA SABLE (2100).
177 * 2 PCI-EISA bridge
181 * 6 PCI on board slot 0
182 * 7 PCI on board slot 1
183 * 8 PCI on board slot 2
187 * above for PCI interrupts. The IRQ relates to which bit the interrupt
257 *32 PCI 0 slot 4 A primary bus 32
258 *33 PCI 0 slot 4 B primary bus 33
259 *34 PCI 0 slot 4 C primary bus 34
260 *35 PCI 0 slot 4 D primary bus
261 *36 PCI 0 slot 5 A primary bus
262 *37 PCI 0 slot 5 B primary bus
263 *38 PCI 0 slot 5 C primary bus
264 *39 PCI 0 slot 5 D primary bus
265 *40 PCI 0 slot 6 A primary bus
266 *41 PCI 0 slot 6 B primary bus
267 *42 PCI 0 slot 6 C primary bus
268 *43 PCI 0 slot 6 D primary bus
269 *44 PCI 0 slot 7 A primary bus
270 *45 PCI 0 slot 7 B primary bus
271 *46 PCI 0 slot 7 C primary bus
272 *47 PCI 0 slot 7 D primary bus
273 *48 PCI 0 slot 0 A secondary bus
274 *49 PCI 0 slot 0 B secondary bus
275 *50 PCI 0 slot 0 C secondary bus
276 *51 PCI 0 slot 0 D secondary bus
277 *52 PCI 0 slot 1 A secondary bus
278 *53 PCI 0 slot 1 B secondary bus
279 *54 PCI 0 slot 1 C secondary bus
280 *55 PCI 0 slot 1 D secondary bus
281 *56 PCI 0 slot 2 A secondary bus
282 *57 PCI 0 slot 2 B secondary bus
283 *58 PCI 0 slot 2 C secondary bus
284 *59 PCI 0 slot 2 D secondary bus
285 *60 PCI 0 slot 3 A secondary bus
286 *61 PCI 0 slot 3 B secondary bus
287 *62 PCI 0 slot 3 C secondary bus
288 *63 PCI 0 slot 3 D secondary bus
349 * PCI Fixup configuration for ALPHA LYNX (2100A)
356 * 2 PCI-EISA bridge
357 * 3 PCI-PCI bridge
360 * 6 PCI on board slot 4
361 * 7 PCI on board slot 5
362 * 8 PCI on board slot 6
363 * 9 PCI on board slot 7
367 * 11 PCI on board slot 0
368 * 12 PCI on board slot 1
369 * 13 PCI on board slot 2
370 * 14 PCI on board slot 3
H A Dsys_rx164.c75 the DIRR register in PCI config space (offset 0x84). */ rx164_device_interrupt()
136 * 5 32 bit PCI option slot 0
137 * 6 64 bit PCI option slot 1
138 * 7 PCI-ISA bridge
139 * 7 64 bit PCI option slot 2
140 * 9 32 bit PCI option slot 3
141 * 10 PCI-PCI bridge
154 { -1, -1, -1, -1, -1}, /* IdSel 8, PCI/ISA bridge */ rx164_map_irq()
163 { -1, -1, -1, -1, -1}, /* IdSel 7, PCI/ISA bridge */ rx164_map_irq()
166 { 16+4, 16+4, 16+10, 16+15, 16+5}, /* IdSel 10, PCI-PCI */ rx164_map_irq()
H A Dpci.c9 /* 2.3.x PCI/resources, 1999 Andrea Arcangeli <andrea@suse.de> */
13 * PCI-PCI bridges cleanup
35 "PCI IO bus 0", "PCI IO bus 1", "PCI IO bus 2", "PCI IO bus 3",
36 "PCI IO bus 4", "PCI IO bus 5", "PCI IO bus 6", "PCI IO bus 7"
40 "PCI mem bus 0", "PCI mem bus 1", "PCI mem bus 2", "PCI mem bus 3",
41 "PCI mem bus 4", "PCI mem bus 5", "PCI mem bus 6", "PCI mem bus 7"
47 * If PCI_PROBE_ONLY in pci_flags is set, we don't change any PCI resource
52 * The PCI controller list.
87 /* The Cypress bridge responds on the PCI bus in the address range quirk_cypress()
106 /* Called for each device after PCI setup is done. */ pcibios_fixup_final()
151 * Alpha implementation of the PCI interface: pcibios_align_resource()
158 * avoid allocating PCI devices in that range. pcibios_align_resource()
268 printk("PCI: Setting latency timer of device %s to 64\n", pcibios_set_master()
322 /* Scan all of the recorded PCI controllers. */ common_init_pci()
326 /* Adjust hose mem_space limit to prevent PCI allocations common_init_pci()
H A Dsys_rawhide.c141 * The RAWHIDE SRM console reports PCI interrupts with a vector rawhide_srm_device_interrupt()
142 * 0x80 *higher* than one might expect, as PCI IRQ 0 (ie bit 0) rawhide_srm_device_interrupt()
147 * Also, PCI #1 interrupts are offset some more... :-( rawhide_srm_device_interrupt()
192 * PCI Fixup configuration.
212 * 16 EISA interrupt (PCI 0) or SCSI interrupt (PCI 1)
216 * 1 EISA bridge (PCI bus 0 only)
217 * 2 PCI option slot 2
218 * 3 PCI option slot 3
219 * 4 PCI option slot 4
220 * 5 PCI option slot 5
229 { 16+16, 16+16, 16+16, 16+16, 16+16}, /* IdSel 1 SCSI PCI 1 */ rawhide_map_irq()
H A Dsys_miata.c47 * for reporting any interrupts (the PCI-ISA bridge, bit 7, isn't miata_srm_device_interrupt()
89 * PCI Fixup configuration.
100 * 7 PCI-ISA Bridge
133 * 7 PCI-ISA bridge
134 * 8 PCI-PCI Bridge (SBU Riser)
137 * 11 PCI on board slot 4 (SBU Riser)
138 * 12 PCI on board slot 5 (SBU Riser)
142 * 13 PCI on board slot 1 (SBU Riser)
143 * 14 PCI on board slot 2 (SBU Riser)
144 * 15 PCI on board slot 3 (SBU Riser)
148 * above for PCI interrupts. The IRQ relates to which bit the interrupt
161 { -1, -1, -1, -1, -1}, /* IdSel 18, PCI-ISA */ miata_map_irq()
162 { -1, -1, -1, -1, -1}, /* IdSel 19, PCI-PCI */ miata_map_irq()
167 /* the next 7 are actually on PCI bus 1, across the bridge */ miata_map_irq()
176 { -1, -1, -1, -1, -1}, /* IdSel 31, PCI-PCI */ miata_map_irq()
H A Dsys_wildfire.c169 /* Only need the following for first PCI bus per PCA. */ wildfire_init_irq_per_pca()
242 * PCI Fixup configuration.
244 * Summary per PCA (2 PCI or HIPPI buses):
282 * 1 64 bit PCI 0 option slot 1 (SCSI QLogic builtin)
283 * 2 64 bit PCI 0 option slot 2
284 * 3 64 bit PCI 0 option slot 3
285 * 4 64 bit PCI 1 option slot 4
286 * 5 64 bit PCI 1 option slot 5
287 * 6 64 bit PCI 1 option slot 6
288 * 7 64 bit PCI 1 option slot 7
298 { 40, 40, 40+1, 40+2, 40+3}, /* IdSel 2 PCI 0 slot 2 */ wildfire_map_irq()
299 { 44, 44, 44+1, 44+2, 44+3}, /* IdSel 3 PCI 0 slot 3 */ wildfire_map_irq()
300 { 48, 48, 48+1, 48+2, 48+3}, /* IdSel 4 PCI 1 slot 4 */ wildfire_map_irq()
301 { 52, 52, 52+1, 52+2, 52+3}, /* IdSel 5 PCI 1 slot 5 */ wildfire_map_irq()
302 { 56, 56, 56+1, 56+2, 56+3}, /* IdSel 6 PCI 1 slot 6 */ wildfire_map_irq()
303 { 60, 60, 60+1, 60+2, 60+3}, /* IdSel 7 PCI 1 slot 7 */ wildfire_map_irq()
H A Dpci_impl.h5 * with the PCI initialization routines.
14 * may also have PCI-PCI bridges present, and then we'd configure the
19 * BIOSes (Millennium for one) use PCI Config space "mechanism #2"
31 * will always have a PCI memory address that will never match a IDSEL
32 * address in PCI Config space, which can cause problems with early rev cards.
37 * that get passed through the PCI<->ISA bridge chip. Although this causes
38 * us to set the PCI->Mem window bases lower than normal, we still allocate
39 * PCI bus devices' memory addresses *below* the low DMA mapping window,
49 * APECS and LCA have only 34 bits for physical addresses, thus limiting PCI
78 * later) adheres to the PCI-PCI bridge specification. This says that
125 /* A PCI IOMMU allocation arena. There are typically two of these
159 /* Store PCI device configuration left by SRM here. */
H A Dsys_sx164.c60 * PCI Fixup configuration.
71 * 7 PCI-ISA Bridge
90 * 5 32 bit PCI option slot 2
91 * 6 64 bit PCI option slot 0
92 * 7 64 bit PCI option slot 1
94 * 9 32 bit PCI option slot 3
/linux-4.1.27/arch/powerpc/sysdev/
H A Dfsl_pci.h2 * MPC85xx/86xx PCI Express structure define
20 /* FSL PCI controller BRR1 register */
42 /* PCI/PCI Express outbound window reg */
52 /* PCI/PCI Express inbound window reg */
62 /* PCI/PCI Express IO block registers for 85xx/86xx */
64 __be32 config_addr; /* 0x.000 - PCI/PCIE Configuration Address Register */
65 __be32 config_data; /* 0x.004 - PCI/PCIE Configuration Data Register */
66 __be32 int_ack; /* 0x.008 - PCI Interrupt Acknowledge Register */
80 /* PCI/PCI Express outbound window 0-4
89 /* PCI/PCI Express inbound window 3-0
95 __be32 pex_err_dr; /* 0x.e00 - PCI/PCIE error detect register */
97 __be32 pex_err_en; /* 0x.e08 - PCI/PCIE error interrupt enable register */
99 __be32 pex_err_disr; /* 0x.e10 - PCI/PCIE error disable register */
101 __be32 pex_err_cap_stat; /* 0x.e20 - PCI/PCIE error capture status register */
H A Dtsi108_pci.c76 printk("PCI CFG write : "); tsi108_direct_write_config()
102 * Quietly clear PB and PCI error flags set as result tsi108_clear_pci_error()
103 * of PCI/X configuration read requests. tsi108_clear_pci_error()
120 /* Clear PCI/X bus cfg errors if applicable */ tsi108_clear_pci_error()
179 printk("PCI CFG read : "); tsi108_direct_read_config()
206 /* PCI Config mapping */ tsi108_setup_pci()
225 printk("PCI Host bridge init failed\n"); tsi108_setup_pci()
234 printk(KERN_INFO "Found tsi108 PCI host bridge at 0x%08x. " tsi108_setup_pci()
292 /* Read PCI/X block interrupt status register */ get_pci_source()
297 /* Process Interrupt from PCI bus INTA# - INTD# lines */ get_pci_source()
310 /* Disable interrupts from PCI block */ get_pci_source()
350 /* Enable interrupts from PCI block */ tsi108_pci_irq_unmask()
369 * Interrupt controller descriptor for cascaded PCI interrupt controller.
410 * The Tsi108 PCI interrupts initialization routine.
412 * The INTA# - INTD# interrupts on the PCI bus are reported by the PCI block
414 * PCI block has to be treated as a cascaded interrupt controller connected
420 DBG("Tsi108_pci_int_init: initializing PCI interrupts\n"); tsi108_pci_int_init()
/linux-4.1.27/drivers/staging/comedi/drivers/
H A D8255_pci.c2 * COMEDI driver for generic PCI based 8255 digital i/o boards
26 * Description: Generic PCI based 8255 Digital I/O boards
27 * Devices: [ADLink] PCI-7224 (adl_pci-7224), PCI-7248 (adl_pci-7248),
28 * PCI-7296 (adl_pci-7296),
29 * [Measurement Computing] PCI-DIO24 (cb_pci-dio24),
30 * PCI-DIO24H (cb_pci-dio24h), PCI-DIO48H (cb_pci-dio48h),
31 * PCI-DIO96H (cb_pci-dio96h),
32 * [National Instruments] PCI-DIO-96 (ni_pci-dio-96),
33 * PCI-DIO-96B (ni_pci-dio-96b), PXI-6508 (ni_pxi-6508),
34 * PCI-6503 (ni_pci-6503), PCI-6503B (ni_pci-6503b),
35 * PCI-6503X (ni_pci-6503x), PXI-6503 (ni_pxi-6503)
45 * PCI-7224, PCI-DIO24, PCI-DIO24H, PCI-6503, PCI-6503B, PCI-6503X,
50 * PCI-7248, PCI-DIO48H
54 * PCI-7296, PCI-DIO96H, PCI-DIO-96, PCI-DIO-96B, PXI-6508
61 * Configuration Options: not applicable, uses PCI auto config.
302 MODULE_DESCRIPTION("COMEDI - Generic PCI based 8255 Digital I/O boards");
H A Dadl_pci7x3x.c2 * COMEDI driver for the ADLINK PCI-723x/743x series boards.
27 * Devices: [ADLink] PCI-7230 (adl_pci7230), PCI-7233 (adl_pci7233),
28 * PCI-7234 (adl_pci7234), PCI-7432 (adl_pci7432), PCI-7433 (adl_pci7433),
29 * PCI-7434 (adl_pci7434)
38 * PCI-7230 - 2 subdevices: 0 - 16 input, 1 - 16 output
39 * PCI-7233 - 1 subdevice: 0 - 32 input
40 * PCI-7234 - 1 subdevice: 0 - 32 output
41 * PCI-7432 - 2 subdevices: 0 - 32 input, 1 - 32 output
42 * PCI-7433 - 2 subdevices: 0 - 32 input, 1 - 32 input
43 * PCI-7434 - 2 subdevices: 0 - 32 output, 1 - 32 output
45 * The PCI-7230, PCI-7432 and PCI-7433 boards also support external
46 * interrupt signals on digital input channels 0 and 1. The PCI-7233
52 * Configuration Options: not applicable, uses comedi PCI auto config
128 * It seems the PCI-7230 needs the 16-bit DO state adl_pci7x3x_do_insn_bits()
285 MODULE_DESCRIPTION("ADLINK PCI-723x/743x Isolated Digital I/O boards");
H A Ddas08_pci.c3 * comedi driver for DAS08 PCI boards
23 * Description: DAS-08 PCI compatible boards
24 * Devices: [ComputerBoards] PCI-DAS08 (pci-das08)
29 * This is the PCI-specific support split off from the das08 driver.
31 * Configuration Options: not applicable, uses PCI auto config
H A Dadl_pci6208.c21 * Description: ADLink PCI-6208/6216 Series Multi-channel Analog Output Cards
22 * Devices: [ADLink] PCI-6208 (adl_pci6208), PCI-6216
27 * Configuration Options: not applicable, uses PCI auto config
29 * All supported devices share the same PCI device ID and are treated as a
30 * PCI-6216 with 16 analog output channels. On a PCI-6208, the upper 8
40 * PCI-6208/6216-GL register map
141 s->n_chan = 16; /* Only 8 usable on PCI-6208 */ pci6208_auto_attach()
H A Dni_labpc_pci.c3 * Driver for National Instruments Lab-PC PCI-1200
19 * Description: National Instruments Lab-PC PCI-1200
20 * Devices: [National Instruments] PCI-1200 (ni_pci-1200)
24 * This is the PCI-specific support split off from the ni_labpc driver.
26 * Configuration Options: not applicable, uses PCI auto config
139 MODULE_DESCRIPTION("Comedi: National Instruments Lab-PC PCI-1200 driver");
H A Dadv_pci_dio.c6 * Hardware driver for Advantech PCI DIO cards.
10 Description: Advantech PCI-1730, PCI-1733, PCI-1734, PCI-1735U,
11 PCI-1736UP, PCI-1739U, PCI-1750, PCI-1751, PCI-1752,
12 PCI-1753/E, PCI-1754, PCI-1756, PCI-1760, PCI-1762
14 Devices: [Advantech] PCI-1730 (adv_pci_dio), PCI-1733,
15 PCI-1734, PCI-1735U, PCI-1736UP, PCI-1739U, PCI-1750,
16 PCI-1751, PCI-1752, PCI-1753,
17 PCI-1753+PCI-1753E, PCI-1754, PCI-1756,
18 PCI-1760, PCI-1762
25 [0] - PCI bus of device (optional)
26 [1] - PCI slot of device (optional)
27 If bus/slot is not specified, the first available PCI
66 /* Advantech PCI-1730/3/4 */
79 /* Advantech PCI-1735U */
85 /* Advantech PCI-1736UP */
95 /* Advantech PCI-1739U */
101 /* Advantech PCI-1750 */
107 /* Advantech PCI-1751/3/3E */
123 /* Advantech PCI-1752/4/6 */
137 /* Advantech PCI-1762 registers */
144 /* Advantech PCI-1760 registers */
158 /* PCI-1760 mailbox commands */
224 int addr; /* PCI address ofset */
232 int main_pci_region; /* main I/O PCI region */
390 /* PCI-1760 specific data */
508 dev_err(dev->class_dev, "PCI-1760 mailbox request timeout!\n"); pci1760_unchecked_mbxrequest()
949 * board available. Need to enable PCI device and request the main pci_dio_override_cardtype()
950 * registers PCI BAR temporarily to perform the test. pci_dio_override_cardtype()
H A Dni_pcimio.c3 Hardware driver for NI PCI-MIO E series cards
20 Description: National Instruments PCI-MIO-E series and M series (all boards)
24 Devices: [National Instruments] PCI-MIO-16XE-50 (ni_pcimio),
25 PCI-MIO-16XE-10, PXI-6030E, PCI-MIO-16E-1, PCI-MIO-16E-4, PCI-6014, PCI-6040E,
26 PXI-6040E, PCI-6030E, PCI-6031E, PCI-6032E, PCI-6033E, PCI-6071E, PCI-6023E,
27 PCI-6024E, PCI-6025E, PXI-6025E, PCI-6034E, PCI-6035E, PCI-6052E,
28 PCI-6110, PCI-6111, PCI-6220, PCI-6221, PCI-6224, PXI-6224,
29 PCI-6225, PXI-6225, PCI-6229, PCI-6250, PCI-6251, PCIe-6251, PXIe-6251,
30 PCI-6254, PCI-6259, PCIe-6259,
31 PCI-6280, PCI-6281, PXI-6281, PCI-6284, PCI-6289,
32 PCI-6711, PXI-6711, PCI-6713, PXI-6713,
33 PXI-6071E, PCI-6070E, PXI-6070E,
34 PXI-6052E, PCI-6036E, PCI-6731, PCI-6733, PXI-6733,
35 PCI-6143, PXI-6143
39 they use the PCI bus instead of ISA (i.e., AT). See the notes for
57 Note that the PCI-6143 is a simultaineous sampling device with 8 convertors.
77 The PCI-MIO E series driver was originally written by
82 341079b.pdf PCI E Series Register-Level Programmer Manual
87 320945c.pdf PCI E Series User Manual
88 322138a.pdf PCI-6052E and DAQPad-6052E User Manual
100 two writes to the PCI bus slows IO enough. I would prefer to
/linux-4.1.27/arch/mips/loongson/common/cs5536/
H A Dcs5536_pci.c2 * read/write operation to the PCI config space of CS5536
15 * the Virtual Support Module(VSM) for virtulizing the PCI
18 * after this virtulizing, user can access the PCI configure space
19 * directly as a normal multi-function PCI device which follows
20 * the PCI-2.2 spec.
57 * write to PCI config space and transfer it to MSR write.
71 * read PCI config space and transfer it to MSR access.
/linux-4.1.27/arch/mips/cobalt/
H A Dpci.c2 * Register PCI controller.
22 .name = "PCI memory",
29 .name = "PCI I/O",
/linux-4.1.27/arch/arm/mach-iop32x/include/mach/
H A Dhardware.h11 * Note about PCI IO space mappings
16 * The PCI IO space is located at virtual 0xfe000000 from physical
17 * 0x90000000. The PCI BARs must be programmed with physical addresses,
/linux-4.1.27/arch/arm/mach-iop33x/include/mach/
H A Dhardware.h11 * Note about PCI IO space mappings
16 * The PCI IO space is located at virtual 0xfe000000 from physical
17 * 0x90000000. The PCI BARs must be programmed with physical addresses,
/linux-4.1.27/arch/arm/mach-ks8695/
H A Dpci.c80 .name = "PCI Memory space",
87 .name = "PCI IO space",
113 /* Reserve PCI memory space for PCI-AHB resources */ ks8695_pci_setup()
114 if (!request_mem_region(KS8695_PCIMEM_PA, SZ_64M, "PCI-AHB Bridge")) { ks8695_pci_setup()
115 printk(KERN_ERR "Cannot allocate PCI-AHB Bridge memory.\n"); ks8695_pci_setup()
135 printk(KERN_ERR "PCI abort: address = 0x%08lx fsr = 0x%03x PC = 0x%08lx LR = 0x%08lx [%s%s%s%s%s]\n", ks8695_pci_fault()
177 /* make software reset to avoid freeze if PCI bus was messed up */ ks8695_pci_preinit()
209 printk(KERN_INFO "PCI: CRCFID = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_CRCFID)); ks8695_show_pciregs()
210 printk(KERN_INFO "PCI: CRCFCS = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_CRCFCS)); ks8695_show_pciregs()
211 printk(KERN_INFO "PCI: CRCFRV = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_CRCFRV)); ks8695_show_pciregs()
212 printk(KERN_INFO "PCI: CRCFLT = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_CRCFLT)); ks8695_show_pciregs()
213 printk(KERN_INFO "PCI: CRCBMA = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_CRCBMA)); ks8695_show_pciregs()
214 printk(KERN_INFO "PCI: CRCSID = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_CRCSID)); ks8695_show_pciregs()
215 printk(KERN_INFO "PCI: CRCFIT = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_CRCFIT)); ks8695_show_pciregs()
217 printk(KERN_INFO "PCI: PBM = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_PBM)); ks8695_show_pciregs()
218 printk(KERN_INFO "PCI: PBCS = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_PBCS)); ks8695_show_pciregs()
220 printk(KERN_INFO "PCI: PMBA = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_PMBA)); ks8695_show_pciregs()
221 printk(KERN_INFO "PCI: PMBAC = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_PMBAC)); ks8695_show_pciregs()
222 printk(KERN_INFO "PCI: PMBAM = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_PMBAM)); ks8695_show_pciregs()
223 printk(KERN_INFO "PCI: PMBAT = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_PMBAT)); ks8695_show_pciregs()
225 printk(KERN_INFO "PCI: PIOBA = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_PIOBA)); ks8695_show_pciregs()
226 printk(KERN_INFO "PCI: PIOBAC = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_PIOBAC)); ks8695_show_pciregs()
227 printk(KERN_INFO "PCI: PIOBAM = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_PIOBAM)); ks8695_show_pciregs()
228 printk(KERN_INFO "PCI: PIOBAT = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_PIOBAT)); ks8695_show_pciregs()
244 printk("PCI: KS8695 in guest mode, not initialising\n"); ks8695_init_pci()
251 printk(KERN_INFO "PCI: Initialising\n"); ks8695_init_pci()
H A Dboard-og.c52 * The PCI bus reset is driven by a dedicated GPIO line. Toggle it here
53 * and bring the PCI bus out of reset.
59 /* Some boards use a different GPIO as the PCI reset line */ og_pci_bus_reset()
65 gpio_request(rstline, "PCI reset"); og_pci_bus_reset()
68 /* Drive a reset on the PCI reset line */ og_pci_bus_reset()
77 * Direct connect serial ports (non-PCI that is).
H A DMakefile8 # PCI support is optional
/linux-4.1.27/arch/m68k/include/asm/
H A Dm54xxpci.h4 * m54xxpci.h -- ColdFire 547x and 548x PCI bus support
19 * The core set of PCI support registers are mapped into the MBAR region.
21 #define PCIIDR (CONFIG_MBAR + 0xb00) /* PCI device/vendor ID */
22 #define PCISCR (CONFIG_MBAR + 0xb04) /* PCI status/command */
23 #define PCICCRIR (CONFIG_MBAR + 0xb08) /* PCI class/revision */
24 #define PCICR1 (CONFIG_MBAR + 0xb0c) /* PCI configuration 1 */
25 #define PCIBAR0 (CONFIG_MBAR + 0xb10) /* PCI base address 0 */
26 #define PCIBAR1 (CONFIG_MBAR + 0xb14) /* PCI base address 1 */
27 #define PCICCPR (CONFIG_MBAR + 0xb28) /* PCI cardbus CIS pointer */
28 #define PCISID (CONFIG_MBAR + 0xb2c) /* PCI subsystem IDs */
29 #define PCIERBAR (CONFIG_MBAR + 0xb30) /* PCI expansion ROM */
30 #define PCICPR (CONFIG_MBAR + 0xb34) /* PCI capabilities pointer */
31 #define PCICR2 (CONFIG_MBAR + 0xb3c) /* PCI configuration 2 */
74 #define PACR (CONFIG_MBAR + 0xc00) /* PCI arbiter control */
75 #define PASR (CONFIG_MBAR + 0xc04) /* PCI arbiter status */
125 * PCI arbiter support definitions and macros.
H A Dpci.h7 /* The PCI address space does equal the physical memory
H A Dvga.h8 * Ugh, we don't have PCI space, so map readb() and friends to use raw I/O
/linux-4.1.27/arch/arm/mach-footbridge/
H A Dcats-pci.c4 * PCI bios-type initialisation for PCI machines
36 printk("PCI: device %02x:%02x has unknown irq line %x\n", cats_map_irq()
43 * why not the standard PCI swizzle? does this prevent 4-port tulip
H A Dnetwinder-pci.c4 * PCI bios-type initialisation for PCI machines
39 printk(KERN_ERR "PCI: unknown device in slot %s\n", netwinder_map_irq()
H A Debsa285-pci.c4 * PCI bios-type initialisation for PCI machines
H A Ddc21285.c2 * linux/arch/arm/kernel/dec21285.c: PCI functions for DC21285
155 * Warn on PCI errors.
167 printk(KERN_DEBUG "PCI: master abort, pc=0x%08lx\n", dc21285_abort_irq()
173 printk(KERN_DEBUG "PCI: target abort: "); dc21285_abort_irq()
192 printk(KERN_DEBUG "PCI: system error received: "); dc21285_serr_irq()
211 printk(KERN_DEBUG "PCI: discard timer expired\n"); dc21285_discard_irq()
221 printk(KERN_DEBUG "PCI: data parity error detected: "); dc21285_dparity_irq()
236 printk(KERN_DEBUG "PCI: parity error detected: "); dc21285_parity_irq()
312 printk(KERN_INFO "PCI: DC21285 footbridge, revision %02lX, in " dc21285_preinit()
338 "PCI system error", &serr_timer); dc21285_preinit()
340 "PCI parity error", &perr_timer); dc21285_preinit()
342 "PCI abort", NULL); dc21285_preinit()
346 "PCI data parity", NULL); dc21285_preinit()
350 * Map our SDRAM at a known address in PCI space, just in case dc21285_preinit()
352 * necessary, since some VGA cards forcefully use PCI addresses dc21285_preinit()
368 panic("PCI: this kernel is compiled for central " dc21285_preinit()
H A Dpersonal-pci.c4 * PCI bios-type initialisation for PCI machines
/linux-4.1.27/include/linux/platform_data/
H A Dusb-rcar-gen2-phy.h17 bool chan0_pci:1; /* true: PCI USB host 0, false: USBHS */
19 bool chan2_pci:1; /* true: PCI USB host 2, false: USBSS */
/linux-4.1.27/arch/mips/pci/
H A Dpci-bcm63xx.h10 * Cardbus shares the PCI bus, but has no IDSEL, so a special id is
11 * reserved for it. If you have a standard PCI device at this id, you
H A Dpci-octeon.c29 * Octeon's PCI controller uses did=3, subdid=2 for PCI IO
30 * addresses. Use PCI endian swapping 1 so no address swapping is
36 /* Octeon't PCI controller uses did=3, subdid=3 for PCI memory. */
42 * This is the bit decoding used for the Octeon PCI controller addresses
67 * Map a PCI device to the appropriate interrupt line
69 * @dev: The Linux PCI device structure for the device to map
73 * @pin: The PCI interrupt pin read from the device, then swizzled
87 * Called to perform platform specific PCI setup
176 * Return the mapping of PCI device number to IRQ line. Each
179 * first character, etc. The characters A-D are used for PCI
182 * Returns PCI interrupt mapping
188 * routed based on the PCI specification. From the PCI spec: octeon_get_pci_interrupts()
227 * Map a PCI device to the appropriate interrupt line
229 * @dev: The Linux PCI device structure for the device to map
233 * @pin: The PCI interrupt pin read from the device, then swizzled
292 * Write a value to PCI configuration space
333 .name = "Octeon PCI MEM",
338 * PCI ports must be above 16KB so the ISA bus filtering in the PCI-X to PCI
344 .name = "Octeon PCI IO",
359 * Low level initialize the Octeon PCI controller
371 /* Reset the PCI Bus */ octeon_pci_initialize()
375 udelay(2000); /* Hold PCI reset for 2 ms */ octeon_pci_initialize()
382 /* Deassert PCI reset and advertize PCX Host Mode Device Capability octeon_pci_initialize()
387 udelay(2000); /* Wait 2 ms after deasserting PCI reset */ octeon_pci_initialize()
391 before any PCI reads. */ octeon_pci_initialize()
408 udelay(2000); /* Wait 2 ms before doing PCI reads */ octeon_pci_initialize()
411 pr_notice("PCI Status: %s %s-bit\n", octeon_pci_initialize()
412 ctl_status_2.s.ap_pcix ? "PCI-X" : "PCI", octeon_pci_initialize()
427 pr_notice("PCI Clock: %lu MHz\n", pci_clock); octeon_pci_initialize()
431 * TDOMC must be set to one in PCI mode. TDOMC should be set to 4 octeon_pci_initialize()
432 * in PCI-X mode to allow four outstanding splits. Otherwise, octeon_pci_initialize()
434 * in PCI mode (0x82000001 reset value), write it to 0x82000004 octeon_pci_initialize()
435 * after PCI-X mode is known. MRBCI,MDWE,MDRE -> must be zero. octeon_pci_initialize()
455 * (PCI only). CR4C[26:24] Max SAC cycles MAX DAC octeon_pci_initialize()
460 * 2 SAC cycles. NOTE: For the PCI-X maximum octeon_pci_initialize()
467 * select. 0 = Byte Enables valid. In PCI mode, a octeon_pci_initialize()
470 * (default). In PCI Mode, the memory read byte octeon_pci_initialize()
492 * When OCTEON is a PCI host, most systems will use OCTEON's octeon_pci_initialize()
493 * internal arbiter, so must enable it before any PCI/PCI-X octeon_pci_initialize()
530 * notation) when OCTEON is in PCI-X mode. PCI-X performance is octeon_pci_initialize()
536 cfg56.s.pxcid = 7; /* RO - PCI-X Capability ID */ octeon_pci_initialize()
548 * Affects PCI performance when OCTEON services reads to its octeon_pci_initialize()
553 * of the end of memory if PCI is DMAing a buffer at the end of octeon_pci_initialize()
563 * Initialize the Octeon PCI controller
570 /* Only these chips have PCI */ octeon_pci_setup()
574 /* Point pcibios_map_irq() to the PCI version of it */ octeon_pci_setup()
586 pr_notice("Not in host mode, PCI Controller not initialized\n"); octeon_pci_setup()
590 /* PCI I/O and PCI MEM values */ octeon_pci_setup()
608 mem_access.s.ba = 0; /* PCI Address bits [63:36]. */ octeon_pci_setup()
643 /* Don't put PCI accesses in L2. */ octeon_pci_setup()
679 /* Don't put PCI accesses in L2. */ octeon_pci_setup()
H A Dfixup-malta.c5 /* PCI interrupt pins */
17 {0, 0, 0, 0, 0 }, /* 0: GT64120 PCI bridge */
34 {0, 0, 0, 0, 0 }, /* 17: Bonito/SOC-it PCI Bridge*/
35 {0, PCIA, PCIB, PCIC, PCID }, /* 18: PCI Slot 1 */
36 {0, PCIB, PCIC, PCID, PCIA }, /* 19: PCI Slot 2 */
37 {0, PCIC, PCID, PCIA, PCIB }, /* 20: PCI Slot 3 */
38 {0, PCID, PCIA, PCIB, PCIC } /* 21: PCI Slot 4 */
81 /* Interrogate PIIX4 to get PCI IRQ mapping */ malta_piix_func0_fixup()
144 /* Enable PCI 2.1 compatibility in PIIX4 */ quirk_dlcsetup()
H A Dops-pmcmsp.c59 * DESCRIPTION: Prints the count of how many times each PCI
107 * PCI bus. Intent is that this function by invocable from
126 seq_puts(m, "PMC MSP PCI: Beginning\n"); gen_pci_cfg_wr_show()
133 seq_puts(m, "PMC MSP PCI: Before Cfg Wr\n"); gen_pci_cfg_wr_show()
136 * Generate PCI Configuration Write Cycle gen_pci_cfg_wr_show()
142 /* Setup address that is to appear on PCI bus */ gen_pci_cfg_wr_show()
150 /* Launch the PCI configuration write cycle */ gen_pci_cfg_wr_show()
154 * Check if the PCI configuration cycle (rd or wr) succeeded, by gen_pci_cfg_wr_show()
159 seq_puts(m, "PMC MSP PCI: After Cfg Wr\n"); gen_pci_cfg_wr_show()
202 * assign to the I/O BARs of PCI devices.
204 * Use the start and end addresses of the MSP7120 PCI Host
206 * PCI bus AFTER MSP7120 has performed address translation.
226 * the address on the PCI bus.
229 * the address on the PCI bus.
248 * assign to the memory BARs of PCI devices.
254 * in the form they appear on the PCI bus AFTER MSP7120 has
261 * the address on the PCI bus.
264 * the address on the PCI bus.
282 * DESCRIPTION: PCI status interrupt handler. Updates the count of how
309 /* printk("PCI ISR: Status=%08X\n", stat); */ bpci_interrupt()
322 * DESCRIPTION: Performs a PCI configuration access (rd or wr), then
324 * PCI status bits.
327 * access_type - kind of PCI configuration cycle to perform
337 * PCI Host, any non-zero bus->number generates
386 * an interrupt line for PCI host status interrupts. The msp_pcibios_config_access()
393 "PMC MSP PCI Host", msp_pcibios_config_access()
405 * Clear PCI cause register bits. msp_pcibios_config_access()
407 * In Polo, the PCI Host had a dedicated DMA called the msp_pcibios_config_access()
417 * Write to clear all interrupts in the PCI status register, aside msp_pcibios_config_access()
422 /* Setup address that is to appear on PCI bus */ msp_pcibios_config_access()
428 /* IF access is a PCI configuration write */ msp_pcibios_config_access()
433 /* ELSE access is a PCI configuration read */ msp_pcibios_config_access()
439 * Check if the PCI configuration cycle (rd or wr) succeeded, by msp_pcibios_config_access()
471 * DESCRIPTION: Read a byte from PCI configuration address spac
476 * INPUTS bus - structure containing attributes for the PCI bus
499 * master abort) do the PCI compliant thing, which is to supply an msp_pcibios_read_config_byte()
518 * DESCRIPTION: Read a word (16 bits) from PCI configuration address space.
523 * INPUTS bus - structure containing attributes for the PCI bus
558 * master abort) do the PCI compliant thing, which is to supply an msp_pcibios_read_config_word()
577 * DESCRIPTION: Read a double word (32 bits) from PCI configuration
580 * INPUTS bus - structure containing attributes for the PCI bus
610 * master abort) do the PCI compliant thing, which is to supply an msp_pcibios_read_config_dword()
629 * DESCRIPTION: Write a byte to PCI configuration address space.
633 * INPUTS bus - structure containing attributes for the PCI bus
677 * DESCRIPTION: Write a word (16-bits) to PCI configuration address space.
681 * INPUTS bus - structure containing attributes for the PCI bus
730 * DESCRIPTION: Write a double word (32-bits) to PCI configuration address
733 * INPUTS bus - structure containing attributes for the PCI bus
771 * DESCRIPTION: Interface the PCI configuration read request with
775 * INPUTS bus - structure containing attributes for the PCI bus
822 * DESCRIPTION: Interface the PCI configuration write request with
826 * INPUTS bus - structure containing attributes for the PCI bus
874 * DESCRIPTION: structure to abstract the hardware specific PCI
878 * read - function for Linux to generate PCI Configuration reads.
879 * write - function for Linux to generate PCI Configuration writes.
892 * Describes the attributes of the MSP7120 PCI Host Controller
895 * pci_ops - abstracts the hardware specific PCI configuration
898 * mem_resource - address range pciauto() uses to assign to PCI device
901 * mem_offset - offset between how MSP7120 outbound PCI memory
902 * transaction addresses appear on the PCI bus and how Linux
903 * wants to configure memory BARs of the PCI devices.
906 * io_resource - address range pciauto() uses to assign to PCI device
909 * io_offset - offset between how MSP7120 outbound PCI I/O
910 * transaction addresses appear on the PCI bus and how
911 * Linux defaults to configure I/O BARs of the PCI devices.
913 * bottom 4K of PCI address space (and ignores OATRAN).
932 * DESCRIPTION: Initialize the PCI Host Controller and register it with
933 * Linux so Linux can seize control of the PCI bus.
946 printk(KERN_WARNING "PCI: No PCI; id reads as %x\n", id); msp_pci_init()
951 * Enable flushing of the PCI-SDRAM queue upon a read msp_pci_init()
956 /* Configure PCI Host Controller. */ msp_pci_init()
959 preg->oatran = MSP_PCI_OATRAN; /* PCI outbound addr translation */ msp_pci_init()
960 preg->if_mask = 0xF8BF87C0; /* Enable all PCI status interrupts */ msp_pci_init()
965 /* Tell Linux the details of the MSP7120 PCI Host Controller */ msp_pci_init()
971 /* Disable PCI channel */ msp_pci_init()
972 printk(KERN_WARNING "PCI: no host PCI bus detected\n"); msp_pci_init()
H A Dfixup-pmcmsp.c43 /* PCI interrupt pins */
49 /* Garibaldi Board IRQ wiring to PCI slots */
88 /* MSP7120 Eval Board IRQ wiring to PCI slots */
109 {0, IRQ4, IRQ4, IRQ4, IRQ4}, /* 8 (AD[18]): slot 0 (PCI) */
110 {0, IRQ5, IRQ5, IRQ5, IRQ5}, /* 9 (AD[19]): slot 1 (PCI) */
172 * None are needed for the MSP7120 PCI Controller.
174 * INPUTS: dev - structure describing the PCI device
191 * DESCRIPTION: Perform board supplied PCI IRQ mapping routine.
194 * slot - PCI slot. Identified by which bit of the AD[] bus
208 printk(KERN_WARNING "PCI: unknown board, no PCI IRQs assigned.\n"); pcibios_map_irq()
210 printk(KERN_WARNING "PCI: irq_tab returned %d for slot=%d pin=%d\n", pcibios_map_irq()
H A Dfixup-sb1250.c14 * Set the BCM1250, etc. PCI host bridge's TRDY timeout
25 * The BCM1250, etc. PCI/HT bridge reports as a host bridge.
35 * Set the SP1011 HT/PCI bridge's TRDY timeout to the finite max.
H A Dpci-bcm63xx.c22 * Allow PCI to be disabled at runtime depending on board nvram
28 .name = "bcm63xx PCI memory space",
35 .name = "bcm63xx PCI IO space",
53 * have to be clearly separated from PCI one since we have different
228 /* setup local bus to PCI access (PCI memory) */ bcm63xx_register_pci()
242 /* setup local bus to PCI access (Cardbus memory) */ bcm63xx_register_pci()
253 /* setup local bus to PCI access (IO memory), we have only 1 bcm63xx_register_pci()
254 * IO window for both PCI and cardbus, but it cannot handle bcm63xx_register_pci()
255 * both at the same time, assume standard PCI for now, if bcm63xx_register_pci()
256 * cardbus card has IO zone, PCI fixup will change window to bcm63xx_register_pci()
263 /* enable PCI related GPIO pins */ bcm63xx_register_pci()
266 /* setup PCI to local bus access, used by PCI device to target bcm63xx_register_pci()
281 * PCI, throw a warning if we have more memory */ bcm63xx_register_pci()
286 "of RAM for PCI bus mastering\n"); bcm63xx_register_pci()
327 "bcm63xx PCI IO space"); bcm63xx_register_pci()
H A Dpci-rc32434.c3 * PCI initialization for IDT EB434 board
39 /* define an unsigned array for the PCI registers */
52 .name = "PCI MEM1",
61 .name = "PCI Mem2",
71 .name = "PCI I/O1",
120 pr_err("PCI init error!!!\n"); rc32434_pcibridge_init()
126 rc32434_pci->pcic = pcicdata; /* Enable the PCI bus Interface */ rc32434_pcibridge_init()
127 /* Zero out the PCI status & PCI Status Mask */ rc32434_pcibridge_init()
136 /* Zero out the PCI decoupled registers */ rc32434_pcibridge_init()
138 * disable PCI decoupled accesses at rc32434_pcibridge_init()
143 /* Mask PCI Messaging Interrupts */ rc32434_pcibridge_init()
153 /* setup the PCI map address as same as the local address */ rc32434_pcibridge_init()
209 pr_info("PCI: Initializing PCI\n"); rc32434_pci_init()
H A Dfixup-sni.c6 * SNI specific PCI support for RM200/RM300.
30 * Device 0: PCI EISA Bridge (directly routed)
105 { 0, INTA, INTB, INTC, INTD }, /* PCI-PCI bridge */
119 { 0, INTB, INTC, INTD, INTA }, /* PCI Slot 9 */
120 { 0, 0, 0, 0, 0 }, /* PCI-EISA */
122 { 0, INTA, INTB, INTC, INTD }, /* PCI-PCI bridge */
140 * PCI bus 1; we need to fix this up here pcibios_map_irq()
H A Dpci-ar2315.c17 * Both AR2315 and AR2316 chips have PCI interface unit, which supports DMA
18 * and interrupt. PCI interface supports MMIO access method, but does not
22 * a memory read/write command on the PCI bus. 30 LSBs of address on
24 * determined by PCI unit configuration.
29 * Devices on the bus can perform DMA requests via chip BAR1. PCI host
34 * We know (and support) only one board that uses the PCI interface -
36 * AR2315 PCI bus. IDSEL pin of USB controller is connected to AD[13] line
54 * PCI Bus Interface Registers
73 #define AR2315_PCICACHE_DIS 0x00001000 /* PCI external access cache
106 /* PCI interrupt status (write one to clear) */
119 #define AR2315_PCI_INT_EXT 0x02000000 /* Extern PCI INTA */
120 #define AR2315_PCI_INT_ABORT 0x04000000 /* PCI bus abort event */
122 /* PCI interrupt mask */
125 /* Global PCI interrupt enable */
139 * PCI interrupts, which share IP5
218 mb(); /* PCI must see space change before we begin */ ar2315_pci_cfg_access()
361 .name = "AR2315-PCI",
424 apc->mem_res.name = "AR2315 PCI mem space"; ar2315_pci_probe()
430 /* Remap PCI config space */ ar2315_pci_probe()
434 dev_err(dev, "failed to remap PCI config space\n"); ar2315_pci_probe()
438 /* Reset the PCI bus by setting bits 5-4 in PCI_MCFG */ ar2315_pci_probe()
444 /* Bring the PCI out of reset */ ar2315_pci_probe()
470 /* PCI controller does not support I/O ports */ ar2315_pci_probe()
482 dev_info(dev, "register PCI controller\n"); ar2315_pci_probe()
H A Dpci-ip32.c88 .name = "SGI O2 PCI MEM",
94 .name = "SGI O2 PCI IO",
102 .name = "SGI O2 PCI MEM",
108 .name = "SGI O2 PCI IO",
134 printk("MACE PCI rev %d\n", mace->pci.rev); mace_init()
137 "MACE PCI error", NULL)); mace_init()
H A Dfixup-rbtx4938.c26 /* PCI CardSlot (IDSEL=A23) */ rbtx4938_pci_map_irq()
30 /* PCI Backplane */ rbtx4938_pci_map_irq()
H A Dops-nile4.c24 * 8 devices on the first busnum (besides the PCI nile4_pcibios_config_access()
38 /* Temporarily map PCI Window 1 to config space */ nile4_pcibios_config_access()
42 /* Clear PCI Error register. This also clears the Error Type nile4_pcibios_config_access()
65 /* Restore PCI Window 1 */ nile4_pcibios_config_access()
/linux-4.1.27/arch/arm/mach-orion5x/
H A Dboard-rd88f5182.c29 * PCI
37 * PCI
45 * Configure PCI GPIO IRQ pins rd88f5182_pci_preinit()
48 if (gpio_request(pin, "PCI IntA") == 0) { rd88f5182_pci_preinit()
61 if (gpio_request(pin, "PCI IntB") == 0) { rd88f5182_pci_preinit()
87 * PCI IRQs are connected via GPIOs rd88f5182_pci_map_irq()
H A Drd88f5182-setup.c49 * PCI
108 * PCI
116 * Configure PCI GPIO IRQ pins rd88f5182_pci_preinit()
119 if (gpio_request(pin, "PCI IntA") == 0) { rd88f5182_pci_preinit()
132 if (gpio_request(pin, "PCI IntB") == 0) { rd88f5182_pci_preinit()
158 * PCI IRQs are connected via GPIOs rd88f5182_pci_map_irq()
248 * MPP[20] PCI Clock to MV88F5182 rd88f5182_init()
249 * MPP[21] PCI Clock to mini PCI CON11 rd88f5182_init()
/linux-4.1.27/arch/arm/plat-iop/
H A Dpci.c4 * PCI support for the Intel IOP32X and IOP33X processors
169 * When a PCI device does not exist during config cycles, the 80200 gets a
175 DBG("PCI abort: address = 0x%08lx fsr = 0x%03x PC = 0x%08lx LR = 0x%08lx\n", iop3xx_pci_abort()
197 panic("PCI: unable to alloc resources"); iop3xx_pci_setup()
201 res->name = "IOP3XX PCI Memory Space"; iop3xx_pci_setup()
313 /* Flag to determine whether the ATU is initialized and the PCI bus scanned */
326 DBG("PCI: Intel IOP3xx PCI init.\n"); iop3xx_atu_debug()
327 DBG("PCI: Outbound memory window 0: PCI 0x%08x%08x\n", iop3xx_atu_debug()
329 DBG("PCI: Outbound memory window 1: PCI 0x%08x%08x\n", iop3xx_atu_debug()
331 DBG("PCI: Outbound IO window: PCI 0x%08x\n", iop3xx_atu_debug()
334 DBG("PCI: Inbound memory window 0: PCI 0x%08x%08x 0x%08x -> 0x%08x\n", iop3xx_atu_debug()
336 DBG("PCI: Inbound memory window 1: PCI 0x%08x%08x 0x%08x\n", iop3xx_atu_debug()
338 DBG("PCI: Inbound memory window 2: PCI 0x%08x%08x 0x%08x -> 0x%08x\n", iop3xx_atu_debug()
340 DBG("PCI: Inbound memory window 3: PCI 0x%08x%08x 0x%08x -> 0x%08x\n", iop3xx_atu_debug()
343 DBG("PCI: Expansion ROM window: PCI 0x%08x%08x 0x%08x -> 0x%08x\n", iop3xx_atu_debug()
/linux-4.1.27/arch/powerpc/kernel/
H A Dpci_of_scan.c2 * Helper routines to scan the device tree for PCI devices and busses
9 * Rework, based on alpha PCI code.
37 * pci_parse_of_flags - Parse the flags cell of a device tree PCI address
38 * @addr0: value of 1st cell of a device tree PCI address.
67 * of_pci_parse_addrs - Parse PCI addresses assigned in the device tree node
68 * @node: device tree node for the PCI device
71 * This function parses the 'assigned-addresses' property of a PCI devices'
107 printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i); of_pci_parse_addrs()
122 * @devfn: PCI function number, extracted from device tree by caller.
175 /* a PCI-PCI bridge */ of_create_pci_dev()
199 * of_scan_pci_bridge - Set up a PCI bridge and scan for child nodes
202 * of_scan_bus() calls this routine for each PCI bridge that it finds, and
223 printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n", of_scan_pci_bridge()
229 printk(KERN_DEBUG "Can't get ranges for PCI-PCI bridge %s\n", of_scan_pci_bridge()
252 /* PCI #address-cells == 3 and #size-cells == 2 always */ of_scan_pci_bridge()
268 printk(KERN_ERR "PCI: ignoring extra I/O range" of_scan_pci_bridge()
274 printk(KERN_ERR "PCI: too many memory ranges" of_scan_pci_bridge()
286 sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus), of_scan_pci_bridge()
323 /* Check if the PCI device is already there */ of_scan_pci_dev()
346 * __of_scan_bus - given a PCI bus node, setup bus and scan for child devices
347 * @node: device tree node for the PCI bus
348 * @bus: pci_bus structure for the PCI bus
384 * of_scan_bus - given a PCI bus node, setup bus and scan for child devices
385 * @node: device tree node for the PCI bus
386 * @bus: pci_bus structure for the PCI bus
395 * of_rescan_bus - given a PCI bus node, scan for child devices
396 * @node: device tree node for the PCI bus
397 * @bus: pci_bus structure for the PCI bus
H A Deeh_dev.c3 * be bound with OF node and PCI device simutaneously. The EEH devices would
8 * 1) Before PCI emunation starts, we need create EEH devices according to the
9 * PCI sensitive OF nodes.
10 * 2) When PCI emunation is done, we need do the binding between PCI device and
12 * 3) DR (Dynamic Reconfiguration) would create PCI sensitive OF node. EEH device
13 * will be created while PCI sensitive OF node is detected from DR.
14 * 4) PCI hotplug needs redoing the binding between PCI device and EEH device. If
46 * @pdn: PCI device node
50 * might be called by PCI emunation, DR, PHB hotplug.
H A Dpci-hotplug.c25 * pcibios_release_device - release PCI device
26 * @dev: PCI device
28 * The function is called before releasing the indicated PCI device.
37 * @bus: the indicated PCI bus
39 * Remove all of the PCI devices under this bus both from the
51 pr_debug("PCI: Removing devices on bus %04x:%02x\n", pcibios_remove_pci_devices()
63 * @bus: the indicated PCI bus
/linux-4.1.27/arch/frv/mb93090-mb00/
H A Dpci-vdk.c1 /* pci-vdk.c: MB93090-MB00 (VDK) PCI support
31 * The accessible PCI window does not cover the entire CPU address space, but
33 * insert specific PCI bus resources instead of using the platform-level bus
34 * resources directly for the PCI root bus.
40 .name = "PCI IO",
47 .name = "PCI mem",
54 * Functions for accessing PCI configuration space
180 * attempt to make use of direct access hints provided by the PCI BIOS).
193 printk("PCI: VDK Bridge device:vendor: %08x\n", id); pci_sanity_check()
198 printk("PCI: VDK Bridge: Sanity check failed\n"); pci_sanity_check()
211 printk("PCI: Using configuration frv\n"); pci_check_direct()
213 // request_mem_region(0xBFFFFFF4, 12, "PCI frv"); pci_check_direct()
233 printk("PCI: Fixing base address flags for device %s\n", pci_name(d)); pci_fixup_umc_ide()
243 * PCI IDE controllers use non-standard I/O port decoding, respect it. pci_fixup_ide_bases()
247 printk("PCI: IDE base address fixup for %s\n", pci_name(d)); pci_fixup_ide_bases()
262 * There exist PCI IDE controllers which have utter garbage pci_fixup_ide_trash()
265 printk("PCI: IDE base address trash cleared for %s\n", pci_name(d)); pci_fixup_ide_trash()
276 DBG("PCI: Setting max latency to 32\n"); pci_fixup_latency()
311 * Initialization. Try all known PCI access methods. Note that we support
312 * using both PCI BIOS and direct access: in such cases, we use I/O ports
340 /* enable PCI arbitration */ pcibios_init()
347 printk("PCI IO window: %08llx-%08llx\n", pcibios_init()
357 * CPU-PCI bridge to flush as this doesn't happen automatically when a pcibios_init()
362 printk("PCI MEM window: %08llx-%08llx\n", pcibios_init()
365 printk("PCI DMA memory: %08lx-%08lx\n", pcibios_init()
369 panic("Unable to insert PCI IOMEM resource\n"); pcibios_init()
371 panic("Unable to insert PCI IOPORT resource\n"); pcibios_init()
380 printk("PCI: No PCI bus detected\n"); pcibios_init()
384 printk("PCI: Probing PCI hardware\n"); pcibios_init()
H A Dpci-frv.h2 * Low-Level PCI Access for FRV machines.
/linux-4.1.27/arch/arm/mach-ixp4xx/
H A Dcommon-pci.c4 * IXP4XX PCI routines for all platforms
40 * IXP4xx PCI read function is dependent on whether we are
46 * Base address for PCI regsiter region
51 * PCI cfg an I/O routines are done by programming a
60 * Read from PCI config space
72 * Write to PCI config space
109 * PCI workaround - only works if NP PCI space reads have ixp4xx_pci_read_errata()
292 * PCI abort handler
300 pr_debug("PCI: abort_handler addr = %#lx, isr = %#x, " abort_handler()
323 pcibios_min_mem = 0x10000000; /* 1 GB of indirect PCI MMIO space */ ixp4xx_pci_preinit()
325 pcibios_min_mem = 0x48000000; /* 64 MB of PCI MMIO space */ ixp4xx_pci_preinit()
328 * Determine which PCI read method to use. ixp4xx_pci_preinit()
332 printk("PCI: IXP42x A0 silicon detected - " ixp4xx_pci_preinit()
333 "PCI Non-Prefetch Workaround Enabled\n"); ixp4xx_pci_preinit()
339 /* hook in our fault handler for PCI errors */ ixp4xx_pci_preinit()
343 pr_debug("setup PCI-AHB(inbound) and AHB-PCI(outbound) address mappings\n"); ixp4xx_pci_preinit()
346 * We use identity AHB->PCI address translation ixp4xx_pci_preinit()
352 * We also use identity PCI->AHB address translation ixp4xx_pci_preinit()
362 printk("PCI: IXP4xx is host\n"); ixp4xx_pci_preinit()
367 * We configure the PCI inbound memory windows to be ixp4xx_pci_preinit()
377 * Enable CSR window at 64 MiB to allow PCI masters ixp4xx_pci_preinit()
388 printk("PCI: IXP4xx is target - No bus scan performed\n"); ixp4xx_pci_preinit()
391 printk("PCI: IXP4xx Using %s access for memory space\n", ixp4xx_pci_preinit()
403 * Set Initialize Complete in PCI Control Register: allow IXP4XX to ixp4xx_pci_preinit()
404 * respond to PCI configuration cycles. Specify that the AHB bus is ixp4xx_pci_preinit()
406 * little-endian PCI and the big-endian AHB bus ixp4xx_pci_preinit()
430 panic("PCI: unable to allocate resources?\n"); ixp4xx_setup()
435 res[0].name = "PCI I/O Space"; ixp4xx_setup()
440 res[1].name = "PCI Memory Space"; ixp4xx_setup()
H A Dvulcan-pci.c4 * Vulcan board-level PCI initialization
24 /* PCI controller GPIO to IRQ pin mappings */
33 * and leaves the whole PCI bus in a mess. Artificially limit it vulcan_pci_preinit()
38 pr_info("Vulcan PCI: limiting CardBus memory size to %dMB\n", vulcan_pci_preinit()
H A Dcoyote-pci.c4 * PCI setup routines for ADI Engineering Coyote platform
29 /* PCI controller GPIO to IRQ pin mappings */
/linux-4.1.27/include/linux/bcma/
H A Dbcma_driver_pci.h8 /** PCI core registers. **/
9 #define BCMA_CORE_PCI_CTL 0x0000 /* PCI Control */
14 #define BCMA_CORE_PCI_ARBCTL 0x0010 /* PCI Arbiter Control */
23 #define BCMA_CORE_PCI_ISTAT_INTA 0x00000001 /* PCI INTA# */
24 #define BCMA_CORE_PCI_ISTAT_INTB 0x00000002 /* PCI INTB# */
25 #define BCMA_CORE_PCI_ISTAT_SERR 0x00000004 /* PCI SERR# (write to clear) */
26 #define BCMA_CORE_PCI_ISTAT_PERR 0x00000008 /* PCI PERR# (write to clear) */
27 #define BCMA_CORE_PCI_ISTAT_PME 0x00000010 /* PCI PME# */
29 #define BCMA_CORE_PCI_IMASK_INTA 0x00000001 /* PCI INTA# */
30 #define BCMA_CORE_PCI_IMASK_INTB 0x00000002 /* PCI INTB# */
31 #define BCMA_CORE_PCI_IMASK_SERR 0x00000004 /* PCI SERR# */
32 #define BCMA_CORE_PCI_IMASK_PERR 0x00000008 /* PCI PERR# */
33 #define BCMA_CORE_PCI_IMASK_PME 0x00000010 /* PCI PME# */
34 #define BCMA_CORE_PCI_MBOX 0x0028 /* Backplane to PCI Mailbox */
35 #define BCMA_CORE_PCI_MBOX_F0_0 0x00000100 /* PCI function 0, INT 0 */
36 #define BCMA_CORE_PCI_MBOX_F0_1 0x00000200 /* PCI function 0, INT 1 */
37 #define BCMA_CORE_PCI_MBOX_F1_0 0x00000400 /* PCI function 1, INT 0 */
38 #define BCMA_CORE_PCI_MBOX_F1_1 0x00000800 /* PCI function 1, INT 1 */
39 #define BCMA_CORE_PCI_MBOX_F2_0 0x00001000 /* PCI function 2, INT 0 */
40 #define BCMA_CORE_PCI_MBOX_F2_1 0x00002000 /* PCI function 2, INT 1 */
41 #define BCMA_CORE_PCI_MBOX_F3_0 0x00004000 /* PCI function 3, INT 0 */
42 #define BCMA_CORE_PCI_MBOX_F3_1 0x00008000 /* PCI function 3, INT 1 */
50 #define BCMA_CORE_PCI_SBTOPCI0 0x0100 /* Backplane to PCI translation 0 (sbtopci0) */
52 #define BCMA_CORE_PCI_SBTOPCI1 0x0104 /* Backplane to PCI translation 1 (sbtopci1) */
54 #define BCMA_CORE_PCI_SBTOPCI2 0x0108 /* Backplane to PCI translation 2 (sbtopci2) */
85 #define BCMA_CORE_PCI_PCICFG0 0x0400 /* PCI config space 0 (rev >= 8) */
86 #define BCMA_CORE_PCI_PCICFG1 0x0500 /* PCI config space 1 (rev >= 8) */
87 #define BCMA_CORE_PCI_PCICFG2 0x0600 /* PCI config space 2 (rev >= 8) */
88 #define BCMA_CORE_PCI_PCICFG3 0x0700 /* PCI config space 3 (rev >= 8) */
169 #define BCMA_CORE_PCI_BFL_NOPCI 0x00000400 /* Board leaves PCI floating */
/linux-4.1.27/arch/arm/mach-integrator/
H A Dpci_v3.c4 * PCI functions for V3 host PCI bridge
46 * Where in the memory map does PCI live?
62 * V3 Local Bus to PCI Bridge definitions
66 * PCI definitions. Their names match the user's manual.
124 /* PCI COMMAND REGISTER bits
148 /* PCI_BASE register bits (PCI -> Local Bus)
156 /* PCI MAP register bits (PCI -> Local bus)
167 * LB_BASE0,1 register bits (Local bus -> PCI)
191 * LB_MAP0,1 register bits (Local bus -> PCI)
206 * LB_BASE2 register bits (Local bus -> PCI IO)
215 * LB_MAP2 register bits (Local bus -> PCI IO)
222 * The V3 PCI interface chip in Integrator provides several windows from
223 * local bus memory into the PCI memory areas. Unfortunately, there
225 * one of the windows for access to PCI configuration space. The
230 * 40000000 - 4FFFFFFF PCI memory. 256M non-prefetchable
231 * 50000000 - 5FFFFFFF PCI memory. 256M prefetchable
232 * 60000000 - 60FFFFFF PCI IO. 16M
233 * 61000000 - 61FFFFFF PCI Configuration. 16M
237 * Base0 and Base1 can be used for any type of PCI memory access. Base2
238 * can be used either for PCI I/O or for I20 accesses. By default, uHAL
239 * uses this only for PCI IO space.
250 * This means that I20 and PCI configuration space accesses will fail.
251 * When PCI configuration accesses are needed (via the uHAL PCI
269 * To allow PCI Configuration space access, the code enlarges the
274 * At the end of the PCI Configuration space accesses,
275 * LB_BASE1/LB_MAP1 is reset to map PCI Memory. Finally the window
281 * the mappings into PCI memory.
291 /* PCI side memory ranges */
321 * returns: configuration address to play on the PCI bus
323 * To generate the appropriate PCI configuration cycles in the PCI
327 * the local to PCI aperatures to 16Mbytes in length translating to
328 * PCI configuration space starting at 0x0000.0000.
330 * PCI configuration cycles look like this:
383 * build the PCI configuration "address" with one-hot in v3_open_config_window()
388 * 0 = PCI A1 & A0 are 0 (0) v3_open_config_window()
414 * 0 = PCI A1 & A0 from host bus (1) v3_open_config_window()
441 * Reassign base1 for use by prefetchable PCI memory v3_close_config_window()
481 printk(KERN_ERR "PCI: unable to allocate non-prefetchable " pci_v3_setup_resources()
487 printk(KERN_ERR "PCI: unable to allocate prefetchable " pci_v3_setup_resources()
620 * Hook in our fault handler for PCI errors pci_v3_preinit()
634 * Setup window 0 - PCI non-prefetchable memory pci_v3_preinit()
643 * Setup window 1 - PCI prefetchable memory pci_v3_preinit()
653 * Setup window 2 - PCI IO pci_v3_preinit()
660 * Disable PCI to host IO cycles pci_v3_preinit()
672 * Same for PCI. pci_v3_preinit()
707 printk(KERN_ERR "PCI: unable to grab local bus timeout " pci_v3_postinit()
716 * later) adheres to the PCI-PCI bridge specification. This says that
876 * e8000000 40000000 PCI memory PHYS_PCI_MEM_BASE (max 512M)
877 * ec000000 61000000 PCI config space PHYS_PCI_CONFIG_BASE (max 16M)
878 * fee00000 60000000 PCI IO PHYS_PCI_IO_BASE (max 16M)
/linux-4.1.27/arch/arm/include/asm/hardware/
H A Dit8152.h66 IT8152_PD_IRQ(13) CPU/PCI bridge target abort (h2pTADR)
67 IT8152_PD_IRQ(12) CPU/PCI bridge master abort (h2pMADR)
68 IT8152_PD_IRQ(11) PCI INTD
69 IT8152_PD_IRQ(10) PCI INTC
70 IT8152_PD_IRQ(9) PCI INTB
71 IT8152_PD_IRQ(8) PCI INTA
84 /* IRQ-sources in 3 groups - local devices, LPC (serial), and external PCI */
/linux-4.1.27/arch/unicore32/include/mach/
H A DPKUnity.h27 * PKUNITY System Bus Addresses (PCI): 0x80000000 - 0xBFFFFFFF (1GB)
28 * 0x80000000 - 0x8000000B 12B PCI Configuration regs
29 * 0x80010000 - 0x80010250 592B PCI Bridge Base
30 * 0x80030000 - 0x8003FFFF 64KB PCI Legacy IO
31 * 0x90000000 - 0x97FFFFFF 128MB PCI AHB-PCI MEM-mapping
32 * 0x98000000 - 0x9FFFFFFF 128MB PCI PCI-AHB MEM-mapping
49 /* AHB-1 is PCI Space */
/linux-4.1.27/drivers/usb/chipidea/
H A Dci_hdrc_pci.c30 * PCI block
49 * ci_hdrc_pci_probe: PCI probe
51 * @id: PCI hotplug ID connecting controller to UDC framework
54 * Allocates basic PCI resources for this USB device controller, and then
79 dev_err(&pdev->dev, "No IRQ, check BIOS/PCI setup!"); ci_hdrc_pci_probe()
111 * ci_hdrc_pci_remove: PCI remove
116 * all PCI resources allocated for this USB device controller
127 * PCI device table
128 * PCI device structure
/linux-4.1.27/arch/tile/include/asm/
H A Dpci.h25 * Structure of a PCI controller (host bridge)
28 int index; /* PCI domain number */
72 * space to serve as the PCI window, emulating the BAR0 space of an endpoint pci_iounmap()
88 * This is the PCI address where the Mem-Map interrupt regions start. pci_iounmap()
100 * Allocate the PCI BAR window right below 4GB. pci_iounmap()
105 * Allocate 1GB for the PCI BAR window. pci_iounmap()
111 * can be generated by legacy PCI devices with 32-bit or less pci_iounmap()
118 * We shift the PCI bus range for all the physical memory up by the whole PA pci_iounmap()
119 * range. The corresponding CPA of an incoming PCI request will be the PCI pci_iounmap()
126 * This design lets us avoid the "PCI hole" problem where the host bridge pci_iounmap()
134 * Start of the PCI memory resource, which starts at the end of the pci_iounmap()
140 * Structure of a PCI controller (host bridge) on Gx. pci_iounmap()
157 * map all of its physical memory space to the PCI bus. pci_iounmap()
161 int index; /* PCI domain number */ pci_iounmap()
164 /* PCI I/O space resource for this controller. */ pci_iounmap()
168 /* PCI memory space resource for this controller. */ pci_iounmap()
189 * The PCI address space does not equal the physical memory address
223 /* Minimum PCI I/O address, starting at the page boundary. */
226 /* Use any cpu for PCI. */
/linux-4.1.27/arch/sh/include/mach-landisk/mach/
H A Diodata_landisk.h21 #define PA_PCIPME 0xb0000004 /* PCI PME Status Register */
29 #define IRQ_PCIINTA evt2irq(0x2a0) /* PCI INTA IRQ */
30 #define IRQ_PCIINTB evt2irq(0x2c0) /* PCI INTB IRQ */
31 #define IRQ_PCIINTC evt2irq(0x2e0) /* PCI INTC IRQ */
32 #define IRQ_PCIINTD evt2irq(0x300) /* PCI INTD IRQ */
/linux-4.1.27/arch/parisc/include/asm/
H A Dpci.h9 ** HP PCI platforms generally support multiple bus adapters.
12 ** Newer platforms number the busses across PCI bus adapters *sparsely*.
15 ** Under a PCI bus, most HP platforms support PPBs up to two or three
24 * accessing the PCI bus once #RESET is de-asserted.
25 * PCI spec somewhere says 1 second but with multi-PCI bus systems,
27 * 20ms seems to work for all the HP PCI implementations to date.
44 struct pci_bus *hba_bus; /* primary PCI bus below HBA */
46 struct resource bus_num; /* PCI bus numbers */
57 unsigned long lmmio_space_offset; /* CPU view - PCI view */
97 * If the PCI device's view of memory is the same as the CPU's view of memory,
120 ** Most PCI devices (eg Tulip, NCR720) also export the same registers
122 ** access under HP PCI bus adapters, strongly recommend the use of MMIO
174 * 1 == pci_do_scan_bus() should automatically number all PCI-PCI bridges.
180 * Bus controller. Adding a 4-port Tulip card on the first PCI root
182 * The second PCI host bus controller's root bus had already been
186 * is its own PCI domain. It's simpler and easier for us to renumber
187 * the busses rather than treat each Dino as a separate PCI domain.
188 * Eventually, we may want to introduce PCI domains for Superdome or
/linux-4.1.27/arch/tile/kernel/
H A Dpci.c39 * This files contains the routines to search for PCI buses,
48 * This probes the PCI bus(es) for any attached hardware. It's
50 * generic Linux PCI layer.
80 * Open a FD to the hypervisor PCI device.
112 pr_err("PCI: hv_dev_open(%s) failed\n", filename); tile_init_irqs()
119 pr_err("PCI: wanted %zd bytes, got %d\n", tile_init_irqs()
149 pr_info("PCI: disabled by boot argument\n"); tile_pci_init()
153 pr_info("PCI: Searching for controllers...\n"); tile_pci_init()
181 pr_err("PCI: Couldn't open config fd to HV for controller %d\n", tile_pci_init()
189 pr_err("PCI: Could not open mem fd to HV!\n"); tile_pci_init()
193 pr_info("PCI: Found PCI controller #%d\n", i); tile_pci_init()
233 * (pin - 1) converts from the PCI standard's [1:4] convention to
270 * Second PCI initialization entry point, called by subsys_initcall.
279 pr_info("PCI: Probing PCI hardware\n"); pcibios_init()
288 /* Scan all of the recorded PCI controllers. */ pcibios_init()
301 pr_err("PCI: Could not initialize IRQs\n"); pcibios_init()
305 pr_info("PCI: initializing controller #%d\n", i); pcibios_init()
316 /* Do machine dependent PCI interrupt routing */ pcibios_init()
320 * This comes from the generic Linux PCI driver. pcibios_init()
330 /* Record the I/O resources in the PCI controller structure. */ pcibios_init()
346 * Find the PCI host controller, ie. the 1st pcibios_init()
399 * This is called from the generic PCI layer, and can be called
428 pr_err("PCI: Device %s not available because of resource collisions\n", pcibios_enable_device()
449 * Tile PCI config space read/write routines
457 * devfn is the combined PCI slot & function.
552 * In the following, each PCI controller's mem_resources[1]
553 * represents its (non-prefetchable) PCI memory resource.
554 * mem_resources[0] and mem_resources[2] refer to its PCI I/O and
555 * prefetchable PCI memory resources, respectively.
557 * By comparing the target PCI memory address against the
559 * that should accept the PCI memory access.
571 pr_err("PCI: read %zd bytes at 0x%lX failed\n", \
591 pr_err("PCI: write %zd bytes at 0x%lX failed\n", \
/linux-4.1.27/arch/xtensa/lib/
H A Dpci-auto.c4 * PCI autoconfiguration library
27 * Setting up a PCI
31 * pci_ctrl->ops = <PCI config operations>
34 * pci_ctrl->io_space.start = <IO space start address (PCI view)>
35 * pci_ctrl->io_space.end = <IO space end address (PCI view)>
37 * pci_ctrl->mem_space.start = <MEM space start address (PCI view)>
38 * pci_ctrl->mem_space.end = <MEM space end address (PCI view)>
42 * <IO space end>, IORESOURCE_IO, "PCI host bridge");
44 * <MEM space end>, IORESOURCE_MEM, "PCI host bridge");
73 /* Initialize the bars of a PCI device. */
100 DBG("PCI Autoconfig: BAR %d, I/O, ", bar_nr); pciauto_setup_bars()
110 DBG("PCI Autoconfig: BAR %d, Mem, ", bar_nr); pciauto_setup_bars()
153 DBG("PCI Autoconfig: Interrupt %d, pin %d\n", irq, pin); pciauto_setup_irq()
233 * Scan the current PCI bus.
292 DBG("PCI Autoconfig: Found P2P bridge, device %d\n", pciauto_bus_scan()
295 /* Allocate PCI I/O and/or memory space */ pciauto_bus_scan()
319 DBG("PCI Autoconfig: Skipping legacy mode " pciauto_bus_scan()
339 /* Allocate PCI I/O and/or memory space */ pciauto_bus_scan()
340 DBG("PCI Autoconfig: Found Bus %d, Device %d, Function %d\n", pciauto_bus_scan()
/linux-4.1.27/drivers/net/wireless/orinoco/
H A Dorinoco_pci.h3 * Common code for all Orinoco drivers for PCI devices, including
4 * both native PCI and PCMCIA-to-PCI bridges.
/linux-4.1.27/drivers/pci/hotplug/
H A Dacpiphp.h2 * ACPI PCI Hot Plug Controller Driver
62 * struct acpiphp_bridge - PCI bridge information
75 /* This bus (host bridge) or Secondary bus (PCI-to-PCI bridge) */
78 /* PCI-to-PCI bridge device */
86 * struct acpiphp_slot - PCI slot information
88 * PCI slot information for each *physical* PCI slot
103 * struct acpiphp_func - PCI function information
105 * PCI function information for each object in ACPI namespace
106 * typically 8 objects per slot (i.e. for each PCI function)
/linux-4.1.27/drivers/acpi/
H A Dreboot.c31 /* The reset register can only exist in I/O, Memory or PCI config space acpi_reboot()
39 /* Form PCI device/function pair. */ acpi_reboot()
42 printk(KERN_DEBUG "Resetting with ACPI PCI RESET_REG."); acpi_reboot()
/linux-4.1.27/arch/s390/include/asm/
H A Dpci_clp.h14 /* PCI function handle list entry */
20 u32 fid; /* PCI function id */
21 u32 fh; /* PCI function handle */
24 #define CLP_RC_SETPCIFN_FH 0x0101 /* Invalid PCI fn handle */
49 /* List PCI functions request */
59 /* List PCI functions response */
73 /* Query PCI function request */
84 /* Query PCI function response */
108 /* Query PCI function group request */
120 /* Query PCI function group response */
141 /* Set PCI function request */
154 /* Set PCI function response */
/linux-4.1.27/arch/mips/txx9/rbtx4927/
H A Dirq.c72 * TXX9_IRQ_BASE+16 TX4927 PCI PCI-C
78 * TXX9_IRQ_BASE+22 TX4927 PCI PCI-ERR
79 * TXX9_IRQ_BASE+23 TX4927 PCI PCI-PMA (not used)
89 * RBTX4927_IRQ_IOC+00 FPCIB0 PCI-D (SouthBridge)
90 * RBTX4927_IRQ_IOC+01 FPCIB0 PCI-C (SouthBridge)
91 * RBTX4927_IRQ_IOC+02 FPCIB0 PCI-B (SouthBridge/IDE/pin=1,INTR)
92 * RBTX4927_IRQ_IOC+03 FPCIB0 PCI-A (SouthBridge/USB/pin=4)
99 * SouthBridge/INTR is mapped to SouthBridge/A=PCI-B/#58
103 * SouthBridge/USB/pin=4 using pci irq SouthBridge/D=PCI-A=#59
H A Dsetup.c73 /* Reset PCI Bus */ tx4927_pci_setup()
91 /* Reset PCI Bus */ tx4927_pci_setup()
120 /* Reset PCI Bus */ tx4937_pci_setup()
138 /* Reset PCI Bus */ tx4937_pci_setup()
219 * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz. rbtx4927_clock_init()
223 * CPU 166MHz: PCI 66MHz : PCIDIVMODE: 00 (1/2.5) rbtx4927_clock_init()
224 * CPU 200MHz: PCI 66MHz : PCIDIVMODE: 01 (1/3) rbtx4927_clock_init()
225 * CPU 166MHz: PCI 33MHz : PCIDIVMODE: 10 (1/5) rbtx4927_clock_init()
226 * CPU 200MHz: PCI 33MHz : PCIDIVMODE: 11 (1/6) rbtx4927_clock_init()
243 * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz. rbtx4937_clock_init()
248 * CPU 266MHz: PCI 33MHz : PCIDIVMODE: 000 (1/8) rbtx4937_clock_init()
249 * CPU 266MHz: PCI 66MHz : PCIDIVMODE: 001 (1/4) rbtx4937_clock_init()
250 * CPU 300MHz: PCI 33MHz : PCIDIVMODE: 010 (1/9) rbtx4937_clock_init()
251 * CPU 300MHz: PCI 66MHz : PCIDIVMODE: 011 (1/4.5) rbtx4937_clock_init()
252 * CPU 333MHz: PCI 33MHz : PCIDIVMODE: 100 (1/10) rbtx4937_clock_init()
253 * CPU 333MHz: PCI 66MHz : PCIDIVMODE: 101 (1/5) rbtx4937_clock_init()
/linux-4.1.27/drivers/ide/
H A Dide-scan-pci.c2 * support for probing IDE PCI devices in the PCI bus order
29 * hands the controllers off to the core PCI code to do the rest of
48 * @dev: PCI device to check
80 * PCI drivers. After this all IDE pci handling becomes standard
95 * Hand the drivers over to the PCI layer now we ide_scan_pcibus()
H A Dsetup-pci.c21 * ide_setup_pci_baseregs - place a PCI IDE controller native
22 * @dev: PCI device of interface to switch native
25 * We attempt to place the PCI interface into PCI native mode. If
26 * we succeed the BARs are ok and the controller is in PCI mode.
38 * Place both IDE interfaces into PCI "native" mode: ide_setup_pci_baseregs()
44 "native PCI mode\n", name, pci_name(dev)); ide_setup_pci_baseregs()
47 printk(KERN_INFO "%s %s: placing both ports into native PCI " ide_setup_pci_baseregs()
77 * Fetch the DMA Bus-Master-I/O-Base-Address (BMIBA) from PCI space.
180 * ide_pci_enable - do PCI enables
181 * @dev: PCI device
184 * Enable the IDE PCI device. We attempt to enable the device in full
185 * but if that fails then we only need IO space. The PCI code should
241 * @dev: PCI device
244 * Enable and configure the PCI device we have been passed.
265 printk(KERN_ERR "%s %s: error accessing PCI regs\n", ide_pci_configure()
279 * @dev: PCI device
306 * @dev: PCI device holding interface
312 * is done per interface port rather than per PCI device. There may be
341 printk(KERN_ERR "%s %s: bad PCI BARs for port %d, skipping\n", ide_hw_configure()
404 * ide_setup_pci_controller - set up IDE PCI
405 * @dev: PCI device
409 * Set up the PCI and controller side of the IDE interface. This brings
410 * up the PCI side of the device, checks that the device is enabled
429 printk(KERN_ERR "%s %s: error accessing PCI regs\n", ide_setup_pci_controller()
446 * ide_pci_setup_ports - configure ports/devices on PCI IDE
447 * @dev: PCI device
449 * @hw: struct ide_hw instances corresponding to this PCI IDE device
458 * where the chipset setup is not the default PCI IDE one.
491 * on a PCI IDE device and, if they are enabled, prepares the IDE driver
492 * for use with them. This generic code works for most PCI chipsets.
/linux-4.1.27/drivers/eisa/
H A Dpci_eisa.c2 * Minimalist driver for a generic PCI-to-EISA bridge.
33 * The Intel 82375 PCI-EISA bridge is a subtractive-decode PCI pci_eisa_init()
35 * available on the 82375 bus. This works the same as a PCI-PCI pci_eisa_init()
37 * We assume other PCI-EISA bridges are similar. pci_eisa_init()
/linux-4.1.27/drivers/pci/host/
H A Dpci-rcar-gen2.c2 * pci-rcar-gen2: internal PCI bus support
25 /* AHB-PCI Bridge PCI communication registers */
107 /* PCI configuration space operations */ rcar_pci_cfg_base()
134 /* PCI interrupt mapping */ rcar_pci_map_irq()
188 /* PCI host controller setup */ rcar_pci_setup()
199 dev_info(priv->dev, "PCI: bus%u revision %x\n", sys->busnr, val); rcar_pci_setup()
236 /* Configure PCI arbiter */ rcar_pci_setup()
242 /* PCI-AHB mapping: 0x40000000 base */ rcar_pci_setup()
246 /* AHB-PCI mapping: OHCI/EHCI registers */ rcar_pci_setup()
250 /* Enable AHB-PCI bridge PCI configuration access */ rcar_pci_setup()
253 /* Set PCI-AHB Window1 address */ rcar_pci_setup()
256 /* Set AHB-PCI bridge PCI communication area address */ rcar_pci_setup()
265 /* Enable PCI interrupts */ rcar_pci_setup()
272 /* Add PCI resources */ rcar_pci_setup()
382 MODULE_DESCRIPTION("Renesas R-Car Gen2 internal PCI");
H A Dpcie-iproc.h23 * @resources: linked list of all PCI resources
24 * @sysdata: Per PCI controller data
H A Dpci-keystone.h2 * Keystone PCI Controller's common includes
22 /* PCI Device ID */
42 /* Keystone specific PCI controller APIs */
/linux-4.1.27/arch/xtensa/platforms/xt2000/include/platform/
H A Dhardware.h39 * V3-PCI
42 /* The XT2000 uses the V3 as a cascaded interrupt controller for the PCI bus */
/linux-4.1.27/arch/arm64/include/asm/
H A Dpci.h17 * Set to 1 if the kernel should re-assign all PCI bus numbers
23 * PCI address space differs from physical memory address space
/linux-4.1.27/arch/arm/mach-pxa/
H A Dcm-x2xx-pci.c4 * PCI bios-type initialisation for PCI machines
79 /* PCI IRQ mapping*/ cmx2xx_pci_map_irq()
95 /* ATXBASE PCI slot */ cmx2xx_pci_map_irq()
126 pr_info("Initializing CM-X2XX PCI subsystem\n"); cmx2xx_pci_preinit()
133 pr_info("PCI Bridge found.\n"); cmx2xx_pci_preinit()
135 /* set PCI I/O base at 0 */ cmx2xx_pci_preinit()
139 /* set PCI memory base at 0 */ cmx2xx_pci_preinit()
/linux-4.1.27/arch/arm/mach-sa1100/
H A Dpci-nanoengine.c4 * PCI functions for BSE nanoEngine PCI
55 DEFINE_RES_IO_NAMED(0x400, 0x400, "PCI IO");
58 .name = "PCI non-prefetchable",
61 * but PCI reports just 128 + 8 kbytes. */
68 * nanoEngine PCI reports 1 Megabyte of prefetchable memory, but it
83 PCI: bus0: Fast back to back transfers enabled
86 pci 0000:00:00.0: BAR 2: set to [mem 0x18600000-0x1861ffff] (PCI address [0x0-0x1ffff])
88 pci 0000:00:00.0: BAR 0: set to [mem 0x18620000-0x18620fff] (PCI address [0x20000-0x20fff])
90 pci 0000:00:00.0: BAR 1: set to [io 0x0400-0x043f] (PCI address [0x0-0x3f])
109 PCI: bus0: Fast back to back transfers enabled
112 pci 0000:00:00.0: BAR 2: set to [mem 0x18600000-0x1861ffff] (PCI address [0x0-0x1ffff])
114 pci 0000:00:00.0: BAR 0: set to [mem 0x18620000-0x18620fff] (PCI address [0x20000-0x20fff])
116 pci 0000:00:00.0: BAR 1: set to [io 0x0400-0x043f] (PCI address [0x0-0x3f])
136 .name = "PCI prefetchable",
145 printk(KERN_ERR "PCI: unable to allocate io port region\n"); pci_nanoengine_setup_resources()
150 printk(KERN_ERR "PCI: unable to allocate non prefetchable\n"); pci_nanoengine_setup_resources()
156 printk(KERN_ERR "PCI: unable to allocate prefetchable\n"); pci_nanoengine_setup_resources()
/linux-4.1.27/include/linux/
H A D8250_pci.h2 * Definitions for PCI support.
12 /* Use successive BARs (PCI base address registers),
/linux-4.1.27/drivers/staging/comedi/
H A Dcomedi_pci.c3 * Comedi PCI driver specific functions.
35 * comedi_pci_enable() - Enable the PCI device and request the regions.
61 * comedi_pci_disable() - Release the regions and disable the PCI device.
77 * comedi_pci_detach() - A generic (*detach) function for PCI drivers.
100 * comedi_pci_auto_config() - Configure/probe a comedi PCI driver.
116 * comedi_pci_auto_unconfig() - Unconfigure/remove a comedi PCI driver.
128 * comedi_pci_driver_register() - Register a comedi PCI driver.
132 * This function is used for the module_init() of comedi PCI drivers.
156 * comedi_pci_driver_unregister() - Unregister a comedi PCI driver.
160 * This function is used for the module_exit() of comedi PCI drivers.
184 MODULE_DESCRIPTION("Comedi PCI interface module");
H A Dcomedi_pci.h3 * header file for Comedi PCI drivers
27 * PCI Vendor IDs not in <linux/pci_ids.h>
51 * module_comedi_pci_driver() - Helper macro for registering a comedi PCI driver
55 * Helper macro for comedi PCI drivers which do not do anything special
/linux-4.1.27/arch/sparc/kernel/
H A Dpci_impl.h1 /* pci_impl.h: Helper definitions for PCI controller support.
18 /* The abstraction used here is that there are PCI controllers,
19 * each with one (Sabre) or two (PSYCHO/SCHIZO) PCI bus modules
20 * underneath. Each PCI bus module uses an IOMMU (shared by both
22 * is present, each PCI bus module has it's own. (ie. the IOMMU
24 * Furthermore, each PCI bus module controls it's own autonomous
25 * PCI bus.
102 /* Base of PCI Config space, can be per-PBM or shared. */
105 /* This will be 12 on PCI-E controllers, 8 elsewhere. */
147 /* Now things for the actual PCI bus probes. */
160 /* PCI bus scanning and fixup support. */
H A Dleon_pci.c2 * leon_pci.c: LEON Host PCI support
17 * PCI for us. The Linux generic routines are used to setup resources,
20 * PCI Memory and Prefetchable Memory is direct-mapped. However I/O Space is
21 * accessed through a Window which is translated to low 64KB in PCI space, the
59 * or memory access to PCI devices. Instead we enable it here pcibios_fixup_bus()
H A Dleon_pci_grpci1.c2 * leon_pci_grpci1.c: GRPCI1 Host PCI driver
6 * This GRPCI1 driver does not support PCI interrupts taken from
7 * GPIO pins. Interrupt generation at PCI parity and system error
43 unsigned int stat_cmd; /* 0x18 PCI Status & Command (RO) */
87 unsigned char irq_map[4]; /* GRPCI nexus PCI INTX# IRQs */
90 /* AHB PCI Windows */
109 /* Use default IRQ decoding on PCI BUS0 according slot numbering */ grpci1_map_irq()
142 /* Clear Master abort bit in PCI cfg space (is set) */ grpci1_cfg_r32()
235 /* Read from Configuration Space. When entering here the PCI layer has taken
274 /* Write to Configuration Space. When entering here the PCI layer has taken
310 * 3 where all PCI Interrupts has a separate IRQ on the system IRQ controller
320 if (irqidx > 3) /* only mask PCI interrupts here */ grpci1_mask_irq()
333 if (irqidx > 3) /* only unmask PCI interrupts here */ grpci1_unmask_irq()
359 /* Handle one or multiple IRQs from the PCI core */ grpci1_pci_flow_irq()
375 /* PCI Interrupt? */ grpci1_pci_flow_irq()
377 /* Call respective PCI Interrupt handler */ grpci1_pci_flow_irq()
413 * Initialize mappings AMBA<->PCI, clear IRQ state, setup PCI interface
425 /* set 1:1 mapping between AHB -> PCI memory space */ grpci1_hw_init()
428 /* map PCI accesses to target BAR1 to Linux kernel memory 1:1 */ grpci1_hw_init()
432 /* translate I/O accesses to 0, I/O Space always @ PCI low 64Kbytes */ grpci1_hw_init()
448 * Setup the Host's PCI Target BAR1 for other peripherals to access, grpci1_hw_init()
456 * will set it according to the max size of the PCI FIFO. grpci1_hw_init()
561 /* hardware must support little-endian PCI (byte-twisting) */ grpci1_of_probe()
571 /* Find PCI Memory, I/O and Configuration Space Windows */ grpci1_of_probe()
579 dev_err(&ofdev->dev, "unable to map PCI I/O area\n"); grpci1_of_probe()
596 priv->info.io_space.name = "GRPCI1 PCI I/O Space"; grpci1_of_probe()
605 priv->info.mem_space.name = "GRPCI1 PCI MEM Space"; grpci1_of_probe()
611 dev_err(&ofdev->dev, "unable to request PCI memory area\n"); grpci1_of_probe()
617 dev_err(&ofdev->dev, "unable to request PCI I/O area\n"); grpci1_of_probe()
622 /* setup maximum supported PCI buses */ grpci1_of_probe()
633 * Get PCI Interrupt to System IRQ mapping and setup IRQ handling grpci1_of_probe()
634 * Error IRQ. All PCI and PCI-Error interrupts are shared using the grpci1_of_probe()
645 printk(KERN_INFO " PCI INTA..D#: IRQ%d, IRQ%d, IRQ%d, IRQ%d\n", grpci1_of_probe()
676 * Enable Error Interrupts. PCI interrupts are unmasked once request_irq grpci1_of_probe()
677 * is called by the PCI Device drivers grpci1_of_probe()
H A Dleon_pci_grpci2.c2 * leon_pci_grpci2.c: GRPCI2 Host PCI driver
23 unsigned long pciadr; /* PCI Space Address */
24 unsigned long ahbadr; /* PCI Base address mapped to this AHB addr */
29 * - irq_mask : Limit which PCI interrupts are enabled
30 * - do_reset : Force PCI Reset on startup
40 * [i*2+0] = PCI Address of BAR[i] on target interface
41 * [i*2+1] = Accessing PCI address of BAR[i] result in this AMBA address
47 * Limit which PCI interrupts are enabled. 0=Disable, 1=Enable. By default
48 * all are enabled. Use this when PCI interrupt pins are floating on PCB.
50 * bit0 = PCI INTA#
51 * bit1 = PCI INTB#
52 * bit2 = PCI INTC#
53 * bit3 = PCI INTD#
59 * Force PCI reset on startup. int, len=4
76 unsigned int bars[6]; /* 0x20 read-only PCI BARs */
78 unsigned int ahbmst_map[16]; /* 0x40 AHB->PCI Map per AHB Master */
80 /* PCI Trace Buffer Registers (OPTIONAL) */
159 unsigned int pci_adr; /* 0x04 PCI Start Address */
200 u32 pciid; /* PCI ID of Host */
207 /* AHB PCI Windows */
226 /* Use default IRQ decoding on PCI BUS0 according slot numbering */ grpci2_map_irq()
372 /* Read from Configuration Space. When entering here the PCI layer has taken
411 /* Write to Configuration Space. When entering here the PCI layer has taken
447 * 3 where all PCI Interrupts has a separate IRQ on the system IRQ controller
458 if (irqidx > 3) /* only mask PCI interrupts here */ grpci2_mask_irq()
473 if (irqidx > 3) /* only unmask PCI interrupts here */ grpci2_unmask_irq()
500 /* Handle one or multiple IRQs from the PCI core */ grpci2_pci_flow_irq()
516 /* PCI Interrupt? */ grpci2_pci_flow_irq()
519 /* Call respective PCI Interrupt handler */ grpci2_pci_flow_irq()
528 * Decode DMA Interrupt only when shared with Err and PCI INTX#, when grpci2_pci_flow_irq()
573 printk(KERN_INFO "GRPCI2: Resetting PCI bus\n"); grpci2_hw_init()
582 /* Translate I/O accesses to 0, I/O Space always @ PCI low 64Kbytes */ grpci2_hw_init()
585 /* set 1:1 mapping between AHB -> PCI memory space, for all Masters grpci2_hw_init()
591 /* Get the GRPCI2 Host PCI ID */ grpci2_hw_init()
602 /* Setup the Host's PCI Target BARs for other peripherals to access, grpci2_hw_init()
609 * PCI bus, the other BARs are disabled. We assume that the first BAR grpci2_hw_init()
635 printk(KERN_INFO " TGT BAR[%d]: 0x%08x (PCI)-> 0x%08x\n", grpci2_hw_init()
749 /* Optional PCI reset. Force PCI reset on startup */ grpci2_of_probe()
756 /* Find PCI Memory, I/O and Configuration Space Windows */ grpci2_of_probe()
782 priv->info.io_space.name = "GRPCI2 PCI I/O Space"; grpci2_of_probe()
792 priv->info.mem_space.name = "GRPCI2 PCI MEM Space"; grpci2_of_probe()
802 /* setup maximum supported PCI buses */ grpci2_of_probe()
810 * Get PCI Interrupt to System IRQ mapping and setup IRQ handling grpci2_of_probe()
811 * Error IRQ always on PCI INTA. grpci2_of_probe()
814 /* All PCI interrupts are shared using the same system IRQ */ grpci2_of_probe()
835 /* All PCI interrupts have an unique IRQ interrupt */ grpci2_of_probe()
849 /* Unmask all PCI interrupts, request_irq will not do that */ grpci2_of_probe()
862 * Enable Error Interrupts. PCI interrupts are unmasked once request_irq grpci2_of_probe()
863 * is called by the PCI Device drivers grpci2_of_probe()
/linux-4.1.27/arch/microblaze/include/asm/
H A Dpci-bridge.h27 * Structure of a PCI controller (host bridge)
47 * the PCI memory space in the CPU bus space
63 * Used for variants of PCI indirect handling and possible quirks:
65 * EXT_REG - provides access to PCI-e extended registers
67 * on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
70 * NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
91 int global_number; /* PCI domain number */
103 * all goes through PCI isa_vaddr_is_ioport()
109 /* These are used for config access before all the PCI probing
131 /* Get the PCI host controller for an OF device */
139 /* Allocate & free a PCI host bridge structure */
/linux-4.1.27/sound/pci/trident/
H A Dtrident.c2 * Driver for Trident 4DWave DX/NX & SiS SI7018 Audio PCI soundcard
37 "{SiS,SI7018 PCI Audio},"
38 "{Best Union,Miss Melody 4DWave PCI},"
39 "{HIS,4DWave PCI},"
40 "{Warpspeed,ONSpeed 4DWave PCI},"
41 "{Aztech Systems,PCI 64-Q3D},"
44 "{Shark,Predator4D-PCI},"
55 MODULE_PARM_DESC(index, "Index value for Trident 4DWave PCI soundcard.");
57 MODULE_PARM_DESC(id, "ID string for Trident 4DWave PCI soundcard.");
59 MODULE_PARM_DESC(enable, "Enable Trident 4DWave PCI soundcard.");
127 sprintf(card->longname, "%s PCI Audio at 0x%lx, irq %d", snd_trident_probe()
/linux-4.1.27/drivers/edac/
H A Dedac_pci_sysfs.c20 static int check_pci_errors; /* default NO check PCI parity */
21 static int edac_pci_panic_on_pe; /* default NO panic on PCI Parity */
22 static int edac_pci_log_pe = 1; /* log PCI parity errors */
23 static int edac_pci_log_npe = 1; /* log PCI non-parity error errors */
58 /**************************** EDAC PCI sysfs instance *******************/ instance_pe_count_show()
154 * construct one EDAC PCI instance's kobject for use
164 * track the number of PCI instances we have, and thus nest edac_pci_create_instance_kobj()
195 * unregister the kobj for the EDAC PCI instance
209 /***************************** EDAC PCI sysfs root **********************/
237 /* Set of show/store abstract level functions for PCI Parity object */ edac_pci_dev_show()
282 /* PCI Parity control files */
311 * This kobj is the 'main' kobject that EDAC PCI instances
320 /* last reference to top EDAC PCI kobject has been removed, edac_pci_release_main_kobj()
326 /* ktype struct for the EDAC PCI main kobj */
336 * setup the sysfs for EDAC PCI attributes
362 * level main kobj for EDAC PCI edac_pci_main_kobj_setup()
387 * for EDAC PCI, then edac_pci_main_kobj_teardown() edac_pci_main_kobj_setup()
415 * if no longer linked (needed) remove the top level EDAC PCI
437 * Create the controls/attributes for the specified EDAC PCI device
446 /* create the top main EDAC PCI kobject, IF needed */ edac_pci_create_sysfs()
477 * remove the controls and attributes for this EDAC PCI device
486 /* remove this PCI instance's sysfs entries */ edac_pci_remove_sysfs()
497 /************************ PCI error handling *************************/ get_pci_parity_status()
507 * pulled but the Linux PCI layer has not yet finished cleaning up. get_pci_parity_status()
531 /* Clear any PCI parity errors logged by this device. */ edac_pci_dev_parity_clear()
546 * PCI Parity polling
569 edac_dbg(4, "PCI STATUS= 0x%04x %s\n", status, dev_name(&dev->dev)); edac_pci_dev_parity_test()
600 edac_dbg(4, "PCI HEADER TYPE= 0x%02x %s\n", edac_pci_dev_parity_test()
607 edac_dbg(4, "PCI SEC_STATUS= 0x%04x %s\n", edac_pci_dev_parity_test()
646 * Scan the PCI device list looking for SERRORs, Master Parity ERRORS or
660 * performs the actual PCI parity check operation
668 /* if policy has PCI check off, leave now */ edac_pci_do_parity_check()
674 /* scan all PCI devices looking for a Parity Error on devices and edac_pci_do_parity_check()
681 /* Only if operator has selected panic on PCI Error */ edac_pci_do_parity_check()
685 panic("EDAC: PCI Parity Error"); edac_pci_do_parity_check()
692 * function to perform an iteration over the PCI devices
697 /* Clear any PCI bus parity errors that devices initially have logged edac_pci_clear_parity_errors()
720 * poke all PCI devices and see which one is the troublemaker edac_pci_handle_pe()
745 * poke all PCI devices and see which one is the troublemaker edac_pci_handle_npe()
753 * Define the PCI parameter to the module
757 "Check for PCI bus parity errors: 0=off 1=on");
760 "Panic on PCI Bus Parity error: 0=off 1=on");
/linux-4.1.27/drivers/scsi/csiostor/
H A Dcsio_hw_t5.c46 * accesses to our Configuration Space and we need to set up the PCI-E csio_t5_set_mem_win()
48 * coming across the PCI-E link. csio_t5_set_mem_win()
104 { PIOCPLGRPPERR_F, "PCI PIO completion Group FIFO parity error", csio_t5_pcie_intr_handler()
106 { PIOREQGRPPERR_F, "PCI PIO request Group FIFO parity error", csio_t5_pcie_intr_handler()
108 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 }, csio_t5_pcie_intr_handler()
109 { MSTTAGQPERR_F, "PCI master tag queue parity error", -1, 1 }, csio_t5_pcie_intr_handler()
110 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 }, csio_t5_pcie_intr_handler()
111 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 }, csio_t5_pcie_intr_handler()
112 { DREQWRPERR_F, "PCI DMA channel write request parity error", csio_t5_pcie_intr_handler()
114 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 }, csio_t5_pcie_intr_handler()
115 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 }, csio_t5_pcie_intr_handler()
116 { HREQWRPERR_F, "PCI HMA channel count parity error", -1, 1 }, csio_t5_pcie_intr_handler()
117 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 }, csio_t5_pcie_intr_handler()
118 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 }, csio_t5_pcie_intr_handler()
119 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 }, csio_t5_pcie_intr_handler()
120 { FIDPERR_F, "PCI FID parity error", -1, 1 }, csio_t5_pcie_intr_handler()
121 { VFIDPERR_F, "PCI INTx clear parity error", -1, 1 }, csio_t5_pcie_intr_handler()
122 { MAGRPPERR_F, "PCI MA group FIFO parity error", -1, 1 }, csio_t5_pcie_intr_handler()
123 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 }, csio_t5_pcie_intr_handler()
124 { IPRXHDRGRPPERR_F, "PCI IP Rx header group parity error", csio_t5_pcie_intr_handler()
126 { IPRXDATAGRPPERR_F, "PCI IP Rx data group parity error", csio_t5_pcie_intr_handler()
128 { RPLPERR_F, "PCI IP replay buffer parity error", -1, 1 }, csio_t5_pcie_intr_handler()
129 { IPSOTPERR_F, "PCI IP SOT buffer parity error", -1, 1 }, csio_t5_pcie_intr_handler()
130 { TRGT1GRPPERR_F, "PCI TRGT1 group FIFOs parity error", -1, 1 }, csio_t5_pcie_intr_handler()
267 * @win: PCI-E memory Window to use
314 * Each PCI-E Memory Window is programmed with a window size -- or csio_t5_memory_rw()
319 * space. For T4 this is an absolute PCI-E Bus Address. For T5 csio_t5_memory_rw()
342 * Move PCI-E Memory Window to our current transfer csio_t5_memory_rw()
/linux-4.1.27/arch/xtensa/include/asm/
H A Dpci.h18 * or architectures with incomplete PCI setup by the loader
42 /* The PCI address space does equal the physical memory address space.
49 /* Map a range of PCI memory or I/O space for a device into user space */
61 /* Generic PCI */
/linux-4.1.27/include/video/
H A Diga.h2 * iga1682.h: Sparc/PCI iga1682 driver constants etc.
/linux-4.1.27/arch/powerpc/platforms/chrp/
H A Dgg2.h26 #define GG2_PCI_CONFIG_BASE 0xfec00000 /* PCI configuration space */
28 /* special PCI cycles */
34 * GG2 specific PCI Registers
44 #define GG2_PCI_PCI_CTRL 0x60 /* PCI interface control register */
/linux-4.1.27/arch/sh/boards/mach-landisk/
H A Dirq.c26 PCI_INTA, /* PCI int A */
27 PCI_INTB, /* PCI int B */
28 PCI_INTC, /* PCI int C */
29 PCI_INTD, /* PCI int D */
/linux-4.1.27/arch/mips/include/asm/octeon/
H A Dpci-octeon.h30 * function needs to change for PCI or PCIe based hosts.
36 * For PCI (not PCIe) the BAR2 base address.
41 * For PCI (not PCIe) the base of the memory mapped by BAR1
61 * This tells the DMA mapping system in dma-octeon.c how to map PCI
/linux-4.1.27/arch/powerpc/include/asm/
H A Dtce.h29 * format for PCI. PCI TCEs can have hardware or software maintianed
49 #define TCE_PCI_WRITE 0x2 /* write from PCI allowed */
50 #define TCE_PCI_READ 0x1 /* read from PCI allowed */
H A Dhydra.h88 #define HYDRA_INT_EXT1 12 /* PCI IRQW */
89 #define HYDRA_INT_EXT2 13 /* PCI IRQX */
90 #define HYDRA_INT_EXT3 14 /* PCI IRQY */
91 #define HYDRA_INT_EXT4 15 /* PCI IRQZ */
/linux-4.1.27/arch/cris/include/asm/
H A Ddma.h13 /* From PCI */
/linux-4.1.27/arch/arm/mach-pxa/include/mach/
H A Dio.h12 * We don't actually have real ISA nor PCI buses, but there is so many
/linux-4.1.27/include/asm-generic/
H A Dparport.h10 * to devices on the PCI bus.
H A Dpci.h30 * By default, assume that no iommu is in use and that the PCI
/linux-4.1.27/include/linux/mfd/
H A Drdc321x.h7 /* Offsets to be accessed in the southbridge PCI
/linux-4.1.27/drivers/watchdog/
H A Dwd501p.h27 #define WDT_SR (io+4) /* Start buzzer on PCI write */
28 #define WDT_RT (io+5) /* Stop buzzer on PCI write */
29 #define WDT_BUZZER (io+6) /* PCI only: rd=disable, wr=enable */
32 /* The following are only on the PCI card, they're outside of I/O space on
/linux-4.1.27/drivers/isdn/hardware/eicon/
H A Dcardtype.h376 "Diva PRO 2.0 S/T PCI", 0xe001, 0x0200,
382 "Diva 2.0 S/T PCI", 0xe002, 0x0200,
460 "Diva Server BRI-2M PCI", 0xE010, 0x0100,
466 "Diva Server 4BRI-8M PCI", 0xE012, 0x0100,
472 "Diva Server PRI-30M PCI", 0xE014, 0x0100,
478 "Diva Server PRI-2M PCI", 0xe014, 0x0100,
484 "Diva Server PRI-9M PCI", 0x0000, 0x0100,
502 "Diva 2.0 U PCI", 0xe004, 0x0200,
520 "Diva PRO 2.0 U PCI", 0xe003, 0x0200,
543 { /* 35 (OEM version of 7 - "Diva PRO 2.0 S/T PCI") */
544 "BT ExLane PCI", 0xe101, 0x0200,
568 "Diva 2.01 S/T PCI", 0xe005, 0x0300,
574 "Diva 2.01 U PCI", 0x0000, 0x0300,
592 "Diva Server PRI-23M PCI", 0xe014, 0x0100,
604 "Diva CT S/T PCI", 0xe006, 0x0300,
610 "Diva CT U PCI", 0xe007, 0x0300,
616 "Diva CT Lite S/T PCI", 0xe008, 0x0300,
622 "Diva CT Lite U PCI", 0xe009, 0x0300,
634 "Diva ISDN+V.90 PCI", 0xe00A, 0x0100,
645 { /* 52 (Diva Server 4BRI-8M PCI adapter enabled for Voice) */
646 "Diva Server Voice 4BRI-8M PCI", 0xE016, 0x0100,
652 "Diva Server 4BRI-8M 2.0 PCI", 0xE013, 0x0200,
658 "Diva Server PRI 2.0 PCI", 0xE015, 0x0200,
663 { /* 55 (Diva Server 4BRI-8M 2.0 PCI adapter enabled for Voice) */
664 "Diva Server Voice 4BRI-8M 2.0 PCI", 0xE017, 0x0200,
669 { /* 56 (Diva Server PRI 2.0 PCI adapter enabled for Voice) */
670 "Diva Server Voice PRI 2.0 PCI", 0xE019, 0x0200,
683 "Diva 2.02 PCI S/T", 0xE00B, 0x0300,
689 "Diva 2.02 PCI U", 0xE00C, 0x0300,
695 "Diva Server BRI-2M 2.0 PCI", 0xE018, 0x0200,
700 { /* 61 (the previous name was Diva Server BRI-2F 2.0 PCI) */
712 { /* 63 (Diva Server BRI-2M 2.0 PCI adapter enabled for Voice) */
713 "Diva Server Voice BRI-2M 2.0 PCI", 0xE01B, 0x0200,
719 "Diva Pro 3.0 PCI", 0xe00d, 0x0300,
760 /* 7*/ { 3,4,5,7,9,10,11,12,14,15, 0x0,0x8,8192, 0x0,0x0,0 }, // DIVA PRO 2.0 PCI
761 /* 8*/ { 3,4,5,7,9,10,11,12,14,15, 0x0,0x8,8192, 0x0,0x0,0 }, // DIVA 2.0 PCI
774 /*21*/ { 3,4,5,7,9,10,11,12,14,15, 0x0,0x8,8192, 0x0,0x0,0 }, // MAESTRA PCI
776 /*23*/ { 3,4,5,7,9,10,11,12,14,15, 0x0,0x20,2048, 0x0,0x0,0 }, // MAESTRA QUADRO PCI
778 /*25*/ { 3,4,5,7,9,10,11,12,14,15, 0x0,0x8,8192, 0x0,0x0,0 }, // MAESTRA PRIMARY PCI
781 /*28*/ { 3,4,5,7,9,10,11,12,14,15, 0x0,0x8,8192, 0x0,0x0,0 }, // DIVA 2.0 /U PCI
784 /*31*/ { 3,4,5,7,9,10,11,12,14,15, 0x0,0x8,8192, 0x0,0x0,0 }, // DIVA PRO 2.0 /U PCI
788 /*35*/ { 3,4,5,7,9,10,11,12,14,15, 0x0,0x8,8192, 0x0,0x0,0 }, // BT ExLane PCI (same as DIVA PRO 2.0 PCI [7])
792 /*39*/ { 3,4,5,7,9,10,11,12,14,15, 0x0,0x8,8192, 0x0,0x0,0 }, // DIVA 2.01 S/T PCI
793 /*40*/ { 3,4,5,7,9,10,11,12,14,15, 0x0,0x8,8192, 0x0,0x0,0 }, // DIVA 2.01 U PCI
796 /*43*/ { 3,4,5,7,9,10,11,12,14,15, 0x0,0x20,2048, 0x0,0x0,0 }, // DIVA Server PRI-23M PCI
798 /*45*/ { 0,0,0,0,0,0,0,0,0,0, 0x0,0x0,0, 0x0,0x0,0 }, // DIVA CT S/T PCI
799 /*46*/ { 0,0,0,0,0,0,0,0,0,0, 0x0,0x0,0, 0x0,0x0,0 }, // DIVA CT U PCI
800 /*47*/ { 0,0,0,0,0,0,0,0,0,0, 0x0,0x0,0, 0x0,0x0,0 }, // DIVA CT Lite S/T PCI
801 /*48*/ { 0,0,0,0,0,0,0,0,0,0, 0x0,0x0,0, 0x0,0x0,0 }, // DIVA CT Lite U PCI
803 /*50*/ { 3,4,5,7,9,10,11,12,14,15, 0x0,0x8,8192, 0x0,0x0,0 }, // DIVA ISDN+V.90 PCI
805 /*52*/ { 3,4,5,7,9,10,11,12,14,15, 0x0,0x20,2048, 0x0,0x0,0 }, // MAESTRA VOICE QUADRO PCI
806 /*53*/ { 3,4,5,7,9,10,11,12,14,15, 0x0,0x20,2048, 0x0,0x0,0 }, // MAESTRA VOICE QUADRO PCI
807 /*54*/ { 3,4,5,7,9,10,11,12,14,15, 0x0,0x8,8192, 0x0,0x0,0 }, // MAESTRA VOICE PRIMARY PCI
808 /*55*/ { 3,4,5,7,9,10,11,12,14,15, 0x0,0x20,2048, 0x0,0x0,0 }, // MAESTRA VOICE QUADRO PCI
809 /*56*/ { 3,4,5,7,9,10,11,12,14,15, 0x0,0x8,8192, 0x0,0x0,0 }, // MAESTRA VOICE PRIMARY PCI
811 /*58*/ { 3,4,5,7,9,10,11,12,14,15, 0x0,0x8,8192, 0x0,0x0,0 }, // DIVA 2.02 S/T PCI
812 /*59*/ { 3,4,5,7,9,10,11,12,14,15, 0x0,0x8,8192, 0x0,0x0,0 }, // DIVA 2.02 U PCI
813 /*60*/ { 0,0,0,0,0,0,0,0,0,0, 0x0,0x0,0, 0x0,0x0,0 }, // Diva Server BRI-2M 2.0 PCI
814 /*61*/ { 0,0,0,0,0,0,0,0,0,0, 0x0,0x0,0, 0x0,0x0,0 }, // Diva Server BRI-2F PCI
816 /*63*/ { 0,0,0,0,0,0,0,0,0,0, 0x0,0x0,0, 0x0,0x0,0 }, // Diva Server Voice BRI-2M 2.0 PCI
817 /*64*/ { 3,4,5,7,9,10,11,12,14,15, 0x0,0x8,8192, 0x0,0x0,0 }, // DIVA 3.0 PCI
818 /*65*/ { 0,0,0,0,0,0,0,0,0,0, 0x0,0x0,0, 0x0,0x0,0 }, // DIVA CT S/T PCI V2.0
/linux-4.1.27/arch/mips/include/asm/mach-loongson/cs5536/
H A Dcs5536_pci.h27 /************** PCI BUS DEVICE FUNCTION ***************/
30 * PCI bus device function
35 /********** STANDARD PCI-2.2 EXPANSION ****************/
38 * PCI configuration space
39 * we have to virtualize the PCI configure space head, so we should
43 /* CONFIG of PCI VENDOR ID*/
115 /*********** EXPANSION PCI REG ************************/
/linux-4.1.27/drivers/of/
H A Dof_pci_irq.c7 * of_irq_parse_pci - Resolve the interrupt for a PCI device
11 * This function resolves the PCI interrupt for a given PCI device. If a
14 * PCI tree until an device-node is found, at which point it will finish
37 * for PCI. If you do different, then don't use that routine. of_irq_parse_pci()
46 /* Now we walk up the PCI tree */ of_irq_parse_pci()
72 * create device nodes for all PCI devices). of_irq_parse_pci()
94 * of_irq_parse_and_map_pci() - Decode a PCI irq from the device tree and map to a virq
96 * @slot: PCI slot number; passed when used as map_irq callback. Unused
97 * @pin: PCI irq pin number; passed when used as map_irq callback. Unused
/linux-4.1.27/arch/x86/xen/
H A Dplatform-pci-unplug.c4 * Xen platform PCI device driver
45 printk(KERN_ERR "Xen Platform PCI: unrecognised magic value\n"); check_platform_magic()
51 printk(KERN_DEBUG "Xen Platform PCI: I/O protocol version %d\n", check_platform_magic()
64 printk(KERN_WARNING "Xen Platform PCI: unknown I/O protocol version"); check_platform_magic()
152 /* check the version of the xen platform PCI device */ xen_unplug_emulated_devices()
154 /* If the version matches enable the Xen platform PCI driver. xen_unplug_emulated_devices()
155 * Also enable the Xen platform PCI driver if the host does xen_unplug_emulated_devices()
162 * not the Xen PV frontends and the Xen platform PCI driver have xen_unplug_emulated_devices()
166 printk(KERN_INFO "Netfront and the Xen platform PCI driver have " xen_unplug_emulated_devices()
171 printk(KERN_INFO "Blkfront and the Xen platform PCI driver have " xen_unplug_emulated_devices()
/linux-4.1.27/arch/mips/loongson/common/
H A Dpci.c41 * local to PCI mapping for CPU accessing PCI space setup_pcimap()
54 * PCI-DMA to local mapping: [2G,2G+256M] -> [0M,256M] setup_pcimap()
65 /* avoid deadlock of PCI reading/writing lock operation */ setup_pcimap()
74 * set cpu addr window2 to map CPU address space to PCI address space setup_pcimap()
/linux-4.1.27/arch/mips/txx9/generic/
H A Dpci.c59 /* It seems SLC90E66 needs some time after PCI reset... */ txx9_pci66_check()
62 printk(KERN_INFO "PCI: Checking 66MHz capabilities...\n"); txx9_pci66_check()
82 "PCI: %02x:%02x not 66MHz capable.\n", txx9_pci66_check()
93 { .name = "PCI MEM" },
94 { .name = "PCI MMIO" },
96 static struct resource primary_pci_io_res = { .name = "PCI IO" };
130 new->r_mem[0].name = "PCI mem"; txx9_alloc_pci_controller()
131 new->r_mem[1].name = "PCI mmio"; txx9_alloc_pci_controller()
132 new->r_io.name = "PCI io"; txx9_alloc_pci_controller()
141 * for auto assignment, first search a (big) region for PCI txx9_alloc_pci_controller()
142 * MEM, then search a region for PCI IO. txx9_alloc_pci_controller()
162 /* search free region for PCI MEM */ txx9_alloc_pci_controller()
184 /* search free region for PCI IO in low 512MB */ txx9_alloc_pci_controller()
200 /* map ioport 0 to PCI I/O space address 0 */ txx9_alloc_pci_controller()
216 printk(KERN_INFO "PCI: IO %pR MEM %pR\n", txx9_alloc_pci_controller()
226 printk(KERN_ERR "PCI: Failed to allocate resources.\n"); txx9_alloc_pci_controller()
267 printk(KERN_INFO "PCI-ISA bridge PIC (irq %d)\n", irq); txx9_i8259_irq_setup()
273 int irq; /* PCI/ISA Bridge interrupt */ quirk_slc90e66_bridge()
315 printk(KERN_INFO "PCI: %s: IRQ %02x", pci_name(dev), dat); quirk_slc90e66_ide()
359 printk(KERN_INFO "PCI: %s BIST...", pci_name(dev)); final_fixup()
/linux-4.1.27/arch/mn10300/include/asm/
H A Dpci.h1 /* MN10300 PCI definitions
24 printk(KERN_DEBUG "PCI[%02x:%02x.%x + %02x]: "FMT"\n", \
38 * architectures with incomplete PCI setup by the loader */
64 /* The PCI address space does equal the physical memory
70 /* Return the index of the PCI controller for device. */ pci_controller_num()
/linux-4.1.27/arch/alpha/include/asm/
H A Dcore_polaris.h9 * memory controller and PCI access for the 21164PC chip based systems.
31 /* The Polaris command/status registers live in PCI Config space for
59 * POLARIS, the PCI/memory support chipset for the PCA56 (21164PC)
61 * so-called byte-word PCI address space, to get at PCI memory and I/O.
/linux-4.1.27/drivers/net/can/sja1000/
H A Dplx_pci.c37 MODULE_DESCRIPTION("Socket-CAN driver for PLX90xx PCI-bridge cards with "
39 MODULE_SUPPORTED_DEVICE("Adlink PCI-7841/cPCI-7841, "
40 "Adlink PCI-7841/cPCI-7841 SE, "
41 "Marathon CAN-bus-PCI, "
43 "esd CAN-PCI/CPCI/PCI104/200, "
44 "esd CAN-PCI/PMC/266, "
47 "IXXAT PC-I 04/PCI, "
48 "ELCUS CAN-200-PCI")
73 #define PLX_PCI_INT_EN (1 << 6) /* PCI Interrupt Enable */
74 #define PLX_PCI_RESET (1 << 30) /* PCI Adapter Software Reset */
171 "Adlink PCI-7841/cPCI-7841", 2,
179 "Adlink PCI-7841/cPCI-7841 SE", 2,
187 "esd CAN-PCI/CPCI/PCI104/200", 2,
195 "esd CAN-PCI/PMC/266", 2,
211 "IXXAT PC-I 04/PCI", 2,
219 "Marathon CAN-bus-PCI", 2,
243 "Eclus CAN-200-PCI", 2,
252 /* Adlink PCI-7841/cPCI-7841 */
259 /* Adlink PCI-7841/cPCI-7841 SE */
266 /* esd CAN-PCI/200 */
287 /* esd CAN-PCI/266 */
308 /* IXXAT PC-I 04/PCI card */
315 /* Marathon CAN-bus-PCI card */
336 /* Elcus CAN-200-PCI */
486 * Disable interrupts from PCI-card and disable local plx_pci_del_card()
520 dev_err(&pdev->dev, "Failed to enable PCI device\n"); plx_pci_add_card()
619 * Enable interrupts from PCI-card (PLX90xx) and enable Local_1, plx_pci_add_card()
/linux-4.1.27/drivers/infiniband/hw/mthca/
H A Dmthca_reset.c60 * save off the PCI header before reset and then restore it mthca_reset()
64 * To make matters worse, for Tavor (PCI-X HCA) we have to mthca_reset()
65 * find the associated bridge device and save off its PCI mthca_reset()
95 /* For Arbel do we need to save off the full 4K PCI Express header?? */ mthca_reset()
100 "PCI header, aborting.\n"); mthca_reset()
110 "PCI header, aborting.\n"); mthca_reset()
123 "bridge PCI header, aborting.\n"); mthca_reset()
133 "PCI header, aborting.\n"); mthca_reset()
141 "PCI-X capability, aborting.\n"); mthca_reset()
165 /* Now wait for PCI device to start responding again */ mthca_reset()
185 mthca_err(mdev, "PCI device did not come back after reset, " mthca_reset()
191 /* Now restore the PCI headers */ mthca_reset()
236 mthca_err(mdev, "Couldn't restore HCA PCI-X " mthca_reset()
247 mthca_err(mdev, "Couldn't restore HCA PCI Express " mthca_reset()
255 mthca_err(mdev, "Couldn't restore HCA PCI Express " mthca_reset()
/linux-4.1.27/arch/arm/mach-versatile/
H A Dpci.c12 * ARM Versatile PCI driver.
38 * Cfg 42000000 - 42FFFFFF PCI config
174 .name = "PCI unused",
181 .name = "PCI non-prefetchable",
188 .name = "PCI prefetchable",
200 printk(KERN_ERR "PCI: unable to allocate unused " pci_versatile_setup_resources()
206 printk(KERN_ERR "PCI: unable to allocate non-prefetchable " pci_versatile_setup_resources()
212 printk(KERN_ERR "PCI: unable to allocate prefetchable " pci_versatile_setup_resources()
244 printk("Not plugged into PCI backplane!\n"); pci_versatile_setup()
265 * We need to discover the PCI core first to configure itself pci_versatile_setup()
266 * before the main PCI probing is performed pci_versatile_setup()
276 printk("Cannot find PCI core!\n"); pci_versatile_setup()
281 printk("PCI core found (slot %d)\n",myslot); pci_versatile_setup()
291 * Configure the PCI inbound memory windows to be 1:1 mapped to SDRAM pci_versatile_setup()
311 * Do not to map Versatile FPGA PCI device into memory space pci_versatile_setup()
/linux-4.1.27/arch/mips/include/asm/mach-rc32434/
H A Dpci.h71 * PCI Control Register
95 * PCI Status Register
118 * PCI Status Mask Register
141 * PCI Configuration Address Register
170 #define PCI CFGA_BUS 0x00ff0000 macro
174 /* PCI CFG04 commands */
183 /* PCI CFG04 status fields */
199 /* PCI PBAC registers */
219 * PCI Local Base Address [0|1|2|3] Register
226 * PCI Local Base Address Control Register
240 * PCI Local Base Address [0|1|2|3] Mapping Register
246 * PCI Decoupled Access Control Register
251 * PCI Decoupled Access Status Register
262 * PCI DMA Channel 8 Configuration Register
269 * PCI DMA Channel 9 Configuration Register
275 * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
295 * PCI Target Control Register
306 * PCI messaging unit [applies to both inbound and outbound registers ]
/linux-4.1.27/drivers/scsi/ufs/
H A Dufshcd-pci.c2 * Universal Flash Storage Host controller PCI glue driver
43 * @pdev: pointer to PCI device handle
56 * @pdev: pointer to PCI device handle
88 * @pdev: pointer to PCI device handle
96 * ufshcd_pci_remove - de-allocate PCI/SCSI host and host memory space
98 * @pdev - pointer to PCI handle
111 * @pdev: pointer to PCI device handle
112 * @id: PCI device id
190 MODULE_DESCRIPTION("UFS host controller PCI glue driver");
/linux-4.1.27/arch/m68k/coldfire/
H A Dpci.c2 * pci.c -- PCI bus support for ColdFire processors
26 * PCI bus memory (no reason not to really). IO space doesn't matter, we
230 * Initialize the PCI bus registers, and scan the bus.
233 .name = "PCI Memory space",
240 .name = "PCI IO space",
261 pr_info("ColdFire: PCI bus initialization...\n"); mcf_pci_init()
263 /* Reset the external PCI bus */ mcf_pci_init()
270 /* Configure PCI arbiter */ mcf_pci_init()
274 /* Set required multi-function pins for PCI bus use */ mcf_pci_init()
286 * These give the CPU bus access onto the PCI bus. One for each of mcf_pci_init()
287 * PCI memory and IO address spaces. mcf_pci_init()
297 * Set up the target windows for access from the PCI bus back to the mcf_pci_init()
307 pr_info("Coldfire: PCI IO/config window mapped to 0x%x\n", mcf_pci_init()
310 /* Turn of PCI reset, and wait for devices to settle */ mcf_pci_init()
/linux-4.1.27/arch/tile/include/arch/
H A Dtrio_pcie_rc.h50 * Undefined since PCI Express 1.1 (Was Attention Button Present for PCI
55 * Undefined since PCI Express 1.1 (Was Attention Indicator Present for
56 * PCI Express 1.0a)
60 * Undefined since PCI Express 1.1 (Was Power Indicator Present for PCI
/linux-4.1.27/arch/powerpc/platforms/pseries/
H A Dpci_dlpar.c2 * PCI Dynamic LPAR, PCI Hot Plug and PCI EEH recovery code
73 pr_debug("PCI: Initializing new hotplug PHB %s\n", dn->full_name); init_phb_dynamic()
104 pr_debug("PCI: Removing PHB %04x:%02x...\n", remove_phb_dynamic()
124 /* Remove the PCI bus and unregister the bridge device from sysfs */ remove_phb_dynamic()
/linux-4.1.27/arch/s390/pci/
H A Dpci_event.c16 /* Content Code Description for PCI Function Error */
30 u16 pec; /* PCI event code */
33 /* Content Code Description for PCI Function Availability */
43 u16 pec; /* PCI event code */
56 pr_err("%s: Event 0x%x reports an error for PCI function 0x%x\n", __zpci_event_error()
72 pr_info("%s: Event 0x%x reconfigured PCI function 0x%x\n", __zpci_event_availability()
/linux-4.1.27/arch/arm/mach-iop32x/
H A Diq80321.c68 * IQ80321 PCI.
76 /* PCI-X Slot INTA */ iq80321_pci_map_irq()
79 /* PCI-X Slot INTA */ iq80321_pci_map_irq()
82 /* PCI-X Slot INTA */ iq80321_pci_map_irq()
85 /* PCI-X Slot INTA */ iq80321_pci_map_irq()
92 "device PCI:%d:%d:%d\n", dev->bus->number, iq80321_pci_map_irq()
/linux-4.1.27/arch/arm/mach-iop33x/
H A Diq80331.c50 * IQ80331 PCI.
58 /* PCI-X Slot INTA */ iq80331_pci_map_irq()
61 /* PCI-X Slot INTB */ iq80331_pci_map_irq()
64 /* PCI-X Slot INTC */ iq80331_pci_map_irq()
67 /* PCI-X Slot INTD */ iq80331_pci_map_irq()
74 "device PCI:%d:%d:%d\n", dev->bus->number, iq80331_pci_map_irq()
H A Diq80332.c50 * IQ80332 PCI.
58 /* PCI-X Slot INTA */ iq80332_pci_map_irq()
61 /* PCI-X Slot INTB */ iq80332_pci_map_irq()
64 /* PCI-X Slot INTC */ iq80332_pci_map_irq()
67 /* PCI-X Slot INTD */ iq80332_pci_map_irq()
74 "device PCI:%d:%d:%d\n", dev->bus->number, iq80332_pci_map_irq()
/linux-4.1.27/arch/mips/include/asm/mach-pmcs-msp71xx/
H A Dmsp_pci.h33 * Athena virtual address space and PCI address space are
39 * PCI address space. This region is hardcoded
40 * for use as Athena PCI Host Controller target
47 * and PCI address space have the same values, OATRAN
50 * by the PCI Host controller.
54 * the address appearing on the PCI bus will be
69 /* IRQ for PCI status interrupts */
178 #define BPCI_IFSTATUS_PCIU (1<<15) /* PCI unable to respond */
179 #define BPCI_IFSTATUS_BSIZ (1<<16) /* PCI access with illegal size */
180 #define BPCI_IFSTATUS_BADD (1<<17) /* PCI access with illegal addr */
196 #define BPCI_RESETCTL_PE (1<<12) /* PCI enabled */
197 #define BPCI_RESETCTL_HM (1<<13) /* PCI host mode */
198 #define BPCI_RESETCTL_RI (1<<14) /* PCI reset in */
H A Dmsp_slp_int.h33 * comprises the Peripherial block, the PCI block, the PCI MSI block and
34 * the SLP. The PCI interrupts and the SLP errors are handled by the
101 /* PCI subsystem */
103 /* PCI doorbell */
105 /* PCI Message Signal */
107 /* PCI Block Copy 0 */
109 /* PCI Block Copy 1 */
/linux-4.1.27/arch/ia64/include/asm/sn/
H A Dpic.h15 * PIC handles PCI/X busses. PCI/X requires that the 'bridge' (i.e. PIC)
17 * PCI bridges. Because of that we use config space 1 to access the
18 * config space of the first actual PCI device on the bus.
21 * The current PCI-X bus specification now defines that the parent
28 * numbering which PCI-X requires in configuration space. In the past we
30 * PCI-X requires we start a 1, not 0 and currently the PX brick
115 /* 0x0000C0-0x0000FF -- PCI/GIO */
168 /* 0x000600-0x0009FF -- PCI/X registers */
180 /* 0x000A00-0x000BFF -- PCI/X Read&Write Buffer */
212 /* 0x020000-0x027FFF -- PCI Device Configuration Spaces */
226 /* 0x028000-0x028FFF -- PCI Type 1 Configuration Space */
242 /* 0x030000-0x030007 -- PCI Interrupt Acknowledge Cycle */
/linux-4.1.27/arch/mn10300/unit-asb2305/
H A Dpci.c1 /* ASB2305 PCI support
30 * The accessible PCI window does not cover the entire CPU address space, but
32 * insert specific PCI bus resources instead of using the platform-level bus
33 * resources directly for the PCI root bus.
38 .name = "PCI IO",
45 .name = "PCI mem",
52 * Functions for accessing PCI configuration space
240 * attempt to make use of direct access hints provided by the PCI BIOS).
258 printk(KERN_ERR "PCI: Sanity check failed\n"); pci_sanity_check()
273 printk(KERN_INFO "PCI: Using configuration ampci\n"); pci_check_direct()
275 request_mem_region(0xBFFFFFF4, 12, "PCI ampci"); pci_check_direct()
276 request_mem_region(0xBC000000, 32 * 1024 * 1024, "PCI SRAM"); pci_check_direct()
336 * Initialization. Try all known PCI access methods. Note that we support
337 * using both PCI BIOS and direct access: in such cases, we use I/O ports
353 panic("Unable to insert PCI IOMEM resource\n"); pcibios_init()
355 panic("Unable to insert PCI IOPORT resource\n"); pcibios_init()
361 printk(KERN_WARNING "PCI: No PCI bus detected\n"); pcibios_init()
365 printk(KERN_INFO "PCI: Probing PCI hardware [mempage %08x]\n", pcibios_init()
461 * PCI config registers unit_pci_init()
480 /* we also need to set up the PCI-PCI bridge */ unit_pci_init()
H A Dpci-irq.c0 /* PCI IRQ routing on the MN103E010 based ASB2305
11 * This is simple: All PCI interrupts route through the CPU's XIRQ1 pin [IRQ 35]
/linux-4.1.27/drivers/net/ethernet/intel/igb/
H A DMakefile3 # Intel 82575 PCI-Express Ethernet Linux driver
29 # Makefile for the Intel(R) 82575 PCI-Express ethernet driver
/linux-4.1.27/drivers/net/ethernet/mellanox/mlx4/
H A Dreset.c66 * save off the PCI header before reset and then restore it mlx4_reset()
71 /* Do we need to save off the full 4K PCI Express header?? */ mlx4_reset()
75 mlx4_err(dev, "Couldn't allocate memory to save HCA PCI header, aborting\n"); mlx4_reset()
87 mlx4_err(dev, "Couldn't save HCA PCI header, aborting\n"); mlx4_reset()
136 mlx4_err(dev, "PCI device did not come back after reset, aborting\n"); mlx4_reset()
140 /* Now restore the PCI headers */ mlx4_reset()
147 mlx4_err(dev, "Couldn't restore HCA PCI Express Device Control register, aborting\n"); mlx4_reset()
155 mlx4_err(dev, "Couldn't restore HCA PCI Express Link control register, aborting\n"); mlx4_reset()
/linux-4.1.27/drivers/ssb/
H A Db43_pci_bridge.c2 * Broadcom 43xx PCI-SSB bridge module
4 * This technically is a separate PCI driver module, but
/linux-4.1.27/drivers/gpu/drm/mga/
H A Dmga_drv.c115 * function detects PCI G450 cards that appear to the system exactly like
121 * If the device is a PCI G450, zero is returned. Otherwise 2 is returned.
127 /* There are PCI versions of the G450. These cards have the mga_driver_device_is_agp()
128 * same PCI ID as the AGP G450, but have an additional PCI-to-PCI mga_driver_device_is_agp()
132 * device is 0x0021 (HB6 Universal PCI-PCI bridge), we reject the mga_driver_device_is_agp()
/linux-4.1.27/arch/mips/lib/
H A Diomap-pci.c30 printk(KERN_WARNING "io_map_base of root PCI bus %s unset. " __pci_ioport_map()
36 "multiple PCI domains."); __pci_ioport_map()
/linux-4.1.27/arch/mips/rb532/
H A Dsetup.c54 printk(KERN_ERR "Could not remap PCI registers\n"); plat_mem_setup()
63 /* Enable PCI interrupts in EPLD Mask register */ plat_mem_setup()
/linux-4.1.27/drivers/xen/xen-pciback/
H A Dvpci.c2 * PCI Backend - Provides a Virtual PCI bus (with real devices)
78 "Can't export bridges on the virtual PCI bus"); __xen_pcibk_add_pci_dev()
86 "Error adding entry to virtual PCI bus"); __xen_pcibk_add_pci_dev()
95 * Keep multi-function devices together on the virtual PCI bus, except __xen_pcibk_add_pci_dev()
118 /* Assign to a new slot on the virtual PCI bus */ __xen_pcibk_add_pci_dev()
132 "No more space on root virtual PCI bus"); __xen_pcibk_add_pci_dev()
203 /* The Virtual PCI bus has only one root */ __xen_pcibk_publish_pci_roots()
H A Dconf_space_quirks.h2 * PCI Backend - Data structures for special overlays for broken devices.
/linux-4.1.27/arch/microblaze/pci/
H A Dpci-common.c9 * Rework, based on alpha PCI code.
138 * PCI bus numbers have not yet been assigned, and you need to
139 * issue PCI config cycles to an OF device.
141 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
189 /* If memory, add on the PCI bridge address offset */ __pci_mmap_make_offset()
259 * PCI device, it tries to find the PCI device first and calls the
300 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
307 * Perform the actual remap of the pages for a PCI device mapping, as
451 pr_debug("Process %s (pid:%d) mapped non-existing PCI", pci_mmap_legacy_page_range()
521 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
526 * This function will parse the "ranges" property of a PCI host bridge device
538 * between CPU addresses and PCI addresses. Unfortunately, some bridges
540 * maps PCI address 0 to some arbitrary high address of the CPU space in
562 pr_info("PCI host bridge %s %s ranges:\n", pci_process_bridge_OF_ranges()
643 /* We get the PCI/Mem offset from the first range or pci_process_bridge_OF_ranges()
702 pr_err("No host bridge for PCI dev %s !\n", pcibios_fixup_resources()
711 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]", pcibios_fixup_resources()
723 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]\n", pcibios_fixup_resources()
784 * doesn't have IO enabled in the PCI command register, pcibios_uninitialized_bridge_resource()
798 /* Fixup resources of a PCI<->PCI bridge */ pcibios_fixup_bridge()
814 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x] fixup...\n", pci_bus_for_each_resource()
825 pr_debug("PCI:%s (unassigned)\n", pci_bus_for_each_resource()
828 pr_debug("PCI:%s %016llx-%016llx\n", pci_bus_for_each_resource()
847 pr_debug("PCI: Fixup bus devices %d (%s)\n", pcibios_setup_bus_devices()
866 /* When called from the generic PCI probe, read PCI<->PCI bridge pcibios_fixup_bus()
867 * bases. This is -not- called when generating the PCI tree from pcibios_fixup_bus()
945 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n", reparent_resources()
954 * Handle resources of PCI devices. If the world were perfect, we could
966 * the fact the PCI specs explicitly allow address decoders to be
971 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
992 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n", pcibios_allocate_bus_resources()
1011 /* this happens when the generic PCI pci_bus_for_each_resource()
1019 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx ", pci_bus_for_each_resource()
1047 pr_warn("PCI: Cannot allocate resource region "); pci_bus_for_each_resource()
1048 pr_cont("%d of PCI bridge %d, will remap\n", i, bus->number); pci_bus_for_each_resource()
1061 pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n", alloc_resource()
1070 pr_warn("PCI: Cannot allocate resource region %d ", idx); alloc_resource()
1073 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n", alloc_resource()
1122 pr_debug("PCI: Switching off ROM of %s\n", for_each_pci_dev()
1154 pr_debug("PCI %04x:%02x Cannot reserve Legacy IO %pR\n", pcibios_reserve_legacy_regions()
1182 pr_debug("PCI %04x:%02x Cannot reserve VGA memory %pR\n", pcibios_reserve_legacy_regions()
1209 pr_debug("PCI: Assigning unassigned resources...\n"); pcibios_resource_survey()
1213 /* This is used by the PCI hotplug driver to allocate resource
1232 pr_debug("PCI: Claiming %s: ", pci_name(dev)); pcibios_claim_one_bus()
1259 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n", pcibios_finish_adding_to_bus()
1290 pr_warn("PCI: I/O resource not set for host "); pcibios_setup_phb_resources()
1301 pr_debug("PCI: PHB IO resource = %016llx-%016llx [%lx]\n", pcibios_setup_phb_resources()
1312 pr_err("PCI: Memory resource 0 not set for "); pcibios_setup_phb_resources()
1324 pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n", pcibios_setup_phb_resources()
1330 pr_debug("PCI: PHB MEM offset = %016llx\n", pcibios_setup_phb_resources()
1332 pr_debug("PCI: PHB IO offset = %08lx\n", pcibios_setup_phb_resources()
1349 pr_debug("PCI: Scanning PHB %s\n", of_node_full_name(node)); pcibios_scan_phb()
1356 pr_err("Failed to create bus for PCI domain %04x\n", pcibios_scan_phb()
1372 pr_info("PCI: Probing PCI hardware\n"); pcibios_init()
1374 /* Scan all of the recorded PCI controllers. */ pcibios_init()
1437 * Null PCI config access functions, for the case when we can't
1467 * These functions are used early on before PCI scanning is done
1476 pr_err("Can't find hose for PCI bus %d!\n", busnr); fake_pci_bus()
/linux-4.1.27/drivers/staging/i2o/
H A Dpci.c2 * PCI handling of I2O controller
39 /* PCI device id table for all I2O controllers */
81 * Allocate DMA memory for a PCI (or in theory AGP) I2O controller. All
138 printk(KERN_INFO "%s: PCI I2O controller\n", c->name); i2o_pci_alloc()
145 printk(KERN_INFO "%s: PCI I2O controller at %08lX size=%ld\n", i2o_pci_alloc()
228 * Handle an interrupt from a PCI based I2O controller. This turns out
308 * i2o_pci_probe - Probe the PCI device for an I2O controller
309 * @pdev: PCI device to test
310 * @id: id which matched with the PCI device id table
312 * Probe the PCI device for any device which is a memory of the
324 printk(KERN_INFO "i2o: Checking for PCI I2O controllers...\n"); i2o_pci_probe()
474 /* PCI driver for I2O controller */
483 * i2o_pci_init - registers I2O PCI driver in PCI subsystem
493 * i2o_pci_exit - unregisters I2O PCI driver from PCI subsystem
/linux-4.1.27/arch/mips/include/asm/mach-lasat/
H A Dmach-gt64120.h17 * PCI Bus allocation
/linux-4.1.27/drivers/ata/
H A Dpata_netcell.c44 * netcell_init_one - Register Netcell ATA PCI device with kernel services
45 * @pdev: PCI device to register
48 * Called from kernel PCI layer.
51 * Inherited from PCI layer (may sleep).
/linux-4.1.27/drivers/atm/
H A Dtonga.h1 /* drivers/atm/tonga.h - Efficient Networks Tonga (PCI bridge) declarations */
/linux-4.1.27/arch/cris/arch-v32/drivers/pci/
H A Dbios.c13 printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n", pci_name(dev), lat); pcibios_set_master()
22 /* Leave vm_pgoff as-is, the PCI space address is the physical pci_mmap_page_range()
66 printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev)); pcibios_enable_resources()
77 printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev), old_cmd, cmd); pcibios_enable_resources()
/linux-4.1.27/arch/arm/mach-footbridge/include/mach/
H A Dhardware.h17 * 0xff000000 0x7c000000 1MB PCI I/O space
20 * 0xfc000000 0x79000000 1MB PCI IACK/special space
21 * 0xfb000000 0x7a000000 16MB PCI Config type 1
22 * 0xfa000000 0x7b000000 16MB PCI Config type 0
/linux-4.1.27/lib/
H A Dpci_iomap.c13 * pci_iomap_range - create a virtual mapping cookie for a PCI BAR
14 * @dev: PCI device that owns the BAR
55 * pci_iomap - create a virtual mapping cookie for a PCI BAR
56 * @dev: PCI device that owns the BAR

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