1/*
2 * pci.c -- PCI bus support for ColdFire processors
3 *
4 * (C) Copyright 2012, Greg Ungerer <gerg@uclinux.com>
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License.  See the file COPYING in the main directory of this archive
8 * for more details.
9 */
10
11#include <linux/types.h>
12#include <linux/module.h>
13#include <linux/init.h>
14#include <linux/kernel.h>
15#include <linux/interrupt.h>
16#include <linux/irq.h>
17#include <linux/io.h>
18#include <linux/pci.h>
19#include <linux/delay.h>
20#include <asm/coldfire.h>
21#include <asm/mcfsim.h>
22#include <asm/m54xxpci.h>
23
24/*
25 * Memory and IO mappings. We use a 1:1 mapping for local host memory to
26 * PCI bus memory (no reason not to really). IO space doesn't matter, we
27 * always use access functions for that. The device configuration space is
28 * mapped over the IO map space when we enable it in the PCICAR register.
29 */
30#define	PCI_MEM_PA	0xf0000000		/* Host physical address */
31#define	PCI_MEM_BA	0xf0000000		/* Bus physical address */
32#define	PCI_MEM_SIZE	0x08000000		/* 128 MB */
33#define	PCI_MEM_MASK	(PCI_MEM_SIZE - 1)
34
35#define	PCI_IO_PA	0xf8000000		/* Host physical address */
36#define	PCI_IO_BA	0x00000000		/* Bus physical address */
37#define	PCI_IO_SIZE	0x00010000		/* 64k */
38#define	PCI_IO_MASK	(PCI_IO_SIZE - 1)
39
40static struct pci_bus *rootbus;
41static unsigned long iospace;
42
43/*
44 * We need to be carefull probing on bus 0 (directly connected to host
45 * bridge). We should only acccess the well defined possible devices in
46 * use, ignore aliases and the like.
47 */
48static unsigned char mcf_host_slot2sid[32] = {
49	0, 0, 0, 0, 0, 0, 0, 0,
50	0, 0, 0, 0, 0, 0, 0, 0,
51	0, 1, 2, 0, 3, 4, 0, 0,
52	0, 0, 0, 0, 0, 0, 0, 0,
53};
54
55static unsigned char mcf_host_irq[] = {
56	0, 69, 69, 71, 71,
57};
58
59
60static inline void syncio(void)
61{
62	/* The ColdFire "nop" instruction waits for all bus IO to complete */
63	__asm__ __volatile__ ("nop");
64}
65
66/*
67 * Configuration space access functions. Configuration space access is
68 * through the IO mapping window, enabling it via the PCICAR register.
69 */
70static unsigned long mcf_mk_pcicar(int bus, unsigned int devfn, int where)
71{
72	return (bus << PCICAR_BUSN) | (devfn << PCICAR_DEVFNN) | (where & 0xfc);
73}
74
75static int mcf_pci_readconfig(struct pci_bus *bus, unsigned int devfn,
76	int where, int size, u32 *value)
77{
78	unsigned long addr;
79
80	*value = 0xffffffff;
81
82	if (bus->number == 0) {
83		if (mcf_host_slot2sid[PCI_SLOT(devfn)] == 0)
84			return PCIBIOS_SUCCESSFUL;
85	}
86
87	syncio();
88	addr = mcf_mk_pcicar(bus->number, devfn, where);
89	__raw_writel(PCICAR_E | addr, PCICAR);
90	addr = iospace + (where & 0x3);
91
92	switch (size) {
93	case 1:
94		*value = __raw_readb(addr);
95		break;
96	case 2:
97		*value = le16_to_cpu(__raw_readw(addr));
98		break;
99	default:
100		*value = le32_to_cpu(__raw_readl(addr));
101		break;
102	}
103
104	syncio();
105	__raw_writel(0, PCICAR);
106	return PCIBIOS_SUCCESSFUL;
107}
108
109static int mcf_pci_writeconfig(struct pci_bus *bus, unsigned int devfn,
110	int where, int size, u32 value)
111{
112	unsigned long addr;
113
114	if (bus->number == 0) {
115		if (mcf_host_slot2sid[PCI_SLOT(devfn)] == 0)
116			return PCIBIOS_SUCCESSFUL;
117	}
118
119	syncio();
120	addr = mcf_mk_pcicar(bus->number, devfn, where);
121	__raw_writel(PCICAR_E | addr, PCICAR);
122	addr = iospace + (where & 0x3);
123
124	switch (size) {
125	case 1:
126		 __raw_writeb(value, addr);
127		break;
128	case 2:
129		__raw_writew(cpu_to_le16(value), addr);
130		break;
131	default:
132		__raw_writel(cpu_to_le32(value), addr);
133		break;
134	}
135
136	syncio();
137	__raw_writel(0, PCICAR);
138	return PCIBIOS_SUCCESSFUL;
139}
140
141static struct pci_ops mcf_pci_ops = {
142	.read	= mcf_pci_readconfig,
143	.write	= mcf_pci_writeconfig,
144};
145
146/*
147 *	IO address space access functions. Pretty strait forward, these are
148 *	directly mapped in to the IO mapping window. And that is mapped into
149 *	virtual address space.
150 */
151u8 mcf_pci_inb(u32 addr)
152{
153	return __raw_readb(iospace + (addr & PCI_IO_MASK));
154}
155EXPORT_SYMBOL(mcf_pci_inb);
156
157u16 mcf_pci_inw(u32 addr)
158{
159	return le16_to_cpu(__raw_readw(iospace + (addr & PCI_IO_MASK)));
160}
161EXPORT_SYMBOL(mcf_pci_inw);
162
163u32 mcf_pci_inl(u32 addr)
164{
165	return le32_to_cpu(__raw_readl(iospace + (addr & PCI_IO_MASK)));
166}
167EXPORT_SYMBOL(mcf_pci_inl);
168
169void mcf_pci_insb(u32 addr, u8 *buf, u32 len)
170{
171	for (; len; len--)
172		*buf++ = mcf_pci_inb(addr);
173}
174EXPORT_SYMBOL(mcf_pci_insb);
175
176void mcf_pci_insw(u32 addr, u16 *buf, u32 len)
177{
178	for (; len; len--)
179		*buf++ = mcf_pci_inw(addr);
180}
181EXPORT_SYMBOL(mcf_pci_insw);
182
183void mcf_pci_insl(u32 addr, u32 *buf, u32 len)
184{
185	for (; len; len--)
186		*buf++ = mcf_pci_inl(addr);
187}
188EXPORT_SYMBOL(mcf_pci_insl);
189
190void mcf_pci_outb(u8 v, u32 addr)
191{
192	__raw_writeb(v, iospace + (addr & PCI_IO_MASK));
193}
194EXPORT_SYMBOL(mcf_pci_outb);
195
196void mcf_pci_outw(u16 v, u32 addr)
197{
198	__raw_writew(cpu_to_le16(v), iospace + (addr & PCI_IO_MASK));
199}
200EXPORT_SYMBOL(mcf_pci_outw);
201
202void mcf_pci_outl(u32 v, u32 addr)
203{
204	__raw_writel(cpu_to_le32(v), iospace + (addr & PCI_IO_MASK));
205}
206EXPORT_SYMBOL(mcf_pci_outl);
207
208void mcf_pci_outsb(u32 addr, const u8 *buf, u32 len)
209{
210	for (; len; len--)
211		mcf_pci_outb(*buf++, addr);
212}
213EXPORT_SYMBOL(mcf_pci_outsb);
214
215void mcf_pci_outsw(u32 addr, const u16 *buf, u32 len)
216{
217	for (; len; len--)
218		mcf_pci_outw(*buf++, addr);
219}
220EXPORT_SYMBOL(mcf_pci_outsw);
221
222void mcf_pci_outsl(u32 addr, const u32 *buf, u32 len)
223{
224	for (; len; len--)
225		mcf_pci_outl(*buf++, addr);
226}
227EXPORT_SYMBOL(mcf_pci_outsl);
228
229/*
230 * Initialize the PCI bus registers, and scan the bus.
231 */
232static struct resource mcf_pci_mem = {
233	.name	= "PCI Memory space",
234	.start	= PCI_MEM_PA,
235	.end	= PCI_MEM_PA + PCI_MEM_SIZE - 1,
236	.flags	= IORESOURCE_MEM,
237};
238
239static struct resource mcf_pci_io = {
240	.name	= "PCI IO space",
241	.start	= 0x400,
242	.end	= 0x10000 - 1,
243	.flags	= IORESOURCE_IO,
244};
245
246/*
247 * Interrupt mapping and setting.
248 */
249static int mcf_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
250{
251	int sid;
252
253	sid = mcf_host_slot2sid[slot];
254	if (sid)
255		return mcf_host_irq[sid];
256	return 0;
257}
258
259static int __init mcf_pci_init(void)
260{
261	pr_info("ColdFire: PCI bus initialization...\n");
262
263	/* Reset the external PCI bus */
264	__raw_writel(PCIGSCR_RESET, PCIGSCR);
265	__raw_writel(0, PCITCR);
266
267	request_resource(&iomem_resource, &mcf_pci_mem);
268	request_resource(&iomem_resource, &mcf_pci_io);
269
270	/* Configure PCI arbiter */
271	__raw_writel(PACR_INTMPRI | PACR_INTMINTE | PACR_EXTMPRI(0x1f) |
272		PACR_EXTMINTE(0x1f), PACR);
273
274	/* Set required multi-function pins for PCI bus use */
275	__raw_writew(0x3ff, MCFGPIO_PAR_PCIBG);
276	__raw_writew(0x3ff, MCFGPIO_PAR_PCIBR);
277
278	/* Set up config space for local host bus controller */
279	__raw_writel(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
280		PCI_COMMAND_INVALIDATE, PCISCR);
281	__raw_writel(PCICR1_LT(32) | PCICR1_CL(8), PCICR1);
282	__raw_writel(0, PCICR2);
283
284	/*
285	 * Set up the initiator windows for memory and IO mapping.
286	 * These give the CPU bus access onto the PCI bus. One for each of
287	 * PCI memory and IO address spaces.
288	 */
289	__raw_writel(WXBTAR(PCI_MEM_PA, PCI_MEM_BA, PCI_MEM_SIZE),
290		PCIIW0BTAR);
291	__raw_writel(WXBTAR(PCI_IO_PA, PCI_IO_BA, PCI_IO_SIZE),
292		PCIIW1BTAR);
293	__raw_writel(PCIIWCR_W0_MEM /*| PCIIWCR_W0_MRDL*/ | PCIIWCR_W0_E |
294		PCIIWCR_W1_IO | PCIIWCR_W1_E, PCIIWCR);
295
296	/*
297	 * Set up the target windows for access from the PCI bus back to the
298	 * CPU bus. All we need is access to system RAM (for mastering).
299	 */
300	__raw_writel(CONFIG_RAMBASE, PCIBAR1);
301	__raw_writel(CONFIG_RAMBASE | PCITBATR1_E, PCITBATR1);
302
303	/* Keep a virtual mapping to IO/config space active */
304	iospace = (unsigned long) ioremap(PCI_IO_PA, PCI_IO_SIZE);
305	if (iospace == 0)
306		return -ENODEV;
307	pr_info("Coldfire: PCI IO/config window mapped to 0x%x\n",
308		(u32) iospace);
309
310	/* Turn of PCI reset, and wait for devices to settle */
311	__raw_writel(0, PCIGSCR);
312	set_current_state(TASK_UNINTERRUPTIBLE);
313	schedule_timeout(msecs_to_jiffies(200));
314
315	rootbus = pci_scan_bus(0, &mcf_pci_ops, NULL);
316	if (!rootbus)
317		return -ENODEV;
318
319	rootbus->resource[0] = &mcf_pci_io;
320	rootbus->resource[1] = &mcf_pci_mem;
321
322	pci_fixup_irqs(pci_common_swizzle, mcf_pci_map_irq);
323	pci_bus_size_bridges(rootbus);
324	pci_bus_assign_resources(rootbus);
325	pci_bus_add_devices(rootbus);
326	return 0;
327}
328
329subsys_initcall(mcf_pci_init);
330