1/* 2 * Low-Level PCI Support for SH7780 targets 3 * 4 * Dustin McIntire (dustin@sensoria.com) (c) 2001 5 * Paul Mundt (lethal@linux-sh.org) (c) 2003 6 * 7 * May be copied or modified under the terms of the GNU General Public 8 * License. See linux/COPYING for more information. 9 * 10 */ 11 12#ifndef _PCI_SH7780_H_ 13#define _PCI_SH7780_H_ 14 15/* SH7780 Control Registers */ 16#define PCIECR 0xFE000008 17#define PCIECR_ENBL 0x01 18 19/* SH7780 Specific Values */ 20#define SH7780_PCI_CONFIG_BASE 0xFD000000 /* Config space base addr */ 21#define SH7780_PCI_CONFIG_SIZE 0x01000000 /* Config space size */ 22 23#define SH7780_PCIREG_BASE 0xFE040000 /* PCI regs base address */ 24 25/* SH7780 PCI Config Registers */ 26#define SH7780_PCIIR 0x114 /* PCI Interrupt Register */ 27#define SH7780_PCIIMR 0x118 /* PCI Interrupt Mask Register */ 28#define SH7780_PCIAIR 0x11C /* Error Address Register */ 29#define SH7780_PCICIR 0x120 /* Error Command/Data Register */ 30#define SH7780_PCIAINT 0x130 /* Arbiter Interrupt Register */ 31#define SH7780_PCIAINTM 0x134 /* Arbiter Int. Mask Register */ 32#define SH7780_PCIBMIR 0x138 /* Error Bus Master Register */ 33#define SH7780_PCIPAR 0x1C0 /* PIO Address Register */ 34#define SH7780_PCIPINT 0x1CC /* Power Mgmnt Int. Register */ 35#define SH7780_PCIPINTM 0x1D0 /* Power Mgmnt Mask Register */ 36 37#define SH7780_PCIMBR(x) (0x1E0 + ((x) * 8)) 38#define SH7780_PCIMBMR(x) (0x1E4 + ((x) * 8)) 39#define SH7780_PCIIOBR 0x1F8 40#define SH7780_PCIIOBMR 0x1FC 41#define SH7780_PCICSCR0 0x210 /* Cache Snoop1 Cnt. Register */ 42#define SH7780_PCICSCR1 0x214 /* Cache Snoop2 Cnt. Register */ 43#define SH7780_PCICSAR0 0x218 /* Cache Snoop1 Addr. Register */ 44#define SH7780_PCICSAR1 0x21C /* Cache Snoop2 Addr. Register */ 45 46#endif /* _PCI_SH7780_H_ */ 47