1/* pci-vdk.c: MB93090-MB00 (VDK) PCI support
2 *
3 * Copyright (C) 2003, 2004 Red Hat, Inc. All Rights Reserved.
4 * Written by David Howells (dhowells@redhat.com)
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12#include <linux/types.h>
13#include <linux/kernel.h>
14#include <linux/sched.h>
15#include <linux/pci.h>
16#include <linux/init.h>
17#include <linux/ioport.h>
18#include <linux/delay.h>
19
20#include <asm/segment.h>
21#include <asm/io.h>
22#include <asm/mb-regs.h>
23#include <asm/mb86943a.h>
24#include "pci-frv.h"
25
26unsigned int __nongpreldata pci_probe = 1;
27
28struct pci_ops *__nongpreldata pci_root_ops;
29
30/*
31 * The accessible PCI window does not cover the entire CPU address space, but
32 * there are devices we want to access outside of that window, so we need to
33 * insert specific PCI bus resources instead of using the platform-level bus
34 * resources directly for the PCI root bus.
35 *
36 * These are configured and inserted by pcibios_init() and are attached to the
37 * root bus by pcibios_fixup_bus().
38 */
39static struct resource pci_ioport_resource = {
40	.name	= "PCI IO",
41	.start	= 0,
42	.end	= IO_SPACE_LIMIT,
43	.flags	= IORESOURCE_IO,
44};
45
46static struct resource pci_iomem_resource = {
47	.name	= "PCI mem",
48	.start	= 0,
49	.end	= -1,
50	.flags	= IORESOURCE_MEM,
51};
52
53/*
54 * Functions for accessing PCI configuration space
55 */
56
57#define CONFIG_CMD(bus, dev, where) \
58	(0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3))
59
60#define __set_PciCfgAddr(A) writel((A), (volatile void __iomem *) __region_CS1 + 0x80)
61
62#define __get_PciCfgDataB(A) readb((volatile void __iomem *) __region_CS1 + 0x88 + ((A) & 3))
63#define __get_PciCfgDataW(A) readw((volatile void __iomem *) __region_CS1 + 0x88 + ((A) & 2))
64#define __get_PciCfgDataL(A) readl((volatile void __iomem *) __region_CS1 + 0x88)
65
66#define __set_PciCfgDataB(A,V) \
67	writeb((V), (volatile void __iomem *) __region_CS1 + 0x88 + (3 - ((A) & 3)))
68
69#define __set_PciCfgDataW(A,V) \
70	writew((V), (volatile void __iomem *) __region_CS1 + 0x88 + (2 - ((A) & 2)))
71
72#define __set_PciCfgDataL(A,V) \
73	writel((V), (volatile void __iomem *) __region_CS1 + 0x88)
74
75#define __get_PciBridgeDataB(A) readb((volatile void __iomem *) __region_CS1 + 0x800 + (A))
76#define __get_PciBridgeDataW(A) readw((volatile void __iomem *) __region_CS1 + 0x800 + (A))
77#define __get_PciBridgeDataL(A) readl((volatile void __iomem *) __region_CS1 + 0x800 + (A))
78
79#define __set_PciBridgeDataB(A,V) writeb((V), (volatile void __iomem *) __region_CS1 + 0x800 + (A))
80#define __set_PciBridgeDataW(A,V) writew((V), (volatile void __iomem *) __region_CS1 + 0x800 + (A))
81#define __set_PciBridgeDataL(A,V) writel((V), (volatile void __iomem *) __region_CS1 + 0x800 + (A))
82
83static inline int __query(const struct pci_dev *dev)
84{
85//	return dev->bus->number==0 && (dev->devfn==PCI_DEVFN(0,0));
86//	return dev->bus->number==1;
87//	return dev->bus->number==0 &&
88//		(dev->devfn==PCI_DEVFN(2,0) || dev->devfn==PCI_DEVFN(3,0));
89	return 0;
90}
91
92/*****************************************************************************/
93/*
94 *
95 */
96static int pci_frv_read_config(struct pci_bus *bus, unsigned int devfn, int where, int size,
97			       u32 *val)
98{
99	u32 _value;
100
101	if (bus->number == 0 && devfn == PCI_DEVFN(0, 0)) {
102		_value = __get_PciBridgeDataL(where & ~3);
103	}
104	else {
105		__set_PciCfgAddr(CONFIG_CMD(bus, devfn, where));
106		_value = __get_PciCfgDataL(where & ~3);
107	}
108
109	switch (size) {
110	case 1:
111		_value = _value >> ((where & 3) * 8);
112		break;
113
114	case 2:
115		_value = _value >> ((where & 2) * 8);
116		break;
117
118	case 4:
119		break;
120
121	default:
122		BUG();
123	}
124
125	*val = _value;
126	return PCIBIOS_SUCCESSFUL;
127}
128
129static int pci_frv_write_config(struct pci_bus *bus, unsigned int devfn, int where, int size,
130				u32 value)
131{
132	switch (size) {
133	case 1:
134		if (bus->number == 0 && devfn == PCI_DEVFN(0, 0)) {
135			__set_PciBridgeDataB(where, value);
136		}
137		else {
138			__set_PciCfgAddr(CONFIG_CMD(bus, devfn, where));
139			__set_PciCfgDataB(where, value);
140		}
141		break;
142
143	case 2:
144		if (bus->number == 0 && devfn == PCI_DEVFN(0, 0)) {
145			__set_PciBridgeDataW(where, value);
146		}
147		else {
148			__set_PciCfgAddr(CONFIG_CMD(bus, devfn, where));
149			__set_PciCfgDataW(where, value);
150		}
151		break;
152
153	case 4:
154		if (bus->number == 0 && devfn == PCI_DEVFN(0, 0)) {
155			__set_PciBridgeDataL(where, value);
156		}
157		else {
158			__set_PciCfgAddr(CONFIG_CMD(bus, devfn, where));
159			__set_PciCfgDataL(where, value);
160		}
161		break;
162
163	default:
164		BUG();
165	}
166
167	return PCIBIOS_SUCCESSFUL;
168}
169
170static struct pci_ops pci_direct_frv = {
171	.read = pci_frv_read_config,
172	.write = pci_frv_write_config,
173};
174
175/*
176 * Before we decide to use direct hardware access mechanisms, we try to do some
177 * trivial checks to ensure it at least _seems_ to be working -- we just test
178 * whether bus 00 contains a host bridge (this is similar to checking
179 * techniques used in XFree86, but ours should be more reliable since we
180 * attempt to make use of direct access hints provided by the PCI BIOS).
181 *
182 * This should be close to trivial, but it isn't, because there are buggy
183 * chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID.
184 */
185static int __init pci_sanity_check(struct pci_ops *o)
186{
187	struct pci_bus bus;		/* Fake bus and device */
188	u32 id;
189
190	bus.number	= 0;
191
192	if (o->read(&bus, 0, PCI_VENDOR_ID, 4, &id) == PCIBIOS_SUCCESSFUL) {
193		printk("PCI: VDK Bridge device:vendor: %08x\n", id);
194		if (id == 0x200e10cf)
195			return 1;
196	}
197
198	printk("PCI: VDK Bridge: Sanity check failed\n");
199	return 0;
200}
201
202static struct pci_ops * __init pci_check_direct(void)
203{
204	unsigned long flags;
205
206	local_irq_save(flags);
207
208	/* check if access works */
209	if (pci_sanity_check(&pci_direct_frv)) {
210		local_irq_restore(flags);
211		printk("PCI: Using configuration frv\n");
212//		request_mem_region(0xBE040000, 256, "FRV bridge");
213//		request_mem_region(0xBFFFFFF4, 12, "PCI frv");
214		return &pci_direct_frv;
215	}
216
217	local_irq_restore(flags);
218	return NULL;
219}
220
221/*
222 * Exceptions for specific devices. Usually work-arounds for fatal design flaws.
223 */
224
225static void __init pci_fixup_umc_ide(struct pci_dev *d)
226{
227	/*
228	 * UM8886BF IDE controller sets region type bits incorrectly,
229	 * therefore they look like memory despite of them being I/O.
230	 */
231	int i;
232
233	printk("PCI: Fixing base address flags for device %s\n", pci_name(d));
234	for(i=0; i<4; i++)
235		d->resource[i].flags |= PCI_BASE_ADDRESS_SPACE_IO;
236}
237
238static void pci_fixup_ide_bases(struct pci_dev *d)
239{
240	int i;
241
242	/*
243	 * PCI IDE controllers use non-standard I/O port decoding, respect it.
244	 */
245	if ((d->class >> 8) != PCI_CLASS_STORAGE_IDE)
246		return;
247	printk("PCI: IDE base address fixup for %s\n", pci_name(d));
248	for(i=0; i<4; i++) {
249		struct resource *r = &d->resource[i];
250		if ((r->start & ~0x80) == 0x374) {
251			r->start |= 2;
252			r->end = r->start;
253		}
254	}
255}
256
257static void pci_fixup_ide_trash(struct pci_dev *d)
258{
259	int i;
260
261	/*
262	 * There exist PCI IDE controllers which have utter garbage
263	 * in first four base registers. Ignore that.
264	 */
265	printk("PCI: IDE base address trash cleared for %s\n", pci_name(d));
266	for(i=0; i<4; i++)
267		d->resource[i].start = d->resource[i].end = d->resource[i].flags = 0;
268}
269
270static void pci_fixup_latency(struct pci_dev *d)
271{
272	/*
273	 *  SiS 5597 and 5598 chipsets require latency timer set to
274	 *  at most 32 to avoid lockups.
275	 */
276	DBG("PCI: Setting max latency to 32\n");
277	pcibios_max_latency = 32;
278}
279
280DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886BF, pci_fixup_umc_ide);
281DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5513, pci_fixup_ide_trash);
282DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, pci_fixup_latency);
283DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5598, pci_fixup_latency);
284DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases);
285
286/*
287 *  Called after each bus is probed, but before its children
288 *  are examined.
289 */
290
291void pcibios_fixup_bus(struct pci_bus *bus)
292{
293#if 0
294	printk("### PCIBIOS_FIXUP_BUS(%d)\n",bus->number);
295#endif
296
297	pci_read_bridge_bases(bus);
298
299	if (bus->number == 0) {
300		struct pci_dev *dev;
301		list_for_each_entry(dev, &bus->devices, bus_list) {
302			if (dev->devfn == 0) {
303				dev->resource[0].start = 0;
304				dev->resource[0].end = 0;
305			}
306		}
307	}
308}
309
310/*
311 * Initialization. Try all known PCI access methods. Note that we support
312 * using both PCI BIOS and direct access: in such cases, we use I/O ports
313 * to access config space, but we still keep BIOS order of cards to be
314 * compatible with 2.0.X. This should go away some day.
315 */
316
317int __init pcibios_init(void)
318{
319	struct pci_bus *bus;
320	struct pci_ops *dir = NULL;
321	LIST_HEAD(resources);
322
323	if (!mb93090_mb00_detected)
324		return -ENXIO;
325
326	__reg_MB86943_sl_ctl |= MB86943_SL_CTL_DRCT_MASTER_SWAP | MB86943_SL_CTL_DRCT_SLAVE_SWAP;
327
328	__reg_MB86943_ecs_base(1)	= ((__region_CS2 + 0x01000000) >> 9) | 0x08000000;
329	__reg_MB86943_ecs_base(2)	= ((__region_CS2 + 0x00000000) >> 9) | 0x08000000;
330
331	*(volatile uint32_t *) (__region_CS1 + 0x848) = 0xe0000000;
332	*(volatile uint32_t *) (__region_CS1 + 0x8b8) = 0x00000000;
333
334	__reg_MB86943_sl_pci_io_base	= (__region_CS2 + 0x04000000) >> 9;
335	__reg_MB86943_sl_pci_mem_base	= (__region_CS2 + 0x08000000) >> 9;
336	__reg_MB86943_pci_sl_io_base	= __region_CS2 + 0x04000000;
337	__reg_MB86943_pci_sl_mem_base	= __region_CS2 + 0x08000000;
338	mb();
339
340	/* enable PCI arbitration */
341	__reg_MB86943_pci_arbiter	= MB86943_PCIARB_EN;
342
343	pci_ioport_resource.start	= (__reg_MB86943_sl_pci_io_base << 9) & 0xfffffc00;
344	pci_ioport_resource.end		= (__reg_MB86943_sl_pci_io_range << 9) | 0x3ff;
345	pci_ioport_resource.end		+= pci_ioport_resource.start;
346
347	printk("PCI IO window:  %08llx-%08llx\n",
348	       (unsigned long long) pci_ioport_resource.start,
349	       (unsigned long long) pci_ioport_resource.end);
350
351	pci_iomem_resource.start	= (__reg_MB86943_sl_pci_mem_base << 9) & 0xfffffc00;
352	pci_iomem_resource.end		= (__reg_MB86943_sl_pci_mem_range << 9) | 0x3ff;
353	pci_iomem_resource.end		+= pci_iomem_resource.start;
354
355	/* Reserve somewhere to write to flush posted writes.  This is used by
356	 * __flush_PCI_writes() from asm/io.h to force the write FIFO in the
357	 * CPU-PCI bridge to flush as this doesn't happen automatically when a
358	 * read is performed on the MB93090 development kit motherboard.
359	 */
360	pci_iomem_resource.start	+= 0x400;
361
362	printk("PCI MEM window: %08llx-%08llx\n",
363	       (unsigned long long) pci_iomem_resource.start,
364	       (unsigned long long) pci_iomem_resource.end);
365	printk("PCI DMA memory: %08lx-%08lx\n",
366	       dma_coherent_mem_start, dma_coherent_mem_end);
367
368	if (insert_resource(&iomem_resource, &pci_iomem_resource) < 0)
369		panic("Unable to insert PCI IOMEM resource\n");
370	if (insert_resource(&ioport_resource, &pci_ioport_resource) < 0)
371		panic("Unable to insert PCI IOPORT resource\n");
372
373	if (!pci_probe)
374		return -ENXIO;
375
376	dir = pci_check_direct();
377	if (dir)
378		pci_root_ops = dir;
379	else {
380		printk("PCI: No PCI bus detected\n");
381		return -ENXIO;
382	}
383
384	printk("PCI: Probing PCI hardware\n");
385	pci_add_resource(&resources, &pci_ioport_resource);
386	pci_add_resource(&resources, &pci_iomem_resource);
387	bus = pci_scan_root_bus(NULL, 0, pci_root_ops, NULL, &resources);
388
389	pcibios_irq_init();
390	pcibios_fixup_irqs();
391	pcibios_resource_survey();
392	if (!bus)
393		return 0;
394
395	pci_bus_add_devices(bus);
396	return 0;
397}
398
399arch_initcall(pcibios_init);
400
401char * __init pcibios_setup(char *str)
402{
403	if (!strcmp(str, "off")) {
404		pci_probe = 0;
405		return NULL;
406	}
407	return str;
408}
409
410int pcibios_enable_device(struct pci_dev *dev, int mask)
411{
412	int err;
413
414	if ((err = pci_enable_resources(dev, mask)) < 0)
415		return err;
416	if (!dev->msi_enabled)
417		pcibios_enable_irq(dev);
418	return 0;
419}
420