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Searched refs:MHZ (Results 1 – 37 of 37) sorted by relevance

/linux-4.1.27/drivers/clk/
Dclk-nspire.c17 #define MHZ (1000 * 1000) macro
48 clk->base_clock = 48 * MHZ; in nspire_clkinfo_cx()
50 clk->base_clock = 6 * EXTRACT(val, CX_BASE) * MHZ; in nspire_clkinfo_cx()
59 clk->base_clock = 27 * MHZ; in nspire_clkinfo_classic()
61 clk->base_clock = (300 - 6 * EXTRACT(val, CLASSIC_BASE)) * MHZ; in nspire_clkinfo_classic()
136 info.base_clock / MHZ, in nspire_clk_setup()
137 info.base_clock / info.base_cpu_ratio / MHZ, in nspire_clk_setup()
138 info.base_clock / info.base_ahb_ratio / MHZ); in nspire_clk_setup()
/linux-4.1.27/drivers/net/can/softing/
Dsofting_cs.c37 #define MHZ (1000*1000) macro
44 .freq = 16 * MHZ, .max_brp = 32, .max_sjw = 4,
56 .freq = 16 * MHZ, .max_brp = 32, .max_sjw = 4,
68 .freq = 20 * MHZ, .max_brp = 32, .max_sjw = 4,
80 .freq = 24 * MHZ, .max_brp = 64, .max_sjw = 4,
92 .freq = 16 * MHZ, .max_brp = 64, .max_sjw = 4,
104 .freq = 20 * MHZ, .max_brp = 32, .max_sjw = 4,
116 .freq = 24 * MHZ, .max_brp = 64, .max_sjw = 4,
128 .freq = 16 * MHZ, .max_brp = 64, .max_sjw = 4,
140 .freq = 24 * MHZ, .max_brp = 64, .max_sjw = 4,
/linux-4.1.27/drivers/video/fbdev/exynos/
Dexynos_mipi_dsi_common.c41 #define MHZ (1000 * 1000) macro
42 #define FIN_HZ (24 * MHZ)
44 #define DFIN_PLL_MIN_HZ (6 * MHZ)
45 #define DFIN_PLL_MAX_HZ (12 * MHZ)
47 #define DFVCO_MIN_HZ (500 * MHZ)
48 #define DFVCO_MAX_HZ (1000 * MHZ)
502 if (dfin_pll < 7 * MHZ) in exynos_mipi_dsi_change_pll()
504 else if (dfin_pll < 8 * MHZ) in exynos_mipi_dsi_change_pll()
506 else if (dfin_pll < 9 * MHZ) in exynos_mipi_dsi_change_pll()
508 else if (dfin_pll < 10 * MHZ) in exynos_mipi_dsi_change_pll()
[all …]
/linux-4.1.27/arch/mips/ralink/
Dmt7620.c242 #define MHZ(x) ((x) * 1000 * 1000) macro
251 return MHZ(40); in mt7620_get_xtal_rate()
253 return MHZ(20); in mt7620_get_xtal_rate()
265 return MHZ(40); in mt7620_get_periph_rate()
282 return MHZ(600); in mt7620_get_cpu_pll_rate()
308 return MHZ(480); in mt7620_get_pll_rate()
385 if (xtal_rate == MHZ(40)) in ralink_clk_init()
386 cpu_rate = MHZ(580); in ralink_clk_init()
388 cpu_rate = MHZ(575); in ralink_clk_init()
390 periph_rate = MHZ(40); in ralink_clk_init()
/linux-4.1.27/arch/arm/mach-s3c64xx/
Dsetup-usb-phy.c37 case 12 * MHZ: in s3c_usb_otgphy_init()
40 case 24 * MHZ: in s3c_usb_otgphy_init()
44 case 48 * MHZ: in s3c_usb_otgphy_init()
/linux-4.1.27/drivers/clk/sirf/
Dclk-common.c11 #define MHZ (KHZ * KHZ) macro
89 WARN_ON(fin % MHZ); in pll_clk_recalc_rate()
90 return fin / MHZ * nf / nr / od * MHZ; in pll_clk_recalc_rate()
104 rate = rate - rate % MHZ; in pll_clk_round_rate()
106 nf = rate / MHZ; in pll_clk_round_rate()
114 nr = fin / MHZ; in pll_clk_round_rate()
136 nf = rate / MHZ; in pll_clk_set_rate()
137 if (unlikely((rate % MHZ) || nf > BIT(13) || nf < 1)) in pll_clk_set_rate()
141 BUG_ON(fin < MHZ); in pll_clk_set_rate()
143 nr = fin / MHZ; in pll_clk_set_rate()
[all …]
/linux-4.1.27/arch/arm/plat-samsung/include/plat/
Dcpu.h84 #ifndef MHZ
85 #define MHZ (1000*1000) macro
88 #define print_mhz(m) ((m) / MHZ), (((m) / 1000) % 1000)
/linux-4.1.27/drivers/gpu/drm/exynos/
Dexynos_drm_dsi.c368 #ifndef MHZ
369 #define MHZ (1000*1000) macro
382 p_min = DIV_ROUND_UP(fin, (12 * MHZ)); in exynos_dsi_pll_find_pms()
383 p_max = fin / (6 * MHZ); in exynos_dsi_pll_find_pms()
398 if (tmp < 500 * MHZ || tmp > 1000 * MHZ) in exynos_dsi_pll_find_pms()
458 100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ, in exynos_dsi_set_pll()
459 270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ, in exynos_dsi_set_pll()
460 510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ, in exynos_dsi_set_pll()
461 770 * MHZ, 870 * MHZ, 950 * MHZ, in exynos_dsi_set_pll()
504 if (esc_clk > 20 * MHZ) { in exynos_dsi_enable_clock()
/linux-4.1.27/drivers/phy/
Dphy-exynos4x12-usb2.c143 case 10 * MHZ: in exynos4x12_rate_to_clk()
146 case 12 * MHZ: in exynos4x12_rate_to_clk()
152 case 20 * MHZ: in exynos4x12_rate_to_clk()
155 case 24 * MHZ: in exynos4x12_rate_to_clk()
158 case 50 * MHZ: in exynos4x12_rate_to_clk()
Dphy-s5pv210-usb2.c76 case 12 * MHZ: in s5pv210_rate_to_clk()
79 case 24 * MHZ: in s5pv210_rate_to_clk()
82 case 48 * MHZ: in s5pv210_rate_to_clk()
Dphy-exynos5250-usb2.c153 case 10 * MHZ: in exynos5250_rate_to_clk()
156 case 12 * MHZ: in exynos5250_rate_to_clk()
162 case 20 * MHZ: in exynos5250_rate_to_clk()
165 case 24 * MHZ: in exynos5250_rate_to_clk()
168 case 50 * MHZ: in exynos5250_rate_to_clk()
Dphy-exynos4210-usb2.c111 case 12 * MHZ: in exynos4210_rate_to_clk()
114 case 24 * MHZ: in exynos4210_rate_to_clk()
117 case 48 * MHZ: in exynos4210_rate_to_clk()
Dphy-exynos5-usbdrd.c122 #define MHZ (KHZ * KHZ) macro
205 case 10 * MHZ: in exynos5_rate_to_clk()
208 case 12 * MHZ: in exynos5_rate_to_clk()
214 case 20 * MHZ: in exynos5_rate_to_clk()
217 case 24 * MHZ: in exynos5_rate_to_clk()
220 case 50 * MHZ: in exynos5_rate_to_clk()
Dphy-samsung-usb2.h22 #define MHZ (KHZ * KHZ) macro
/linux-4.1.27/arch/powerpc/boot/
Dredboot-8xx.c22 #define MHZ(x) ((x + 500000) / 1000000) macro
35 bd.bi_busfreq, MHZ(bd.bi_busfreq)); in platform_fixups()
Dredboot-83xx.c23 #define MHZ(x) ((x + 500000) / 1000000) macro
36 bd.bi_busfreq, MHZ(bd.bi_busfreq)); in platform_fixups()
Ddevtree.c60 #define MHZ(x) ((x + 500000) / 1000000) macro
66 printf("CPU clock-frequency <- 0x%x (%dMHz)\n\r", cpu, MHZ(cpu)); in dt_fixup_cpu_clocks()
67 printf("CPU timebase-frequency <- 0x%x (%dMHz)\n\r", tb, MHZ(tb)); in dt_fixup_cpu_clocks()
69 printf("CPU bus-frequency <- 0x%x (%dMHz)\n\r", bus, MHZ(bus)); in dt_fixup_cpu_clocks()
86 printf("%s: clock-frequency <- %x (%dMHz)\n\r", path, freq, MHZ(freq)); in dt_fixup_clock()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
Dgk20a.c34 #define MHZ (1000 * 1000) macro
165 target_clk_f = rate * 2 / MHZ; in gk20a_pllg_calc_mnp()
166 ref_clk_f = priv->parent_rate / MHZ; in gk20a_pllg_calc_mnp()
260 target_freq = gk20a_pllg_calc_rate(priv) / MHZ; in gk20a_pllg_calc_mnp()
358 priv->parent_rate / MHZ); in _gk20a_pllg_program_mnp()
391 priv->parent_rate / MHZ); in _gk20a_pllg_program_mnp()
449 priv->parent_rate / MHZ); in gk20a_pllg_disable()
662 nv_info(priv, "parent clock rate: %d Mhz\n", priv->parent_rate / MHZ); in gk20a_clk_ctor()
/linux-4.1.27/drivers/mfd/
Dsm501.c87 #define MHZ (1000 * 1000) macro
122 pll2 = 288 * MHZ; in decode_div()
127 #define fmt_freq(x) ((x) / MHZ), ((x) % MHZ), (x)
145 pll2 = 336 * MHZ; in sm501_dump_clk()
148 pll2 = 288 * MHZ; in sm501_dump_clk()
151 pll2 = 240 * MHZ; in sm501_dump_clk()
154 pll2 = 192 * MHZ; in sm501_dump_clk()
158 sdclk0 = (misct & (1<<12)) ? pll2 : 288 * MHZ; in sm501_dump_clk()
161 sdclk1 = (misct & (1<<20)) ? pll2 : 288 * MHZ; in sm501_dump_clk()
1547 .mclk = 72 * MHZ,
[all …]
/linux-4.1.27/arch/arc/boot/dts/
Dskeleton.dtsi16 clock-frequency = <80000000>; /* 80 MHZ */
Dangel4.dts14 clock-frequency = <80000000>; /* 80 MHZ */
Dnsimosci.dts14 clock-frequency = <20000000>; /* 20 MHZ */
Dabilis_tb101.dtsi26 clock-frequency = <500000000>; /* 500 MHZ */
Dabilis_tb100.dtsi26 clock-frequency = <500000000>; /* 500 MHZ */
/linux-4.1.27/arch/arm/mach-s3c24xx/
Dmach-anubis.c317 .mclk = 72 * MHZ,
318 .m1xclk = 144 * MHZ,
/linux-4.1.27/drivers/spi/
Dspi-ath79.c34 #define MHZ (1000 * 1000) macro
260 rate = DIV_ROUND_UP(clk_get_rate(sp->clk), MHZ); in ath79_spi_probe()
/linux-4.1.27/drivers/clk/samsung/
Dclk-s3c2410.c387 if (_get_rate("xti") == 12 * MHZ) { in s3c2410_common_clk_init()
397 if (_get_rate("xti") == 12 * MHZ) { in s3c2410_common_clk_init()
Dclk-exynos5250.c779 if (_get_rate("fin_pll") == 24 * MHZ) { in exynos5250_clk_init()
784 if (_get_rate("mout_vpllsrc") == 24 * MHZ) in exynos5250_clk_init()
Dclk.h51 #define MHZ (1000 * 1000) macro
Dclk-exynos5420.c1279 if (_get_rate("fin_pll") == 24 * MHZ) { in exynos5x_clk_init()
/linux-4.1.27/drivers/staging/sm750fb/
Dsm750.h13 #define MHZ(x) ((x) * 1000000) macro
/linux-4.1.27/drivers/net/wireless/iwlwifi/
Diwl-nvm-parse.c812 CHECK_AND_PRINT_I(40MHZ), in iwl_parse_nvm_mcc_info()
813 CHECK_AND_PRINT_I(80MHZ), in iwl_parse_nvm_mcc_info()
814 CHECK_AND_PRINT_I(160MHZ), in iwl_parse_nvm_mcc_info()
Diwl-eeprom-parse.c450 TXP_CHECK_AND_PRINT(40MHZ), in iwl_eeprom_enhanced_txpower()
/linux-4.1.27/include/linux/
Dhil.h45 #define HIL_CLOCK 8MHZ
/linux-4.1.27/Documentation/devicetree/bindings/mmc/
Dsynopsys-dw-mshc.txt56 clock(cclk_out). If it's not specified, max is 200MHZ and min is 400KHz by default.
/linux-4.1.27/drivers/eisa/
Deisa.ids504 DTK0003 "DTK PLM-3331P EISACACHE486 33/25/50 MHZ"
/linux-4.1.27/Documentation/networking/
Darcnet-hardware.txt2330 20.000000 MHZ